drivers/tty/serial/fsl_lpuart.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Freescale lpuart serial port driver
   4  *
   5  *  Copyright 2012-2014 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/console.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/dmaengine.h>
  12 #include <linux/dmapool.h>
  13 #include <linux/io.h>
  14 #include <linux/irq.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/of_device.h>
  18 #include <linux/of_dma.h>
  19 #include <linux/serial_core.h>
  20 #include <linux/slab.h>
  21 #include <linux/tty_flip.h>
  22
  23 /* All registers are 8-bit width */
  24 #define UARTBDH                 0x00
  25 #define UARTBDL                 0x01
  26 #define UARTCR1                 0x02
  27 #define UARTCR2                 0x03
  28 #define UARTSR1                 0x04
  29 #define UARTCR3                 0x06
  30 #define UARTDR                  0x07
  31 #define UARTCR4                 0x0a
  32 #define UARTCR5                 0x0b
  33 #define UARTMODEM               0x0d
  34 #define UARTPFIFO               0x10
  35 #define UARTCFIFO               0x11
  36 #define UARTSFIFO               0x12
  37 #define UARTTWFIFO              0x13
  38 #define UARTTCFIFO              0x14
  39 #define UARTRWFIFO              0x15
  40
  41 #define UARTBDH_LBKDIE          0x80
  42 #define UARTBDH_RXEDGIE         0x40
  43 #define UARTBDH_SBR_MASK        0x1f
  44
  45 #define UARTCR1_LOOPS           0x80
  46 #define UARTCR1_RSRC            0x20
  47 #define UARTCR1_M               0x10
  48 #define UARTCR1_WAKE            0x08
  49 #define UARTCR1_ILT             0x04
  50 #define UARTCR1_PE              0x02
  51 #define UARTCR1_PT              0x01
  52
  53 #define UARTCR2_TIE             0x80
  54 #define UARTCR2_TCIE            0x40
  55 #define UARTCR2_RIE             0x20
  56 #define UARTCR2_ILIE            0x10
  57 #define UARTCR2_TE              0x08
  58 #define UARTCR2_RE              0x04
  59 #define UARTCR2_RWU             0x02
  60 #define UARTCR2_SBK             0x01
  61
  62 #define UARTSR1_TDRE            0x80
  63 #define UARTSR1_TC              0x40
  64 #define UARTSR1_RDRF            0x20
  65 #define UARTSR1_IDLE            0x10
  66 #define UARTSR1_OR              0x08
  67 #define UARTSR1_NF              0x04
  68 #define UARTSR1_FE              0x02
  69 #define UARTSR1_PE              0x01
  70
  71 #define UARTCR3_R8              0x80
  72 #define UARTCR3_T8              0x40
  73 #define UARTCR3_TXDIR           0x20
  74 #define UARTCR3_TXINV           0x10
  75 #define UARTCR3_ORIE            0x08
  76 #define UARTCR3_NEIE            0x04
  77 #define UARTCR3_FEIE            0x02
  78 #define UARTCR3_PEIE            0x01
  79
  80 #define UARTCR4_MAEN1           0x80
  81 #define UARTCR4_MAEN2           0x40
  82 #define UARTCR4_M10             0x20
  83 #define UARTCR4_BRFA_MASK       0x1f
  84 #define UARTCR4_BRFA_OFF        0
  85
  86 #define UARTCR5_TDMAS           0x80
  87 #define UARTCR5_RDMAS           0x20
  88
  89 #define UARTMODEM_RXRTSE        0x08
  90 #define UARTMODEM_TXRTSPOL      0x04
  91 #define UARTMODEM_TXRTSE        0x02
  92 #define UARTMODEM_TXCTSE        0x01
  93
  94 #define UARTPFIFO_TXFE          0x80
  95 #define UARTPFIFO_FIFOSIZE_MASK 0x7
  96 #define UARTPFIFO_TXSIZE_OFF    4
  97 #define UARTPFIFO_RXFE          0x08
  98 #define UARTPFIFO_RXSIZE_OFF    0
  99
 100 #define UARTCFIFO_TXFLUSH       0x80
 101 #define UARTCFIFO_RXFLUSH       0x40
 102 #define UARTCFIFO_RXOFE         0x04
 103 #define UARTCFIFO_TXOFE         0x02
 104 #define UARTCFIFO_RXUFE         0x01
 105
 106 #define UARTSFIFO_TXEMPT        0x80
 107 #define UARTSFIFO_RXEMPT        0x40
 108 #define UARTSFIFO_RXOF          0x04
 109 #define UARTSFIFO_TXOF          0x02
 110 #define UARTSFIFO_RXUF          0x01
 111
 112 /* 32-bit register definition */
 113 #define UARTBAUD                0x00
 114 #define UARTSTAT                0x04
 115 #define UARTCTRL                0x08
 116 #define UARTDATA                0x0C
 117 #define UARTMATCH               0x10
 118 #define UARTMODIR               0x14
 119 #define UARTFIFO                0x18
 120 #define UARTWATER               0x1c
 121
 122 #define UARTBAUD_MAEN1          0x80000000
 123 #define UARTBAUD_MAEN2          0x40000000
 124 #define UARTBAUD_M10            0x20000000
 125 #define UARTBAUD_TDMAE          0x00800000
 126 #define UARTBAUD_RDMAE          0x00200000
 127 #define UARTBAUD_MATCFG         0x00400000
 128 #define UARTBAUD_BOTHEDGE       0x00020000
 129 #define UARTBAUD_RESYNCDIS      0x00010000
 130 #define UARTBAUD_LBKDIE         0x00008000
 131 #define UARTBAUD_RXEDGIE        0x00004000
 132 #define UARTBAUD_SBNS           0x00002000
 133 #define UARTBAUD_SBR            0x00000000
 134 #define UARTBAUD_SBR_MASK       0x1fff
 135 #define UARTBAUD_OSR_MASK       0x1f
 136 #define UARTBAUD_OSR_SHIFT      24
 137
 138 #define UARTSTAT_LBKDIF         0x80000000
 139 #define UARTSTAT_RXEDGIF        0x40000000
 140 #define UARTSTAT_MSBF           0x20000000
 141 #define UARTSTAT_RXINV          0x10000000
 142 #define UARTSTAT_RWUID          0x08000000
 143 #define UARTSTAT_BRK13          0x04000000
 144 #define UARTSTAT_LBKDE          0x02000000
 145 #define UARTSTAT_RAF            0x01000000
 146 #define UARTSTAT_TDRE           0x00800000
 147 #define UARTSTAT_TC             0x00400000
 148 #define UARTSTAT_RDRF           0x00200000
 149 #define UARTSTAT_IDLE           0x00100000
 150 #define UARTSTAT_OR             0x00080000
 151 #define UARTSTAT_NF             0x00040000
 152 #define UARTSTAT_FE             0x00020000
 153 #define UARTSTAT_PE             0x00010000
 154 #define UARTSTAT_MA1F           0x00008000
 155 #define UARTSTAT_M21F           0x00004000
 156
 157 #define UARTCTRL_R8T9           0x80000000
 158 #define UARTCTRL_R9T8           0x40000000
 159 #define UARTCTRL_TXDIR          0x20000000
 160 #define UARTCTRL_TXINV          0x10000000
 161 #define UARTCTRL_ORIE           0x08000000
 162 #define UARTCTRL_NEIE           0x04000000
 163 #define UARTCTRL_FEIE           0x02000000
 164 #define UARTCTRL_PEIE           0x01000000
 165 #define UARTCTRL_TIE            0x00800000
 166 #define UARTCTRL_TCIE           0x00400000
 167 #define UARTCTRL_RIE            0x00200000
 168 #define UARTCTRL_ILIE           0x00100000
 169 #define UARTCTRL_TE             0x00080000
 170 #define UARTCTRL_RE             0x00040000
 171 #define UARTCTRL_RWU            0x00020000
 172 #define UARTCTRL_SBK            0x00010000
 173 #define UARTCTRL_MA1IE          0x00008000
 174 #define UARTCTRL_MA2IE          0x00004000
 175 #define UARTCTRL_IDLECFG        0x00000100
 176 #define UARTCTRL_LOOPS          0x00000080
 177 #define UARTCTRL_DOZEEN         0x00000040
 178 #define UARTCTRL_RSRC           0x00000020
 179 #define UARTCTRL_M              0x00000010
 180 #define UARTCTRL_WAKE           0x00000008
 181 #define UARTCTRL_ILT            0x00000004
 182 #define UARTCTRL_PE             0x00000002
 183 #define UARTCTRL_PT             0x00000001
 184
 185 #define UARTDATA_NOISY          0x00008000
 186 #define UARTDATA_PARITYE        0x00004000
 187 #define UARTDATA_FRETSC         0x00002000
 188 #define UARTDATA_RXEMPT         0x00001000
 189 #define UARTDATA_IDLINE         0x00000800
 190 #define UARTDATA_MASK           0x3ff
 191
 192 #define UARTMODIR_IREN          0x00020000
 193 #define UARTMODIR_TXCTSSRC      0x00000020
 194 #define UARTMODIR_TXCTSC        0x00000010
 195 #define UARTMODIR_RXRTSE        0x00000008
 196 #define UARTMODIR_TXRTSPOL      0x00000004
 197 #define UARTMODIR_TXRTSE        0x00000002
 198 #define UARTMODIR_TXCTSE        0x00000001
 199
 200 #define UARTFIFO_TXEMPT         0x00800000
 201 #define UARTFIFO_RXEMPT         0x00400000
 202 #define UARTFIFO_TXOF           0x00020000
 203 #define UARTFIFO_RXUF           0x00010000
 204 #define UARTFIFO_TXFLUSH        0x00008000
 205 #define UARTFIFO_RXFLUSH        0x00004000
 206 #define UARTFIFO_TXOFE          0x00000200
 207 #define UARTFIFO_RXUFE          0x00000100
 208 #define UARTFIFO_TXFE           0x00000080
 209 #define UARTFIFO_FIFOSIZE_MASK  0x7
 210 #define UARTFIFO_TXSIZE_OFF     4
 211 #define UARTFIFO_RXFE           0x00000008
 212 #define UARTFIFO_RXSIZE_OFF     0
 213 #define UARTFIFO_DEPTH(x)       (0x1 << ((x) ? ((x) + 1) : 0))
 214
 215 #define UARTWATER_COUNT_MASK    0xff
 216 #define UARTWATER_TXCNT_OFF     8
 217 #define UARTWATER_RXCNT_OFF     24
 218 #define UARTWATER_WATER_MASK    0xff
 219 #define UARTWATER_TXWATER_OFF   0
 220 #define UARTWATER_RXWATER_OFF   16
 221
 222 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
 223 #define DMA_RX_TIMEOUT          (10)
 224
 225 #define DRIVER_NAME     "fsl-lpuart"
 226 #define DEV_NAME        "ttyLP"
 227 #define UART_NR         6
 228
 229 /* IMX lpuart has four extra unused regs located at the beginning */
 230 #define IMX_REG_OFF     0x10
 231
 232 static DEFINE_IDA(fsl_lpuart_ida);
 233
 234 enum lpuart_type {
 235         VF610_LPUART,
 236         LS1021A_LPUART,
 237         LS1028A_LPUART,
 238         IMX7ULP_LPUART,
 239         IMX8QXP_LPUART,
 240 };
 241
 242 struct lpuart_port {
 243         struct uart_port        port;
 244         enum lpuart_type        devtype;
 245         struct clk              *ipg_clk;
 246         struct clk              *baud_clk;
 247         unsigned int            txfifo_size;
 248         unsigned int            rxfifo_size;
 249
 250         bool                    lpuart_dma_tx_use;
 251         bool                    lpuart_dma_rx_use;
 252         struct dma_chan         *dma_tx_chan;
 253         struct dma_chan         *dma_rx_chan;
 254         struct dma_async_tx_descriptor  *dma_tx_desc;
 255         struct dma_async_tx_descriptor  *dma_rx_desc;
 256         dma_cookie_t            dma_tx_cookie;
 257         dma_cookie_t            dma_rx_cookie;
 258         unsigned int            dma_tx_bytes;
 259         unsigned int            dma_rx_bytes;
 260         bool                    dma_tx_in_progress;
 261         unsigned int            dma_rx_timeout;
 262         struct timer_list       lpuart_timer;
 263         struct scatterlist      rx_sgl, tx_sgl[2];
 264         struct circ_buf         rx_ring;
 265         int                     rx_dma_rng_buf_len;
 266         unsigned int            dma_tx_nents;
 267         wait_queue_head_t       dma_wait;
 268         bool                    id_allocated;
 269 };
 270
 271 struct lpuart_soc_data {
 272         enum lpuart_type devtype;
 273         char iotype;
 274         u8 reg_off;
 275 };
 276
 277 static const struct lpuart_soc_data vf_data = {
 278         .devtype = VF610_LPUART,
 279         .iotype = UPIO_MEM,
 280 };
 281
 282 static const struct lpuart_soc_data ls1021a_data = {
 283         .devtype = LS1021A_LPUART,
 284         .iotype = UPIO_MEM32BE,
 285 };
 286
 287 static const struct lpuart_soc_data ls1028a_data = {
 288         .devtype = LS1028A_LPUART,
 289         .iotype = UPIO_MEM32,
 290 };
 291
 292 static struct lpuart_soc_data imx7ulp_data = {
 293         .devtype = IMX7ULP_LPUART,
 294         .iotype = UPIO_MEM32,
 295         .reg_off = IMX_REG_OFF,
 296 };
 297
 298 static struct lpuart_soc_data imx8qxp_data = {
 299         .devtype = IMX8QXP_LPUART,
 300         .iotype = UPIO_MEM32,
 301         .reg_off = IMX_REG_OFF,
 302 };
 303
 304 static const struct of_device_id lpuart_dt_ids[] = {
 305         { .compatible = "fsl,vf610-lpuart",     .data = &vf_data, },
 306         { .compatible = "fsl,ls1021a-lpuart",   .data = &ls1021a_data, },
 307         { .compatible = "fsl,ls1028a-lpuart",   .data = &ls1028a_data, },
 308         { .compatible = "fsl,imx7ulp-lpuart",   .data = &imx7ulp_data, },
 309         { .compatible = "fsl,imx8qxp-lpuart",   .data = &imx8qxp_data, },
 310         { /* sentinel */ }
 311 };
 312 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
 313
 314 /* Forward declare this for the dma callbacks*/
 315 static void lpuart_dma_tx_complete(void *arg);
 316
 317 static inline bool is_layerscape_lpuart(struct lpuart_port *sport)
 318 {
 319         return (sport->devtype == LS1021A_LPUART ||
 320                 sport->devtype == LS1028A_LPUART);
 321 }
 322
 323 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
 324 {
 325         return sport->devtype == IMX8QXP_LPUART;
 326 }
 327
 328 static inline u32 lpuart32_read(struct uart_port *port, u32 off)
 329 {
 330         switch (port->iotype) {
 331         case UPIO_MEM32:
 332                 return readl(port->membase + off);
 333         case UPIO_MEM32BE:
 334                 return ioread32be(port->membase + off);
 335         default:
 336                 return 0;
 337         }
 338 }
 339
 340 static inline void lpuart32_write(struct uart_port *port, u32 val,
 341                                   u32 off)
 342 {
 343         switch (port->iotype) {
 344         case UPIO_MEM32:
 345                 writel(val, port->membase + off);
 346                 break;
 347         case UPIO_MEM32BE:
 348                 iowrite32be(val, port->membase + off);
 349                 break;
 350         }
 351 }
 352
 353 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)
 354 {
 355         int ret = 0;
 356
 357         if (is_en) {
 358                 ret = clk_prepare_enable(sport->ipg_clk);
 359                 if (ret)
 360                         return ret;
 361
 362                 ret = clk_prepare_enable(sport->baud_clk);
 363                 if (ret) {
 364                         clk_disable_unprepare(sport->ipg_clk);
 365                         return ret;
 366                 }
 367         } else {
 368                 clk_disable_unprepare(sport->baud_clk);
 369                 clk_disable_unprepare(sport->ipg_clk);
 370         }
 371
 372         return 0;
 373 }
 374
 375 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
 376 {
 377         if (is_imx8qxp_lpuart(sport))
 378                 return clk_get_rate(sport->baud_clk);
 379
 380         return clk_get_rate(sport->ipg_clk);
 381 }
 382
 383 #define lpuart_enable_clks(x)   __lpuart_enable_clks(x, true)
 384 #define lpuart_disable_clks(x)  __lpuart_enable_clks(x, false)
 385
 386 static void lpuart_stop_tx(struct uart_port *port)
 387 {
 388         unsigned char temp;
 389
 390         temp = readb(port->membase + UARTCR2);
 391         temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
 392         writeb(temp, port->membase + UARTCR2);
 393 }
 394
 395 static void lpuart32_stop_tx(struct uart_port *port)
 396 {
 397         unsigned long temp;
 398
 399         temp = lpuart32_read(port, UARTCTRL);
 400         temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
 401         lpuart32_write(port, temp, UARTCTRL);
 402 }
 403
 404 static void lpuart_stop_rx(struct uart_port *port)
 405 {
 406         unsigned char temp;
 407
 408         temp = readb(port->membase + UARTCR2);
 409         writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
 410 }
 411
 412 static void lpuart32_stop_rx(struct uart_port *port)
 413 {
 414         unsigned long temp;
 415
 416         temp = lpuart32_read(port, UARTCTRL);
 417         lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
 418 }
 419
 420 static void lpuart_dma_tx(struct lpuart_port *sport)
 421 {
 422         struct circ_buf *xmit = &sport->port.state->xmit;
 423         struct scatterlist *sgl = sport->tx_sgl;
 424         struct device *dev = sport->port.dev;
 425         struct dma_chan *chan = sport->dma_tx_chan;
 426         int ret;
 427
 428         if (sport->dma_tx_in_progress)
 429                 return;
 430
 431         sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
 432
 433         if (xmit->tail < xmit->head || xmit->head == 0) {
 434                 sport->dma_tx_nents = 1;
 435                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
 436         } else {
 437                 sport->dma_tx_nents = 2;
 438                 sg_init_table(sgl, 2);
 439                 sg_set_buf(sgl, xmit->buf + xmit->tail,
 440                                 UART_XMIT_SIZE - xmit->tail);
 441                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
 442         }
 443
 444         ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents,
 445                          DMA_TO_DEVICE);
 446         if (!ret) {
 447                 dev_err(dev, "DMA mapping error for TX.\n");
 448                 return;
 449         }
 450
 451         sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl,
 452                                         ret, DMA_MEM_TO_DEV,
 453                                         DMA_PREP_INTERRUPT);
 454         if (!sport->dma_tx_desc) {
 455                 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
 456                               DMA_TO_DEVICE);
 457                 dev_err(dev, "Cannot prepare TX slave DMA!\n");
 458                 return;
 459         }
 460
 461         sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
 462         sport->dma_tx_desc->callback_param = sport;
 463         sport->dma_tx_in_progress = true;
 464         sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
 465         dma_async_issue_pending(chan);
 466 }
 467
 468 static bool lpuart_stopped_or_empty(struct uart_port *port)
 469 {
 470         return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port);
 471 }
 472
 473 static void lpuart_dma_tx_complete(void *arg)
 474 {
 475         struct lpuart_port *sport = arg;
 476         struct scatterlist *sgl = &sport->tx_sgl[0];
 477         struct circ_buf *xmit = &sport->port.state->xmit;
 478         struct dma_chan *chan = sport->dma_tx_chan;
 479         unsigned long flags;
 480
 481         spin_lock_irqsave(&sport->port.lock, flags);
 482
 483         dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
 484                      DMA_TO_DEVICE);
 485
 486         xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
 487
 488         sport->port.icount.tx += sport->dma_tx_bytes;
 489         sport->dma_tx_in_progress = false;
 490         spin_unlock_irqrestore(&sport->port.lock, flags);
 491
 492         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 493                 uart_write_wakeup(&sport->port);
 494
 495         if (waitqueue_active(&sport->dma_wait)) {
 496                 wake_up(&sport->dma_wait);
 497                 return;
 498         }
 499
 500         spin_lock_irqsave(&sport->port.lock, flags);
 501
 502         if (!lpuart_stopped_or_empty(&sport->port))
 503                 lpuart_dma_tx(sport);
 504
 505         spin_unlock_irqrestore(&sport->port.lock, flags);
 506 }
 507
 508 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
 509 {
 510         switch (sport->port.iotype) {
 511         case UPIO_MEM32:
 512                 return sport->port.mapbase + UARTDATA;
 513         case UPIO_MEM32BE:
 514                 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
 515         }
 516         return sport->port.mapbase + UARTDR;
 517 }
 518
 519 static int lpuart_dma_tx_request(struct uart_port *port)
 520 {
 521         struct lpuart_port *sport = container_of(port,
 522                                         struct lpuart_port, port);
 523         struct dma_slave_config dma_tx_sconfig = {};
 524         int ret;
 525
 526         dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
 527         dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 528         dma_tx_sconfig.dst_maxburst = 1;
 529         dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
 530         ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
 531
 532         if (ret) {
 533                 dev_err(sport->port.dev,
 534                                 "DMA slave config failed, err = %d\n", ret);
 535                 return ret;
 536         }
 537
 538         return 0;
 539 }
 540
 541 static bool lpuart_is_32(struct lpuart_port *sport)
 542 {
 543         return sport->port.iotype == UPIO_MEM32 ||
 544                sport->port.iotype ==  UPIO_MEM32BE;
 545 }
 546
 547 static void lpuart_flush_buffer(struct uart_port *port)
 548 {
 549         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 550         struct dma_chan *chan = sport->dma_tx_chan;
 551         u32 val;
 552
 553         if (sport->lpuart_dma_tx_use) {
 554                 if (sport->dma_tx_in_progress) {
 555                         dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0],
 556                                 sport->dma_tx_nents, DMA_TO_DEVICE);
 557                         sport->dma_tx_in_progress = false;
 558                 }
 559                 dmaengine_terminate_all(chan);
 560         }
 561
 562         if (lpuart_is_32(sport)) {
 563                 val = lpuart32_read(&sport->port, UARTFIFO);
 564                 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
 565                 lpuart32_write(&sport->port, val, UARTFIFO);
 566         } else {
 567                 val = readb(sport->port.membase + UARTCFIFO);
 568                 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
 569                 writeb(val, sport->port.membase + UARTCFIFO);
 570         }
 571 }
 572
 573 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset,
 574                                 u8 bit)
 575 {
 576         while (!(readb(port->membase + offset) & bit))
 577                 cpu_relax();
 578 }
 579
 580 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset,
 581                                   u32 bit)
 582 {
 583         while (!(lpuart32_read(port, offset) & bit))
 584                 cpu_relax();
 585 }
 586
 587 #if defined(CONFIG_CONSOLE_POLL)
 588
 589 static int lpuart_poll_init(struct uart_port *port)
 590 {
 591         struct lpuart_port *sport = container_of(port,
 592                                         struct lpuart_port, port);
 593         unsigned long flags;
 594         unsigned char temp;
 595
 596         sport->port.fifosize = 0;
 597
 598         spin_lock_irqsave(&sport->port.lock, flags);
 599         /* Disable Rx & Tx */
 600         writeb(0, sport->port.membase + UARTCR2);
 601
 602         temp = readb(sport->port.membase + UARTPFIFO);
 603         /* Enable Rx and Tx FIFO */
 604         writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
 605                         sport->port.membase + UARTPFIFO);
 606
 607         /* flush Tx and Rx FIFO */
 608         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
 609                         sport->port.membase + UARTCFIFO);
 610
 611         /* explicitly clear RDRF */
 612         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
 613                 readb(sport->port.membase + UARTDR);
 614                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
 615         }
 616
 617         writeb(0, sport->port.membase + UARTTWFIFO);
 618         writeb(1, sport->port.membase + UARTRWFIFO);
 619
 620         /* Enable Rx and Tx */
 621         writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
 622         spin_unlock_irqrestore(&sport->port.lock, flags);
 623
 624         return 0;
 625 }
 626
 627 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
 628 {
 629         /* drain */
 630         lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
 631         writeb(c, port->membase + UARTDR);
 632 }
 633
 634 static int lpuart_poll_get_char(struct uart_port *port)
 635 {
 636         if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
 637                 return NO_POLL_CHAR;
 638
 639         return readb(port->membase + UARTDR);
 640 }
 641
 642 static int lpuart32_poll_init(struct uart_port *port)
 643 {
 644         unsigned long flags;
 645         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 646         u32 temp;
 647
 648         sport->port.fifosize = 0;
 649
 650         spin_lock_irqsave(&sport->port.lock, flags);
 651
 652         /* Disable Rx & Tx */
 653         lpuart32_write(&sport->port, 0, UARTCTRL);
 654
 655         temp = lpuart32_read(&sport->port, UARTFIFO);
 656
 657         /* Enable Rx and Tx FIFO */
 658         lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
 659
 660         /* flush Tx and Rx FIFO */
 661         lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO);
 662
 663         /* explicitly clear RDRF */
 664         if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
 665                 lpuart32_read(&sport->port, UARTDATA);
 666                 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO);
 667         }
 668
 669         /* Enable Rx and Tx */
 670         lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL);
 671         spin_unlock_irqrestore(&sport->port.lock, flags);
 672
 673         return 0;
 674 }
 675
 676 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
 677 {
 678         lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
 679         lpuart32_write(port, c, UARTDATA);
 680 }
 681
 682 static int lpuart32_poll_get_char(struct uart_port *port)
 683 {
 684         if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF))
 685                 return NO_POLL_CHAR;
 686
 687         return lpuart32_read(port, UARTDATA);
 688 }
 689 #endif
 690
 691 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
 692 {
 693         struct circ_buf *xmit = &sport->port.state->xmit;
 694
 695         if (sport->port.x_char) {
 696                 writeb(sport->port.x_char, sport->port.membase + UARTDR);
 697                 sport->port.icount.tx++;
 698                 sport->port.x_char = 0;
 699                 return;
 700         }
 701
 702         if (lpuart_stopped_or_empty(&sport->port)) {
 703                 lpuart_stop_tx(&sport->port);
 704                 return;
 705         }
 706
 707         while (!uart_circ_empty(xmit) &&
 708                 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
 709                 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
 710                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 711                 sport->port.icount.tx++;
 712         }
 713
 714         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 715                 uart_write_wakeup(&sport->port);
 716
 717         if (uart_circ_empty(xmit))
 718                 lpuart_stop_tx(&sport->port);
 719 }
 720
 721 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
 722 {
 723         struct circ_buf *xmit = &sport->port.state->xmit;
 724         unsigned long txcnt;
 725
 726         if (sport->port.x_char) {
 727                 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
 728                 sport->port.icount.tx++;
 729                 sport->port.x_char = 0;
 730                 return;
 731         }
 732
 733         if (lpuart_stopped_or_empty(&sport->port)) {
 734                 lpuart32_stop_tx(&sport->port);
 735                 return;
 736         }
 737
 738         txcnt = lpuart32_read(&sport->port, UARTWATER);
 739         txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 740         txcnt &= UARTWATER_COUNT_MASK;
 741         while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
 742                 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
 743                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 744                 sport->port.icount.tx++;
 745                 txcnt = lpuart32_read(&sport->port, UARTWATER);
 746                 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 747                 txcnt &= UARTWATER_COUNT_MASK;
 748         }
 749
 750         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 751                 uart_write_wakeup(&sport->port);
 752
 753         if (uart_circ_empty(xmit))
 754                 lpuart32_stop_tx(&sport->port);
 755 }
 756
 757 static void lpuart_start_tx(struct uart_port *port)
 758 {
 759         struct lpuart_port *sport = container_of(port,
 760                         struct lpuart_port, port);
 761         unsigned char temp;
 762
 763         temp = readb(port->membase + UARTCR2);
 764         writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
 765
 766         if (sport->lpuart_dma_tx_use) {
 767                 if (!lpuart_stopped_or_empty(port))
 768                         lpuart_dma_tx(sport);
 769         } else {
 770                 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
 771                         lpuart_transmit_buffer(sport);
 772         }
 773 }
 774
 775 static void lpuart32_start_tx(struct uart_port *port)
 776 {
 777         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 778         unsigned long temp;
 779
 780         if (sport->lpuart_dma_tx_use) {
 781                 if (!lpuart_stopped_or_empty(port))
 782                         lpuart_dma_tx(sport);
 783         } else {
 784                 temp = lpuart32_read(port, UARTCTRL);
 785                 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
 786
 787                 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
 788                         lpuart32_transmit_buffer(sport);
 789         }
 790 }
 791
 792 /* return TIOCSER_TEMT when transmitter is not busy */
 793 static unsigned int lpuart_tx_empty(struct uart_port *port)
 794 {
 795         struct lpuart_port *sport = container_of(port,
 796                         struct lpuart_port, port);
 797         unsigned char sr1 = readb(port->membase + UARTSR1);
 798         unsigned char sfifo = readb(port->membase + UARTSFIFO);
 799
 800         if (sport->dma_tx_in_progress)
 801                 return 0;
 802
 803         if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
 804                 return TIOCSER_TEMT;
 805
 806         return 0;
 807 }
 808
 809 static unsigned int lpuart32_tx_empty(struct uart_port *port)
 810 {
 811         struct lpuart_port *sport = container_of(port,
 812                         struct lpuart_port, port);
 813         unsigned long stat = lpuart32_read(port, UARTSTAT);
 814         unsigned long sfifo = lpuart32_read(port, UARTFIFO);
 815
 816         if (sport->dma_tx_in_progress)
 817                 return 0;
 818
 819         if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT)
 820                 return TIOCSER_TEMT;
 821
 822         return 0;
 823 }
 824
 825 static void lpuart_txint(struct lpuart_port *sport)
 826 {
 827         spin_lock(&sport->port.lock);
 828         lpuart_transmit_buffer(sport);
 829         spin_unlock(&sport->port.lock);
 830 }
 831
 832 static void lpuart_rxint(struct lpuart_port *sport)
 833 {
 834         unsigned int flg, ignored = 0, overrun = 0;
 835         struct tty_port *port = &sport->port.state->port;
 836         unsigned char rx, sr;
 837
 838         spin_lock(&sport->port.lock);
 839
 840         while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
 841                 flg = TTY_NORMAL;
 842                 sport->port.icount.rx++;
 843                 /*
 844                  * to clear the FE, OR, NF, FE, PE flags,
 845                  * read SR1 then read DR
 846                  */
 847                 sr = readb(sport->port.membase + UARTSR1);
 848                 rx = readb(sport->port.membase + UARTDR);
 849
 850                 if (uart_prepare_sysrq_char(&sport->port, rx))
 851                         continue;
 852
 853                 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
 854                         if (sr & UARTSR1_PE)
 855                                 sport->port.icount.parity++;
 856                         else if (sr & UARTSR1_FE)
 857                                 sport->port.icount.frame++;
 858
 859                         if (sr & UARTSR1_OR)
 860                                 overrun++;
 861
 862                         if (sr & sport->port.ignore_status_mask) {
 863                                 if (++ignored > 100)
 864                                         goto out;
 865                                 continue;
 866                         }
 867
 868                         sr &= sport->port.read_status_mask;
 869
 870                         if (sr & UARTSR1_PE)
 871                                 flg = TTY_PARITY;
 872                         else if (sr & UARTSR1_FE)
 873                                 flg = TTY_FRAME;
 874
 875                         if (sr & UARTSR1_OR)
 876                                 flg = TTY_OVERRUN;
 877
 878                         sport->port.sysrq = 0;
 879                 }
 880
 881                 tty_insert_flip_char(port, rx, flg);
 882         }
 883
 884 out:
 885         if (overrun) {
 886                 sport->port.icount.overrun += overrun;
 887
 888                 /*
 889                  * Overruns cause FIFO pointers to become missaligned.
 890                  * Flushing the receive FIFO reinitializes the pointers.
 891                  */
 892                 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
 893                 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
 894         }
 895
 896         uart_unlock_and_check_sysrq(&sport->port);
 897
 898         tty_flip_buffer_push(port);
 899 }
 900
 901 static void lpuart32_txint(struct lpuart_port *sport)
 902 {
 903         spin_lock(&sport->port.lock);
 904         lpuart32_transmit_buffer(sport);
 905         spin_unlock(&sport->port.lock);
 906 }
 907
 908 static void lpuart32_rxint(struct lpuart_port *sport)
 909 {
 910         unsigned int flg, ignored = 0;
 911         struct tty_port *port = &sport->port.state->port;
 912         unsigned long rx, sr;
 913         bool is_break;
 914
 915         spin_lock(&sport->port.lock);
 916
 917         while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
 918                 flg = TTY_NORMAL;
 919                 sport->port.icount.rx++;
 920                 /*
 921                  * to clear the FE, OR, NF, FE, PE flags,
 922                  * read STAT then read DATA reg
 923                  */
 924                 sr = lpuart32_read(&sport->port, UARTSTAT);
 925                 rx = lpuart32_read(&sport->port, UARTDATA);
 926                 rx &= UARTDATA_MASK;
 927
 928                 /*
 929                  * The LPUART can't distinguish between a break and a framing error,
 930                  * thus we assume it is a break if the received data is zero.
 931                  */
 932                 is_break = (sr & UARTSTAT_FE) && !rx;
 933
 934                 if (is_break && uart_handle_break(&sport->port))
 935                         continue;
 936
 937                 if (uart_prepare_sysrq_char(&sport->port, rx))
 938                         continue;
 939
 940                 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
 941                         if (sr & UARTSTAT_PE) {
 942                                 if (is_break)
 943                                         sport->port.icount.brk++;
 944                                 else
 945                                         sport->port.icount.parity++;
 946                         } else if (sr & UARTSTAT_FE) {
 947                                 sport->port.icount.frame++;
 948                         }
 949
 950                         if (sr & UARTSTAT_OR)
 951                                 sport->port.icount.overrun++;
 952
 953                         if (sr & sport->port.ignore_status_mask) {
 954                                 if (++ignored > 100)
 955                                         goto out;
 956                                 continue;
 957                         }
 958
 959                         sr &= sport->port.read_status_mask;
 960
 961                         if (sr & UARTSTAT_PE) {
 962                                 if (is_break)
 963                                         flg = TTY_BREAK;
 964                                 else
 965                                         flg = TTY_PARITY;
 966                         } else if (sr & UARTSTAT_FE) {
 967                                 flg = TTY_FRAME;
 968                         }
 969
 970                         if (sr & UARTSTAT_OR)
 971                                 flg = TTY_OVERRUN;
 972                 }
 973
 974                 tty_insert_flip_char(port, rx, flg);
 975         }
 976
 977 out:
 978         uart_unlock_and_check_sysrq(&sport->port);
 979
 980         tty_flip_buffer_push(port);
 981 }
 982
 983 static irqreturn_t lpuart_int(int irq, void *dev_id)
 984 {
 985         struct lpuart_port *sport = dev_id;
 986         unsigned char sts;
 987
 988         sts = readb(sport->port.membase + UARTSR1);
 989
 990         /* SysRq, using dma, check for linebreak by framing err. */
 991         if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) {
 992                 readb(sport->port.membase + UARTDR);
 993                 uart_handle_break(&sport->port);
 994                 /* linebreak produces some garbage, removing it */
 995                 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
 996                 return IRQ_HANDLED;
 997         }
 998
 999         if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use)
1000                 lpuart_rxint(sport);
1001
1002         if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use)
1003                 lpuart_txint(sport);
1004
1005         return IRQ_HANDLED;
1006 }
1007
1008 static irqreturn_t lpuart32_int(int irq, void *dev_id)
1009 {
1010         struct lpuart_port *sport = dev_id;
1011         unsigned long sts, rxcount;
1012
1013         sts = lpuart32_read(&sport->port, UARTSTAT);
1014         rxcount = lpuart32_read(&sport->port, UARTWATER);
1015         rxcount = rxcount >> UARTWATER_RXCNT_OFF;
1016
1017         if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use)
1018                 lpuart32_rxint(sport);
1019
1020         if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
1021                 lpuart32_txint(sport);
1022
1023         lpuart32_write(&sport->port, sts, UARTSTAT);
1024         return IRQ_HANDLED;
1025 }
1026
1027
1028 static inline void lpuart_handle_sysrq_chars(struct uart_port *port,
1029                                              unsigned char *p, int count)
1030 {
1031         while (count--) {
1032                 if (*p && uart_handle_sysrq_char(port, *p))
1033                         return;
1034                 p++;
1035         }
1036 }
1037
1038 static void lpuart_handle_sysrq(struct lpuart_port *sport)
1039 {
1040         struct circ_buf *ring = &sport->rx_ring;
1041         int count;
1042
1043         if (ring->head < ring->tail) {
1044                 count = sport->rx_sgl.length - ring->tail;
1045                 lpuart_handle_sysrq_chars(&sport->port,
1046                                           ring->buf + ring->tail, count);
1047                 ring->tail = 0;
1048         }
1049
1050         if (ring->head > ring->tail) {
1051                 count = ring->head - ring->tail;
1052                 lpuart_handle_sysrq_chars(&sport->port,
1053                                           ring->buf + ring->tail, count);
1054                 ring->tail = ring->head;
1055         }
1056 }
1057
1058 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
1059 {
1060         struct tty_port *port = &sport->port.state->port;
1061         struct dma_tx_state state;
1062         enum dma_status dmastat;
1063         struct dma_chan *chan = sport->dma_rx_chan;
1064         struct circ_buf *ring = &sport->rx_ring;
1065         unsigned long flags;
1066         int count = 0;
1067
1068         if (lpuart_is_32(sport)) {
1069                 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
1070
1071                 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) {
1072                         /* Read DR to clear the error flags */
1073                         lpuart32_read(&sport->port, UARTDATA);
1074
1075                         if (sr & UARTSTAT_PE)
1076                                 sport->port.icount.parity++;
1077                         else if (sr & UARTSTAT_FE)
1078                                 sport->port.icount.frame++;
1079                 }
1080         } else {
1081                 unsigned char sr = readb(sport->port.membase + UARTSR1);
1082
1083                 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
1084                         unsigned char cr2;
1085
1086                         /* Disable receiver during this operation... */
1087                         cr2 = readb(sport->port.membase + UARTCR2);
1088                         cr2 &= ~UARTCR2_RE;
1089                         writeb(cr2, sport->port.membase + UARTCR2);
1090
1091                         /* Read DR to clear the error flags */
1092                         readb(sport->port.membase + UARTDR);
1093
1094                         if (sr & UARTSR1_PE)
1095                                 sport->port.icount.parity++;
1096                         else if (sr & UARTSR1_FE)
1097                                 sport->port.icount.frame++;
1098                         /*
1099                          * At this point parity/framing error is
1100                          * cleared However, since the DMA already read
1101                          * the data register and we had to read it
1102                          * again after reading the status register to
1103                          * properly clear the flags, the FIFO actually
1104                          * underflowed... This requires a clearing of
1105                          * the FIFO...
1106                          */
1107                         if (readb(sport->port.membase + UARTSFIFO) &
1108                             UARTSFIFO_RXUF) {
1109                                 writeb(UARTSFIFO_RXUF,
1110                                        sport->port.membase + UARTSFIFO);
1111                                 writeb(UARTCFIFO_RXFLUSH,
1112                                        sport->port.membase + UARTCFIFO);
1113                         }
1114
1115                         cr2 |= UARTCR2_RE;
1116                         writeb(cr2, sport->port.membase + UARTCR2);
1117                 }
1118         }
1119
1120         async_tx_ack(sport->dma_rx_desc);
1121
1122         spin_lock_irqsave(&sport->port.lock, flags);
1123
1124         dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
1125         if (dmastat == DMA_ERROR) {
1126                 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1127                 spin_unlock_irqrestore(&sport->port.lock, flags);
1128                 return;
1129         }
1130
1131         /* CPU claims ownership of RX DMA buffer */
1132         dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1,
1133                             DMA_FROM_DEVICE);
1134
1135         /*
1136          * ring->head points to the end of data already written by the DMA.
1137          * ring->tail points to the beginning of data to be read by the
1138          * framework.
1139          * The current transfer size should not be larger than the dma buffer
1140          * length.
1141          */
1142         ring->head = sport->rx_sgl.length - state.residue;
1143         BUG_ON(ring->head > sport->rx_sgl.length);
1144
1145         /*
1146          * Silent handling of keys pressed in the sysrq timeframe
1147          */
1148         if (sport->port.sysrq) {
1149                 lpuart_handle_sysrq(sport);
1150                 goto exit;
1151         }
1152
1153         /*
1154          * At this point ring->head may point to the first byte right after the
1155          * last byte of the dma buffer:
1156          * 0 <= ring->head <= sport->rx_sgl.length
1157          *
1158          * However ring->tail must always points inside the dma buffer:
1159          * 0 <= ring->tail <= sport->rx_sgl.length - 1
1160          *
1161          * Since we use a ring buffer, we have to handle the case
1162          * where head is lower than tail. In such a case, we first read from
1163          * tail to the end of the buffer then reset tail.
1164          */
1165         if (ring->head < ring->tail) {
1166                 count = sport->rx_sgl.length - ring->tail;
1167
1168                 tty_insert_flip_string(port, ring->buf + ring->tail, count);
1169                 ring->tail = 0;
1170                 sport->port.icount.rx += count;
1171         }
1172
1173         /* Finally we read data from tail to head */
1174         if (ring->tail < ring->head) {
1175                 count = ring->head - ring->tail;
1176                 tty_insert_flip_string(port, ring->buf + ring->tail, count);
1177                 /* Wrap ring->head if needed */
1178                 if (ring->head >= sport->rx_sgl.length)
1179                         ring->head = 0;
1180                 ring->tail = ring->head;
1181                 sport->port.icount.rx += count;
1182         }
1183
1184 exit:
1185         dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1,
1186                                DMA_FROM_DEVICE);
1187
1188         spin_unlock_irqrestore(&sport->port.lock, flags);
1189
1190         tty_flip_buffer_push(port);
1191         mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
1192 }
1193
1194 static void lpuart_dma_rx_complete(void *arg)
1195 {
1196         struct lpuart_port *sport = arg;
1197
1198         lpuart_copy_rx_to_tty(sport);
1199 }
1200
1201 static void lpuart_timer_func(struct timer_list *t)
1202 {
1203         struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
1204
1205         lpuart_copy_rx_to_tty(sport);
1206 }
1207
1208 static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
1209 {
1210         struct dma_slave_config dma_rx_sconfig = {};
1211         struct circ_buf *ring = &sport->rx_ring;
1212         int ret, nent;
1213         int bits, baud;
1214         struct tty_port *port = &sport->port.state->port;
1215         struct tty_struct *tty = port->tty;
1216         struct ktermios *termios = &tty->termios;
1217         struct dma_chan *chan = sport->dma_rx_chan;
1218
1219         baud = tty_get_baud_rate(tty);
1220
1221         bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10;
1222         if (termios->c_cflag & PARENB)
1223                 bits++;
1224
1225         /*
1226          * Calculate length of one DMA buffer size to keep latency below
1227          * 10ms at any baud rate.
1228          */
1229         sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud /  bits / 1000) * 2;
1230         sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
1231         if (sport->rx_dma_rng_buf_len < 16)
1232                 sport->rx_dma_rng_buf_len = 16;
1233
1234         ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1235         if (!ring->buf)
1236                 return -ENOMEM;
1237
1238         sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1239         nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1,
1240                           DMA_FROM_DEVICE);
1241
1242         if (!nent) {
1243                 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1244                 return -EINVAL;
1245         }
1246
1247         dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
1248         dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1249         dma_rx_sconfig.src_maxburst = 1;
1250         dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1251         ret = dmaengine_slave_config(chan, &dma_rx_sconfig);
1252
1253         if (ret < 0) {
1254                 dev_err(sport->port.dev,
1255                                 "DMA Rx slave config failed, err = %d\n", ret);
1256                 return ret;
1257         }
1258
1259         sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan,
1260                                  sg_dma_address(&sport->rx_sgl),
1261                                  sport->rx_sgl.length,
1262                                  sport->rx_sgl.length / 2,
1263                                  DMA_DEV_TO_MEM,
1264                                  DMA_PREP_INTERRUPT);
1265         if (!sport->dma_rx_desc) {
1266                 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1267                 return -EFAULT;
1268         }
1269
1270         sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1271         sport->dma_rx_desc->callback_param = sport;
1272         sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1273         dma_async_issue_pending(chan);
1274
1275         if (lpuart_is_32(sport)) {
1276                 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
1277
1278                 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
1279         } else {
1280                 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1281                        sport->port.membase + UARTCR5);
1282         }
1283
1284         return 0;
1285 }
1286
1287 static void lpuart_dma_rx_free(struct uart_port *port)
1288 {
1289         struct lpuart_port *sport = container_of(port,
1290                                         struct lpuart_port, port);
1291         struct dma_chan *chan = sport->dma_rx_chan;
1292
1293         dmaengine_terminate_all(chan);
1294         dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1295         kfree(sport->rx_ring.buf);
1296         sport->rx_ring.tail = 0;
1297         sport->rx_ring.head = 0;
1298         sport->dma_rx_desc = NULL;
1299         sport->dma_rx_cookie = -EINVAL;
1300 }
1301
1302 static int lpuart_config_rs485(struct uart_port *port,
1303                         struct serial_rs485 *rs485)
1304 {
1305         struct lpuart_port *sport = container_of(port,
1306                         struct lpuart_port, port);
1307
1308         u8 modem = readb(sport->port.membase + UARTMODEM) &
1309                 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1310         writeb(modem, sport->port.membase + UARTMODEM);
1311
1312         /* clear unsupported configurations */
1313         rs485->delay_rts_before_send = 0;
1314         rs485->delay_rts_after_send = 0;
1315         rs485->flags &= ~SER_RS485_RX_DURING_TX;
1316
1317         if (rs485->flags & SER_RS485_ENABLED) {
1318                 /* Enable auto RS-485 RTS mode */
1319                 modem |= UARTMODEM_TXRTSE;
1320
1321                 /*
1322                  * RTS needs to be logic HIGH either during transfer _or_ after
1323                  * transfer, other variants are not supported by the hardware.
1324                  */
1325
1326                 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1327                                 SER_RS485_RTS_AFTER_SEND)))
1328                         rs485->flags |= SER_RS485_RTS_ON_SEND;
1329
1330                 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1331                                 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1332                         rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1333
1334                 /*
1335                  * The hardware defaults to RTS logic HIGH while transfer.
1336                  * Switch polarity in case RTS shall be logic HIGH
1337                  * after transfer.
1338                  * Note: UART is assumed to be active high.
1339                  */
1340                 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1341                         modem &= ~UARTMODEM_TXRTSPOL;
1342                 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1343                         modem |= UARTMODEM_TXRTSPOL;
1344         }
1345
1346         /* Store the new configuration */
1347         sport->port.rs485 = *rs485;
1348
1349         writeb(modem, sport->port.membase + UARTMODEM);
1350         return 0;
1351 }
1352
1353 static int lpuart32_config_rs485(struct uart_port *port,
1354                         struct serial_rs485 *rs485)
1355 {
1356         struct lpuart_port *sport = container_of(port,
1357                         struct lpuart_port, port);
1358
1359         unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)
1360                                 & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1361         lpuart32_write(&sport->port, modem, UARTMODIR);
1362
1363         /* clear unsupported configurations */
1364         rs485->delay_rts_before_send = 0;
1365         rs485->delay_rts_after_send = 0;
1366         rs485->flags &= ~SER_RS485_RX_DURING_TX;
1367
1368         if (rs485->flags & SER_RS485_ENABLED) {
1369                 /* Enable auto RS-485 RTS mode */
1370                 modem |= UARTMODEM_TXRTSE;
1371
1372                 /*
1373                  * RTS needs to be logic HIGH either during transfer _or_ after
1374                  * transfer, other variants are not supported by the hardware.
1375                  */
1376
1377                 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1378                                 SER_RS485_RTS_AFTER_SEND)))
1379                         rs485->flags |= SER_RS485_RTS_ON_SEND;
1380
1381                 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1382                                 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1383                         rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1384
1385                 /*
1386                  * The hardware defaults to RTS logic HIGH while transfer.
1387                  * Switch polarity in case RTS shall be logic HIGH
1388                  * after transfer.
1389                  * Note: UART is assumed to be active high.
1390                  */
1391                 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1392                         modem &= ~UARTMODEM_TXRTSPOL;
1393                 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1394                         modem |= UARTMODEM_TXRTSPOL;
1395         }
1396
1397         /* Store the new configuration */
1398         sport->port.rs485 = *rs485;
1399
1400         lpuart32_write(&sport->port, modem, UARTMODIR);
1401         return 0;
1402 }
1403
1404 static unsigned int lpuart_get_mctrl(struct uart_port *port)
1405 {
1406         unsigned int mctrl = 0;
1407         u8 reg;
1408
1409         reg = readb(port->membase + UARTCR1);
1410         if (reg & UARTCR1_LOOPS)
1411                 mctrl |= TIOCM_LOOP;
1412
1413         return mctrl;
1414 }
1415
1416 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1417 {
1418         unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
1419         u32 reg;
1420
1421         reg = lpuart32_read(port, UARTCTRL);
1422         if (reg & UARTCTRL_LOOPS)
1423                 mctrl |= TIOCM_LOOP;
1424
1425         return mctrl;
1426 }
1427
1428 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1429 {
1430         u8 reg;
1431
1432         reg = readb(port->membase + UARTCR1);
1433
1434         /* for internal loopback we need LOOPS=1 and RSRC=0 */
1435         reg &= ~(UARTCR1_LOOPS | UARTCR1_RSRC);
1436         if (mctrl & TIOCM_LOOP)
1437                 reg |= UARTCR1_LOOPS;
1438
1439         writeb(reg, port->membase + UARTCR1);
1440 }
1441
1442 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1443 {
1444         u32 reg;
1445
1446         reg = lpuart32_read(port, UARTCTRL);
1447
1448         /* for internal loopback we need LOOPS=1 and RSRC=0 */
1449         reg &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC);
1450         if (mctrl & TIOCM_LOOP)
1451                 reg |= UARTCTRL_LOOPS;
1452
1453         lpuart32_write(port, reg, UARTCTRL);
1454 }
1455
1456 static void lpuart_break_ctl(struct uart_port *port, int break_state)
1457 {
1458         unsigned char temp;
1459
1460         temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1461
1462         if (break_state != 0)
1463                 temp |= UARTCR2_SBK;
1464
1465         writeb(temp, port->membase + UARTCR2);
1466 }
1467
1468 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1469 {
1470         unsigned long temp;
1471
1472         temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK;
1473
1474         if (break_state != 0)
1475                 temp |= UARTCTRL_SBK;
1476
1477         lpuart32_write(port, temp, UARTCTRL);
1478 }
1479
1480 static void lpuart_setup_watermark(struct lpuart_port *sport)
1481 {
1482         unsigned char val, cr2;
1483         unsigned char cr2_saved;
1484
1485         cr2 = readb(sport->port.membase + UARTCR2);
1486         cr2_saved = cr2;
1487         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1488                         UARTCR2_RIE | UARTCR2_RE);
1489         writeb(cr2, sport->port.membase + UARTCR2);
1490
1491         val = readb(sport->port.membase + UARTPFIFO);
1492         writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1493                         sport->port.membase + UARTPFIFO);
1494
1495         /* flush Tx and Rx FIFO */
1496         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1497                         sport->port.membase + UARTCFIFO);
1498
1499         /* explicitly clear RDRF */
1500         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1501                 readb(sport->port.membase + UARTDR);
1502                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1503         }
1504
1505         writeb(0, sport->port.membase + UARTTWFIFO);
1506         writeb(1, sport->port.membase + UARTRWFIFO);
1507
1508         /* Restore cr2 */
1509         writeb(cr2_saved, sport->port.membase + UARTCR2);
1510 }
1511
1512 static void lpuart_setup_watermark_enable(struct lpuart_port *sport)
1513 {
1514         unsigned char cr2;
1515
1516         lpuart_setup_watermark(sport);
1517
1518         cr2 = readb(sport->port.membase + UARTCR2);
1519         cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE;
1520         writeb(cr2, sport->port.membase + UARTCR2);
1521 }
1522
1523 static void lpuart32_setup_watermark(struct lpuart_port *sport)
1524 {
1525         unsigned long val, ctrl;
1526         unsigned long ctrl_saved;
1527
1528         ctrl = lpuart32_read(&sport->port, UARTCTRL);
1529         ctrl_saved = ctrl;
1530         ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1531                         UARTCTRL_RIE | UARTCTRL_RE);
1532         lpuart32_write(&sport->port, ctrl, UARTCTRL);
1533
1534         /* enable FIFO mode */
1535         val = lpuart32_read(&sport->port, UARTFIFO);
1536         val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1537         val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1538         lpuart32_write(&sport->port, val, UARTFIFO);
1539
1540         /* set the watermark */
1541         val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
1542         lpuart32_write(&sport->port, val, UARTWATER);
1543
1544         /* Restore cr2 */
1545         lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1546 }
1547
1548 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
1549 {
1550         u32 temp;
1551
1552         lpuart32_setup_watermark(sport);
1553
1554         temp = lpuart32_read(&sport->port, UARTCTRL);
1555         temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE;
1556         lpuart32_write(&sport->port, temp, UARTCTRL);
1557 }
1558
1559 static void rx_dma_timer_init(struct lpuart_port *sport)
1560 {
1561         timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1562         sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1563         add_timer(&sport->lpuart_timer);
1564 }
1565
1566 static void lpuart_request_dma(struct lpuart_port *sport)
1567 {
1568         sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx");
1569         if (IS_ERR(sport->dma_tx_chan)) {
1570                 dev_dbg_once(sport->port.dev,
1571                              "DMA tx channel request failed, operating without tx DMA (%ld)\n",
1572                              PTR_ERR(sport->dma_tx_chan));
1573                 sport->dma_tx_chan = NULL;
1574         }
1575
1576         sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx");
1577         if (IS_ERR(sport->dma_rx_chan)) {
1578                 dev_dbg_once(sport->port.dev,
1579                              "DMA rx channel request failed, operating without rx DMA (%ld)\n",
1580                              PTR_ERR(sport->dma_rx_chan));
1581                 sport->dma_rx_chan = NULL;
1582         }
1583 }
1584
1585 static void lpuart_tx_dma_startup(struct lpuart_port *sport)
1586 {
1587         u32 uartbaud;
1588         int ret;
1589
1590         if (uart_console(&sport->port))
1591                 goto err;
1592
1593         if (!sport->dma_tx_chan)
1594                 goto err;
1595
1596         ret = lpuart_dma_tx_request(&sport->port);
1597         if (ret)
1598                 goto err;
1599
1600         init_waitqueue_head(&sport->dma_wait);
1601         sport->lpuart_dma_tx_use = true;
1602         if (lpuart_is_32(sport)) {
1603                 uartbaud = lpuart32_read(&sport->port, UARTBAUD);
1604                 lpuart32_write(&sport->port,
1605                                uartbaud | UARTBAUD_TDMAE, UARTBAUD);
1606         } else {
1607                 writeb(readb(sport->port.membase + UARTCR5) |
1608                        UARTCR5_TDMAS, sport->port.membase + UARTCR5);
1609         }
1610
1611         return;
1612
1613 err:
1614         sport->lpuart_dma_tx_use = false;
1615 }
1616
1617 static void lpuart_rx_dma_startup(struct lpuart_port *sport)
1618 {
1619         int ret;
1620         unsigned char cr3;
1621
1622         if (uart_console(&sport->port))
1623                 goto err;
1624
1625         if (!sport->dma_rx_chan)
1626                 goto err;
1627
1628         ret = lpuart_start_rx_dma(sport);
1629         if (ret)
1630                 goto err;
1631
1632         /* set Rx DMA timeout */
1633         sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1634         if (!sport->dma_rx_timeout)
1635                 sport->dma_rx_timeout = 1;
1636
1637         sport->lpuart_dma_rx_use = true;
1638         rx_dma_timer_init(sport);
1639
1640         if (sport->port.has_sysrq && !lpuart_is_32(sport)) {
1641                 cr3 = readb(sport->port.membase + UARTCR3);
1642                 cr3 |= UARTCR3_FEIE;
1643                 writeb(cr3, sport->port.membase + UARTCR3);
1644         }
1645
1646         return;
1647
1648 err:
1649         sport->lpuart_dma_rx_use = false;
1650 }
1651
1652 static int lpuart_startup(struct uart_port *port)
1653 {
1654         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1655         unsigned long flags;
1656         unsigned char temp;
1657
1658         /* determine FIFO size and enable FIFO mode */
1659         temp = readb(sport->port.membase + UARTPFIFO);
1660
1661         sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
1662                                             UARTPFIFO_FIFOSIZE_MASK);
1663         sport->port.fifosize = sport->txfifo_size;
1664
1665         sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
1666                                             UARTPFIFO_FIFOSIZE_MASK);
1667
1668         lpuart_request_dma(sport);
1669
1670         spin_lock_irqsave(&sport->port.lock, flags);
1671
1672         lpuart_setup_watermark_enable(sport);
1673
1674         lpuart_rx_dma_startup(sport);
1675         lpuart_tx_dma_startup(sport);
1676
1677         spin_unlock_irqrestore(&sport->port.lock, flags);
1678
1679         return 0;
1680 }
1681
1682 static void lpuart32_configure(struct lpuart_port *sport)
1683 {
1684         unsigned long temp;
1685
1686         if (sport->lpuart_dma_rx_use) {
1687                 /* RXWATER must be 0 */
1688                 temp = lpuart32_read(&sport->port, UARTWATER);
1689                 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF);
1690                 lpuart32_write(&sport->port, temp, UARTWATER);
1691         }
1692         temp = lpuart32_read(&sport->port, UARTCTRL);
1693         if (!sport->lpuart_dma_rx_use)
1694                 temp |= UARTCTRL_RIE;
1695         if (!sport->lpuart_dma_tx_use)
1696                 temp |= UARTCTRL_TIE;
1697         lpuart32_write(&sport->port, temp, UARTCTRL);
1698 }
1699
1700 static int lpuart32_startup(struct uart_port *port)
1701 {
1702         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1703         unsigned long flags;
1704         unsigned long temp;
1705
1706         /* determine FIFO size */
1707         temp = lpuart32_read(&sport->port, UARTFIFO);
1708
1709         sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
1710                                             UARTFIFO_FIFOSIZE_MASK);
1711         sport->port.fifosize = sport->txfifo_size;
1712
1713         sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
1714                                             UARTFIFO_FIFOSIZE_MASK);
1715
1716         /*
1717          * The LS1021A and LS1028A have a fixed FIFO depth of 16 words.
1718          * Although they support the RX/TXSIZE fields, their encoding is
1719          * different. Eg the reference manual states 0b101 is 16 words.
1720          */
1721         if (is_layerscape_lpuart(sport)) {
1722                 sport->rxfifo_size = 16;
1723                 sport->txfifo_size = 16;
1724                 sport->port.fifosize = sport->txfifo_size;
1725         }
1726
1727         lpuart_request_dma(sport);
1728
1729         spin_lock_irqsave(&sport->port.lock, flags);
1730
1731         lpuart32_setup_watermark_enable(sport);
1732
1733         lpuart_rx_dma_startup(sport);
1734         lpuart_tx_dma_startup(sport);
1735
1736         lpuart32_configure(sport);
1737
1738         spin_unlock_irqrestore(&sport->port.lock, flags);
1739         return 0;
1740 }
1741
1742 static void lpuart_dma_shutdown(struct lpuart_port *sport)
1743 {
1744         if (sport->lpuart_dma_rx_use) {
1745                 del_timer_sync(&sport->lpuart_timer);
1746                 lpuart_dma_rx_free(&sport->port);
1747         }
1748
1749         if (sport->lpuart_dma_tx_use) {
1750                 if (wait_event_interruptible(sport->dma_wait,
1751                         !sport->dma_tx_in_progress) != false) {
1752                         sport->dma_tx_in_progress = false;
1753                         dmaengine_terminate_all(sport->dma_tx_chan);
1754                 }
1755         }
1756
1757         if (sport->dma_tx_chan)
1758                 dma_release_channel(sport->dma_tx_chan);
1759         if (sport->dma_rx_chan)
1760                 dma_release_channel(sport->dma_rx_chan);
1761 }
1762
1763 static void lpuart_shutdown(struct uart_port *port)
1764 {
1765         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1766         unsigned char temp;
1767         unsigned long flags;
1768
1769         spin_lock_irqsave(&port->lock, flags);
1770
1771         /* disable Rx/Tx and interrupts */
1772         temp = readb(port->membase + UARTCR2);
1773         temp &= ~(UARTCR2_TE | UARTCR2_RE |
1774                         UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1775         writeb(temp, port->membase + UARTCR2);
1776
1777         spin_unlock_irqrestore(&port->lock, flags);
1778
1779         lpuart_dma_shutdown(sport);
1780 }
1781
1782 static void lpuart32_shutdown(struct uart_port *port)
1783 {
1784         struct lpuart_port *sport =
1785                 container_of(port, struct lpuart_port, port);
1786         unsigned long temp;
1787         unsigned long flags;
1788
1789         spin_lock_irqsave(&port->lock, flags);
1790
1791         /* disable Rx/Tx and interrupts */
1792         temp = lpuart32_read(port, UARTCTRL);
1793         temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1794                         UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1795         lpuart32_write(port, temp, UARTCTRL);
1796
1797         spin_unlock_irqrestore(&port->lock, flags);
1798
1799         lpuart_dma_shutdown(sport);
1800 }
1801
1802 static void
1803 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1804                    struct ktermios *old)
1805 {
1806         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1807         unsigned long flags;
1808         unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1809         unsigned int  baud;
1810         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1811         unsigned int sbr, brfa;
1812
1813         cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1814         old_cr2 = readb(sport->port.membase + UARTCR2);
1815         cr3 = readb(sport->port.membase + UARTCR3);
1816         cr4 = readb(sport->port.membase + UARTCR4);
1817         bdh = readb(sport->port.membase + UARTBDH);
1818         modem = readb(sport->port.membase + UARTMODEM);
1819         /*
1820          * only support CS8 and CS7, and for CS7 must enable PE.
1821          * supported mode:
1822          *  - (7,e/o,1)
1823          *  - (8,n,1)
1824          *  - (8,m/s,1)
1825          *  - (8,e/o,1)
1826          */
1827         while ((termios->c_cflag & CSIZE) != CS8 &&
1828                 (termios->c_cflag & CSIZE) != CS7) {
1829                 termios->c_cflag &= ~CSIZE;
1830                 termios->c_cflag |= old_csize;
1831                 old_csize = CS8;
1832         }
1833
1834         if ((termios->c_cflag & CSIZE) == CS8 ||
1835                 (termios->c_cflag & CSIZE) == CS7)
1836                 cr1 = old_cr1 & ~UARTCR1_M;
1837
1838         if (termios->c_cflag & CMSPAR) {
1839                 if ((termios->c_cflag & CSIZE) != CS8) {
1840                         termios->c_cflag &= ~CSIZE;
1841                         termios->c_cflag |= CS8;
1842                 }
1843                 cr1 |= UARTCR1_M;
1844         }
1845
1846         /*
1847          * When auto RS-485 RTS mode is enabled,
1848          * hardware flow control need to be disabled.
1849          */
1850         if (sport->port.rs485.flags & SER_RS485_ENABLED)
1851                 termios->c_cflag &= ~CRTSCTS;
1852
1853         if (termios->c_cflag & CRTSCTS)
1854                 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE;
1855         else
1856                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1857
1858         termios->c_cflag &= ~CSTOPB;
1859
1860         /* parity must be enabled when CS7 to match 8-bits format */
1861         if ((termios->c_cflag & CSIZE) == CS7)
1862                 termios->c_cflag |= PARENB;
1863
1864         if (termios->c_cflag & PARENB) {
1865                 if (termios->c_cflag & CMSPAR) {
1866                         cr1 &= ~UARTCR1_PE;
1867                         if (termios->c_cflag & PARODD)
1868                                 cr3 |= UARTCR3_T8;
1869                         else
1870                                 cr3 &= ~UARTCR3_T8;
1871                 } else {
1872                         cr1 |= UARTCR1_PE;
1873                         if ((termios->c_cflag & CSIZE) == CS8)
1874                                 cr1 |= UARTCR1_M;
1875                         if (termios->c_cflag & PARODD)
1876                                 cr1 |= UARTCR1_PT;
1877                         else
1878                                 cr1 &= ~UARTCR1_PT;
1879                 }
1880         } else {
1881                 cr1 &= ~UARTCR1_PE;
1882         }
1883
1884         /* ask the core to calculate the divisor */
1885         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1886
1887         /*
1888          * Need to update the Ring buffer length according to the selected
1889          * baud rate and restart Rx DMA path.
1890          *
1891          * Since timer function acqures sport->port.lock, need to stop before
1892          * acquring same lock because otherwise del_timer_sync() can deadlock.
1893          */
1894         if (old && sport->lpuart_dma_rx_use) {
1895                 del_timer_sync(&sport->lpuart_timer);
1896                 lpuart_dma_rx_free(&sport->port);
1897         }
1898
1899         spin_lock_irqsave(&sport->port.lock, flags);
1900
1901         sport->port.read_status_mask = 0;
1902         if (termios->c_iflag & INPCK)
1903                 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE;
1904         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1905                 sport->port.read_status_mask |= UARTSR1_FE;
1906
1907         /* characters to ignore */
1908         sport->port.ignore_status_mask = 0;
1909         if (termios->c_iflag & IGNPAR)
1910                 sport->port.ignore_status_mask |= UARTSR1_PE;
1911         if (termios->c_iflag & IGNBRK) {
1912                 sport->port.ignore_status_mask |= UARTSR1_FE;
1913                 /*
1914                  * if we're ignoring parity and break indicators,
1915                  * ignore overruns too (for real raw support).
1916                  */
1917                 if (termios->c_iflag & IGNPAR)
1918                         sport->port.ignore_status_mask |= UARTSR1_OR;
1919         }
1920
1921         /* update the per-port timeout */
1922         uart_update_timeout(port, termios->c_cflag, baud);
1923
1924         /* wait transmit engin complete */
1925         lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
1926
1927         /* disable transmit and receive */
1928         writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1929                         sport->port.membase + UARTCR2);
1930
1931         sbr = sport->port.uartclk / (16 * baud);
1932         brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1933         bdh &= ~UARTBDH_SBR_MASK;
1934         bdh |= (sbr >> 8) & 0x1F;
1935         cr4 &= ~UARTCR4_BRFA_MASK;
1936         brfa &= UARTCR4_BRFA_MASK;
1937         writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1938         writeb(bdh, sport->port.membase + UARTBDH);
1939         writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1940         writeb(cr3, sport->port.membase + UARTCR3);
1941         writeb(cr1, sport->port.membase + UARTCR1);
1942         writeb(modem, sport->port.membase + UARTMODEM);
1943
1944         /* restore control register */
1945         writeb(old_cr2, sport->port.membase + UARTCR2);
1946
1947         if (old && sport->lpuart_dma_rx_use) {
1948                 if (!lpuart_start_rx_dma(sport))
1949                         rx_dma_timer_init(sport);
1950                 else
1951                         sport->lpuart_dma_rx_use = false;
1952         }
1953
1954         spin_unlock_irqrestore(&sport->port.lock, flags);
1955 }
1956
1957 static void __lpuart32_serial_setbrg(struct uart_port *port,
1958                                      unsigned int baudrate, bool use_rx_dma,
1959                                      bool use_tx_dma)
1960 {
1961         u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
1962         u32 clk = port->uartclk;
1963
1964         /*
1965          * The idea is to use the best OSR (over-sampling rate) possible.
1966          * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
1967          * Loop to find the best OSR value possible, one that generates minimum
1968          * baud_diff iterate through the rest of the supported values of OSR.
1969          *
1970          * Calculation Formula:
1971          *  Baud Rate = baud clock / ((OSR+1) × SBR)
1972          */
1973         baud_diff = baudrate;
1974         osr = 0;
1975         sbr = 0;
1976
1977         for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
1978                 /* calculate the temporary sbr value  */
1979                 tmp_sbr = (clk / (baudrate * tmp_osr));
1980                 if (tmp_sbr == 0)
1981                         tmp_sbr = 1;
1982
1983                 /*
1984                  * calculate the baud rate difference based on the temporary
1985                  * osr and sbr values
1986                  */
1987                 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
1988
1989                 /* select best values between sbr and sbr+1 */
1990                 tmp = clk / (tmp_osr * (tmp_sbr + 1));
1991                 if (tmp_diff > (baudrate - tmp)) {
1992                         tmp_diff = baudrate - tmp;
1993                         tmp_sbr++;
1994                 }
1995
1996                 if (tmp_sbr > UARTBAUD_SBR_MASK)
1997                         continue;
1998
1999                 if (tmp_diff <= baud_diff) {
2000                         baud_diff = tmp_diff;
2001                         osr = tmp_osr;
2002                         sbr = tmp_sbr;
2003
2004                         if (!baud_diff)
2005                                 break;
2006                 }
2007         }
2008
2009         /* handle buadrate outside acceptable rate */
2010         if (baud_diff > ((baudrate / 100) * 3))
2011                 dev_warn(port->dev,
2012                          "unacceptable baud rate difference of more than 3%%\n");
2013
2014         tmp = lpuart32_read(port, UARTBAUD);
2015
2016         if ((osr > 3) && (osr < 8))
2017                 tmp |= UARTBAUD_BOTHEDGE;
2018
2019         tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
2020         tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
2021
2022         tmp &= ~UARTBAUD_SBR_MASK;
2023         tmp |= sbr & UARTBAUD_SBR_MASK;
2024
2025         if (!use_rx_dma)
2026                 tmp &= ~UARTBAUD_RDMAE;
2027         if (!use_tx_dma)
2028                 tmp &= ~UARTBAUD_TDMAE;
2029
2030         lpuart32_write(port, tmp, UARTBAUD);
2031 }
2032
2033 static void lpuart32_serial_setbrg(struct lpuart_port *sport,
2034                                    unsigned int baudrate)
2035 {
2036         __lpuart32_serial_setbrg(&sport->port, baudrate,
2037                                  sport->lpuart_dma_rx_use,
2038                                  sport->lpuart_dma_tx_use);
2039 }
2040
2041
2042 static void
2043 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
2044                    struct ktermios *old)
2045 {
2046         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
2047         unsigned long flags;
2048         unsigned long ctrl, old_ctrl, modem;
2049         unsigned int  baud;
2050         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
2051
2052         ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
2053         modem = lpuart32_read(&sport->port, UARTMODIR);
2054         /*
2055          * only support CS8 and CS7, and for CS7 must enable PE.
2056          * supported mode:
2057          *  - (7,e/o,1)
2058          *  - (8,n,1)
2059          *  - (8,m/s,1)
2060          *  - (8,e/o,1)
2061          */
2062         while ((termios->c_cflag & CSIZE) != CS8 &&
2063                 (termios->c_cflag & CSIZE) != CS7) {
2064                 termios->c_cflag &= ~CSIZE;
2065                 termios->c_cflag |= old_csize;
2066                 old_csize = CS8;
2067         }
2068
2069         if ((termios->c_cflag & CSIZE) == CS8 ||
2070                 (termios->c_cflag & CSIZE) == CS7)
2071                 ctrl = old_ctrl & ~UARTCTRL_M;
2072
2073         if (termios->c_cflag & CMSPAR) {
2074                 if ((termios->c_cflag & CSIZE) != CS8) {
2075                         termios->c_cflag &= ~CSIZE;
2076                         termios->c_cflag |= CS8;
2077                 }
2078                 ctrl |= UARTCTRL_M;
2079         }
2080
2081         /*
2082          * When auto RS-485 RTS mode is enabled,
2083          * hardware flow control need to be disabled.
2084          */
2085         if (sport->port.rs485.flags & SER_RS485_ENABLED)
2086                 termios->c_cflag &= ~CRTSCTS;
2087
2088         if (termios->c_cflag & CRTSCTS) {
2089                 modem |= (UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
2090         } else {
2091                 termios->c_cflag &= ~CRTSCTS;
2092                 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
2093         }
2094
2095         if (termios->c_cflag & CSTOPB)
2096                 termios->c_cflag &= ~CSTOPB;
2097
2098         /* parity must be enabled when CS7 to match 8-bits format */
2099         if ((termios->c_cflag & CSIZE) == CS7)
2100                 termios->c_cflag |= PARENB;
2101
2102         if ((termios->c_cflag & PARENB)) {
2103                 if (termios->c_cflag & CMSPAR) {
2104                         ctrl &= ~UARTCTRL_PE;
2105                         ctrl |= UARTCTRL_M;
2106                 } else {
2107                         ctrl |= UARTCTRL_PE;
2108                         if ((termios->c_cflag & CSIZE) == CS8)
2109                                 ctrl |= UARTCTRL_M;
2110                         if (termios->c_cflag & PARODD)
2111                                 ctrl |= UARTCTRL_PT;
2112                         else
2113                                 ctrl &= ~UARTCTRL_PT;
2114                 }
2115         } else {
2116                 ctrl &= ~UARTCTRL_PE;
2117         }
2118
2119         /* ask the core to calculate the divisor */
2120         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
2121
2122         /*
2123          * Need to update the Ring buffer length according to the selected
2124          * baud rate and restart Rx DMA path.
2125          *
2126          * Since timer function acqures sport->port.lock, need to stop before
2127          * acquring same lock because otherwise del_timer_sync() can deadlock.
2128          */
2129         if (old && sport->lpuart_dma_rx_use) {
2130                 del_timer_sync(&sport->lpuart_timer);
2131                 lpuart_dma_rx_free(&sport->port);
2132         }
2133
2134         spin_lock_irqsave(&sport->port.lock, flags);
2135
2136         sport->port.read_status_mask = 0;
2137         if (termios->c_iflag & INPCK)
2138                 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;
2139         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2140                 sport->port.read_status_mask |= UARTSTAT_FE;
2141
2142         /* characters to ignore */
2143         sport->port.ignore_status_mask = 0;
2144         if (termios->c_iflag & IGNPAR)
2145                 sport->port.ignore_status_mask |= UARTSTAT_PE;
2146         if (termios->c_iflag & IGNBRK) {
2147                 sport->port.ignore_status_mask |= UARTSTAT_FE;
2148                 /*
2149                  * if we're ignoring parity and break indicators,
2150                  * ignore overruns too (for real raw support).
2151                  */
2152                 if (termios->c_iflag & IGNPAR)
2153                         sport->port.ignore_status_mask |= UARTSTAT_OR;
2154         }
2155
2156         /* update the per-port timeout */
2157         uart_update_timeout(port, termios->c_cflag, baud);
2158
2159         /* wait transmit engin complete */
2160         lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2161
2162         /* disable transmit and receive */
2163         lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
2164                        UARTCTRL);
2165
2166         lpuart32_serial_setbrg(sport, baud);
2167         lpuart32_write(&sport->port, modem, UARTMODIR);
2168         lpuart32_write(&sport->port, ctrl, UARTCTRL);
2169         /* restore control register */
2170
2171         if (old && sport->lpuart_dma_rx_use) {
2172                 if (!lpuart_start_rx_dma(sport))
2173                         rx_dma_timer_init(sport);
2174                 else
2175                         sport->lpuart_dma_rx_use = false;
2176         }
2177
2178         spin_unlock_irqrestore(&sport->port.lock, flags);
2179 }
2180
2181 static const char *lpuart_type(struct uart_port *port)
2182 {
2183         return "FSL_LPUART";
2184 }
2185
2186 static void lpuart_release_port(struct uart_port *port)
2187 {
2188         /* nothing to do */
2189 }
2190
2191 static int lpuart_request_port(struct uart_port *port)
2192 {
2193         return  0;
2194 }
2195
2196 /* configure/autoconfigure the port */
2197 static void lpuart_config_port(struct uart_port *port, int flags)
2198 {
2199         if (flags & UART_CONFIG_TYPE)
2200                 port->type = PORT_LPUART;
2201 }
2202
2203 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
2204 {
2205         int ret = 0;
2206
2207         if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
2208                 ret = -EINVAL;
2209         if (port->irq != ser->irq)
2210                 ret = -EINVAL;
2211         if (ser->io_type != UPIO_MEM)
2212                 ret = -EINVAL;
2213         if (port->uartclk / 16 != ser->baud_base)
2214                 ret = -EINVAL;
2215         if (port->iobase != ser->port)
2216                 ret = -EINVAL;
2217         if (ser->hub6 != 0)
2218                 ret = -EINVAL;
2219         return ret;
2220 }
2221
2222 static const struct uart_ops lpuart_pops = {
2223         .tx_empty       = lpuart_tx_empty,
2224         .set_mctrl      = lpuart_set_mctrl,
2225         .get_mctrl      = lpuart_get_mctrl,
2226         .stop_tx        = lpuart_stop_tx,
2227         .start_tx       = lpuart_start_tx,
2228         .stop_rx        = lpuart_stop_rx,
2229         .break_ctl      = lpuart_break_ctl,
2230         .startup        = lpuart_startup,
2231         .shutdown       = lpuart_shutdown,
2232         .set_termios    = lpuart_set_termios,
2233         .type           = lpuart_type,
2234         .request_port   = lpuart_request_port,
2235         .release_port   = lpuart_release_port,
2236         .config_port    = lpuart_config_port,
2237         .verify_port    = lpuart_verify_port,
2238         .flush_buffer   = lpuart_flush_buffer,
2239 #if defined(CONFIG_CONSOLE_POLL)
2240         .poll_init      = lpuart_poll_init,
2241         .poll_get_char  = lpuart_poll_get_char,
2242         .poll_put_char  = lpuart_poll_put_char,
2243 #endif
2244 };
2245
2246 static const struct uart_ops lpuart32_pops = {
2247         .tx_empty       = lpuart32_tx_empty,
2248         .set_mctrl      = lpuart32_set_mctrl,
2249         .get_mctrl      = lpuart32_get_mctrl,
2250         .stop_tx        = lpuart32_stop_tx,
2251         .start_tx       = lpuart32_start_tx,
2252         .stop_rx        = lpuart32_stop_rx,
2253         .break_ctl      = lpuart32_break_ctl,
2254         .startup        = lpuart32_startup,
2255         .shutdown       = lpuart32_shutdown,
2256         .set_termios    = lpuart32_set_termios,
2257         .type           = lpuart_type,
2258         .request_port   = lpuart_request_port,
2259         .release_port   = lpuart_release_port,
2260         .config_port    = lpuart_config_port,
2261         .verify_port    = lpuart_verify_port,
2262         .flush_buffer   = lpuart_flush_buffer,
2263 #if defined(CONFIG_CONSOLE_POLL)
2264         .poll_init      = lpuart32_poll_init,
2265         .poll_get_char  = lpuart32_poll_get_char,
2266         .poll_put_char  = lpuart32_poll_put_char,
2267 #endif
2268 };
2269
2270 static struct lpuart_port *lpuart_ports[UART_NR];
2271
2272 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
2273 static void lpuart_console_putchar(struct uart_port *port, int ch)
2274 {
2275         lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
2276         writeb(ch, port->membase + UARTDR);
2277 }
2278
2279 static void lpuart32_console_putchar(struct uart_port *port, int ch)
2280 {
2281         lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
2282         lpuart32_write(port, ch, UARTDATA);
2283 }
2284
2285 static void
2286 lpuart_console_write(struct console *co, const char *s, unsigned int count)
2287 {
2288         struct lpuart_port *sport = lpuart_ports[co->index];
2289         unsigned char  old_cr2, cr2;
2290         unsigned long flags;
2291         int locked = 1;
2292
2293         if (oops_in_progress)
2294                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2295         else
2296                 spin_lock_irqsave(&sport->port.lock, flags);
2297
2298         /* first save CR2 and then disable interrupts */
2299         cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
2300         cr2 |= UARTCR2_TE | UARTCR2_RE;
2301         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
2302         writeb(cr2, sport->port.membase + UARTCR2);
2303
2304         uart_console_write(&sport->port, s, count, lpuart_console_putchar);
2305
2306         /* wait for transmitter finish complete and restore CR2 */
2307         lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2308
2309         writeb(old_cr2, sport->port.membase + UARTCR2);
2310
2311         if (locked)
2312                 spin_unlock_irqrestore(&sport->port.lock, flags);
2313 }
2314
2315 static void
2316 lpuart32_console_write(struct console *co, const char *s, unsigned int count)
2317 {
2318         struct lpuart_port *sport = lpuart_ports[co->index];
2319         unsigned long  old_cr, cr;
2320         unsigned long flags;
2321         int locked = 1;
2322
2323         if (oops_in_progress)
2324                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2325         else
2326                 spin_lock_irqsave(&sport->port.lock, flags);
2327
2328         /* first save CR2 and then disable interrupts */
2329         cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
2330         cr |= UARTCTRL_TE | UARTCTRL_RE;
2331         cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
2332         lpuart32_write(&sport->port, cr, UARTCTRL);
2333
2334         uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
2335
2336         /* wait for transmitter finish complete and restore CR2 */
2337         lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2338
2339         lpuart32_write(&sport->port, old_cr, UARTCTRL);
2340
2341         if (locked)
2342                 spin_unlock_irqrestore(&sport->port.lock, flags);
2343 }
2344
2345 /*
2346  * if the port was already initialised (eg, by a boot loader),
2347  * try to determine the current setup.
2348  */
2349 static void __init
2350 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
2351                            int *parity, int *bits)
2352 {
2353         unsigned char cr, bdh, bdl, brfa;
2354         unsigned int sbr, uartclk, baud_raw;
2355
2356         cr = readb(sport->port.membase + UARTCR2);
2357         cr &= UARTCR2_TE | UARTCR2_RE;
2358         if (!cr)
2359                 return;
2360
2361         /* ok, the port was enabled */
2362
2363         cr = readb(sport->port.membase + UARTCR1);
2364
2365         *parity = 'n';
2366         if (cr & UARTCR1_PE) {
2367                 if (cr & UARTCR1_PT)
2368                         *parity = 'o';
2369                 else
2370                         *parity = 'e';
2371         }
2372
2373         if (cr & UARTCR1_M)
2374                 *bits = 9;
2375         else
2376                 *bits = 8;
2377
2378         bdh = readb(sport->port.membase + UARTBDH);
2379         bdh &= UARTBDH_SBR_MASK;
2380         bdl = readb(sport->port.membase + UARTBDL);
2381         sbr = bdh;
2382         sbr <<= 8;
2383         sbr |= bdl;
2384         brfa = readb(sport->port.membase + UARTCR4);
2385         brfa &= UARTCR4_BRFA_MASK;
2386
2387         uartclk = lpuart_get_baud_clk_rate(sport);
2388         /*
2389          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2390          */
2391         baud_raw = uartclk / (16 * (sbr + brfa / 32));
2392
2393         if (*baud != baud_raw)
2394                 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2395                                 "from %d to %d\n", baud_raw, *baud);
2396 }
2397
2398 static void __init
2399 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
2400                            int *parity, int *bits)
2401 {
2402         unsigned long cr, bd;
2403         unsigned int sbr, uartclk, baud_raw;
2404
2405         cr = lpuart32_read(&sport->port, UARTCTRL);
2406         cr &= UARTCTRL_TE | UARTCTRL_RE;
2407         if (!cr)
2408                 return;
2409
2410         /* ok, the port was enabled */
2411
2412         cr = lpuart32_read(&sport->port, UARTCTRL);
2413
2414         *parity = 'n';
2415         if (cr & UARTCTRL_PE) {
2416                 if (cr & UARTCTRL_PT)
2417                         *parity = 'o';
2418                 else
2419                         *parity = 'e';
2420         }
2421
2422         if (cr & UARTCTRL_M)
2423                 *bits = 9;
2424         else
2425                 *bits = 8;
2426
2427         bd = lpuart32_read(&sport->port, UARTBAUD);
2428         bd &= UARTBAUD_SBR_MASK;
2429         if (!bd)
2430                 return;
2431
2432         sbr = bd;
2433         uartclk = lpuart_get_baud_clk_rate(sport);
2434         /*
2435          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2436          */
2437         baud_raw = uartclk / (16 * sbr);
2438
2439         if (*baud != baud_raw)
2440                 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2441                                 "from %d to %d\n", baud_raw, *baud);
2442 }
2443
2444 static int __init lpuart_console_setup(struct console *co, char *options)
2445 {
2446         struct lpuart_port *sport;
2447         int baud = 115200;
2448         int bits = 8;
2449         int parity = 'n';
2450         int flow = 'n';
2451
2452         /*
2453          * check whether an invalid uart number has been specified, and
2454          * if so, search for the first available port that does have
2455          * console support.
2456          */
2457         if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
2458                 co->index = 0;
2459
2460         sport = lpuart_ports[co->index];
2461         if (sport == NULL)
2462                 return -ENODEV;
2463
2464         if (options)
2465                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2466         else
2467                 if (lpuart_is_32(sport))
2468                         lpuart32_console_get_options(sport, &baud, &parity, &bits);
2469                 else
2470                         lpuart_console_get_options(sport, &baud, &parity, &bits);
2471
2472         if (lpuart_is_32(sport))
2473                 lpuart32_setup_watermark(sport);
2474         else
2475                 lpuart_setup_watermark(sport);
2476
2477         return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2478 }
2479
2480 static struct uart_driver lpuart_reg;
2481 static struct console lpuart_console = {
2482         .name           = DEV_NAME,
2483         .write          = lpuart_console_write,
2484         .device         = uart_console_device,
2485         .setup          = lpuart_console_setup,
2486         .flags          = CON_PRINTBUFFER,
2487         .index          = -1,
2488         .data           = &lpuart_reg,
2489 };
2490
2491 static struct console lpuart32_console = {
2492         .name           = DEV_NAME,
2493         .write          = lpuart32_console_write,
2494         .device         = uart_console_device,
2495         .setup          = lpuart_console_setup,
2496         .flags          = CON_PRINTBUFFER,
2497         .index          = -1,
2498         .data           = &lpuart_reg,
2499 };
2500
2501 static void lpuart_early_write(struct console *con, const char *s, unsigned n)
2502 {
2503         struct earlycon_device *dev = con->data;
2504
2505         uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2506 }
2507
2508 static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
2509 {
2510         struct earlycon_device *dev = con->data;
2511
2512         uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2513 }
2514
2515 static int __init lpuart_early_console_setup(struct earlycon_device *device,
2516                                           const char *opt)
2517 {
2518         if (!device->port.membase)
2519                 return -ENODEV;
2520
2521         device->con->write = lpuart_early_write;
2522         return 0;
2523 }
2524
2525 static int __init lpuart32_early_console_setup(struct earlycon_device *device,
2526                                           const char *opt)
2527 {
2528         if (!device->port.membase)
2529                 return -ENODEV;
2530
2531         if (device->port.iotype != UPIO_MEM32)
2532                 device->port.iotype = UPIO_MEM32BE;
2533
2534         device->con->write = lpuart32_early_write;
2535         return 0;
2536 }
2537
2538 static int __init ls1028a_early_console_setup(struct earlycon_device *device,
2539                                               const char *opt)
2540 {
2541         u32 cr;
2542
2543         if (!device->port.membase)
2544                 return -ENODEV;
2545
2546         device->port.iotype = UPIO_MEM32;
2547         device->con->write = lpuart32_early_write;
2548
2549         /* set the baudrate */
2550         if (device->port.uartclk && device->baud)
2551                 __lpuart32_serial_setbrg(&device->port, device->baud,
2552                                          false, false);
2553
2554         /* enable transmitter */
2555         cr = lpuart32_read(&device->port, UARTCTRL);
2556         cr |= UARTCTRL_TE;
2557         lpuart32_write(&device->port, cr, UARTCTRL);
2558
2559         return 0;
2560 }
2561
2562 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
2563                                                    const char *opt)
2564 {
2565         if (!device->port.membase)
2566                 return -ENODEV;
2567
2568         device->port.iotype = UPIO_MEM32;
2569         device->port.membase += IMX_REG_OFF;
2570         device->con->write = lpuart32_early_write;
2571
2572         return 0;
2573 }
2574 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2575 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2576 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2577 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2578 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2579 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2580
2581 #define LPUART_CONSOLE  (&lpuart_console)
2582 #define LPUART32_CONSOLE        (&lpuart32_console)
2583 #else
2584 #define LPUART_CONSOLE  NULL
2585 #define LPUART32_CONSOLE        NULL
2586 #endif
2587
2588 static struct uart_driver lpuart_reg = {
2589         .owner          = THIS_MODULE,
2590         .driver_name    = DRIVER_NAME,
2591         .dev_name       = DEV_NAME,
2592         .nr             = ARRAY_SIZE(lpuart_ports),
2593         .cons           = LPUART_CONSOLE,
2594 };
2595
2596 static int lpuart_probe(struct platform_device *pdev)
2597 {
2598         const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev);
2599         struct device_node *np = pdev->dev.of_node;
2600         struct lpuart_port *sport;
2601         struct resource *res;
2602         int ret;
2603
2604         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2605         if (!sport)
2606                 return -ENOMEM;
2607
2608         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2609         sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2610         if (IS_ERR(sport->port.membase))
2611                 return PTR_ERR(sport->port.membase);
2612
2613         sport->port.membase += sdata->reg_off;
2614         sport->port.mapbase = res->start;
2615         sport->port.dev = &pdev->dev;
2616         sport->port.type = PORT_LPUART;
2617         sport->devtype = sdata->devtype;
2618         ret = platform_get_irq(pdev, 0);
2619         if (ret < 0)
2620                 return ret;
2621         sport->port.irq = ret;
2622         sport->port.iotype = sdata->iotype;
2623         if (lpuart_is_32(sport))
2624                 sport->port.ops = &lpuart32_pops;
2625         else
2626                 sport->port.ops = &lpuart_pops;
2627         sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);
2628         sport->port.flags = UPF_BOOT_AUTOCONF;
2629
2630         if (lpuart_is_32(sport))
2631                 sport->port.rs485_config = lpuart32_config_rs485;
2632         else
2633                 sport->port.rs485_config = lpuart_config_rs485;
2634
2635         sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
2636         if (IS_ERR(sport->ipg_clk)) {
2637                 ret = PTR_ERR(sport->ipg_clk);
2638                 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret);
2639                 return ret;
2640         }
2641
2642         sport->baud_clk = NULL;
2643         if (is_imx8qxp_lpuart(sport)) {
2644                 sport->baud_clk = devm_clk_get(&pdev->dev, "baud");
2645                 if (IS_ERR(sport->baud_clk)) {
2646                         ret = PTR_ERR(sport->baud_clk);
2647                         dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret);
2648                         return ret;
2649                 }
2650         }
2651
2652         ret = of_alias_get_id(np, "serial");
2653         if (ret < 0) {
2654                 ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL);
2655                 if (ret < 0) {
2656                         dev_err(&pdev->dev, "port line is full, add device failed\n");
2657                         return ret;
2658                 }
2659                 sport->id_allocated = true;
2660         }
2661         if (ret >= ARRAY_SIZE(lpuart_ports)) {
2662                 dev_err(&pdev->dev, "serial%d out of range\n", ret);
2663                 ret = -EINVAL;
2664                 goto failed_out_of_range;
2665         }
2666         sport->port.line = ret;
2667
2668         ret = lpuart_enable_clks(sport);
2669         if (ret)
2670                 goto failed_clock_enable;
2671         sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
2672
2673         lpuart_ports[sport->port.line] = sport;
2674
2675         platform_set_drvdata(pdev, &sport->port);
2676
2677         if (lpuart_is_32(sport)) {
2678                 lpuart_reg.cons = LPUART32_CONSOLE;
2679                 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0,
2680                                         DRIVER_NAME, sport);
2681         } else {
2682                 lpuart_reg.cons = LPUART_CONSOLE;
2683                 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0,
2684                                         DRIVER_NAME, sport);
2685         }
2686
2687         if (ret)
2688                 goto failed_irq_request;
2689
2690         ret = uart_add_one_port(&lpuart_reg, &sport->port);
2691         if (ret)
2692                 goto failed_attach_port;
2693
2694         ret = uart_get_rs485_mode(&sport->port);
2695         if (ret)
2696                 goto failed_get_rs485;
2697
2698         if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX)
2699                 dev_err(&pdev->dev, "driver doesn't support RX during TX\n");
2700
2701         if (sport->port.rs485.delay_rts_before_send ||
2702             sport->port.rs485.delay_rts_after_send)
2703                 dev_err(&pdev->dev, "driver doesn't support RTS delays\n");
2704
2705         sport->port.rs485_config(&sport->port, &sport->port.rs485);
2706
2707         return 0;
2708
2709 failed_get_rs485:
2710 failed_attach_port:
2711 failed_irq_request:
2712         lpuart_disable_clks(sport);
2713 failed_clock_enable:
2714 failed_out_of_range:
2715         if (sport->id_allocated)
2716                 ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
2717         return ret;
2718 }
2719
2720 static int lpuart_remove(struct platform_device *pdev)
2721 {
2722         struct lpuart_port *sport = platform_get_drvdata(pdev);
2723
2724         uart_remove_one_port(&lpuart_reg, &sport->port);
2725
2726         if (sport->id_allocated)
2727                 ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
2728
2729         lpuart_disable_clks(sport);
2730
2731         if (sport->dma_tx_chan)
2732                 dma_release_channel(sport->dma_tx_chan);
2733
2734         if (sport->dma_rx_chan)
2735                 dma_release_channel(sport->dma_rx_chan);
2736
2737         return 0;
2738 }
2739
2740 static int __maybe_unused lpuart_suspend(struct device *dev)
2741 {
2742         struct lpuart_port *sport = dev_get_drvdata(dev);
2743         unsigned long temp;
2744         bool irq_wake;
2745
2746         if (lpuart_is_32(sport)) {
2747                 /* disable Rx/Tx and interrupts */
2748                 temp = lpuart32_read(&sport->port, UARTCTRL);
2749                 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
2750                 lpuart32_write(&sport->port, temp, UARTCTRL);
2751         } else {
2752                 /* disable Rx/Tx and interrupts */
2753                 temp = readb(sport->port.membase + UARTCR2);
2754                 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
2755                 writeb(temp, sport->port.membase + UARTCR2);
2756         }
2757
2758         uart_suspend_port(&lpuart_reg, &sport->port);
2759
2760         /* uart_suspend_port() might set wakeup flag */
2761         irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2762
2763         if (sport->lpuart_dma_rx_use) {
2764                 /*
2765                  * EDMA driver during suspend will forcefully release any
2766                  * non-idle DMA channels. If port wakeup is enabled or if port
2767                  * is console port or 'no_console_suspend' is set the Rx DMA
2768                  * cannot resume as as expected, hence gracefully release the
2769                  * Rx DMA path before suspend and start Rx DMA path on resume.
2770                  */
2771                 if (irq_wake) {
2772                         del_timer_sync(&sport->lpuart_timer);
2773                         lpuart_dma_rx_free(&sport->port);
2774                 }
2775
2776                 /* Disable Rx DMA to use UART port as wakeup source */
2777                 if (lpuart_is_32(sport)) {
2778                         temp = lpuart32_read(&sport->port, UARTBAUD);
2779                         lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
2780                                        UARTBAUD);
2781                 } else {
2782                         writeb(readb(sport->port.membase + UARTCR5) &
2783                                ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
2784                 }
2785         }
2786
2787         if (sport->lpuart_dma_tx_use) {
2788                 sport->dma_tx_in_progress = false;
2789                 dmaengine_terminate_all(sport->dma_tx_chan);
2790         }
2791
2792         if (sport->port.suspended && !irq_wake)
2793                 lpuart_disable_clks(sport);
2794
2795         return 0;
2796 }
2797
2798 static int __maybe_unused lpuart_resume(struct device *dev)
2799 {
2800         struct lpuart_port *sport = dev_get_drvdata(dev);
2801         bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2802
2803         if (sport->port.suspended && !irq_wake)
2804                 lpuart_enable_clks(sport);
2805
2806         if (lpuart_is_32(sport))
2807                 lpuart32_setup_watermark_enable(sport);
2808         else
2809                 lpuart_setup_watermark_enable(sport);
2810
2811         if (sport->lpuart_dma_rx_use) {
2812                 if (irq_wake) {
2813                         if (!lpuart_start_rx_dma(sport))
2814                                 rx_dma_timer_init(sport);
2815                         else
2816                                 sport->lpuart_dma_rx_use = false;
2817                 }
2818         }
2819
2820         lpuart_tx_dma_startup(sport);
2821
2822         if (lpuart_is_32(sport))
2823                 lpuart32_configure(sport);
2824
2825         uart_resume_port(&lpuart_reg, &sport->port);
2826
2827         return 0;
2828 }
2829
2830 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2831
2832 static struct platform_driver lpuart_driver = {
2833         .probe          = lpuart_probe,
2834         .remove         = lpuart_remove,
2835         .driver         = {
2836                 .name   = "fsl-lpuart",
2837                 .of_match_table = lpuart_dt_ids,
2838                 .pm     = &lpuart_pm_ops,
2839         },
2840 };
2841
2842 static int __init lpuart_serial_init(void)
2843 {
2844         int ret = uart_register_driver(&lpuart_reg);
2845
2846         if (ret)
2847                 return ret;
2848
2849         ret = platform_driver_register(&lpuart_driver);
2850         if (ret)
2851                 uart_unregister_driver(&lpuart_reg);
2852
2853         return ret;
2854 }
2855
2856 static void __exit lpuart_serial_exit(void)
2857 {
2858         ida_destroy(&fsl_lpuart_ida);
2859         platform_driver_unregister(&lpuart_driver);
2860         uart_unregister_driver(&lpuart_reg);
2861 }
2862
2863 module_init(lpuart_serial_init);
2864 module_exit(lpuart_serial_exit);
2865
2866 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2867 MODULE_LICENSE("GPL v2");