1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Atmel AT91 Serial ports
4 * Copyright (C) 2003 Rick Bronson
6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
9 * DMA support added by Chip Coldwell.
11 #include <linux/tty.h>
12 #include <linux/ioport.h>
13 #include <linux/slab.h>
14 #include <linux/init.h>
15 #include <linux/serial.h>
16 #include <linux/clk.h>
17 #include <linux/console.h>
18 #include <linux/sysrq.h>
19 #include <linux/tty_flip.h>
20 #include <linux/platform_device.h>
22 #include <linux/of_device.h>
23 #include <linux/of_gpio.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/atmel_pdc.h>
27 #include <linux/uaccess.h>
28 #include <linux/platform_data/atmel.h>
29 #include <linux/timer.h>
30 #include <linux/gpio.h>
31 #include <linux/gpio/consumer.h>
32 #include <linux/err.h>
33 #include <linux/irq.h>
34 #include <linux/suspend.h>
37 #include <asm/div64.h>
39 #include <asm/ioctls.h>
41 #define PDC_BUFFER_SIZE 512
42 /* Revisit: We should calculate this based on the actual port settings */
43 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
45 /* The minium number of data FIFOs should be able to contain */
46 #define ATMEL_MIN_FIFO_SIZE 8
48 * These two offsets are substracted from the RX FIFO size to define the RTS
49 * high and low thresholds
51 #define ATMEL_RTS_HIGH_OFFSET 16
52 #define ATMEL_RTS_LOW_OFFSET 20
54 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
58 #include <linux/serial_core.h>
60 #include "serial_mctrl_gpio.h"
61 #include "atmel_serial.h"
63 static void atmel_start_rx(struct uart_port *port);
64 static void atmel_stop_rx(struct uart_port *port);
66 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
68 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
69 * should coexist with the 8250 driver, such as if we have an external 16C550
71 #define SERIAL_ATMEL_MAJOR 204
72 #define MINOR_START 154
73 #define ATMEL_DEVICENAME "ttyAT"
77 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
78 * name, but it is legally reserved for the 8250 driver. */
79 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
80 #define MINOR_START 64
81 #define ATMEL_DEVICENAME "ttyS"
85 #define ATMEL_ISR_PASS_LIMIT 256
87 struct atmel_dma_buffer {
90 unsigned int dma_size;
94 struct atmel_uart_char {
100 * Be careful, the real size of the ring buffer is
101 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
102 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
105 #define ATMEL_SERIAL_RINGSIZE 1024
108 * at91: 6 USARTs and one DBGU port (SAM9260)
109 * samx7: 3 USARTs and 5 UARTs
111 #define ATMEL_MAX_UART 8
114 * We wrap our port structure around the generic uart_port.
116 struct atmel_uart_port {
117 struct uart_port uart; /* uart */
118 struct clk *clk; /* uart clock */
119 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
120 u32 backup_imr; /* IMR saved during suspend */
121 int break_active; /* break being received */
123 bool use_dma_rx; /* enable DMA receiver */
124 bool use_pdc_rx; /* enable PDC receiver */
125 short pdc_rx_idx; /* current PDC RX buffer */
126 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
128 bool use_dma_tx; /* enable DMA transmitter */
129 bool use_pdc_tx; /* enable PDC transmitter */
130 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
132 spinlock_t lock_tx; /* port lock */
133 spinlock_t lock_rx; /* port lock */
134 struct dma_chan *chan_tx;
135 struct dma_chan *chan_rx;
136 struct dma_async_tx_descriptor *desc_tx;
137 struct dma_async_tx_descriptor *desc_rx;
138 dma_cookie_t cookie_tx;
139 dma_cookie_t cookie_rx;
140 struct scatterlist sg_tx;
141 struct scatterlist sg_rx;
142 struct tasklet_struct tasklet_rx;
143 struct tasklet_struct tasklet_tx;
144 atomic_t tasklet_shutdown;
145 unsigned int irq_status_prev;
148 struct circ_buf rx_ring;
150 struct mctrl_gpios *gpios;
151 u32 backup_mode; /* MR saved during iso7816 operations */
152 u32 backup_brgr; /* BRGR saved during iso7816 operations */
153 unsigned int tx_done_mask;
158 u32 rtor; /* address of receiver timeout register if it exists */
159 bool has_frac_baudrate;
161 struct timer_list uart_timer;
165 unsigned int pending;
166 unsigned int pending_status;
167 spinlock_t lock_suspended;
170 unsigned int fidi_min;
171 unsigned int fidi_max;
186 int (*prepare_rx)(struct uart_port *port);
187 int (*prepare_tx)(struct uart_port *port);
188 void (*schedule_rx)(struct uart_port *port);
189 void (*schedule_tx)(struct uart_port *port);
190 void (*release_rx)(struct uart_port *port);
191 void (*release_tx)(struct uart_port *port);
194 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
195 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
198 static struct console atmel_console;
201 #if defined(CONFIG_OF)
202 static const struct of_device_id atmel_serial_dt_ids[] = {
203 { .compatible = "atmel,at91rm9200-usart-serial" },
208 static inline struct atmel_uart_port *
209 to_atmel_uart_port(struct uart_port *uart)
211 return container_of(uart, struct atmel_uart_port, uart);
214 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
216 return __raw_readl(port->membase + reg);
219 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
221 __raw_writel(value, port->membase + reg);
224 static inline u8 atmel_uart_read_char(struct uart_port *port)
226 return __raw_readb(port->membase + ATMEL_US_RHR);
229 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
231 __raw_writeb(value, port->membase + ATMEL_US_THR);
234 #ifdef CONFIG_SERIAL_ATMEL_PDC
235 static bool atmel_use_pdc_rx(struct uart_port *port)
237 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
239 return atmel_port->use_pdc_rx;
242 static bool atmel_use_pdc_tx(struct uart_port *port)
244 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
246 return atmel_port->use_pdc_tx;
249 static bool atmel_use_pdc_rx(struct uart_port *port)
254 static bool atmel_use_pdc_tx(struct uart_port *port)
260 static bool atmel_use_dma_tx(struct uart_port *port)
262 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
264 return atmel_port->use_dma_tx;
267 static bool atmel_use_dma_rx(struct uart_port *port)
269 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
271 return atmel_port->use_dma_rx;
274 static bool atmel_use_fifo(struct uart_port *port)
276 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
278 return atmel_port->fifo_size;
281 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
282 struct tasklet_struct *t)
284 if (!atomic_read(&atmel_port->tasklet_shutdown))
288 static unsigned int atmel_get_lines_status(struct uart_port *port)
290 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
291 unsigned int status, ret = 0;
293 status = atmel_uart_readl(port, ATMEL_US_CSR);
295 mctrl_gpio_get(atmel_port->gpios, &ret);
297 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
300 status &= ~ATMEL_US_CTS;
302 status |= ATMEL_US_CTS;
305 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
308 status &= ~ATMEL_US_DSR;
310 status |= ATMEL_US_DSR;
313 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
316 status &= ~ATMEL_US_RI;
318 status |= ATMEL_US_RI;
321 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
324 status &= ~ATMEL_US_DCD;
326 status |= ATMEL_US_DCD;
332 /* Enable or disable the rs485 support */
333 static int atmel_config_rs485(struct uart_port *port,
334 struct serial_rs485 *rs485conf)
336 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
339 /* Disable interrupts */
340 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
342 mode = atmel_uart_readl(port, ATMEL_US_MR);
344 /* Resetting serial mode to RS232 (0x0) */
345 mode &= ~ATMEL_US_USMODE;
347 port->rs485 = *rs485conf;
349 if (rs485conf->flags & SER_RS485_ENABLED) {
350 dev_dbg(port->dev, "Setting UART to RS485\n");
351 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
352 atmel_uart_writel(port, ATMEL_US_TTGR,
353 rs485conf->delay_rts_after_send);
354 mode |= ATMEL_US_USMODE_RS485;
356 dev_dbg(port->dev, "Setting UART to RS232\n");
357 if (atmel_use_pdc_tx(port))
358 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
361 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
363 atmel_uart_writel(port, ATMEL_US_MR, mode);
365 /* Enable interrupts */
366 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
371 static unsigned int atmel_calc_cd(struct uart_port *port,
372 struct serial_iso7816 *iso7816conf)
374 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
378 mck_rate = (u64)clk_get_rate(atmel_port->clk);
379 do_div(mck_rate, iso7816conf->clk);
384 static unsigned int atmel_calc_fidi(struct uart_port *port,
385 struct serial_iso7816 *iso7816conf)
389 if (iso7816conf->sc_fi && iso7816conf->sc_di) {
390 fidi = (u64)iso7816conf->sc_fi;
391 do_div(fidi, iso7816conf->sc_di);
396 /* Enable or disable the iso7816 support */
397 /* Called with interrupts disabled */
398 static int atmel_config_iso7816(struct uart_port *port,
399 struct serial_iso7816 *iso7816conf)
401 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
403 unsigned int cd, fidi;
406 /* Disable interrupts */
407 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
409 mode = atmel_uart_readl(port, ATMEL_US_MR);
411 if (iso7816conf->flags & SER_ISO7816_ENABLED) {
412 mode &= ~ATMEL_US_USMODE;
414 if (iso7816conf->tg > 255) {
415 dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n");
416 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
421 if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
422 == SER_ISO7816_T(0)) {
423 mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK;
424 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
425 == SER_ISO7816_T(1)) {
426 mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK;
428 dev_err(port->dev, "ISO7816: Type not supported\n");
429 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
434 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR);
436 /* select mck clock, and output */
437 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
438 /* set parity for normal/inverse mode + max iterations */
439 mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3);
441 cd = atmel_calc_cd(port, iso7816conf);
442 fidi = atmel_calc_fidi(port, iso7816conf);
444 dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n");
445 } else if (fidi < atmel_port->fidi_min
446 || fidi > atmel_port->fidi_max) {
447 dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi);
448 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
453 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) {
454 /* port not yet in iso7816 mode: store configuration */
455 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR);
456 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
459 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg);
460 atmel_uart_writel(port, ATMEL_US_BRGR, cd);
461 atmel_uart_writel(port, ATMEL_US_FIDI, fidi);
463 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN);
464 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION;
466 dev_dbg(port->dev, "Setting UART back to RS232\n");
467 /* back to last RS232 settings */
468 mode = atmel_port->backup_mode;
469 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
470 atmel_uart_writel(port, ATMEL_US_TTGR, 0);
471 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr);
472 atmel_uart_writel(port, ATMEL_US_FIDI, 0x174);
474 if (atmel_use_pdc_tx(port))
475 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
478 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
481 port->iso7816 = *iso7816conf;
483 atmel_uart_writel(port, ATMEL_US_MR, mode);
486 /* Enable interrupts */
487 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
493 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
495 static u_int atmel_tx_empty(struct uart_port *port)
497 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
499 if (atmel_port->tx_stopped)
501 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
507 * Set state of the modem control output lines
509 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
511 unsigned int control = 0;
512 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
513 unsigned int rts_paused, rts_ready;
514 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
516 /* override mode to RS485 if needed, otherwise keep the current mode */
517 if (port->rs485.flags & SER_RS485_ENABLED) {
518 atmel_uart_writel(port, ATMEL_US_TTGR,
519 port->rs485.delay_rts_after_send);
520 mode &= ~ATMEL_US_USMODE;
521 mode |= ATMEL_US_USMODE_RS485;
524 /* set the RTS line state according to the mode */
525 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
526 /* force RTS line to high level */
527 rts_paused = ATMEL_US_RTSEN;
529 /* give the control of the RTS line back to the hardware */
530 rts_ready = ATMEL_US_RTSDIS;
532 /* force RTS line to high level */
533 rts_paused = ATMEL_US_RTSDIS;
535 /* force RTS line to low level */
536 rts_ready = ATMEL_US_RTSEN;
539 if (mctrl & TIOCM_RTS)
540 control |= rts_ready;
542 control |= rts_paused;
544 if (mctrl & TIOCM_DTR)
545 control |= ATMEL_US_DTREN;
547 control |= ATMEL_US_DTRDIS;
549 atmel_uart_writel(port, ATMEL_US_CR, control);
551 mctrl_gpio_set(atmel_port->gpios, mctrl);
553 /* Local loopback mode? */
554 mode &= ~ATMEL_US_CHMODE;
555 if (mctrl & TIOCM_LOOP)
556 mode |= ATMEL_US_CHMODE_LOC_LOOP;
558 mode |= ATMEL_US_CHMODE_NORMAL;
560 atmel_uart_writel(port, ATMEL_US_MR, mode);
564 * Get state of the modem control input lines
566 static u_int atmel_get_mctrl(struct uart_port *port)
568 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
569 unsigned int ret = 0, status;
571 status = atmel_uart_readl(port, ATMEL_US_CSR);
574 * The control signals are active low.
576 if (!(status & ATMEL_US_DCD))
578 if (!(status & ATMEL_US_CTS))
580 if (!(status & ATMEL_US_DSR))
582 if (!(status & ATMEL_US_RI))
585 return mctrl_gpio_get(atmel_port->gpios, &ret);
591 static void atmel_stop_tx(struct uart_port *port)
593 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
595 if (atmel_use_pdc_tx(port)) {
596 /* disable PDC transmit */
597 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
601 * Disable the transmitter.
602 * This is mandatory when DMA is used, otherwise the DMA buffer
603 * is fully transmitted.
605 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
606 atmel_port->tx_stopped = true;
608 /* Disable interrupts */
609 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
611 if (((port->rs485.flags & SER_RS485_ENABLED) &&
612 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
613 port->iso7816.flags & SER_ISO7816_ENABLED)
614 atmel_start_rx(port);
618 * Start transmitting.
620 static void atmel_start_tx(struct uart_port *port)
622 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
624 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
626 /* The transmitter is already running. Yes, we
630 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
631 if (((port->rs485.flags & SER_RS485_ENABLED) &&
632 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
633 port->iso7816.flags & SER_ISO7816_ENABLED)
636 if (atmel_use_pdc_tx(port))
637 /* re-enable PDC transmit */
638 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
640 /* Enable interrupts */
641 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
643 /* re-enable the transmitter */
644 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
645 atmel_port->tx_stopped = false;
649 * start receiving - port is in process of being opened.
651 static void atmel_start_rx(struct uart_port *port)
653 /* reset status and receiver */
654 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
656 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
658 if (atmel_use_pdc_rx(port)) {
659 /* enable PDC controller */
660 atmel_uart_writel(port, ATMEL_US_IER,
661 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
662 port->read_status_mask);
663 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
665 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
670 * Stop receiving - port is in process of being closed.
672 static void atmel_stop_rx(struct uart_port *port)
674 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
676 if (atmel_use_pdc_rx(port)) {
677 /* disable PDC receive */
678 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
679 atmel_uart_writel(port, ATMEL_US_IDR,
680 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
681 port->read_status_mask);
683 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
688 * Enable modem status interrupts
690 static void atmel_enable_ms(struct uart_port *port)
692 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
696 * Interrupt should not be enabled twice
698 if (atmel_port->ms_irq_enabled)
701 atmel_port->ms_irq_enabled = true;
703 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
704 ier |= ATMEL_US_CTSIC;
706 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
707 ier |= ATMEL_US_DSRIC;
709 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
710 ier |= ATMEL_US_RIIC;
712 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
713 ier |= ATMEL_US_DCDIC;
715 atmel_uart_writel(port, ATMEL_US_IER, ier);
717 mctrl_gpio_enable_ms(atmel_port->gpios);
721 * Disable modem status interrupts
723 static void atmel_disable_ms(struct uart_port *port)
725 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
729 * Interrupt should not be disabled twice
731 if (!atmel_port->ms_irq_enabled)
734 atmel_port->ms_irq_enabled = false;
736 mctrl_gpio_disable_ms(atmel_port->gpios);
738 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
739 idr |= ATMEL_US_CTSIC;
741 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
742 idr |= ATMEL_US_DSRIC;
744 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
745 idr |= ATMEL_US_RIIC;
747 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
748 idr |= ATMEL_US_DCDIC;
750 atmel_uart_writel(port, ATMEL_US_IDR, idr);
754 * Control the transmission of a break signal
756 static void atmel_break_ctl(struct uart_port *port, int break_state)
758 if (break_state != 0)
760 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
763 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
767 * Stores the incoming character in the ring buffer
770 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
773 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
774 struct circ_buf *ring = &atmel_port->rx_ring;
775 struct atmel_uart_char *c;
777 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
778 /* Buffer overflow, ignore char */
781 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
785 /* Make sure the character is stored before we update head. */
788 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
792 * Deal with parity, framing and overrun errors.
794 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
797 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
799 if (status & ATMEL_US_RXBRK) {
800 /* ignore side-effect */
801 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
804 if (status & ATMEL_US_PARE)
805 port->icount.parity++;
806 if (status & ATMEL_US_FRAME)
807 port->icount.frame++;
808 if (status & ATMEL_US_OVRE)
809 port->icount.overrun++;
813 * Characters received (called from interrupt handler)
815 static void atmel_rx_chars(struct uart_port *port)
817 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
818 unsigned int status, ch;
820 status = atmel_uart_readl(port, ATMEL_US_CSR);
821 while (status & ATMEL_US_RXRDY) {
822 ch = atmel_uart_read_char(port);
825 * note that the error handling code is
826 * out of the main execution path
828 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
829 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
830 || atmel_port->break_active)) {
833 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
835 if (status & ATMEL_US_RXBRK
836 && !atmel_port->break_active) {
837 atmel_port->break_active = 1;
838 atmel_uart_writel(port, ATMEL_US_IER,
842 * This is either the end-of-break
843 * condition or we've received at
844 * least one character without RXBRK
845 * being set. In both cases, the next
846 * RXBRK will indicate start-of-break.
848 atmel_uart_writel(port, ATMEL_US_IDR,
850 status &= ~ATMEL_US_RXBRK;
851 atmel_port->break_active = 0;
855 atmel_buffer_rx_char(port, status, ch);
856 status = atmel_uart_readl(port, ATMEL_US_CSR);
859 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
863 * Transmit characters (called from tasklet with TXRDY interrupt
866 static void atmel_tx_chars(struct uart_port *port)
868 struct circ_buf *xmit = &port->state->xmit;
869 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
872 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
873 atmel_uart_write_char(port, port->x_char);
877 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
880 while (atmel_uart_readl(port, ATMEL_US_CSR) &
881 atmel_port->tx_done_mask) {
882 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
883 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
885 if (uart_circ_empty(xmit))
889 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
890 uart_write_wakeup(port);
892 if (!uart_circ_empty(xmit))
893 /* Enable interrupts */
894 atmel_uart_writel(port, ATMEL_US_IER,
895 atmel_port->tx_done_mask);
898 static void atmel_complete_tx_dma(void *arg)
900 struct atmel_uart_port *atmel_port = arg;
901 struct uart_port *port = &atmel_port->uart;
902 struct circ_buf *xmit = &port->state->xmit;
903 struct dma_chan *chan = atmel_port->chan_tx;
906 spin_lock_irqsave(&port->lock, flags);
909 dmaengine_terminate_all(chan);
910 xmit->tail += atmel_port->tx_len;
911 xmit->tail &= UART_XMIT_SIZE - 1;
913 port->icount.tx += atmel_port->tx_len;
915 spin_lock_irq(&atmel_port->lock_tx);
916 async_tx_ack(atmel_port->desc_tx);
917 atmel_port->cookie_tx = -EINVAL;
918 atmel_port->desc_tx = NULL;
919 spin_unlock_irq(&atmel_port->lock_tx);
921 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
922 uart_write_wakeup(port);
925 * xmit is a circular buffer so, if we have just send data from
926 * xmit->tail to the end of xmit->buf, now we have to transmit the
927 * remaining data from the beginning of xmit->buf to xmit->head.
929 if (!uart_circ_empty(xmit))
930 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
931 else if (((port->rs485.flags & SER_RS485_ENABLED) &&
932 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
933 port->iso7816.flags & SER_ISO7816_ENABLED) {
934 /* DMA done, stop TX, start RX for RS485 */
935 atmel_start_rx(port);
938 spin_unlock_irqrestore(&port->lock, flags);
941 static void atmel_release_tx_dma(struct uart_port *port)
943 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
944 struct dma_chan *chan = atmel_port->chan_tx;
947 dmaengine_terminate_all(chan);
948 dma_release_channel(chan);
949 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
953 atmel_port->desc_tx = NULL;
954 atmel_port->chan_tx = NULL;
955 atmel_port->cookie_tx = -EINVAL;
959 * Called from tasklet with TXRDY interrupt is disabled.
961 static void atmel_tx_dma(struct uart_port *port)
963 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
964 struct circ_buf *xmit = &port->state->xmit;
965 struct dma_chan *chan = atmel_port->chan_tx;
966 struct dma_async_tx_descriptor *desc;
967 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
968 unsigned int tx_len, part1_len, part2_len, sg_len;
969 dma_addr_t phys_addr;
971 /* Make sure we have an idle channel */
972 if (atmel_port->desc_tx != NULL)
975 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
978 * Port xmit buffer is already mapped,
979 * and it is one page... Just adjust
980 * offsets and lengths. Since it is a circular buffer,
981 * we have to transmit till the end, and then the rest.
982 * Take the port lock to get a
983 * consistent xmit buffer state.
985 tx_len = CIRC_CNT_TO_END(xmit->head,
989 if (atmel_port->fifo_size) {
990 /* multi data mode */
991 part1_len = (tx_len & ~0x3); /* DWORD access */
992 part2_len = (tx_len & 0x3); /* BYTE access */
994 /* single data (legacy) mode */
996 part2_len = tx_len; /* BYTE access only */
999 sg_init_table(sgl, 2);
1001 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
1003 sg = &sgl[sg_len++];
1004 sg_dma_address(sg) = phys_addr;
1005 sg_dma_len(sg) = part1_len;
1007 phys_addr += part1_len;
1011 sg = &sgl[sg_len++];
1012 sg_dma_address(sg) = phys_addr;
1013 sg_dma_len(sg) = part2_len;
1017 * save tx_len so atmel_complete_tx_dma() will increase
1018 * xmit->tail correctly
1020 atmel_port->tx_len = tx_len;
1022 desc = dmaengine_prep_slave_sg(chan,
1026 DMA_PREP_INTERRUPT |
1029 dev_err(port->dev, "Failed to send via dma!\n");
1033 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
1035 atmel_port->desc_tx = desc;
1036 desc->callback = atmel_complete_tx_dma;
1037 desc->callback_param = atmel_port;
1038 atmel_port->cookie_tx = dmaengine_submit(desc);
1041 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1042 uart_write_wakeup(port);
1045 static int atmel_prepare_tx_dma(struct uart_port *port)
1047 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1048 struct device *mfd_dev = port->dev->parent;
1049 dma_cap_mask_t mask;
1050 struct dma_slave_config config;
1054 dma_cap_set(DMA_SLAVE, mask);
1056 atmel_port->chan_tx = dma_request_slave_channel(mfd_dev, "tx");
1057 if (atmel_port->chan_tx == NULL)
1059 dev_info(port->dev, "using %s for tx DMA transfers\n",
1060 dma_chan_name(atmel_port->chan_tx));
1062 spin_lock_init(&atmel_port->lock_tx);
1063 sg_init_table(&atmel_port->sg_tx, 1);
1064 /* UART circular tx buffer is an aligned page. */
1065 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
1066 sg_set_page(&atmel_port->sg_tx,
1067 virt_to_page(port->state->xmit.buf),
1069 offset_in_page(port->state->xmit.buf));
1070 nent = dma_map_sg(port->dev,
1076 dev_dbg(port->dev, "need to release resource of dma\n");
1079 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1080 sg_dma_len(&atmel_port->sg_tx),
1081 port->state->xmit.buf,
1082 &sg_dma_address(&atmel_port->sg_tx));
1085 /* Configure the slave DMA */
1086 memset(&config, 0, sizeof(config));
1087 config.direction = DMA_MEM_TO_DEV;
1088 config.dst_addr_width = (atmel_port->fifo_size) ?
1089 DMA_SLAVE_BUSWIDTH_4_BYTES :
1090 DMA_SLAVE_BUSWIDTH_1_BYTE;
1091 config.dst_addr = port->mapbase + ATMEL_US_THR;
1092 config.dst_maxburst = 1;
1094 ret = dmaengine_slave_config(atmel_port->chan_tx,
1097 dev_err(port->dev, "DMA tx slave configuration failed\n");
1104 dev_err(port->dev, "TX channel not available, switch to pio\n");
1105 atmel_port->use_dma_tx = 0;
1106 if (atmel_port->chan_tx)
1107 atmel_release_tx_dma(port);
1111 static void atmel_complete_rx_dma(void *arg)
1113 struct uart_port *port = arg;
1114 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1116 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1119 static void atmel_release_rx_dma(struct uart_port *port)
1121 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1122 struct dma_chan *chan = atmel_port->chan_rx;
1125 dmaengine_terminate_all(chan);
1126 dma_release_channel(chan);
1127 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1131 atmel_port->desc_rx = NULL;
1132 atmel_port->chan_rx = NULL;
1133 atmel_port->cookie_rx = -EINVAL;
1136 static void atmel_rx_from_dma(struct uart_port *port)
1138 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1139 struct tty_port *tport = &port->state->port;
1140 struct circ_buf *ring = &atmel_port->rx_ring;
1141 struct dma_chan *chan = atmel_port->chan_rx;
1142 struct dma_tx_state state;
1143 enum dma_status dmastat;
1147 /* Reset the UART timeout early so that we don't miss one */
1148 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1149 dmastat = dmaengine_tx_status(chan,
1150 atmel_port->cookie_rx,
1152 /* Restart a new tasklet if DMA status is error */
1153 if (dmastat == DMA_ERROR) {
1154 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1155 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1156 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1160 /* CPU claims ownership of RX DMA buffer */
1161 dma_sync_sg_for_cpu(port->dev,
1167 * ring->head points to the end of data already written by the DMA.
1168 * ring->tail points to the beginning of data to be read by the
1170 * The current transfer size should not be larger than the dma buffer
1173 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1174 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1176 * At this point ring->head may point to the first byte right after the
1177 * last byte of the dma buffer:
1178 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1180 * However ring->tail must always points inside the dma buffer:
1181 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1183 * Since we use a ring buffer, we have to handle the case
1184 * where head is lower than tail. In such a case, we first read from
1185 * tail to the end of the buffer then reset tail.
1187 if (ring->head < ring->tail) {
1188 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1190 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1192 port->icount.rx += count;
1195 /* Finally we read data from tail to head */
1196 if (ring->tail < ring->head) {
1197 count = ring->head - ring->tail;
1199 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1200 /* Wrap ring->head if needed */
1201 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1203 ring->tail = ring->head;
1204 port->icount.rx += count;
1207 /* USART retreives ownership of RX DMA buffer */
1208 dma_sync_sg_for_device(port->dev,
1214 * Drop the lock here since it might end up calling
1215 * uart_start(), which takes the lock.
1217 spin_unlock(&port->lock);
1218 tty_flip_buffer_push(tport);
1219 spin_lock(&port->lock);
1221 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1224 static int atmel_prepare_rx_dma(struct uart_port *port)
1226 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1227 struct device *mfd_dev = port->dev->parent;
1228 struct dma_async_tx_descriptor *desc;
1229 dma_cap_mask_t mask;
1230 struct dma_slave_config config;
1231 struct circ_buf *ring;
1234 ring = &atmel_port->rx_ring;
1237 dma_cap_set(DMA_CYCLIC, mask);
1239 atmel_port->chan_rx = dma_request_slave_channel(mfd_dev, "rx");
1240 if (atmel_port->chan_rx == NULL)
1242 dev_info(port->dev, "using %s for rx DMA transfers\n",
1243 dma_chan_name(atmel_port->chan_rx));
1245 spin_lock_init(&atmel_port->lock_rx);
1246 sg_init_table(&atmel_port->sg_rx, 1);
1247 /* UART circular rx buffer is an aligned page. */
1248 BUG_ON(!PAGE_ALIGNED(ring->buf));
1249 sg_set_page(&atmel_port->sg_rx,
1250 virt_to_page(ring->buf),
1251 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1252 offset_in_page(ring->buf));
1253 nent = dma_map_sg(port->dev,
1259 dev_dbg(port->dev, "need to release resource of dma\n");
1262 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1263 sg_dma_len(&atmel_port->sg_rx),
1265 &sg_dma_address(&atmel_port->sg_rx));
1268 /* Configure the slave DMA */
1269 memset(&config, 0, sizeof(config));
1270 config.direction = DMA_DEV_TO_MEM;
1271 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1272 config.src_addr = port->mapbase + ATMEL_US_RHR;
1273 config.src_maxburst = 1;
1275 ret = dmaengine_slave_config(atmel_port->chan_rx,
1278 dev_err(port->dev, "DMA rx slave configuration failed\n");
1282 * Prepare a cyclic dma transfer, assign 2 descriptors,
1283 * each one is half ring buffer size
1285 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1286 sg_dma_address(&atmel_port->sg_rx),
1287 sg_dma_len(&atmel_port->sg_rx),
1288 sg_dma_len(&atmel_port->sg_rx)/2,
1290 DMA_PREP_INTERRUPT);
1292 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1295 desc->callback = atmel_complete_rx_dma;
1296 desc->callback_param = port;
1297 atmel_port->desc_rx = desc;
1298 atmel_port->cookie_rx = dmaengine_submit(desc);
1303 dev_err(port->dev, "RX channel not available, switch to pio\n");
1304 atmel_port->use_dma_rx = 0;
1305 if (atmel_port->chan_rx)
1306 atmel_release_rx_dma(port);
1310 static void atmel_uart_timer_callback(struct timer_list *t)
1312 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1314 struct uart_port *port = &atmel_port->uart;
1316 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1317 tasklet_schedule(&atmel_port->tasklet_rx);
1318 mod_timer(&atmel_port->uart_timer,
1319 jiffies + uart_poll_timeout(port));
1324 * receive interrupt handler.
1327 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1329 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1331 if (atmel_use_pdc_rx(port)) {
1333 * PDC receive. Just schedule the tasklet and let it
1334 * figure out the details.
1336 * TODO: We're not handling error flags correctly at
1339 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1340 atmel_uart_writel(port, ATMEL_US_IDR,
1341 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1342 atmel_tasklet_schedule(atmel_port,
1343 &atmel_port->tasklet_rx);
1346 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1347 ATMEL_US_FRAME | ATMEL_US_PARE))
1348 atmel_pdc_rxerr(port, pending);
1351 if (atmel_use_dma_rx(port)) {
1352 if (pending & ATMEL_US_TIMEOUT) {
1353 atmel_uart_writel(port, ATMEL_US_IDR,
1355 atmel_tasklet_schedule(atmel_port,
1356 &atmel_port->tasklet_rx);
1360 /* Interrupt receive */
1361 if (pending & ATMEL_US_RXRDY)
1362 atmel_rx_chars(port);
1363 else if (pending & ATMEL_US_RXBRK) {
1365 * End of break detected. If it came along with a
1366 * character, atmel_rx_chars will handle it.
1368 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1369 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1370 atmel_port->break_active = 0;
1375 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1378 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1380 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1382 if (pending & atmel_port->tx_done_mask) {
1383 /* Either PDC or interrupt transmission */
1384 atmel_uart_writel(port, ATMEL_US_IDR,
1385 atmel_port->tx_done_mask);
1386 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1391 * status flags interrupt handler.
1394 atmel_handle_status(struct uart_port *port, unsigned int pending,
1395 unsigned int status)
1397 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1398 unsigned int status_change;
1400 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1401 | ATMEL_US_CTSIC)) {
1402 status_change = status ^ atmel_port->irq_status_prev;
1403 atmel_port->irq_status_prev = status;
1405 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1406 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1407 /* TODO: All reads to CSR will clear these interrupts! */
1408 if (status_change & ATMEL_US_RI)
1410 if (status_change & ATMEL_US_DSR)
1412 if (status_change & ATMEL_US_DCD)
1413 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1414 if (status_change & ATMEL_US_CTS)
1415 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1417 wake_up_interruptible(&port->state->port.delta_msr_wait);
1421 if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION))
1422 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending);
1428 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1430 struct uart_port *port = dev_id;
1431 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1432 unsigned int status, pending, mask, pass_counter = 0;
1434 spin_lock(&atmel_port->lock_suspended);
1437 status = atmel_get_lines_status(port);
1438 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1439 pending = status & mask;
1443 if (atmel_port->suspended) {
1444 atmel_port->pending |= pending;
1445 atmel_port->pending_status = status;
1446 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1451 atmel_handle_receive(port, pending);
1452 atmel_handle_status(port, pending, status);
1453 atmel_handle_transmit(port, pending);
1454 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1456 spin_unlock(&atmel_port->lock_suspended);
1458 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1461 static void atmel_release_tx_pdc(struct uart_port *port)
1463 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1464 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1466 dma_unmap_single(port->dev,
1473 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1475 static void atmel_tx_pdc(struct uart_port *port)
1477 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1478 struct circ_buf *xmit = &port->state->xmit;
1479 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1482 /* nothing left to transmit? */
1483 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1486 xmit->tail += pdc->ofs;
1487 xmit->tail &= UART_XMIT_SIZE - 1;
1489 port->icount.tx += pdc->ofs;
1492 /* more to transmit - setup next transfer */
1494 /* disable PDC transmit */
1495 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1497 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1498 dma_sync_single_for_device(port->dev,
1503 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1506 atmel_uart_writel(port, ATMEL_PDC_TPR,
1507 pdc->dma_addr + xmit->tail);
1508 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1509 /* re-enable PDC transmit */
1510 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1511 /* Enable interrupts */
1512 atmel_uart_writel(port, ATMEL_US_IER,
1513 atmel_port->tx_done_mask);
1515 if (((port->rs485.flags & SER_RS485_ENABLED) &&
1516 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
1517 port->iso7816.flags & SER_ISO7816_ENABLED) {
1518 /* DMA done, stop TX, start RX for RS485 */
1519 atmel_start_rx(port);
1523 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1524 uart_write_wakeup(port);
1527 static int atmel_prepare_tx_pdc(struct uart_port *port)
1529 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1530 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1531 struct circ_buf *xmit = &port->state->xmit;
1533 pdc->buf = xmit->buf;
1534 pdc->dma_addr = dma_map_single(port->dev,
1538 pdc->dma_size = UART_XMIT_SIZE;
1544 static void atmel_rx_from_ring(struct uart_port *port)
1546 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1547 struct circ_buf *ring = &atmel_port->rx_ring;
1549 unsigned int status;
1551 while (ring->head != ring->tail) {
1552 struct atmel_uart_char c;
1554 /* Make sure c is loaded after head. */
1557 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1559 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1566 * note that the error handling code is
1567 * out of the main execution path
1569 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1570 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1571 if (status & ATMEL_US_RXBRK) {
1572 /* ignore side-effect */
1573 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1576 if (uart_handle_break(port))
1579 if (status & ATMEL_US_PARE)
1580 port->icount.parity++;
1581 if (status & ATMEL_US_FRAME)
1582 port->icount.frame++;
1583 if (status & ATMEL_US_OVRE)
1584 port->icount.overrun++;
1586 status &= port->read_status_mask;
1588 if (status & ATMEL_US_RXBRK)
1590 else if (status & ATMEL_US_PARE)
1592 else if (status & ATMEL_US_FRAME)
1597 if (uart_handle_sysrq_char(port, c.ch))
1600 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1604 * Drop the lock here since it might end up calling
1605 * uart_start(), which takes the lock.
1607 spin_unlock(&port->lock);
1608 tty_flip_buffer_push(&port->state->port);
1609 spin_lock(&port->lock);
1612 static void atmel_release_rx_pdc(struct uart_port *port)
1614 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1617 for (i = 0; i < 2; i++) {
1618 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1620 dma_unmap_single(port->dev,
1628 static void atmel_rx_from_pdc(struct uart_port *port)
1630 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1631 struct tty_port *tport = &port->state->port;
1632 struct atmel_dma_buffer *pdc;
1633 int rx_idx = atmel_port->pdc_rx_idx;
1639 /* Reset the UART timeout early so that we don't miss one */
1640 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1642 pdc = &atmel_port->pdc_rx[rx_idx];
1643 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1646 /* If the PDC has switched buffers, RPR won't contain
1647 * any address within the current buffer. Since head
1648 * is unsigned, we just need a one-way comparison to
1651 * In this case, we just need to consume the entire
1652 * buffer and resubmit it for DMA. This will clear the
1653 * ENDRX bit as well, so that we can safely re-enable
1654 * all interrupts below.
1656 head = min(head, pdc->dma_size);
1658 if (likely(head != tail)) {
1659 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1660 pdc->dma_size, DMA_FROM_DEVICE);
1663 * head will only wrap around when we recycle
1664 * the DMA buffer, and when that happens, we
1665 * explicitly set tail to 0. So head will
1666 * always be greater than tail.
1668 count = head - tail;
1670 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1673 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1674 pdc->dma_size, DMA_FROM_DEVICE);
1676 port->icount.rx += count;
1681 * If the current buffer is full, we need to check if
1682 * the next one contains any additional data.
1684 if (head >= pdc->dma_size) {
1686 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1687 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1690 atmel_port->pdc_rx_idx = rx_idx;
1692 } while (head >= pdc->dma_size);
1695 * Drop the lock here since it might end up calling
1696 * uart_start(), which takes the lock.
1698 spin_unlock(&port->lock);
1699 tty_flip_buffer_push(tport);
1700 spin_lock(&port->lock);
1702 atmel_uart_writel(port, ATMEL_US_IER,
1703 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1706 static int atmel_prepare_rx_pdc(struct uart_port *port)
1708 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1711 for (i = 0; i < 2; i++) {
1712 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1714 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1715 if (pdc->buf == NULL) {
1717 dma_unmap_single(port->dev,
1718 atmel_port->pdc_rx[0].dma_addr,
1721 kfree(atmel_port->pdc_rx[0].buf);
1723 atmel_port->use_pdc_rx = 0;
1726 pdc->dma_addr = dma_map_single(port->dev,
1730 pdc->dma_size = PDC_BUFFER_SIZE;
1734 atmel_port->pdc_rx_idx = 0;
1736 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1737 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1739 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1740 atmel_port->pdc_rx[1].dma_addr);
1741 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1747 * tasklet handling tty stuff outside the interrupt handler.
1749 static void atmel_tasklet_rx_func(unsigned long data)
1751 struct uart_port *port = (struct uart_port *)data;
1752 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1754 /* The interrupt handler does not take the lock */
1755 spin_lock(&port->lock);
1756 atmel_port->schedule_rx(port);
1757 spin_unlock(&port->lock);
1760 static void atmel_tasklet_tx_func(unsigned long data)
1762 struct uart_port *port = (struct uart_port *)data;
1763 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1765 /* The interrupt handler does not take the lock */
1766 spin_lock(&port->lock);
1767 atmel_port->schedule_tx(port);
1768 spin_unlock(&port->lock);
1771 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1772 struct platform_device *pdev)
1774 struct device_node *np = pdev->dev.of_node;
1776 /* DMA/PDC usage specification */
1777 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1778 if (of_property_read_bool(np, "dmas")) {
1779 atmel_port->use_dma_rx = true;
1780 atmel_port->use_pdc_rx = false;
1782 atmel_port->use_dma_rx = false;
1783 atmel_port->use_pdc_rx = true;
1786 atmel_port->use_dma_rx = false;
1787 atmel_port->use_pdc_rx = false;
1790 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1791 if (of_property_read_bool(np, "dmas")) {
1792 atmel_port->use_dma_tx = true;
1793 atmel_port->use_pdc_tx = false;
1795 atmel_port->use_dma_tx = false;
1796 atmel_port->use_pdc_tx = true;
1799 atmel_port->use_dma_tx = false;
1800 atmel_port->use_pdc_tx = false;
1804 static void atmel_set_ops(struct uart_port *port)
1806 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1808 if (atmel_use_dma_rx(port)) {
1809 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1810 atmel_port->schedule_rx = &atmel_rx_from_dma;
1811 atmel_port->release_rx = &atmel_release_rx_dma;
1812 } else if (atmel_use_pdc_rx(port)) {
1813 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1814 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1815 atmel_port->release_rx = &atmel_release_rx_pdc;
1817 atmel_port->prepare_rx = NULL;
1818 atmel_port->schedule_rx = &atmel_rx_from_ring;
1819 atmel_port->release_rx = NULL;
1822 if (atmel_use_dma_tx(port)) {
1823 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1824 atmel_port->schedule_tx = &atmel_tx_dma;
1825 atmel_port->release_tx = &atmel_release_tx_dma;
1826 } else if (atmel_use_pdc_tx(port)) {
1827 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1828 atmel_port->schedule_tx = &atmel_tx_pdc;
1829 atmel_port->release_tx = &atmel_release_tx_pdc;
1831 atmel_port->prepare_tx = NULL;
1832 atmel_port->schedule_tx = &atmel_tx_chars;
1833 atmel_port->release_tx = NULL;
1838 * Get ip name usart or uart
1840 static void atmel_get_ip_name(struct uart_port *port)
1842 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1843 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1845 u32 usart, dbgu_uart, new_uart;
1846 /* ASCII decoding for IP version */
1847 usart = 0x55534152; /* USAR(T) */
1848 dbgu_uart = 0x44424755; /* DBGU */
1849 new_uart = 0x55415254; /* UART */
1852 * Only USART devices from at91sam9260 SOC implement fractional
1853 * baudrate. It is available for all asynchronous modes, with the
1854 * following restriction: the sampling clock's duty cycle is not
1857 atmel_port->has_frac_baudrate = false;
1858 atmel_port->has_hw_timer = false;
1860 if (name == new_uart) {
1861 dev_dbg(port->dev, "Uart with hw timer");
1862 atmel_port->has_hw_timer = true;
1863 atmel_port->rtor = ATMEL_UA_RTOR;
1864 } else if (name == usart) {
1865 dev_dbg(port->dev, "Usart\n");
1866 atmel_port->has_frac_baudrate = true;
1867 atmel_port->has_hw_timer = true;
1868 atmel_port->rtor = ATMEL_US_RTOR;
1869 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1871 case 0x814: /* sama5d2 */
1873 case 0x701: /* sama5d4 */
1874 atmel_port->fidi_min = 3;
1875 atmel_port->fidi_max = 65535;
1877 case 0x502: /* sam9x5, sama5d3 */
1878 atmel_port->fidi_min = 3;
1879 atmel_port->fidi_max = 2047;
1882 atmel_port->fidi_min = 1;
1883 atmel_port->fidi_max = 2047;
1885 } else if (name == dbgu_uart) {
1886 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1888 /* fallback for older SoCs: use version field */
1889 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1894 dev_dbg(port->dev, "This version is usart\n");
1895 atmel_port->has_frac_baudrate = true;
1896 atmel_port->has_hw_timer = true;
1897 atmel_port->rtor = ATMEL_US_RTOR;
1901 dev_dbg(port->dev, "This version is uart\n");
1904 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1910 * Perform initialization and enable port for reception
1912 static int atmel_startup(struct uart_port *port)
1914 struct platform_device *pdev = to_platform_device(port->dev);
1915 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1919 * Ensure that no interrupts are enabled otherwise when
1920 * request_irq() is called we could get stuck trying to
1921 * handle an unexpected interrupt
1923 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1924 atmel_port->ms_irq_enabled = false;
1929 retval = request_irq(port->irq, atmel_interrupt,
1930 IRQF_SHARED | IRQF_COND_SUSPEND,
1931 dev_name(&pdev->dev), port);
1933 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1937 atomic_set(&atmel_port->tasklet_shutdown, 0);
1938 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1939 (unsigned long)port);
1940 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1941 (unsigned long)port);
1944 * Initialize DMA (if necessary)
1946 atmel_init_property(atmel_port, pdev);
1947 atmel_set_ops(port);
1949 if (atmel_port->prepare_rx) {
1950 retval = atmel_port->prepare_rx(port);
1952 atmel_set_ops(port);
1955 if (atmel_port->prepare_tx) {
1956 retval = atmel_port->prepare_tx(port);
1958 atmel_set_ops(port);
1962 * Enable FIFO when available
1964 if (atmel_port->fifo_size) {
1965 unsigned int txrdym = ATMEL_US_ONE_DATA;
1966 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1969 atmel_uart_writel(port, ATMEL_US_CR,
1974 if (atmel_use_dma_tx(port))
1975 txrdym = ATMEL_US_FOUR_DATA;
1977 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1978 if (atmel_port->rts_high &&
1979 atmel_port->rts_low)
1980 fmr |= ATMEL_US_FRTSC |
1981 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1982 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1984 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1987 /* Save current CSR for comparison in atmel_tasklet_func() */
1988 atmel_port->irq_status_prev = atmel_get_lines_status(port);
1991 * Finally, enable the serial port
1993 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1994 /* enable xmit & rcvr */
1995 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1996 atmel_port->tx_stopped = false;
1998 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
2000 if (atmel_use_pdc_rx(port)) {
2001 /* set UART timeout */
2002 if (!atmel_port->has_hw_timer) {
2003 mod_timer(&atmel_port->uart_timer,
2004 jiffies + uart_poll_timeout(port));
2005 /* set USART timeout */
2007 atmel_uart_writel(port, atmel_port->rtor,
2009 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
2011 atmel_uart_writel(port, ATMEL_US_IER,
2012 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
2014 /* enable PDC controller */
2015 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
2016 } else if (atmel_use_dma_rx(port)) {
2017 /* set UART timeout */
2018 if (!atmel_port->has_hw_timer) {
2019 mod_timer(&atmel_port->uart_timer,
2020 jiffies + uart_poll_timeout(port));
2021 /* set USART timeout */
2023 atmel_uart_writel(port, atmel_port->rtor,
2025 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
2027 atmel_uart_writel(port, ATMEL_US_IER,
2031 /* enable receive only */
2032 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
2039 * Flush any TX data submitted for DMA. Called when the TX circular
2042 static void atmel_flush_buffer(struct uart_port *port)
2044 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2046 if (atmel_use_pdc_tx(port)) {
2047 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
2048 atmel_port->pdc_tx.ofs = 0;
2051 * in uart_flush_buffer(), the xmit circular buffer has just
2052 * been cleared, so we have to reset tx_len accordingly.
2054 atmel_port->tx_len = 0;
2060 static void atmel_shutdown(struct uart_port *port)
2062 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2064 /* Disable modem control lines interrupts */
2065 atmel_disable_ms(port);
2067 /* Disable interrupts at device level */
2068 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2070 /* Prevent spurious interrupts from scheduling the tasklet */
2071 atomic_inc(&atmel_port->tasklet_shutdown);
2074 * Prevent any tasklets being scheduled during
2077 del_timer_sync(&atmel_port->uart_timer);
2079 /* Make sure that no interrupt is on the fly */
2080 synchronize_irq(port->irq);
2083 * Clear out any scheduled tasklets before
2084 * we destroy the buffers
2086 tasklet_kill(&atmel_port->tasklet_rx);
2087 tasklet_kill(&atmel_port->tasklet_tx);
2090 * Ensure everything is stopped and
2091 * disable port and break condition.
2093 atmel_stop_rx(port);
2094 atmel_stop_tx(port);
2096 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
2099 * Shut-down the DMA.
2101 if (atmel_port->release_rx)
2102 atmel_port->release_rx(port);
2103 if (atmel_port->release_tx)
2104 atmel_port->release_tx(port);
2107 * Reset ring buffer pointers
2109 atmel_port->rx_ring.head = 0;
2110 atmel_port->rx_ring.tail = 0;
2113 * Free the interrupts
2115 free_irq(port->irq, port);
2117 atmel_flush_buffer(port);
2121 * Power / Clock management.
2123 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2124 unsigned int oldstate)
2126 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2131 * Enable the peripheral clock for this serial port.
2132 * This is called on uart_open() or a resume event.
2134 clk_prepare_enable(atmel_port->clk);
2136 /* re-enable interrupts if we disabled some on suspend */
2137 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2140 /* Back up the interrupt mask and disable all interrupts */
2141 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2142 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2145 * Disable the peripheral clock for this serial port.
2146 * This is called on uart_close() or a suspend event.
2148 clk_disable_unprepare(atmel_port->clk);
2151 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2156 * Change the port parameters
2158 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2159 struct ktermios *old)
2161 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2162 unsigned long flags;
2163 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2165 /* save the current mode register */
2166 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2168 /* reset the mode, clock divisor, parity, stop bits and data size */
2169 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2170 ATMEL_US_PAR | ATMEL_US_USMODE);
2172 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2175 switch (termios->c_cflag & CSIZE) {
2177 mode |= ATMEL_US_CHRL_5;
2180 mode |= ATMEL_US_CHRL_6;
2183 mode |= ATMEL_US_CHRL_7;
2186 mode |= ATMEL_US_CHRL_8;
2191 if (termios->c_cflag & CSTOPB)
2192 mode |= ATMEL_US_NBSTOP_2;
2195 if (termios->c_cflag & PARENB) {
2196 /* Mark or Space parity */
2197 if (termios->c_cflag & CMSPAR) {
2198 if (termios->c_cflag & PARODD)
2199 mode |= ATMEL_US_PAR_MARK;
2201 mode |= ATMEL_US_PAR_SPACE;
2202 } else if (termios->c_cflag & PARODD)
2203 mode |= ATMEL_US_PAR_ODD;
2205 mode |= ATMEL_US_PAR_EVEN;
2207 mode |= ATMEL_US_PAR_NONE;
2209 spin_lock_irqsave(&port->lock, flags);
2211 port->read_status_mask = ATMEL_US_OVRE;
2212 if (termios->c_iflag & INPCK)
2213 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2214 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2215 port->read_status_mask |= ATMEL_US_RXBRK;
2217 if (atmel_use_pdc_rx(port))
2218 /* need to enable error interrupts */
2219 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2222 * Characters to ignore
2224 port->ignore_status_mask = 0;
2225 if (termios->c_iflag & IGNPAR)
2226 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2227 if (termios->c_iflag & IGNBRK) {
2228 port->ignore_status_mask |= ATMEL_US_RXBRK;
2230 * If we're ignoring parity and break indicators,
2231 * ignore overruns too (for real raw support).
2233 if (termios->c_iflag & IGNPAR)
2234 port->ignore_status_mask |= ATMEL_US_OVRE;
2236 /* TODO: Ignore all characters if CREAD is set.*/
2238 /* update the per-port timeout */
2239 uart_update_timeout(port, termios->c_cflag, baud);
2242 * save/disable interrupts. The tty layer will ensure that the
2243 * transmitter is empty if requested by the caller, so there's
2244 * no need to wait for it here.
2246 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2247 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2249 /* disable receiver and transmitter */
2250 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2251 atmel_port->tx_stopped = true;
2254 if (port->rs485.flags & SER_RS485_ENABLED) {
2255 atmel_uart_writel(port, ATMEL_US_TTGR,
2256 port->rs485.delay_rts_after_send);
2257 mode |= ATMEL_US_USMODE_RS485;
2258 } else if (port->iso7816.flags & SER_ISO7816_ENABLED) {
2259 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg);
2260 /* select mck clock, and output */
2261 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
2262 /* set max iterations */
2263 mode |= ATMEL_US_MAX_ITER(3);
2264 if ((port->iso7816.flags & SER_ISO7816_T_PARAM)
2265 == SER_ISO7816_T(0))
2266 mode |= ATMEL_US_USMODE_ISO7816_T0;
2268 mode |= ATMEL_US_USMODE_ISO7816_T1;
2269 } else if (termios->c_cflag & CRTSCTS) {
2270 /* RS232 with hardware handshake (RTS/CTS) */
2271 if (atmel_use_fifo(port) &&
2272 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2274 * with ATMEL_US_USMODE_HWHS set, the controller will
2275 * be able to drive the RTS pin high/low when the RX
2276 * FIFO is above RXFTHRES/below RXFTHRES2.
2277 * It will also disable the transmitter when the CTS
2279 * This mode is not activated if CTS pin is a GPIO
2280 * because in this case, the transmitter is always
2281 * disabled (there must be an internal pull-up
2282 * responsible for this behaviour).
2283 * If the RTS pin is a GPIO, the controller won't be
2284 * able to drive it according to the FIFO thresholds,
2285 * but it will be handled by the driver.
2287 mode |= ATMEL_US_USMODE_HWHS;
2290 * For platforms without FIFO, the flow control is
2291 * handled by the driver.
2293 mode |= ATMEL_US_USMODE_NORMAL;
2296 /* RS232 without hadware handshake */
2297 mode |= ATMEL_US_USMODE_NORMAL;
2300 /* set the mode, clock divisor, parity, stop bits and data size */
2301 atmel_uart_writel(port, ATMEL_US_MR, mode);
2304 * when switching the mode, set the RTS line state according to the
2305 * new mode, otherwise keep the former state
2307 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2308 unsigned int rts_state;
2310 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2311 /* let the hardware control the RTS line */
2312 rts_state = ATMEL_US_RTSDIS;
2314 /* force RTS line to low level */
2315 rts_state = ATMEL_US_RTSEN;
2318 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2322 * Set the baud rate:
2323 * Fractional baudrate allows to setup output frequency more
2324 * accurately. This feature is enabled only when using normal mode.
2325 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2326 * Currently, OVER is always set to 0 so we get
2327 * baudrate = selected clock / (16 * (CD + FP / 8))
2329 * 8 CD + FP = selected clock / (2 * baudrate)
2331 if (atmel_port->has_frac_baudrate) {
2332 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2334 fp = div & ATMEL_US_FP_MASK;
2336 cd = uart_get_divisor(port, baud);
2339 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2341 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2343 quot = cd | fp << ATMEL_US_FP_OFFSET;
2345 if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
2346 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2347 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2348 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2349 atmel_port->tx_stopped = false;
2351 /* restore interrupts */
2352 atmel_uart_writel(port, ATMEL_US_IER, imr);
2354 /* CTS flow-control and modem-status interrupts */
2355 if (UART_ENABLE_MS(port, termios->c_cflag))
2356 atmel_enable_ms(port);
2358 atmel_disable_ms(port);
2360 spin_unlock_irqrestore(&port->lock, flags);
2363 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2365 if (termios->c_line == N_PPS) {
2366 port->flags |= UPF_HARDPPS_CD;
2367 spin_lock_irq(&port->lock);
2368 atmel_enable_ms(port);
2369 spin_unlock_irq(&port->lock);
2371 port->flags &= ~UPF_HARDPPS_CD;
2372 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2373 spin_lock_irq(&port->lock);
2374 atmel_disable_ms(port);
2375 spin_unlock_irq(&port->lock);
2381 * Return string describing the specified port
2383 static const char *atmel_type(struct uart_port *port)
2385 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2389 * Release the memory region(s) being used by 'port'.
2391 static void atmel_release_port(struct uart_port *port)
2393 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2394 int size = resource_size(mpdev->resource);
2396 release_mem_region(port->mapbase, size);
2398 if (port->flags & UPF_IOREMAP) {
2399 iounmap(port->membase);
2400 port->membase = NULL;
2405 * Request the memory region(s) being used by 'port'.
2407 static int atmel_request_port(struct uart_port *port)
2409 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2410 int size = resource_size(mpdev->resource);
2412 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2415 if (port->flags & UPF_IOREMAP) {
2416 port->membase = ioremap(port->mapbase, size);
2417 if (port->membase == NULL) {
2418 release_mem_region(port->mapbase, size);
2427 * Configure/autoconfigure the port.
2429 static void atmel_config_port(struct uart_port *port, int flags)
2431 if (flags & UART_CONFIG_TYPE) {
2432 port->type = PORT_ATMEL;
2433 atmel_request_port(port);
2438 * Verify the new serial_struct (for TIOCSSERIAL).
2440 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2443 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2445 if (port->irq != ser->irq)
2447 if (ser->io_type != SERIAL_IO_MEM)
2449 if (port->uartclk / 16 != ser->baud_base)
2451 if (port->mapbase != (unsigned long)ser->iomem_base)
2453 if (port->iobase != ser->port)
2460 #ifdef CONFIG_CONSOLE_POLL
2461 static int atmel_poll_get_char(struct uart_port *port)
2463 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2466 return atmel_uart_read_char(port);
2469 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2471 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2474 atmel_uart_write_char(port, ch);
2478 static const struct uart_ops atmel_pops = {
2479 .tx_empty = atmel_tx_empty,
2480 .set_mctrl = atmel_set_mctrl,
2481 .get_mctrl = atmel_get_mctrl,
2482 .stop_tx = atmel_stop_tx,
2483 .start_tx = atmel_start_tx,
2484 .stop_rx = atmel_stop_rx,
2485 .enable_ms = atmel_enable_ms,
2486 .break_ctl = atmel_break_ctl,
2487 .startup = atmel_startup,
2488 .shutdown = atmel_shutdown,
2489 .flush_buffer = atmel_flush_buffer,
2490 .set_termios = atmel_set_termios,
2491 .set_ldisc = atmel_set_ldisc,
2493 .release_port = atmel_release_port,
2494 .request_port = atmel_request_port,
2495 .config_port = atmel_config_port,
2496 .verify_port = atmel_verify_port,
2497 .pm = atmel_serial_pm,
2498 #ifdef CONFIG_CONSOLE_POLL
2499 .poll_get_char = atmel_poll_get_char,
2500 .poll_put_char = atmel_poll_put_char,
2505 * Configure the port from the platform device resource info.
2507 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2508 struct platform_device *pdev)
2511 struct uart_port *port = &atmel_port->uart;
2512 struct platform_device *mpdev = to_platform_device(pdev->dev.parent);
2514 atmel_init_property(atmel_port, pdev);
2515 atmel_set_ops(port);
2517 uart_get_rs485_mode(&mpdev->dev, &port->rs485);
2519 port->iotype = UPIO_MEM;
2520 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
2521 port->ops = &atmel_pops;
2523 port->dev = &pdev->dev;
2524 port->mapbase = mpdev->resource[0].start;
2525 port->irq = mpdev->resource[1].start;
2526 port->rs485_config = atmel_config_rs485;
2527 port->iso7816_config = atmel_config_iso7816;
2528 port->membase = NULL;
2530 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2532 /* for console, the clock could already be configured */
2533 if (!atmel_port->clk) {
2534 atmel_port->clk = clk_get(&mpdev->dev, "usart");
2535 if (IS_ERR(atmel_port->clk)) {
2536 ret = PTR_ERR(atmel_port->clk);
2537 atmel_port->clk = NULL;
2540 ret = clk_prepare_enable(atmel_port->clk);
2542 clk_put(atmel_port->clk);
2543 atmel_port->clk = NULL;
2546 port->uartclk = clk_get_rate(atmel_port->clk);
2547 clk_disable_unprepare(atmel_port->clk);
2548 /* only enable clock when USART is in use */
2552 * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or
2555 if (port->rs485.flags & SER_RS485_ENABLED ||
2556 port->iso7816.flags & SER_ISO7816_ENABLED)
2557 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2558 else if (atmel_use_pdc_tx(port)) {
2559 port->fifosize = PDC_BUFFER_SIZE;
2560 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2562 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2568 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2569 static void atmel_console_putchar(struct uart_port *port, int ch)
2571 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2573 atmel_uart_write_char(port, ch);
2577 * Interrupts are disabled on entering
2579 static void atmel_console_write(struct console *co, const char *s, u_int count)
2581 struct uart_port *port = &atmel_ports[co->index].uart;
2582 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2583 unsigned int status, imr;
2584 unsigned int pdc_tx;
2587 * First, save IMR and then disable interrupts
2589 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2590 atmel_uart_writel(port, ATMEL_US_IDR,
2591 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2593 /* Store PDC transmit status and disable it */
2594 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2595 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2597 /* Make sure that tx path is actually able to send characters */
2598 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2599 atmel_port->tx_stopped = false;
2601 uart_console_write(port, s, count, atmel_console_putchar);
2604 * Finally, wait for transmitter to become empty
2608 status = atmel_uart_readl(port, ATMEL_US_CSR);
2609 } while (!(status & ATMEL_US_TXRDY));
2611 /* Restore PDC transmit status */
2613 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2615 /* set interrupts back the way they were */
2616 atmel_uart_writel(port, ATMEL_US_IER, imr);
2620 * If the port was already initialised (eg, by a boot loader),
2621 * try to determine the current setup.
2623 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2624 int *parity, int *bits)
2626 unsigned int mr, quot;
2629 * If the baud rate generator isn't running, the port wasn't
2630 * initialized by the boot loader.
2632 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2636 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2637 if (mr == ATMEL_US_CHRL_8)
2642 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2643 if (mr == ATMEL_US_PAR_EVEN)
2645 else if (mr == ATMEL_US_PAR_ODD)
2649 * The serial core only rounds down when matching this to a
2650 * supported baud rate. Make sure we don't end up slightly
2651 * lower than one of those, as it would make us fall through
2652 * to a much lower baud rate than we really want.
2654 *baud = port->uartclk / (16 * (quot - 1));
2657 static int __init atmel_console_setup(struct console *co, char *options)
2660 struct uart_port *port = &atmel_ports[co->index].uart;
2661 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2667 if (port->membase == NULL) {
2668 /* Port not initialized yet - delay setup */
2672 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2676 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2677 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2678 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2679 atmel_port->tx_stopped = false;
2682 uart_parse_options(options, &baud, &parity, &bits, &flow);
2684 atmel_console_get_options(port, &baud, &parity, &bits);
2686 return uart_set_options(port, co, baud, parity, bits, flow);
2689 static struct uart_driver atmel_uart;
2691 static struct console atmel_console = {
2692 .name = ATMEL_DEVICENAME,
2693 .write = atmel_console_write,
2694 .device = uart_console_device,
2695 .setup = atmel_console_setup,
2696 .flags = CON_PRINTBUFFER,
2698 .data = &atmel_uart,
2701 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2703 static inline bool atmel_is_console_port(struct uart_port *port)
2705 return port->cons && port->cons->index == port->line;
2709 #define ATMEL_CONSOLE_DEVICE NULL
2711 static inline bool atmel_is_console_port(struct uart_port *port)
2717 static struct uart_driver atmel_uart = {
2718 .owner = THIS_MODULE,
2719 .driver_name = "atmel_serial",
2720 .dev_name = ATMEL_DEVICENAME,
2721 .major = SERIAL_ATMEL_MAJOR,
2722 .minor = MINOR_START,
2723 .nr = ATMEL_MAX_UART,
2724 .cons = ATMEL_CONSOLE_DEVICE,
2728 static bool atmel_serial_clk_will_stop(void)
2730 #ifdef CONFIG_ARCH_AT91
2731 return at91_suspend_entering_slow_clock();
2737 static int atmel_serial_suspend(struct platform_device *pdev,
2740 struct uart_port *port = platform_get_drvdata(pdev);
2741 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2743 if (atmel_is_console_port(port) && console_suspend_enabled) {
2744 /* Drain the TX shifter */
2745 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2750 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2751 /* Cache register values as we won't get a full shutdown/startup
2754 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2755 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2756 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2757 atmel_port->cache.rtor = atmel_uart_readl(port,
2759 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2760 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2761 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2764 /* we can not wake up if we're running on slow clock */
2765 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2766 if (atmel_serial_clk_will_stop()) {
2767 unsigned long flags;
2769 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2770 atmel_port->suspended = true;
2771 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2772 device_set_wakeup_enable(&pdev->dev, 0);
2775 uart_suspend_port(&atmel_uart, port);
2780 static int atmel_serial_resume(struct platform_device *pdev)
2782 struct uart_port *port = platform_get_drvdata(pdev);
2783 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2784 unsigned long flags;
2786 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2787 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2788 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2789 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2790 atmel_uart_writel(port, atmel_port->rtor,
2791 atmel_port->cache.rtor);
2792 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2794 if (atmel_port->fifo_size) {
2795 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2796 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2797 atmel_uart_writel(port, ATMEL_US_FMR,
2798 atmel_port->cache.fmr);
2799 atmel_uart_writel(port, ATMEL_US_FIER,
2800 atmel_port->cache.fimr);
2802 atmel_start_rx(port);
2805 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2806 if (atmel_port->pending) {
2807 atmel_handle_receive(port, atmel_port->pending);
2808 atmel_handle_status(port, atmel_port->pending,
2809 atmel_port->pending_status);
2810 atmel_handle_transmit(port, atmel_port->pending);
2811 atmel_port->pending = 0;
2813 atmel_port->suspended = false;
2814 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2816 uart_resume_port(&atmel_uart, port);
2817 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2822 #define atmel_serial_suspend NULL
2823 #define atmel_serial_resume NULL
2826 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2827 struct platform_device *pdev)
2829 atmel_port->fifo_size = 0;
2830 atmel_port->rts_low = 0;
2831 atmel_port->rts_high = 0;
2833 if (of_property_read_u32(pdev->dev.of_node,
2835 &atmel_port->fifo_size))
2838 if (!atmel_port->fifo_size)
2841 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2842 atmel_port->fifo_size = 0;
2843 dev_err(&pdev->dev, "Invalid FIFO size\n");
2848 * 0 <= rts_low <= rts_high <= fifo_size
2849 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2850 * to flush their internal TX FIFO, commonly up to 16 data, before
2851 * actually stopping to send new data. So we try to set the RTS High
2852 * Threshold to a reasonably high value respecting this 16 data
2853 * empirical rule when possible.
2855 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2856 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2857 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2858 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2860 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2861 atmel_port->fifo_size);
2862 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2863 atmel_port->rts_high);
2864 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2865 atmel_port->rts_low);
2868 static int atmel_serial_probe(struct platform_device *pdev)
2870 struct atmel_uart_port *atmel_port;
2871 struct device_node *np = pdev->dev.parent->of_node;
2876 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2879 * In device tree there is no node with "atmel,at91rm9200-usart-serial"
2880 * as compatible string. This driver is probed by at91-usart mfd driver
2881 * which is just a wrapper over the atmel_serial driver and
2882 * spi-at91-usart driver. All attributes needed by this driver are
2883 * found in of_node of parent.
2885 pdev->dev.of_node = np;
2887 ret = of_alias_get_id(np, "serial");
2889 /* port id not found in platform data nor device-tree aliases:
2890 * auto-enumerate it */
2891 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2893 if (ret >= ATMEL_MAX_UART) {
2898 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2899 /* port already in use */
2904 atmel_port = &atmel_ports[ret];
2905 atmel_port->backup_imr = 0;
2906 atmel_port->uart.line = ret;
2907 atmel_serial_probe_fifos(atmel_port, pdev);
2909 atomic_set(&atmel_port->tasklet_shutdown, 0);
2910 spin_lock_init(&atmel_port->lock_suspended);
2912 ret = atmel_init_port(atmel_port, pdev);
2916 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2917 if (IS_ERR(atmel_port->gpios)) {
2918 ret = PTR_ERR(atmel_port->gpios);
2922 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2924 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
2925 sizeof(struct atmel_uart_char),
2928 goto err_alloc_ring;
2929 atmel_port->rx_ring.buf = data;
2932 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2934 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2938 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2939 if (atmel_is_console_port(&atmel_port->uart)
2940 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2942 * The serial core enabled the clock for us, so undo
2943 * the clk_prepare_enable() in atmel_console_setup()
2945 clk_disable_unprepare(atmel_port->clk);
2949 device_init_wakeup(&pdev->dev, 1);
2950 platform_set_drvdata(pdev, atmel_port);
2953 * The peripheral clock has been disabled by atmel_init_port():
2954 * enable it before accessing I/O registers
2956 clk_prepare_enable(atmel_port->clk);
2958 if (rs485_enabled) {
2959 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2960 ATMEL_US_USMODE_NORMAL);
2961 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2966 * Get port name of usart or uart
2968 atmel_get_ip_name(&atmel_port->uart);
2971 * The peripheral clock can now safely be disabled till the port
2974 clk_disable_unprepare(atmel_port->clk);
2979 kfree(atmel_port->rx_ring.buf);
2980 atmel_port->rx_ring.buf = NULL;
2982 if (!atmel_is_console_port(&atmel_port->uart)) {
2983 clk_put(atmel_port->clk);
2984 atmel_port->clk = NULL;
2987 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2993 * Even if the driver is not modular, it makes sense to be able to
2994 * unbind a device: there can be many bound devices, and there are
2995 * situations where dynamic binding and unbinding can be useful.
2997 * For example, a connected device can require a specific firmware update
2998 * protocol that needs bitbanging on IO lines, but use the regular serial
2999 * port in the normal case.
3001 static int atmel_serial_remove(struct platform_device *pdev)
3003 struct uart_port *port = platform_get_drvdata(pdev);
3004 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
3007 tasklet_kill(&atmel_port->tasklet_rx);
3008 tasklet_kill(&atmel_port->tasklet_tx);
3010 device_init_wakeup(&pdev->dev, 0);
3012 ret = uart_remove_one_port(&atmel_uart, port);
3014 kfree(atmel_port->rx_ring.buf);
3016 /* "port" is allocated statically, so we shouldn't free it */
3018 clear_bit(port->line, atmel_ports_in_use);
3020 clk_put(atmel_port->clk);
3021 atmel_port->clk = NULL;
3022 pdev->dev.of_node = NULL;
3027 static struct platform_driver atmel_serial_driver = {
3028 .probe = atmel_serial_probe,
3029 .remove = atmel_serial_remove,
3030 .suspend = atmel_serial_suspend,
3031 .resume = atmel_serial_resume,
3033 .name = "atmel_usart_serial",
3034 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
3038 static int __init atmel_serial_init(void)
3042 ret = uart_register_driver(&atmel_uart);
3046 ret = platform_driver_register(&atmel_serial_driver);
3048 uart_unregister_driver(&atmel_uart);
3052 device_initcall(atmel_serial_init);