1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for AMBA serial ports
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 * Copyright 1999 ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
9 * Copyright (C) 2010 ST-Ericsson SA
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
13 * Note that although they do have CTS, DCD and DSR inputs, they do
14 * not have an RI input, nor do they have DTR or RTS outputs. If
15 * required, these have to be supplied via some other means (eg, GPIO)
16 * and hooked into this driver.
19 #include <linux/module.h>
20 #include <linux/ioport.h>
21 #include <linux/init.h>
22 #include <linux/console.h>
23 #include <linux/sysrq.h>
24 #include <linux/device.h>
25 #include <linux/tty.h>
26 #include <linux/tty_flip.h>
27 #include <linux/serial_core.h>
28 #include <linux/serial.h>
29 #include <linux/amba/bus.h>
30 #include <linux/amba/serial.h>
31 #include <linux/clk.h>
32 #include <linux/slab.h>
33 #include <linux/dmaengine.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/scatterlist.h>
36 #include <linux/delay.h>
37 #include <linux/types.h>
39 #include <linux/of_device.h>
40 #include <linux/pinctrl/consumer.h>
41 #include <linux/sizes.h>
43 #include <linux/acpi.h>
45 #include "amba-pl011.h"
49 #define SERIAL_AMBA_MAJOR 204
50 #define SERIAL_AMBA_MINOR 64
51 #define SERIAL_AMBA_NR UART_NR
53 #define AMBA_ISR_PASS_LIMIT 256
55 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
56 #define UART_DUMMY_DR_RX (1 << 16)
58 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
59 [REG_DR] = UART01x_DR,
60 [REG_FR] = UART01x_FR,
61 [REG_LCRH_RX] = UART011_LCRH,
62 [REG_LCRH_TX] = UART011_LCRH,
63 [REG_IBRD] = UART011_IBRD,
64 [REG_FBRD] = UART011_FBRD,
65 [REG_CR] = UART011_CR,
66 [REG_IFLS] = UART011_IFLS,
67 [REG_IMSC] = UART011_IMSC,
68 [REG_RIS] = UART011_RIS,
69 [REG_MIS] = UART011_MIS,
70 [REG_ICR] = UART011_ICR,
71 [REG_DMACR] = UART011_DMACR,
74 /* There is by now at least one vendor with differing details, so handle it */
76 const u16 *reg_offset;
86 bool cts_event_workaround;
90 unsigned int (*get_fifosize)(struct amba_device *dev);
93 static unsigned int get_fifosize_arm(struct amba_device *dev)
95 return amba_rev(dev) < 3 ? 16 : 32;
98 static struct vendor_data vendor_arm = {
99 .reg_offset = pl011_std_offsets,
100 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
101 .fr_busy = UART01x_FR_BUSY,
102 .fr_dsr = UART01x_FR_DSR,
103 .fr_cts = UART01x_FR_CTS,
104 .fr_ri = UART011_FR_RI,
105 .oversampling = false,
106 .dma_threshold = false,
107 .cts_event_workaround = false,
108 .always_enabled = false,
109 .fixed_options = false,
110 .get_fifosize = get_fifosize_arm,
113 static const struct vendor_data vendor_sbsa = {
114 .reg_offset = pl011_std_offsets,
115 .fr_busy = UART01x_FR_BUSY,
116 .fr_dsr = UART01x_FR_DSR,
117 .fr_cts = UART01x_FR_CTS,
118 .fr_ri = UART011_FR_RI,
120 .oversampling = false,
121 .dma_threshold = false,
122 .cts_event_workaround = false,
123 .always_enabled = true,
124 .fixed_options = true,
127 #ifdef CONFIG_ACPI_SPCR_TABLE
128 static const struct vendor_data vendor_qdt_qdf2400_e44 = {
129 .reg_offset = pl011_std_offsets,
130 .fr_busy = UART011_FR_TXFE,
131 .fr_dsr = UART01x_FR_DSR,
132 .fr_cts = UART01x_FR_CTS,
133 .fr_ri = UART011_FR_RI,
134 .inv_fr = UART011_FR_TXFE,
136 .oversampling = false,
137 .dma_threshold = false,
138 .cts_event_workaround = false,
139 .always_enabled = true,
140 .fixed_options = true,
144 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
145 [REG_DR] = UART01x_DR,
146 [REG_ST_DMAWM] = ST_UART011_DMAWM,
147 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
148 [REG_FR] = UART01x_FR,
149 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
150 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
151 [REG_IBRD] = UART011_IBRD,
152 [REG_FBRD] = UART011_FBRD,
153 [REG_CR] = UART011_CR,
154 [REG_IFLS] = UART011_IFLS,
155 [REG_IMSC] = UART011_IMSC,
156 [REG_RIS] = UART011_RIS,
157 [REG_MIS] = UART011_MIS,
158 [REG_ICR] = UART011_ICR,
159 [REG_DMACR] = UART011_DMACR,
160 [REG_ST_XFCR] = ST_UART011_XFCR,
161 [REG_ST_XON1] = ST_UART011_XON1,
162 [REG_ST_XON2] = ST_UART011_XON2,
163 [REG_ST_XOFF1] = ST_UART011_XOFF1,
164 [REG_ST_XOFF2] = ST_UART011_XOFF2,
165 [REG_ST_ITCR] = ST_UART011_ITCR,
166 [REG_ST_ITIP] = ST_UART011_ITIP,
167 [REG_ST_ABCR] = ST_UART011_ABCR,
168 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
171 static unsigned int get_fifosize_st(struct amba_device *dev)
176 static struct vendor_data vendor_st = {
177 .reg_offset = pl011_st_offsets,
178 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
179 .fr_busy = UART01x_FR_BUSY,
180 .fr_dsr = UART01x_FR_DSR,
181 .fr_cts = UART01x_FR_CTS,
182 .fr_ri = UART011_FR_RI,
183 .oversampling = true,
184 .dma_threshold = true,
185 .cts_event_workaround = true,
186 .always_enabled = false,
187 .fixed_options = false,
188 .get_fifosize = get_fifosize_st,
191 /* Deals with DMA transactions */
194 struct scatterlist sg;
198 struct pl011_dmarx_data {
199 struct dma_chan *chan;
200 struct completion complete;
202 struct pl011_sgbuf sgbuf_a;
203 struct pl011_sgbuf sgbuf_b;
206 struct timer_list timer;
207 unsigned int last_residue;
208 unsigned long last_jiffies;
210 unsigned int poll_rate;
211 unsigned int poll_timeout;
214 struct pl011_dmatx_data {
215 struct dma_chan *chan;
216 struct scatterlist sg;
222 * We wrap our port structure around the generic uart_port.
224 struct uart_amba_port {
225 struct uart_port port;
226 const u16 *reg_offset;
228 const struct vendor_data *vendor;
229 unsigned int dmacr; /* dma control reg */
230 unsigned int im; /* interrupt mask */
231 unsigned int old_status;
232 unsigned int fifosize; /* vendor-specific */
233 unsigned int fixed_baud; /* vendor-set fixed baud rate */
235 bool rs485_tx_started;
236 unsigned int rs485_tx_drain_interval; /* usecs */
237 #ifdef CONFIG_DMA_ENGINE
241 struct pl011_dmarx_data dmarx;
242 struct pl011_dmatx_data dmatx;
247 static unsigned int pl011_tx_empty(struct uart_port *port);
249 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
252 return uap->reg_offset[reg];
255 static unsigned int pl011_read(const struct uart_amba_port *uap,
258 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
260 return (uap->port.iotype == UPIO_MEM32) ?
261 readl_relaxed(addr) : readw_relaxed(addr);
264 static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
267 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
269 if (uap->port.iotype == UPIO_MEM32)
270 writel_relaxed(val, addr);
272 writew_relaxed(val, addr);
276 * Reads up to 256 characters from the FIFO or until it's empty and
277 * inserts them into the TTY layer. Returns the number of characters
278 * read from the FIFO.
280 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
282 unsigned int ch, flag, fifotaken;
286 for (fifotaken = 0; fifotaken != 256; fifotaken++) {
287 status = pl011_read(uap, REG_FR);
288 if (status & UART01x_FR_RXFE)
291 /* Take chars from the FIFO and update status */
292 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
294 uap->port.icount.rx++;
296 if (unlikely(ch & UART_DR_ERROR)) {
297 if (ch & UART011_DR_BE) {
298 ch &= ~(UART011_DR_FE | UART011_DR_PE);
299 uap->port.icount.brk++;
300 if (uart_handle_break(&uap->port))
302 } else if (ch & UART011_DR_PE)
303 uap->port.icount.parity++;
304 else if (ch & UART011_DR_FE)
305 uap->port.icount.frame++;
306 if (ch & UART011_DR_OE)
307 uap->port.icount.overrun++;
309 ch &= uap->port.read_status_mask;
311 if (ch & UART011_DR_BE)
313 else if (ch & UART011_DR_PE)
315 else if (ch & UART011_DR_FE)
319 spin_unlock(&uap->port.lock);
320 sysrq = uart_handle_sysrq_char(&uap->port, ch & 255);
321 spin_lock(&uap->port.lock);
324 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
332 * All the DMA operation mode stuff goes inside this ifdef.
333 * This assumes that you have a generic DMA device interface,
334 * no custom DMA interfaces are supported.
336 #ifdef CONFIG_DMA_ENGINE
338 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
340 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
341 enum dma_data_direction dir)
345 sg->buf = dma_alloc_coherent(chan->device->dev,
346 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
350 sg_init_table(&sg->sg, 1);
351 sg_set_page(&sg->sg, phys_to_page(dma_addr),
352 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
353 sg_dma_address(&sg->sg) = dma_addr;
354 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
359 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
360 enum dma_data_direction dir)
363 dma_free_coherent(chan->device->dev,
364 PL011_DMA_BUFFER_SIZE, sg->buf,
365 sg_dma_address(&sg->sg));
369 static void pl011_dma_probe(struct uart_amba_port *uap)
371 /* DMA is the sole user of the platform data right now */
372 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
373 struct device *dev = uap->port.dev;
374 struct dma_slave_config tx_conf = {
375 .dst_addr = uap->port.mapbase +
376 pl011_reg_to_offset(uap, REG_DR),
377 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
378 .direction = DMA_MEM_TO_DEV,
379 .dst_maxburst = uap->fifosize >> 1,
382 struct dma_chan *chan;
385 uap->dma_probed = true;
386 chan = dma_request_chan(dev, "tx");
388 if (PTR_ERR(chan) == -EPROBE_DEFER) {
389 uap->dma_probed = false;
393 /* We need platform data */
394 if (!plat || !plat->dma_filter) {
395 dev_info(uap->port.dev, "no DMA platform data\n");
399 /* Try to acquire a generic DMA engine slave TX channel */
401 dma_cap_set(DMA_SLAVE, mask);
403 chan = dma_request_channel(mask, plat->dma_filter,
406 dev_err(uap->port.dev, "no TX DMA channel!\n");
411 dmaengine_slave_config(chan, &tx_conf);
412 uap->dmatx.chan = chan;
414 dev_info(uap->port.dev, "DMA channel TX %s\n",
415 dma_chan_name(uap->dmatx.chan));
417 /* Optionally make use of an RX channel as well */
418 chan = dma_request_slave_channel(dev, "rx");
420 if (!chan && plat && plat->dma_rx_param) {
421 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
424 dev_err(uap->port.dev, "no RX DMA channel!\n");
430 struct dma_slave_config rx_conf = {
431 .src_addr = uap->port.mapbase +
432 pl011_reg_to_offset(uap, REG_DR),
433 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
434 .direction = DMA_DEV_TO_MEM,
435 .src_maxburst = uap->fifosize >> 2,
438 struct dma_slave_caps caps;
441 * Some DMA controllers provide information on their capabilities.
442 * If the controller does, check for suitable residue processing
443 * otherwise assime all is well.
445 if (0 == dma_get_slave_caps(chan, &caps)) {
446 if (caps.residue_granularity ==
447 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
448 dma_release_channel(chan);
449 dev_info(uap->port.dev,
450 "RX DMA disabled - no residue processing\n");
454 dmaengine_slave_config(chan, &rx_conf);
455 uap->dmarx.chan = chan;
457 uap->dmarx.auto_poll_rate = false;
458 if (plat && plat->dma_rx_poll_enable) {
459 /* Set poll rate if specified. */
460 if (plat->dma_rx_poll_rate) {
461 uap->dmarx.auto_poll_rate = false;
462 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
465 * 100 ms defaults to poll rate if not
466 * specified. This will be adjusted with
467 * the baud rate at set_termios.
469 uap->dmarx.auto_poll_rate = true;
470 uap->dmarx.poll_rate = 100;
472 /* 3 secs defaults poll_timeout if not specified. */
473 if (plat->dma_rx_poll_timeout)
474 uap->dmarx.poll_timeout =
475 plat->dma_rx_poll_timeout;
477 uap->dmarx.poll_timeout = 3000;
478 } else if (!plat && dev->of_node) {
479 uap->dmarx.auto_poll_rate = of_property_read_bool(
480 dev->of_node, "auto-poll");
481 if (uap->dmarx.auto_poll_rate) {
484 if (0 == of_property_read_u32(dev->of_node,
486 uap->dmarx.poll_rate = x;
488 uap->dmarx.poll_rate = 100;
489 if (0 == of_property_read_u32(dev->of_node,
490 "poll-timeout-ms", &x))
491 uap->dmarx.poll_timeout = x;
493 uap->dmarx.poll_timeout = 3000;
496 dev_info(uap->port.dev, "DMA channel RX %s\n",
497 dma_chan_name(uap->dmarx.chan));
501 static void pl011_dma_remove(struct uart_amba_port *uap)
504 dma_release_channel(uap->dmatx.chan);
506 dma_release_channel(uap->dmarx.chan);
509 /* Forward declare these for the refill routine */
510 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
511 static void pl011_start_tx_pio(struct uart_amba_port *uap);
514 * The current DMA TX buffer has been sent.
515 * Try to queue up another DMA buffer.
517 static void pl011_dma_tx_callback(void *data)
519 struct uart_amba_port *uap = data;
520 struct pl011_dmatx_data *dmatx = &uap->dmatx;
524 spin_lock_irqsave(&uap->port.lock, flags);
525 if (uap->dmatx.queued)
526 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
530 uap->dmacr = dmacr & ~UART011_TXDMAE;
531 pl011_write(uap->dmacr, uap, REG_DMACR);
534 * If TX DMA was disabled, it means that we've stopped the DMA for
535 * some reason (eg, XOFF received, or we want to send an X-char.)
537 * Note: we need to be careful here of a potential race between DMA
538 * and the rest of the driver - if the driver disables TX DMA while
539 * a TX buffer completing, we must update the tx queued status to
540 * get further refills (hence we check dmacr).
542 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
543 uart_circ_empty(&uap->port.state->xmit)) {
544 uap->dmatx.queued = false;
545 spin_unlock_irqrestore(&uap->port.lock, flags);
549 if (pl011_dma_tx_refill(uap) <= 0)
551 * We didn't queue a DMA buffer for some reason, but we
552 * have data pending to be sent. Re-enable the TX IRQ.
554 pl011_start_tx_pio(uap);
556 spin_unlock_irqrestore(&uap->port.lock, flags);
560 * Try to refill the TX DMA buffer.
561 * Locking: called with port lock held and IRQs disabled.
563 * 1 if we queued up a TX DMA buffer.
564 * 0 if we didn't want to handle this by DMA
567 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
569 struct pl011_dmatx_data *dmatx = &uap->dmatx;
570 struct dma_chan *chan = dmatx->chan;
571 struct dma_device *dma_dev = chan->device;
572 struct dma_async_tx_descriptor *desc;
573 struct circ_buf *xmit = &uap->port.state->xmit;
577 * Try to avoid the overhead involved in using DMA if the
578 * transaction fits in the first half of the FIFO, by using
579 * the standard interrupt handling. This ensures that we
580 * issue a uart_write_wakeup() at the appropriate time.
582 count = uart_circ_chars_pending(xmit);
583 if (count < (uap->fifosize >> 1)) {
584 uap->dmatx.queued = false;
589 * Bodge: don't send the last character by DMA, as this
590 * will prevent XON from notifying us to restart DMA.
594 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
595 if (count > PL011_DMA_BUFFER_SIZE)
596 count = PL011_DMA_BUFFER_SIZE;
598 if (xmit->tail < xmit->head)
599 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
601 size_t first = UART_XMIT_SIZE - xmit->tail;
606 second = count - first;
608 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
610 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
613 dmatx->sg.length = count;
615 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
616 uap->dmatx.queued = false;
617 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
621 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
622 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
624 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
625 uap->dmatx.queued = false;
627 * If DMA cannot be used right now, we complete this
628 * transaction via IRQ and let the TTY layer retry.
630 dev_dbg(uap->port.dev, "TX DMA busy\n");
634 /* Some data to go along to the callback */
635 desc->callback = pl011_dma_tx_callback;
636 desc->callback_param = uap;
638 /* All errors should happen at prepare time */
639 dmaengine_submit(desc);
641 /* Fire the DMA transaction */
642 dma_dev->device_issue_pending(chan);
644 uap->dmacr |= UART011_TXDMAE;
645 pl011_write(uap->dmacr, uap, REG_DMACR);
646 uap->dmatx.queued = true;
649 * Now we know that DMA will fire, so advance the ring buffer
650 * with the stuff we just dispatched.
652 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
653 uap->port.icount.tx += count;
655 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
656 uart_write_wakeup(&uap->port);
662 * We received a transmit interrupt without a pending X-char but with
663 * pending characters.
664 * Locking: called with port lock held and IRQs disabled.
666 * false if we want to use PIO to transmit
667 * true if we queued a DMA buffer
669 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
671 if (!uap->using_tx_dma)
675 * If we already have a TX buffer queued, but received a
676 * TX interrupt, it will be because we've just sent an X-char.
677 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
679 if (uap->dmatx.queued) {
680 uap->dmacr |= UART011_TXDMAE;
681 pl011_write(uap->dmacr, uap, REG_DMACR);
682 uap->im &= ~UART011_TXIM;
683 pl011_write(uap->im, uap, REG_IMSC);
688 * We don't have a TX buffer queued, so try to queue one.
689 * If we successfully queued a buffer, mask the TX IRQ.
691 if (pl011_dma_tx_refill(uap) > 0) {
692 uap->im &= ~UART011_TXIM;
693 pl011_write(uap->im, uap, REG_IMSC);
700 * Stop the DMA transmit (eg, due to received XOFF).
701 * Locking: called with port lock held and IRQs disabled.
703 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
705 if (uap->dmatx.queued) {
706 uap->dmacr &= ~UART011_TXDMAE;
707 pl011_write(uap->dmacr, uap, REG_DMACR);
712 * Try to start a DMA transmit, or in the case of an XON/OFF
713 * character queued for send, try to get that character out ASAP.
714 * Locking: called with port lock held and IRQs disabled.
716 * false if we want the TX IRQ to be enabled
717 * true if we have a buffer queued
719 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
723 if (!uap->using_tx_dma)
726 if (!uap->port.x_char) {
727 /* no X-char, try to push chars out in DMA mode */
730 if (!uap->dmatx.queued) {
731 if (pl011_dma_tx_refill(uap) > 0) {
732 uap->im &= ~UART011_TXIM;
733 pl011_write(uap->im, uap, REG_IMSC);
736 } else if (!(uap->dmacr & UART011_TXDMAE)) {
737 uap->dmacr |= UART011_TXDMAE;
738 pl011_write(uap->dmacr, uap, REG_DMACR);
744 * We have an X-char to send. Disable DMA to prevent it loading
745 * the TX fifo, and then see if we can stuff it into the FIFO.
748 uap->dmacr &= ~UART011_TXDMAE;
749 pl011_write(uap->dmacr, uap, REG_DMACR);
751 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
753 * No space in the FIFO, so enable the transmit interrupt
754 * so we know when there is space. Note that once we've
755 * loaded the character, we should just re-enable DMA.
760 pl011_write(uap->port.x_char, uap, REG_DR);
761 uap->port.icount.tx++;
762 uap->port.x_char = 0;
764 /* Success - restore the DMA state */
766 pl011_write(dmacr, uap, REG_DMACR);
772 * Flush the transmit buffer.
773 * Locking: called with port lock held and IRQs disabled.
775 static void pl011_dma_flush_buffer(struct uart_port *port)
776 __releases(&uap->port.lock)
777 __acquires(&uap->port.lock)
779 struct uart_amba_port *uap =
780 container_of(port, struct uart_amba_port, port);
782 if (!uap->using_tx_dma)
785 dmaengine_terminate_async(uap->dmatx.chan);
787 if (uap->dmatx.queued) {
788 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
790 uap->dmatx.queued = false;
791 uap->dmacr &= ~UART011_TXDMAE;
792 pl011_write(uap->dmacr, uap, REG_DMACR);
796 static void pl011_dma_rx_callback(void *data);
798 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
800 struct dma_chan *rxchan = uap->dmarx.chan;
801 struct pl011_dmarx_data *dmarx = &uap->dmarx;
802 struct dma_async_tx_descriptor *desc;
803 struct pl011_sgbuf *sgbuf;
808 /* Start the RX DMA job */
809 sgbuf = uap->dmarx.use_buf_b ?
810 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
811 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
813 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
815 * If the DMA engine is busy and cannot prepare a
816 * channel, no big deal, the driver will fall back
817 * to interrupt mode as a result of this error code.
820 uap->dmarx.running = false;
821 dmaengine_terminate_all(rxchan);
825 /* Some data to go along to the callback */
826 desc->callback = pl011_dma_rx_callback;
827 desc->callback_param = uap;
828 dmarx->cookie = dmaengine_submit(desc);
829 dma_async_issue_pending(rxchan);
831 uap->dmacr |= UART011_RXDMAE;
832 pl011_write(uap->dmacr, uap, REG_DMACR);
833 uap->dmarx.running = true;
835 uap->im &= ~UART011_RXIM;
836 pl011_write(uap->im, uap, REG_IMSC);
842 * This is called when either the DMA job is complete, or
843 * the FIFO timeout interrupt occurred. This must be called
844 * with the port spinlock uap->port.lock held.
846 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
847 u32 pending, bool use_buf_b,
850 struct tty_port *port = &uap->port.state->port;
851 struct pl011_sgbuf *sgbuf = use_buf_b ?
852 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
854 u32 fifotaken = 0; /* only used for vdbg() */
856 struct pl011_dmarx_data *dmarx = &uap->dmarx;
859 if (uap->dmarx.poll_rate) {
860 /* The data can be taken by polling */
861 dmataken = sgbuf->sg.length - dmarx->last_residue;
862 /* Recalculate the pending size */
863 if (pending >= dmataken)
867 /* Pick the remain data from the DMA */
871 * First take all chars in the DMA pipe, then look in the FIFO.
872 * Note that tty_insert_flip_buf() tries to take as many chars
875 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
878 uap->port.icount.rx += dma_count;
879 if (dma_count < pending)
880 dev_warn(uap->port.dev,
881 "couldn't insert all characters (TTY is full?)\n");
884 /* Reset the last_residue for Rx DMA poll */
885 if (uap->dmarx.poll_rate)
886 dmarx->last_residue = sgbuf->sg.length;
889 * Only continue with trying to read the FIFO if all DMA chars have
892 if (dma_count == pending && readfifo) {
893 /* Clear any error flags */
894 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
895 UART011_FEIS, uap, REG_ICR);
898 * If we read all the DMA'd characters, and we had an
899 * incomplete buffer, that could be due to an rx error, or
900 * maybe we just timed out. Read any pending chars and check
903 * Error conditions will only occur in the FIFO, these will
904 * trigger an immediate interrupt and stop the DMA job, so we
905 * will always find the error in the FIFO, never in the DMA
908 fifotaken = pl011_fifo_to_tty(uap);
911 dev_vdbg(uap->port.dev,
912 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
913 dma_count, fifotaken);
914 tty_flip_buffer_push(port);
917 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
919 struct pl011_dmarx_data *dmarx = &uap->dmarx;
920 struct dma_chan *rxchan = dmarx->chan;
921 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
922 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
924 struct dma_tx_state state;
925 enum dma_status dmastat;
928 * Pause the transfer so we can trust the current counter,
929 * do this before we pause the PL011 block, else we may
932 if (dmaengine_pause(rxchan))
933 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
934 dmastat = rxchan->device->device_tx_status(rxchan,
935 dmarx->cookie, &state);
936 if (dmastat != DMA_PAUSED)
937 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
939 /* Disable RX DMA - incoming data will wait in the FIFO */
940 uap->dmacr &= ~UART011_RXDMAE;
941 pl011_write(uap->dmacr, uap, REG_DMACR);
942 uap->dmarx.running = false;
944 pending = sgbuf->sg.length - state.residue;
945 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
946 /* Then we terminate the transfer - we now know our residue */
947 dmaengine_terminate_all(rxchan);
950 * This will take the chars we have so far and insert
951 * into the framework.
953 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
955 /* Switch buffer & re-trigger DMA job */
956 dmarx->use_buf_b = !dmarx->use_buf_b;
957 if (pl011_dma_rx_trigger_dma(uap)) {
958 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
959 "fall back to interrupt mode\n");
960 uap->im |= UART011_RXIM;
961 pl011_write(uap->im, uap, REG_IMSC);
965 static void pl011_dma_rx_callback(void *data)
967 struct uart_amba_port *uap = data;
968 struct pl011_dmarx_data *dmarx = &uap->dmarx;
969 struct dma_chan *rxchan = dmarx->chan;
970 bool lastbuf = dmarx->use_buf_b;
971 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
972 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
974 struct dma_tx_state state;
978 * This completion interrupt occurs typically when the
979 * RX buffer is totally stuffed but no timeout has yet
980 * occurred. When that happens, we just want the RX
981 * routine to flush out the secondary DMA buffer while
982 * we immediately trigger the next DMA job.
984 spin_lock_irq(&uap->port.lock);
986 * Rx data can be taken by the UART interrupts during
987 * the DMA irq handler. So we check the residue here.
989 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
990 pending = sgbuf->sg.length - state.residue;
991 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
992 /* Then we terminate the transfer - we now know our residue */
993 dmaengine_terminate_all(rxchan);
995 uap->dmarx.running = false;
996 dmarx->use_buf_b = !lastbuf;
997 ret = pl011_dma_rx_trigger_dma(uap);
999 pl011_dma_rx_chars(uap, pending, lastbuf, false);
1000 spin_unlock_irq(&uap->port.lock);
1002 * Do this check after we picked the DMA chars so we don't
1003 * get some IRQ immediately from RX.
1006 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1007 "fall back to interrupt mode\n");
1008 uap->im |= UART011_RXIM;
1009 pl011_write(uap->im, uap, REG_IMSC);
1014 * Stop accepting received characters, when we're shutting down or
1015 * suspending this port.
1016 * Locking: called with port lock held and IRQs disabled.
1018 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1020 /* FIXME. Just disable the DMA enable */
1021 uap->dmacr &= ~UART011_RXDMAE;
1022 pl011_write(uap->dmacr, uap, REG_DMACR);
1026 * Timer handler for Rx DMA polling.
1027 * Every polling, It checks the residue in the dma buffer and transfer
1028 * data to the tty. Also, last_residue is updated for the next polling.
1030 static void pl011_dma_rx_poll(struct timer_list *t)
1032 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer);
1033 struct tty_port *port = &uap->port.state->port;
1034 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1035 struct dma_chan *rxchan = uap->dmarx.chan;
1036 unsigned long flags;
1037 unsigned int dmataken = 0;
1038 unsigned int size = 0;
1039 struct pl011_sgbuf *sgbuf;
1041 struct dma_tx_state state;
1043 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
1044 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1045 if (likely(state.residue < dmarx->last_residue)) {
1046 dmataken = sgbuf->sg.length - dmarx->last_residue;
1047 size = dmarx->last_residue - state.residue;
1048 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
1050 if (dma_count == size)
1051 dmarx->last_residue = state.residue;
1052 dmarx->last_jiffies = jiffies;
1054 tty_flip_buffer_push(port);
1057 * If no data is received in poll_timeout, the driver will fall back
1058 * to interrupt mode. We will retrigger DMA at the first interrupt.
1060 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1061 > uap->dmarx.poll_timeout) {
1063 spin_lock_irqsave(&uap->port.lock, flags);
1064 pl011_dma_rx_stop(uap);
1065 uap->im |= UART011_RXIM;
1066 pl011_write(uap->im, uap, REG_IMSC);
1067 spin_unlock_irqrestore(&uap->port.lock, flags);
1069 uap->dmarx.running = false;
1070 dmaengine_terminate_all(rxchan);
1071 del_timer(&uap->dmarx.timer);
1073 mod_timer(&uap->dmarx.timer,
1074 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1078 static void pl011_dma_startup(struct uart_amba_port *uap)
1082 if (!uap->dma_probed)
1083 pl011_dma_probe(uap);
1085 if (!uap->dmatx.chan)
1088 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
1089 if (!uap->dmatx.buf) {
1090 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1091 uap->port.fifosize = uap->fifosize;
1095 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
1097 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1098 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1099 uap->using_tx_dma = true;
1101 if (!uap->dmarx.chan)
1104 /* Allocate and map DMA RX buffers */
1105 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1108 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1109 "RX buffer A", ret);
1113 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1116 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1117 "RX buffer B", ret);
1118 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1123 uap->using_rx_dma = true;
1126 /* Turn on DMA error (RX/TX will be enabled on demand) */
1127 uap->dmacr |= UART011_DMAONERR;
1128 pl011_write(uap->dmacr, uap, REG_DMACR);
1131 * ST Micro variants has some specific dma burst threshold
1132 * compensation. Set this to 16 bytes, so burst will only
1133 * be issued above/below 16 bytes.
1135 if (uap->vendor->dma_threshold)
1136 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1139 if (uap->using_rx_dma) {
1140 if (pl011_dma_rx_trigger_dma(uap))
1141 dev_dbg(uap->port.dev, "could not trigger initial "
1142 "RX DMA job, fall back to interrupt mode\n");
1143 if (uap->dmarx.poll_rate) {
1144 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0);
1145 mod_timer(&uap->dmarx.timer,
1147 msecs_to_jiffies(uap->dmarx.poll_rate));
1148 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1149 uap->dmarx.last_jiffies = jiffies;
1154 static void pl011_dma_shutdown(struct uart_amba_port *uap)
1156 if (!(uap->using_tx_dma || uap->using_rx_dma))
1159 /* Disable RX and TX DMA */
1160 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
1163 spin_lock_irq(&uap->port.lock);
1164 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1165 pl011_write(uap->dmacr, uap, REG_DMACR);
1166 spin_unlock_irq(&uap->port.lock);
1168 if (uap->using_tx_dma) {
1169 /* In theory, this should already be done by pl011_dma_flush_buffer */
1170 dmaengine_terminate_all(uap->dmatx.chan);
1171 if (uap->dmatx.queued) {
1172 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1174 uap->dmatx.queued = false;
1177 kfree(uap->dmatx.buf);
1178 uap->using_tx_dma = false;
1181 if (uap->using_rx_dma) {
1182 dmaengine_terminate_all(uap->dmarx.chan);
1183 /* Clean up the RX DMA */
1184 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1185 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
1186 if (uap->dmarx.poll_rate)
1187 del_timer_sync(&uap->dmarx.timer);
1188 uap->using_rx_dma = false;
1192 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1194 return uap->using_rx_dma;
1197 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1199 return uap->using_rx_dma && uap->dmarx.running;
1203 /* Blank functions if the DMA engine is not available */
1204 static inline void pl011_dma_remove(struct uart_amba_port *uap)
1208 static inline void pl011_dma_startup(struct uart_amba_port *uap)
1212 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1216 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1221 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1225 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1230 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1234 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1238 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1243 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1248 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1253 #define pl011_dma_flush_buffer NULL
1256 static void pl011_rs485_tx_stop(struct uart_amba_port *uap)
1259 * To be on the safe side only time out after twice as many iterations
1262 const int MAX_TX_DRAIN_ITERS = uap->port.fifosize * 2;
1263 struct uart_port *port = &uap->port;
1267 /* Wait until hardware tx queue is empty */
1268 while (!pl011_tx_empty(port)) {
1269 if (i > MAX_TX_DRAIN_ITERS) {
1271 "timeout while draining hardware tx queue\n");
1275 udelay(uap->rs485_tx_drain_interval);
1279 if (port->rs485.delay_rts_after_send)
1280 mdelay(port->rs485.delay_rts_after_send);
1282 cr = pl011_read(uap, REG_CR);
1284 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1285 cr &= ~UART011_CR_RTS;
1287 cr |= UART011_CR_RTS;
1289 /* Disable the transmitter and reenable the transceiver */
1290 cr &= ~UART011_CR_TXE;
1291 cr |= UART011_CR_RXE;
1292 pl011_write(cr, uap, REG_CR);
1294 uap->rs485_tx_started = false;
1297 static void pl011_stop_tx(struct uart_port *port)
1299 struct uart_amba_port *uap =
1300 container_of(port, struct uart_amba_port, port);
1302 uap->im &= ~UART011_TXIM;
1303 pl011_write(uap->im, uap, REG_IMSC);
1304 pl011_dma_tx_stop(uap);
1306 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started)
1307 pl011_rs485_tx_stop(uap);
1310 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1312 /* Start TX with programmed I/O only (no DMA) */
1313 static void pl011_start_tx_pio(struct uart_amba_port *uap)
1315 if (pl011_tx_chars(uap, false)) {
1316 uap->im |= UART011_TXIM;
1317 pl011_write(uap->im, uap, REG_IMSC);
1321 static void pl011_start_tx(struct uart_port *port)
1323 struct uart_amba_port *uap =
1324 container_of(port, struct uart_amba_port, port);
1326 if (!pl011_dma_tx_start(uap))
1327 pl011_start_tx_pio(uap);
1330 static void pl011_stop_rx(struct uart_port *port)
1332 struct uart_amba_port *uap =
1333 container_of(port, struct uart_amba_port, port);
1335 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1336 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1337 pl011_write(uap->im, uap, REG_IMSC);
1339 pl011_dma_rx_stop(uap);
1342 static void pl011_enable_ms(struct uart_port *port)
1344 struct uart_amba_port *uap =
1345 container_of(port, struct uart_amba_port, port);
1347 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1348 pl011_write(uap->im, uap, REG_IMSC);
1351 static void pl011_rx_chars(struct uart_amba_port *uap)
1352 __releases(&uap->port.lock)
1353 __acquires(&uap->port.lock)
1355 pl011_fifo_to_tty(uap);
1357 spin_unlock(&uap->port.lock);
1358 tty_flip_buffer_push(&uap->port.state->port);
1360 * If we were temporarily out of DMA mode for a while,
1361 * attempt to switch back to DMA mode again.
1363 if (pl011_dma_rx_available(uap)) {
1364 if (pl011_dma_rx_trigger_dma(uap)) {
1365 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1366 "fall back to interrupt mode again\n");
1367 uap->im |= UART011_RXIM;
1368 pl011_write(uap->im, uap, REG_IMSC);
1370 #ifdef CONFIG_DMA_ENGINE
1371 /* Start Rx DMA poll */
1372 if (uap->dmarx.poll_rate) {
1373 uap->dmarx.last_jiffies = jiffies;
1374 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1375 mod_timer(&uap->dmarx.timer,
1377 msecs_to_jiffies(uap->dmarx.poll_rate));
1382 spin_lock(&uap->port.lock);
1385 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1388 if (unlikely(!from_irq) &&
1389 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1390 return false; /* unable to transmit character */
1392 pl011_write(c, uap, REG_DR);
1393 uap->port.icount.tx++;
1398 static void pl011_rs485_tx_start(struct uart_amba_port *uap)
1400 struct uart_port *port = &uap->port;
1403 /* Enable transmitter */
1404 cr = pl011_read(uap, REG_CR);
1405 cr |= UART011_CR_TXE;
1407 /* Disable receiver if half-duplex */
1408 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
1409 cr &= ~UART011_CR_RXE;
1411 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
1412 cr &= ~UART011_CR_RTS;
1414 cr |= UART011_CR_RTS;
1416 pl011_write(cr, uap, REG_CR);
1418 if (port->rs485.delay_rts_before_send)
1419 mdelay(port->rs485.delay_rts_before_send);
1421 uap->rs485_tx_started = true;
1424 /* Returns true if tx interrupts have to be (kept) enabled */
1425 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1427 struct circ_buf *xmit = &uap->port.state->xmit;
1428 int count = uap->fifosize >> 1;
1430 if (uap->port.x_char) {
1431 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1433 uap->port.x_char = 0;
1436 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1437 pl011_stop_tx(&uap->port);
1441 if ((uap->port.rs485.flags & SER_RS485_ENABLED) &&
1442 !uap->rs485_tx_started)
1443 pl011_rs485_tx_start(uap);
1445 /* If we are using DMA mode, try to send some characters. */
1446 if (pl011_dma_tx_irq(uap))
1450 if (likely(from_irq) && count-- == 0)
1453 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1456 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1457 } while (!uart_circ_empty(xmit));
1459 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1460 uart_write_wakeup(&uap->port);
1462 if (uart_circ_empty(xmit)) {
1463 pl011_stop_tx(&uap->port);
1469 static void pl011_modem_status(struct uart_amba_port *uap)
1471 unsigned int status, delta;
1473 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1475 delta = status ^ uap->old_status;
1476 uap->old_status = status;
1481 if (delta & UART01x_FR_DCD)
1482 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1484 if (delta & uap->vendor->fr_dsr)
1485 uap->port.icount.dsr++;
1487 if (delta & uap->vendor->fr_cts)
1488 uart_handle_cts_change(&uap->port,
1489 status & uap->vendor->fr_cts);
1491 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1494 static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1496 if (!uap->vendor->cts_event_workaround)
1499 /* workaround to make sure that all bits are unlocked.. */
1500 pl011_write(0x00, uap, REG_ICR);
1503 * WA: introduce 26ns(1 uart clk) delay before W1C;
1504 * single apb access will incur 2 pclk(133.12Mhz) delay,
1505 * so add 2 dummy reads
1507 pl011_read(uap, REG_ICR);
1508 pl011_read(uap, REG_ICR);
1511 static irqreturn_t pl011_int(int irq, void *dev_id)
1513 struct uart_amba_port *uap = dev_id;
1514 unsigned long flags;
1515 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1518 spin_lock_irqsave(&uap->port.lock, flags);
1519 status = pl011_read(uap, REG_RIS) & uap->im;
1522 check_apply_cts_event_workaround(uap);
1524 pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
1528 if (status & (UART011_RTIS|UART011_RXIS)) {
1529 if (pl011_dma_rx_running(uap))
1530 pl011_dma_rx_irq(uap);
1532 pl011_rx_chars(uap);
1534 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1535 UART011_CTSMIS|UART011_RIMIS))
1536 pl011_modem_status(uap);
1537 if (status & UART011_TXIS)
1538 pl011_tx_chars(uap, true);
1540 if (pass_counter-- == 0)
1543 status = pl011_read(uap, REG_RIS) & uap->im;
1544 } while (status != 0);
1548 spin_unlock_irqrestore(&uap->port.lock, flags);
1550 return IRQ_RETVAL(handled);
1553 static unsigned int pl011_tx_empty(struct uart_port *port)
1555 struct uart_amba_port *uap =
1556 container_of(port, struct uart_amba_port, port);
1558 /* Allow feature register bits to be inverted to work around errata */
1559 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1561 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1565 static unsigned int pl011_get_mctrl(struct uart_port *port)
1567 struct uart_amba_port *uap =
1568 container_of(port, struct uart_amba_port, port);
1569 unsigned int result = 0;
1570 unsigned int status = pl011_read(uap, REG_FR);
1572 #define TIOCMBIT(uartbit, tiocmbit) \
1573 if (status & uartbit) \
1576 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1577 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR);
1578 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS);
1579 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG);
1584 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1586 struct uart_amba_port *uap =
1587 container_of(port, struct uart_amba_port, port);
1590 cr = pl011_read(uap, REG_CR);
1592 #define TIOCMBIT(tiocmbit, uartbit) \
1593 if (mctrl & tiocmbit) \
1598 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1599 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1600 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1601 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1602 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1604 if (port->status & UPSTAT_AUTORTS) {
1605 /* We need to disable auto-RTS if we want to turn RTS off */
1606 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1610 pl011_write(cr, uap, REG_CR);
1613 static void pl011_break_ctl(struct uart_port *port, int break_state)
1615 struct uart_amba_port *uap =
1616 container_of(port, struct uart_amba_port, port);
1617 unsigned long flags;
1620 spin_lock_irqsave(&uap->port.lock, flags);
1621 lcr_h = pl011_read(uap, REG_LCRH_TX);
1622 if (break_state == -1)
1623 lcr_h |= UART01x_LCRH_BRK;
1625 lcr_h &= ~UART01x_LCRH_BRK;
1626 pl011_write(lcr_h, uap, REG_LCRH_TX);
1627 spin_unlock_irqrestore(&uap->port.lock, flags);
1630 #ifdef CONFIG_CONSOLE_POLL
1632 static void pl011_quiesce_irqs(struct uart_port *port)
1634 struct uart_amba_port *uap =
1635 container_of(port, struct uart_amba_port, port);
1637 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
1639 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1640 * we simply mask it. start_tx() will unmask it.
1642 * Note we can race with start_tx(), and if the race happens, the
1643 * polling user might get another interrupt just after we clear it.
1644 * But it should be OK and can happen even w/o the race, e.g.
1645 * controller immediately got some new data and raised the IRQ.
1647 * And whoever uses polling routines assumes that it manages the device
1648 * (including tx queue), so we're also fine with start_tx()'s caller
1651 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1655 static int pl011_get_poll_char(struct uart_port *port)
1657 struct uart_amba_port *uap =
1658 container_of(port, struct uart_amba_port, port);
1659 unsigned int status;
1662 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1665 pl011_quiesce_irqs(port);
1667 status = pl011_read(uap, REG_FR);
1668 if (status & UART01x_FR_RXFE)
1669 return NO_POLL_CHAR;
1671 return pl011_read(uap, REG_DR);
1674 static void pl011_put_poll_char(struct uart_port *port,
1677 struct uart_amba_port *uap =
1678 container_of(port, struct uart_amba_port, port);
1680 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1683 pl011_write(ch, uap, REG_DR);
1686 #endif /* CONFIG_CONSOLE_POLL */
1688 static int pl011_hwinit(struct uart_port *port)
1690 struct uart_amba_port *uap =
1691 container_of(port, struct uart_amba_port, port);
1694 /* Optionaly enable pins to be muxed in and configured */
1695 pinctrl_pm_select_default_state(port->dev);
1698 * Try to enable the clock producer.
1700 retval = clk_prepare_enable(uap->clk);
1704 uap->port.uartclk = clk_get_rate(uap->clk);
1706 /* Clear pending error and receive interrupts */
1707 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1708 UART011_FEIS | UART011_RTIS | UART011_RXIS,
1712 * Save interrupts enable mask, and enable RX interrupts in case if
1713 * the interrupt is used for NMI entry.
1715 uap->im = pl011_read(uap, REG_IMSC);
1716 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
1718 if (dev_get_platdata(uap->port.dev)) {
1719 struct amba_pl011_data *plat;
1721 plat = dev_get_platdata(uap->port.dev);
1728 static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1730 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1731 pl011_reg_to_offset(uap, REG_LCRH_TX);
1734 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1736 pl011_write(lcr_h, uap, REG_LCRH_RX);
1737 if (pl011_split_lcrh(uap)) {
1740 * Wait 10 PCLKs before writing LCRH_TX register,
1741 * to get this delay write read only register 10 times
1743 for (i = 0; i < 10; ++i)
1744 pl011_write(0xff, uap, REG_MIS);
1745 pl011_write(lcr_h, uap, REG_LCRH_TX);
1749 static int pl011_allocate_irq(struct uart_amba_port *uap)
1751 pl011_write(uap->im, uap, REG_IMSC);
1753 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap);
1757 * Enable interrupts, only timeouts when using DMA
1758 * if initial RX DMA job failed, start in interrupt mode
1761 static void pl011_enable_interrupts(struct uart_amba_port *uap)
1765 spin_lock_irq(&uap->port.lock);
1767 /* Clear out any spuriously appearing RX interrupts */
1768 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
1771 * RXIS is asserted only when the RX FIFO transitions from below
1772 * to above the trigger threshold. If the RX FIFO is already
1773 * full to the threshold this can't happen and RXIS will now be
1774 * stuck off. Drain the RX FIFO explicitly to fix this:
1776 for (i = 0; i < uap->fifosize * 2; ++i) {
1777 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)
1780 pl011_read(uap, REG_DR);
1783 uap->im = UART011_RTIM;
1784 if (!pl011_dma_rx_running(uap))
1785 uap->im |= UART011_RXIM;
1786 pl011_write(uap->im, uap, REG_IMSC);
1787 spin_unlock_irq(&uap->port.lock);
1790 static int pl011_startup(struct uart_port *port)
1792 struct uart_amba_port *uap =
1793 container_of(port, struct uart_amba_port, port);
1797 retval = pl011_hwinit(port);
1801 retval = pl011_allocate_irq(uap);
1805 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1807 spin_lock_irq(&uap->port.lock);
1809 cr = pl011_read(uap, REG_CR);
1810 cr &= UART011_CR_RTS | UART011_CR_DTR;
1811 cr |= UART01x_CR_UARTEN | UART011_CR_RXE;
1813 if (!(port->rs485.flags & SER_RS485_ENABLED))
1814 cr |= UART011_CR_TXE;
1816 pl011_write(cr, uap, REG_CR);
1818 spin_unlock_irq(&uap->port.lock);
1821 * initialise the old status of the modem signals
1823 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1826 pl011_dma_startup(uap);
1828 pl011_enable_interrupts(uap);
1833 clk_disable_unprepare(uap->clk);
1837 static int sbsa_uart_startup(struct uart_port *port)
1839 struct uart_amba_port *uap =
1840 container_of(port, struct uart_amba_port, port);
1843 retval = pl011_hwinit(port);
1847 retval = pl011_allocate_irq(uap);
1851 /* The SBSA UART does not support any modem status lines. */
1852 uap->old_status = 0;
1854 pl011_enable_interrupts(uap);
1859 static void pl011_shutdown_channel(struct uart_amba_port *uap,
1864 val = pl011_read(uap, lcrh);
1865 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1866 pl011_write(val, uap, lcrh);
1870 * disable the port. It should not disable RTS and DTR.
1871 * Also RTS and DTR state should be preserved to restore
1872 * it during startup().
1874 static void pl011_disable_uart(struct uart_amba_port *uap)
1878 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1879 spin_lock_irq(&uap->port.lock);
1880 cr = pl011_read(uap, REG_CR);
1881 cr &= UART011_CR_RTS | UART011_CR_DTR;
1882 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1883 pl011_write(cr, uap, REG_CR);
1884 spin_unlock_irq(&uap->port.lock);
1887 * disable break condition and fifos
1889 pl011_shutdown_channel(uap, REG_LCRH_RX);
1890 if (pl011_split_lcrh(uap))
1891 pl011_shutdown_channel(uap, REG_LCRH_TX);
1894 static void pl011_disable_interrupts(struct uart_amba_port *uap)
1896 spin_lock_irq(&uap->port.lock);
1898 /* mask all interrupts and clear all pending ones */
1900 pl011_write(uap->im, uap, REG_IMSC);
1901 pl011_write(0xffff, uap, REG_ICR);
1903 spin_unlock_irq(&uap->port.lock);
1906 static void pl011_shutdown(struct uart_port *port)
1908 struct uart_amba_port *uap =
1909 container_of(port, struct uart_amba_port, port);
1911 pl011_disable_interrupts(uap);
1913 pl011_dma_shutdown(uap);
1915 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started)
1916 pl011_rs485_tx_stop(uap);
1918 free_irq(uap->port.irq, uap);
1920 pl011_disable_uart(uap);
1923 * Shut down the clock producer
1925 clk_disable_unprepare(uap->clk);
1926 /* Optionally let pins go into sleep states */
1927 pinctrl_pm_select_sleep_state(port->dev);
1929 if (dev_get_platdata(uap->port.dev)) {
1930 struct amba_pl011_data *plat;
1932 plat = dev_get_platdata(uap->port.dev);
1937 if (uap->port.ops->flush_buffer)
1938 uap->port.ops->flush_buffer(port);
1941 static void sbsa_uart_shutdown(struct uart_port *port)
1943 struct uart_amba_port *uap =
1944 container_of(port, struct uart_amba_port, port);
1946 pl011_disable_interrupts(uap);
1948 free_irq(uap->port.irq, uap);
1950 if (uap->port.ops->flush_buffer)
1951 uap->port.ops->flush_buffer(port);
1955 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
1957 port->read_status_mask = UART011_DR_OE | 255;
1958 if (termios->c_iflag & INPCK)
1959 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1960 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1961 port->read_status_mask |= UART011_DR_BE;
1964 * Characters to ignore
1966 port->ignore_status_mask = 0;
1967 if (termios->c_iflag & IGNPAR)
1968 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1969 if (termios->c_iflag & IGNBRK) {
1970 port->ignore_status_mask |= UART011_DR_BE;
1972 * If we're ignoring parity and break indicators,
1973 * ignore overruns too (for real raw support).
1975 if (termios->c_iflag & IGNPAR)
1976 port->ignore_status_mask |= UART011_DR_OE;
1980 * Ignore all characters if CREAD is not set.
1982 if ((termios->c_cflag & CREAD) == 0)
1983 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1987 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1988 struct ktermios *old)
1990 struct uart_amba_port *uap =
1991 container_of(port, struct uart_amba_port, port);
1992 unsigned int lcr_h, old_cr;
1993 unsigned long flags;
1994 unsigned int baud, quot, clkdiv;
1997 if (uap->vendor->oversampling)
2003 * Ask the core to calculate the divisor for us.
2005 baud = uart_get_baud_rate(port, termios, old, 0,
2006 port->uartclk / clkdiv);
2007 #ifdef CONFIG_DMA_ENGINE
2009 * Adjust RX DMA polling rate with baud rate if not specified.
2011 if (uap->dmarx.auto_poll_rate)
2012 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
2015 if (baud > port->uartclk/16)
2016 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
2018 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
2020 switch (termios->c_cflag & CSIZE) {
2022 lcr_h = UART01x_LCRH_WLEN_5;
2025 lcr_h = UART01x_LCRH_WLEN_6;
2028 lcr_h = UART01x_LCRH_WLEN_7;
2031 lcr_h = UART01x_LCRH_WLEN_8;
2034 if (termios->c_cflag & CSTOPB)
2035 lcr_h |= UART01x_LCRH_STP2;
2036 if (termios->c_cflag & PARENB) {
2037 lcr_h |= UART01x_LCRH_PEN;
2038 if (!(termios->c_cflag & PARODD))
2039 lcr_h |= UART01x_LCRH_EPS;
2040 if (termios->c_cflag & CMSPAR)
2041 lcr_h |= UART011_LCRH_SPS;
2043 if (uap->fifosize > 1)
2044 lcr_h |= UART01x_LCRH_FEN;
2046 bits = tty_get_frame_size(termios->c_cflag);
2048 spin_lock_irqsave(&port->lock, flags);
2051 * Update the per-port timeout.
2053 uart_update_timeout(port, termios->c_cflag, baud);
2056 * Calculate the approximated time it takes to transmit one character
2057 * with the given baud rate. We use this as the poll interval when we
2058 * wait for the tx queue to empty.
2060 uap->rs485_tx_drain_interval = DIV_ROUND_UP(bits * 1000 * 1000, baud);
2062 pl011_setup_status_masks(port, termios);
2064 if (UART_ENABLE_MS(port, termios->c_cflag))
2065 pl011_enable_ms(port);
2067 if (port->rs485.flags & SER_RS485_ENABLED)
2068 termios->c_cflag &= ~CRTSCTS;
2070 old_cr = pl011_read(uap, REG_CR);
2072 if (termios->c_cflag & CRTSCTS) {
2073 if (old_cr & UART011_CR_RTS)
2074 old_cr |= UART011_CR_RTSEN;
2076 old_cr |= UART011_CR_CTSEN;
2077 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
2079 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
2080 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
2083 if (uap->vendor->oversampling) {
2084 if (baud > port->uartclk / 16)
2085 old_cr |= ST_UART011_CR_OVSFACT;
2087 old_cr &= ~ST_UART011_CR_OVSFACT;
2091 * Workaround for the ST Micro oversampling variants to
2092 * increase the bitrate slightly, by lowering the divisor,
2093 * to avoid delayed sampling of start bit at high speeds,
2094 * else we see data corruption.
2096 if (uap->vendor->oversampling) {
2097 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
2099 else if ((baud > 3250000) && (quot > 2))
2103 pl011_write(quot & 0x3f, uap, REG_FBRD);
2104 pl011_write(quot >> 6, uap, REG_IBRD);
2107 * ----------v----------v----------v----------v-----
2108 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
2109 * REG_FBRD & REG_IBRD.
2110 * ----------^----------^----------^----------^-----
2112 pl011_write_lcr_h(uap, lcr_h);
2113 pl011_write(old_cr, uap, REG_CR);
2115 spin_unlock_irqrestore(&port->lock, flags);
2119 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2120 struct ktermios *old)
2122 struct uart_amba_port *uap =
2123 container_of(port, struct uart_amba_port, port);
2124 unsigned long flags;
2126 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2128 /* The SBSA UART only supports 8n1 without hardware flow control. */
2129 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2130 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2131 termios->c_cflag |= CS8 | CLOCAL;
2133 spin_lock_irqsave(&port->lock, flags);
2134 uart_update_timeout(port, CS8, uap->fixed_baud);
2135 pl011_setup_status_masks(port, termios);
2136 spin_unlock_irqrestore(&port->lock, flags);
2139 static const char *pl011_type(struct uart_port *port)
2141 struct uart_amba_port *uap =
2142 container_of(port, struct uart_amba_port, port);
2143 return uap->port.type == PORT_AMBA ? uap->type : NULL;
2147 * Configure/autoconfigure the port.
2149 static void pl011_config_port(struct uart_port *port, int flags)
2151 if (flags & UART_CONFIG_TYPE)
2152 port->type = PORT_AMBA;
2156 * verify the new serial_struct (for TIOCSSERIAL).
2158 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
2161 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2163 if (ser->irq < 0 || ser->irq >= nr_irqs)
2165 if (ser->baud_base < 9600)
2167 if (port->mapbase != (unsigned long) ser->iomem_base)
2172 static int pl011_rs485_config(struct uart_port *port,
2173 struct serial_rs485 *rs485)
2175 struct uart_amba_port *uap =
2176 container_of(port, struct uart_amba_port, port);
2178 /* pick sane settings if the user hasn't */
2179 if (!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
2180 !(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
2181 rs485->flags |= SER_RS485_RTS_ON_SEND;
2182 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
2184 /* clamp the delays to [0, 100ms] */
2185 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
2186 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
2187 memset(rs485->padding, 0, sizeof(rs485->padding));
2189 if (port->rs485.flags & SER_RS485_ENABLED)
2190 pl011_rs485_tx_stop(uap);
2192 /* Set new configuration */
2193 port->rs485 = *rs485;
2195 /* Make sure auto RTS is disabled */
2196 if (port->rs485.flags & SER_RS485_ENABLED) {
2197 u32 cr = pl011_read(uap, REG_CR);
2199 cr &= ~UART011_CR_RTSEN;
2200 pl011_write(cr, uap, REG_CR);
2201 port->status &= ~UPSTAT_AUTORTS;
2207 static const struct uart_ops amba_pl011_pops = {
2208 .tx_empty = pl011_tx_empty,
2209 .set_mctrl = pl011_set_mctrl,
2210 .get_mctrl = pl011_get_mctrl,
2211 .stop_tx = pl011_stop_tx,
2212 .start_tx = pl011_start_tx,
2213 .stop_rx = pl011_stop_rx,
2214 .enable_ms = pl011_enable_ms,
2215 .break_ctl = pl011_break_ctl,
2216 .startup = pl011_startup,
2217 .shutdown = pl011_shutdown,
2218 .flush_buffer = pl011_dma_flush_buffer,
2219 .set_termios = pl011_set_termios,
2221 .config_port = pl011_config_port,
2222 .verify_port = pl011_verify_port,
2223 #ifdef CONFIG_CONSOLE_POLL
2224 .poll_init = pl011_hwinit,
2225 .poll_get_char = pl011_get_poll_char,
2226 .poll_put_char = pl011_put_poll_char,
2230 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2234 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2239 static const struct uart_ops sbsa_uart_pops = {
2240 .tx_empty = pl011_tx_empty,
2241 .set_mctrl = sbsa_uart_set_mctrl,
2242 .get_mctrl = sbsa_uart_get_mctrl,
2243 .stop_tx = pl011_stop_tx,
2244 .start_tx = pl011_start_tx,
2245 .stop_rx = pl011_stop_rx,
2246 .startup = sbsa_uart_startup,
2247 .shutdown = sbsa_uart_shutdown,
2248 .set_termios = sbsa_uart_set_termios,
2250 .config_port = pl011_config_port,
2251 .verify_port = pl011_verify_port,
2252 #ifdef CONFIG_CONSOLE_POLL
2253 .poll_init = pl011_hwinit,
2254 .poll_get_char = pl011_get_poll_char,
2255 .poll_put_char = pl011_put_poll_char,
2259 static struct uart_amba_port *amba_ports[UART_NR];
2261 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2263 static void pl011_console_putchar(struct uart_port *port, unsigned char ch)
2265 struct uart_amba_port *uap =
2266 container_of(port, struct uart_amba_port, port);
2268 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2270 pl011_write(ch, uap, REG_DR);
2274 pl011_console_write(struct console *co, const char *s, unsigned int count)
2276 struct uart_amba_port *uap = amba_ports[co->index];
2277 unsigned int old_cr = 0, new_cr;
2278 unsigned long flags;
2281 clk_enable(uap->clk);
2283 local_irq_save(flags);
2284 if (uap->port.sysrq)
2286 else if (oops_in_progress)
2287 locked = spin_trylock(&uap->port.lock);
2289 spin_lock(&uap->port.lock);
2292 * First save the CR then disable the interrupts
2294 if (!uap->vendor->always_enabled) {
2295 old_cr = pl011_read(uap, REG_CR);
2296 new_cr = old_cr & ~UART011_CR_CTSEN;
2297 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
2298 pl011_write(new_cr, uap, REG_CR);
2301 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2304 * Finally, wait for transmitter to become empty and restore the
2305 * TCR. Allow feature register bits to be inverted to work around
2308 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2309 & uap->vendor->fr_busy)
2311 if (!uap->vendor->always_enabled)
2312 pl011_write(old_cr, uap, REG_CR);
2315 spin_unlock(&uap->port.lock);
2316 local_irq_restore(flags);
2318 clk_disable(uap->clk);
2321 static void pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2322 int *parity, int *bits)
2324 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
2325 unsigned int lcr_h, ibrd, fbrd;
2327 lcr_h = pl011_read(uap, REG_LCRH_TX);
2330 if (lcr_h & UART01x_LCRH_PEN) {
2331 if (lcr_h & UART01x_LCRH_EPS)
2337 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2342 ibrd = pl011_read(uap, REG_IBRD);
2343 fbrd = pl011_read(uap, REG_FBRD);
2345 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
2347 if (uap->vendor->oversampling) {
2348 if (pl011_read(uap, REG_CR)
2349 & ST_UART011_CR_OVSFACT)
2355 static int pl011_console_setup(struct console *co, char *options)
2357 struct uart_amba_port *uap;
2365 * Check whether an invalid uart number has been specified, and
2366 * if so, search for the first available port that does have
2369 if (co->index >= UART_NR)
2371 uap = amba_ports[co->index];
2375 /* Allow pins to be muxed in and configured */
2376 pinctrl_pm_select_default_state(uap->port.dev);
2378 ret = clk_prepare(uap->clk);
2382 if (dev_get_platdata(uap->port.dev)) {
2383 struct amba_pl011_data *plat;
2385 plat = dev_get_platdata(uap->port.dev);
2390 uap->port.uartclk = clk_get_rate(uap->clk);
2392 if (uap->vendor->fixed_options) {
2393 baud = uap->fixed_baud;
2396 uart_parse_options(options,
2397 &baud, &parity, &bits, &flow);
2399 pl011_console_get_options(uap, &baud, &parity, &bits);
2402 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2406 * pl011_console_match - non-standard console matching
2407 * @co: registering console
2408 * @name: name from console command line
2409 * @idx: index from console command line
2410 * @options: ptr to option string from console command line
2412 * Only attempts to match console command lines of the form:
2413 * console=pl011,mmio|mmio32,<addr>[,<options>]
2414 * console=pl011,0x<addr>[,<options>]
2415 * This form is used to register an initial earlycon boot console and
2416 * replace it with the amba_console at pl011 driver init.
2418 * Performs console setup for a match (as required by interface)
2419 * If no <options> are specified, then assume the h/w is already setup.
2421 * Returns 0 if console matches; otherwise non-zero to use default matching
2423 static int pl011_console_match(struct console *co, char *name, int idx,
2426 unsigned char iotype;
2427 resource_size_t addr;
2431 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum
2432 * have a distinct console name, so make sure we check for that.
2433 * The actual implementation of the erratum occurs in the probe
2436 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0))
2439 if (uart_parse_earlycon(options, &iotype, &addr, &options))
2442 if (iotype != UPIO_MEM && iotype != UPIO_MEM32)
2445 /* try to match the port specified on the command line */
2446 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2447 struct uart_port *port;
2452 port = &amba_ports[i]->port;
2454 if (port->mapbase != addr)
2459 return pl011_console_setup(co, options);
2465 static struct uart_driver amba_reg;
2466 static struct console amba_console = {
2468 .write = pl011_console_write,
2469 .device = uart_console_device,
2470 .setup = pl011_console_setup,
2471 .match = pl011_console_match,
2472 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2477 #define AMBA_CONSOLE (&amba_console)
2479 static void qdf2400_e44_putc(struct uart_port *port, unsigned char c)
2481 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2483 writel(c, port->membase + UART01x_DR);
2484 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE))
2488 static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n)
2490 struct earlycon_device *dev = con->data;
2492 uart_console_write(&dev->port, s, n, qdf2400_e44_putc);
2495 static void pl011_putc(struct uart_port *port, unsigned char c)
2497 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2499 if (port->iotype == UPIO_MEM32)
2500 writel(c, port->membase + UART01x_DR);
2502 writeb(c, port->membase + UART01x_DR);
2503 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2507 static void pl011_early_write(struct console *con, const char *s, unsigned n)
2509 struct earlycon_device *dev = con->data;
2511 uart_console_write(&dev->port, s, n, pl011_putc);
2514 #ifdef CONFIG_CONSOLE_POLL
2515 static int pl011_getc(struct uart_port *port)
2517 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE)
2518 return NO_POLL_CHAR;
2520 if (port->iotype == UPIO_MEM32)
2521 return readl(port->membase + UART01x_DR);
2523 return readb(port->membase + UART01x_DR);
2526 static int pl011_early_read(struct console *con, char *s, unsigned int n)
2528 struct earlycon_device *dev = con->data;
2529 int ch, num_read = 0;
2531 while (num_read < n) {
2532 ch = pl011_getc(&dev->port);
2533 if (ch == NO_POLL_CHAR)
2542 #define pl011_early_read NULL
2546 * On non-ACPI systems, earlycon is enabled by specifying
2547 * "earlycon=pl011,<address>" on the kernel command line.
2549 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table,
2550 * by specifying only "earlycon" on the command line. Because it requires
2551 * SPCR, the console starts after ACPI is parsed, which is later than a
2552 * traditional early console.
2554 * To get the traditional early console that starts before ACPI is parsed,
2555 * specify the full "earlycon=pl011,<address>" option.
2557 static int __init pl011_early_console_setup(struct earlycon_device *device,
2560 if (!device->port.membase)
2563 device->con->write = pl011_early_write;
2564 device->con->read = pl011_early_read;
2568 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
2569 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
2572 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by
2573 * Erratum 44, traditional earlycon can be enabled by specifying
2574 * "earlycon=qdf2400_e44,<address>". Any options are ignored.
2576 * Alternatively, you can just specify "earlycon", and the early console
2577 * will be enabled with the information from the SPCR table. In this
2578 * case, the SPCR code will detect the need for the E44 work-around,
2579 * and set the console name to "qdf2400_e44".
2582 qdf2400_e44_early_console_setup(struct earlycon_device *device,
2585 if (!device->port.membase)
2588 device->con->write = qdf2400_e44_early_write;
2591 EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup);
2594 #define AMBA_CONSOLE NULL
2597 static struct uart_driver amba_reg = {
2598 .owner = THIS_MODULE,
2599 .driver_name = "ttyAMA",
2600 .dev_name = "ttyAMA",
2601 .major = SERIAL_AMBA_MAJOR,
2602 .minor = SERIAL_AMBA_MINOR,
2604 .cons = AMBA_CONSOLE,
2607 static int pl011_probe_dt_alias(int index, struct device *dev)
2609 struct device_node *np;
2610 static bool seen_dev_with_alias = false;
2611 static bool seen_dev_without_alias = false;
2614 if (!IS_ENABLED(CONFIG_OF))
2621 ret = of_alias_get_id(np, "serial");
2623 seen_dev_without_alias = true;
2626 seen_dev_with_alias = true;
2627 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2628 dev_warn(dev, "requested serial port %d not available.\n", ret);
2633 if (seen_dev_with_alias && seen_dev_without_alias)
2634 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2639 /* unregisters the driver also if no more ports are left */
2640 static void pl011_unregister_port(struct uart_amba_port *uap)
2645 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2646 if (amba_ports[i] == uap)
2647 amba_ports[i] = NULL;
2648 else if (amba_ports[i])
2651 pl011_dma_remove(uap);
2653 uart_unregister_driver(&amba_reg);
2656 static int pl011_find_free_port(void)
2660 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2661 if (amba_ports[i] == NULL)
2667 static int pl011_get_rs485_mode(struct uart_amba_port *uap)
2669 struct uart_port *port = &uap->port;
2670 struct serial_rs485 *rs485 = &port->rs485;
2673 ret = uart_get_rs485_mode(port);
2677 /* clamp the delays to [0, 100ms] */
2678 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
2679 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
2684 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2685 struct resource *mmiobase, int index)
2690 base = devm_ioremap_resource(dev, mmiobase);
2692 return PTR_ERR(base);
2694 index = pl011_probe_dt_alias(index, dev);
2696 uap->port.dev = dev;
2697 uap->port.mapbase = mmiobase->start;
2698 uap->port.membase = base;
2699 uap->port.fifosize = uap->fifosize;
2700 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE);
2701 uap->port.flags = UPF_BOOT_AUTOCONF;
2702 uap->port.line = index;
2704 ret = pl011_get_rs485_mode(uap);
2708 amba_ports[index] = uap;
2713 static int pl011_register_port(struct uart_amba_port *uap)
2717 /* Ensure interrupts from this UART are masked and cleared */
2718 pl011_write(0, uap, REG_IMSC);
2719 pl011_write(0xffff, uap, REG_ICR);
2721 if (!amba_reg.state) {
2722 ret = uart_register_driver(&amba_reg);
2724 dev_err(uap->port.dev,
2725 "Failed to register AMBA-PL011 driver\n");
2726 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2727 if (amba_ports[i] == uap)
2728 amba_ports[i] = NULL;
2733 ret = uart_add_one_port(&amba_reg, &uap->port);
2735 pl011_unregister_port(uap);
2740 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2742 struct uart_amba_port *uap;
2743 struct vendor_data *vendor = id->data;
2746 portnr = pl011_find_free_port();
2750 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2755 uap->clk = devm_clk_get(&dev->dev, NULL);
2756 if (IS_ERR(uap->clk))
2757 return PTR_ERR(uap->clk);
2759 uap->reg_offset = vendor->reg_offset;
2760 uap->vendor = vendor;
2761 uap->fifosize = vendor->get_fifosize(dev);
2762 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2763 uap->port.irq = dev->irq[0];
2764 uap->port.ops = &amba_pl011_pops;
2765 uap->port.rs485_config = pl011_rs485_config;
2766 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2768 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2772 amba_set_drvdata(dev, uap);
2774 return pl011_register_port(uap);
2777 static void pl011_remove(struct amba_device *dev)
2779 struct uart_amba_port *uap = amba_get_drvdata(dev);
2781 uart_remove_one_port(&amba_reg, &uap->port);
2782 pl011_unregister_port(uap);
2785 #ifdef CONFIG_PM_SLEEP
2786 static int pl011_suspend(struct device *dev)
2788 struct uart_amba_port *uap = dev_get_drvdata(dev);
2793 return uart_suspend_port(&amba_reg, &uap->port);
2796 static int pl011_resume(struct device *dev)
2798 struct uart_amba_port *uap = dev_get_drvdata(dev);
2803 return uart_resume_port(&amba_reg, &uap->port);
2807 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2809 static int sbsa_uart_probe(struct platform_device *pdev)
2811 struct uart_amba_port *uap;
2817 * Check the mandatory baud rate parameter in the DT node early
2818 * so that we can easily exit with the error.
2820 if (pdev->dev.of_node) {
2821 struct device_node *np = pdev->dev.of_node;
2823 ret = of_property_read_u32(np, "current-speed", &baudrate);
2830 portnr = pl011_find_free_port();
2834 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2839 ret = platform_get_irq(pdev, 0);
2842 uap->port.irq = ret;
2844 #ifdef CONFIG_ACPI_SPCR_TABLE
2845 if (qdf2400_e44_present) {
2846 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n");
2847 uap->vendor = &vendor_qdt_qdf2400_e44;
2850 uap->vendor = &vendor_sbsa;
2852 uap->reg_offset = uap->vendor->reg_offset;
2854 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2855 uap->port.ops = &sbsa_uart_pops;
2856 uap->fixed_baud = baudrate;
2858 snprintf(uap->type, sizeof(uap->type), "SBSA");
2860 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2862 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2866 platform_set_drvdata(pdev, uap);
2868 return pl011_register_port(uap);
2871 static int sbsa_uart_remove(struct platform_device *pdev)
2873 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2875 uart_remove_one_port(&amba_reg, &uap->port);
2876 pl011_unregister_port(uap);
2880 static const struct of_device_id sbsa_uart_of_match[] = {
2881 { .compatible = "arm,sbsa-uart", },
2884 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2886 static const struct acpi_device_id __maybe_unused sbsa_uart_acpi_match[] = {
2891 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2893 static struct platform_driver arm_sbsa_uart_platform_driver = {
2894 .probe = sbsa_uart_probe,
2895 .remove = sbsa_uart_remove,
2897 .name = "sbsa-uart",
2898 .pm = &pl011_dev_pm_ops,
2899 .of_match_table = of_match_ptr(sbsa_uart_of_match),
2900 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
2901 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2905 static const struct amba_id pl011_ids[] = {
2909 .data = &vendor_arm,
2919 MODULE_DEVICE_TABLE(amba, pl011_ids);
2921 static struct amba_driver pl011_driver = {
2923 .name = "uart-pl011",
2924 .pm = &pl011_dev_pm_ops,
2925 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2927 .id_table = pl011_ids,
2928 .probe = pl011_probe,
2929 .remove = pl011_remove,
2932 static int __init pl011_init(void)
2934 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2936 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
2937 pr_warn("could not register SBSA UART platform driver\n");
2938 return amba_driver_register(&pl011_driver);
2941 static void __exit pl011_exit(void)
2943 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
2944 amba_driver_unregister(&pl011_driver);
2948 * While this can be a module, if builtin it's most likely the console
2949 * So let's leave module_exit but move module_init to an earlier place
2951 arch_initcall(pl011_init);
2952 module_exit(pl011_exit);
2954 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2955 MODULE_DESCRIPTION("ARM AMBA serial port driver");
2956 MODULE_LICENSE("GPL");