1 // SPDX-License-Identifier: GPL-2.0+
3 * Base port operations for 8250/16550-type serial ports
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
8 * A note about mapbase / membase
10 * mapbase is the physical address of the IO port.
11 * membase is an 'ioremapped' cookie.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/ioport.h>
17 #include <linux/init.h>
18 #include <linux/console.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/sysrq.h>
21 #include <linux/delay.h>
22 #include <linux/platform_device.h>
23 #include <linux/tty.h>
24 #include <linux/ratelimit.h>
25 #include <linux/tty_flip.h>
26 #include <linux/serial.h>
27 #include <linux/serial_8250.h>
28 #include <linux/nmi.h>
29 #include <linux/mutex.h>
30 #include <linux/slab.h>
31 #include <linux/uaccess.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/ktime.h>
40 /* Nuvoton NPCM timeout register */
41 #define UART_NPCM_TOR 7
42 #define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */
48 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
50 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
53 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
56 * Here we define the default xmit fifo size used for each type of UART.
58 static const struct serial8250_config uart_config[] = {
83 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
84 .rxtrig_bytes = {1, 4, 8, 14},
85 .flags = UART_CAP_FIFO,
96 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
102 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
104 .rxtrig_bytes = {8, 16, 24, 28},
105 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
111 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
113 .rxtrig_bytes = {1, 16, 32, 56},
114 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
122 .name = "16C950/954",
125 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
126 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
127 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
133 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
135 .rxtrig_bytes = {8, 16, 56, 60},
136 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
142 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
143 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
149 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
150 .flags = UART_CAP_FIFO,
156 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
157 .flags = UART_CAP_FIFO | UART_NATSEMI,
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
170 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
171 .flags = UART_CAP_FIFO,
177 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
178 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
184 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
185 .flags = UART_CAP_FIFO | UART_CAP_AFE,
191 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
193 .rxtrig_bytes = {1, 4, 8, 14},
194 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
200 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
201 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
208 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
210 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
217 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
218 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
219 .flags = UART_CAP_FIFO,
221 [PORT_BRCM_TRUMANAGE] = {
225 .flags = UART_CAP_HFIFO,
230 [PORT_ALTR_16550_F32] = {
231 .name = "Altera 16550 FIFO32",
234 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
235 .rxtrig_bytes = {1, 8, 16, 30},
236 .flags = UART_CAP_FIFO | UART_CAP_AFE,
238 [PORT_ALTR_16550_F64] = {
239 .name = "Altera 16550 FIFO64",
242 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
243 .rxtrig_bytes = {1, 16, 32, 62},
244 .flags = UART_CAP_FIFO | UART_CAP_AFE,
246 [PORT_ALTR_16550_F128] = {
247 .name = "Altera 16550 FIFO128",
250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
251 .rxtrig_bytes = {1, 32, 64, 126},
252 .flags = UART_CAP_FIFO | UART_CAP_AFE,
255 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
256 * workaround of errata A-008006 which states that tx_loadsz should
257 * be configured less than Maximum supported fifo bytes.
259 [PORT_16550A_FSL64] = {
260 .name = "16550A_FSL64",
263 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
265 .flags = UART_CAP_FIFO,
268 .name = "Palmchip BK-3103",
271 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
272 .rxtrig_bytes = {1, 4, 8, 14},
273 .flags = UART_CAP_FIFO,
276 .name = "TI DA8xx/66AK2x",
279 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
281 .rxtrig_bytes = {1, 4, 8, 14},
282 .flags = UART_CAP_FIFO | UART_CAP_AFE,
285 .name = "MediaTek BTIF",
288 .fcr = UART_FCR_ENABLE_FIFO |
289 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
290 .flags = UART_CAP_FIFO,
293 .name = "Nuvoton 16550",
296 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
297 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
298 .rxtrig_bytes = {1, 4, 8, 14},
299 .flags = UART_CAP_FIFO,
305 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
306 .rxtrig_bytes = {1, 32, 64, 112},
307 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
311 /* Uart divisor latch read */
312 static int default_serial_dl_read(struct uart_8250_port *up)
314 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
317 /* Uart divisor latch write */
318 static void default_serial_dl_write(struct uart_8250_port *up, int value)
320 serial_out(up, UART_DLL, value & 0xff);
321 serial_out(up, UART_DLM, value >> 8 & 0xff);
324 #ifdef CONFIG_SERIAL_8250_RT288X
326 /* Au1x00/RT288x UART hardware has a weird register layout */
327 static const s8 au_io_in_map[8] = {
335 -1, /* UART_SCR (unmapped) */
338 static const s8 au_io_out_map[8] = {
344 -1, /* UART_LSR (unmapped) */
345 -1, /* UART_MSR (unmapped) */
346 -1, /* UART_SCR (unmapped) */
349 unsigned int au_serial_in(struct uart_port *p, int offset)
351 if (offset >= ARRAY_SIZE(au_io_in_map))
353 offset = au_io_in_map[offset];
356 return __raw_readl(p->membase + (offset << p->regshift));
359 void au_serial_out(struct uart_port *p, int offset, int value)
361 if (offset >= ARRAY_SIZE(au_io_out_map))
363 offset = au_io_out_map[offset];
366 __raw_writel(value, p->membase + (offset << p->regshift));
369 /* Au1x00 haven't got a standard divisor latch */
370 static int au_serial_dl_read(struct uart_8250_port *up)
372 return __raw_readl(up->port.membase + 0x28);
375 static void au_serial_dl_write(struct uart_8250_port *up, int value)
377 __raw_writel(value, up->port.membase + 0x28);
382 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
384 offset = offset << p->regshift;
385 outb(p->hub6 - 1 + offset, p->iobase);
386 return inb(p->iobase + 1);
389 static void hub6_serial_out(struct uart_port *p, int offset, int value)
391 offset = offset << p->regshift;
392 outb(p->hub6 - 1 + offset, p->iobase);
393 outb(value, p->iobase + 1);
396 static unsigned int mem_serial_in(struct uart_port *p, int offset)
398 offset = offset << p->regshift;
399 return readb(p->membase + offset);
402 static void mem_serial_out(struct uart_port *p, int offset, int value)
404 offset = offset << p->regshift;
405 writeb(value, p->membase + offset);
408 static void mem16_serial_out(struct uart_port *p, int offset, int value)
410 offset = offset << p->regshift;
411 writew(value, p->membase + offset);
414 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
416 offset = offset << p->regshift;
417 return readw(p->membase + offset);
420 static void mem32_serial_out(struct uart_port *p, int offset, int value)
422 offset = offset << p->regshift;
423 writel(value, p->membase + offset);
426 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
428 offset = offset << p->regshift;
429 return readl(p->membase + offset);
432 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
434 offset = offset << p->regshift;
435 iowrite32be(value, p->membase + offset);
438 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
440 offset = offset << p->regshift;
441 return ioread32be(p->membase + offset);
444 static unsigned int io_serial_in(struct uart_port *p, int offset)
446 offset = offset << p->regshift;
447 return inb(p->iobase + offset);
450 static void io_serial_out(struct uart_port *p, int offset, int value)
452 offset = offset << p->regshift;
453 outb(value, p->iobase + offset);
456 static int serial8250_default_handle_irq(struct uart_port *port);
458 static void set_io_from_upio(struct uart_port *p)
460 struct uart_8250_port *up = up_to_u8250p(p);
462 up->dl_read = default_serial_dl_read;
463 up->dl_write = default_serial_dl_write;
467 p->serial_in = hub6_serial_in;
468 p->serial_out = hub6_serial_out;
472 p->serial_in = mem_serial_in;
473 p->serial_out = mem_serial_out;
477 p->serial_in = mem16_serial_in;
478 p->serial_out = mem16_serial_out;
482 p->serial_in = mem32_serial_in;
483 p->serial_out = mem32_serial_out;
487 p->serial_in = mem32be_serial_in;
488 p->serial_out = mem32be_serial_out;
491 #ifdef CONFIG_SERIAL_8250_RT288X
493 p->serial_in = au_serial_in;
494 p->serial_out = au_serial_out;
495 up->dl_read = au_serial_dl_read;
496 up->dl_write = au_serial_dl_write;
501 p->serial_in = io_serial_in;
502 p->serial_out = io_serial_out;
505 /* Remember loaded iotype */
506 up->cur_iotype = p->iotype;
507 p->handle_irq = serial8250_default_handle_irq;
511 serial_port_out_sync(struct uart_port *p, int offset, int value)
519 p->serial_out(p, offset, value);
520 p->serial_in(p, UART_LCR); /* safe, no side-effects */
523 p->serial_out(p, offset, value);
530 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
532 serial_out(up, UART_SCR, offset);
533 serial_out(up, UART_ICR, value);
536 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
540 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
541 serial_out(up, UART_SCR, offset);
542 value = serial_in(up, UART_ICR);
543 serial_icr_write(up, UART_ACR, up->acr);
551 static void serial8250_clear_fifos(struct uart_8250_port *p)
553 if (p->capabilities & UART_CAP_FIFO) {
554 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
555 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
556 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
557 serial_out(p, UART_FCR, 0);
561 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
562 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
564 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
566 serial8250_clear_fifos(p);
567 serial_out(p, UART_FCR, p->fcr);
569 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
571 void serial8250_rpm_get(struct uart_8250_port *p)
573 if (!(p->capabilities & UART_CAP_RPM))
575 pm_runtime_get_sync(p->port.dev);
577 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
579 void serial8250_rpm_put(struct uart_8250_port *p)
581 if (!(p->capabilities & UART_CAP_RPM))
583 pm_runtime_mark_last_busy(p->port.dev);
584 pm_runtime_put_autosuspend(p->port.dev);
586 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
589 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
590 * @p: uart_8250_port port instance
592 * The function is used to start rs485 software emulating on the
593 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
594 * transmission. The function is idempotent, so it is safe to call it
597 * The caller MUST enable interrupt on empty shift register before
598 * calling serial8250_em485_init(). This interrupt is not a part of
599 * 8250 standard, but implementation defined.
601 * The function is supposed to be called from .rs485_config callback
602 * or from any other callback protected with p->port.lock spinlock.
604 * See also serial8250_em485_destroy()
606 * Return 0 - success, -errno - otherwise
608 static int serial8250_em485_init(struct uart_8250_port *p)
613 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
617 hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
619 hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
621 p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
622 p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
624 p->em485->active_timer = NULL;
625 p->em485->tx_stopped = true;
633 * serial8250_em485_destroy() - put uart_8250_port into normal state
634 * @p: uart_8250_port port instance
636 * The function is used to stop rs485 software emulating on the
637 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
638 * call it multiple times.
640 * The function is supposed to be called from .rs485_config callback
641 * or from any other callback protected with p->port.lock spinlock.
643 * See also serial8250_em485_init()
645 void serial8250_em485_destroy(struct uart_8250_port *p)
650 hrtimer_cancel(&p->em485->start_tx_timer);
651 hrtimer_cancel(&p->em485->stop_tx_timer);
656 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
659 * serial8250_em485_config() - generic ->rs485_config() callback
661 * @rs485: rs485 settings
663 * Generic callback usable by 8250 uart drivers to activate rs485 settings
664 * if the uart is incapable of driving RTS as a Transmit Enable signal in
665 * hardware, relying on software emulation instead.
667 int serial8250_em485_config(struct uart_port *port, struct serial_rs485 *rs485)
669 struct uart_8250_port *up = up_to_u8250p(port);
671 /* pick sane settings if the user hasn't */
672 if (!!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
673 !!(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
674 rs485->flags |= SER_RS485_RTS_ON_SEND;
675 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
678 /* clamp the delays to [0, 100ms] */
679 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
680 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
682 memset(rs485->padding, 0, sizeof(rs485->padding));
683 port->rs485 = *rs485;
685 gpiod_set_value(port->rs485_term_gpio,
686 rs485->flags & SER_RS485_TERMINATE_BUS);
689 * Both serial8250_em485_init() and serial8250_em485_destroy()
692 if (rs485->flags & SER_RS485_ENABLED) {
693 int ret = serial8250_em485_init(up);
696 rs485->flags &= ~SER_RS485_ENABLED;
697 port->rs485.flags &= ~SER_RS485_ENABLED;
702 serial8250_em485_destroy(up);
705 EXPORT_SYMBOL_GPL(serial8250_em485_config);
708 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
709 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
710 * empty and the HW can idle again.
712 void serial8250_rpm_get_tx(struct uart_8250_port *p)
714 unsigned char rpm_active;
716 if (!(p->capabilities & UART_CAP_RPM))
719 rpm_active = xchg(&p->rpm_tx_active, 1);
722 pm_runtime_get_sync(p->port.dev);
724 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
726 void serial8250_rpm_put_tx(struct uart_8250_port *p)
728 unsigned char rpm_active;
730 if (!(p->capabilities & UART_CAP_RPM))
733 rpm_active = xchg(&p->rpm_tx_active, 0);
736 pm_runtime_mark_last_busy(p->port.dev);
737 pm_runtime_put_autosuspend(p->port.dev);
739 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
742 * IER sleep support. UARTs which have EFRs need the "extended
743 * capability" bit enabled. Note that on XR16C850s, we need to
744 * reset LCR to write to IER.
746 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
748 unsigned char lcr = 0, efr = 0;
750 serial8250_rpm_get(p);
752 if (p->capabilities & UART_CAP_SLEEP) {
753 if (p->capabilities & UART_CAP_EFR) {
754 lcr = serial_in(p, UART_LCR);
755 efr = serial_in(p, UART_EFR);
756 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
757 serial_out(p, UART_EFR, UART_EFR_ECB);
758 serial_out(p, UART_LCR, 0);
760 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
761 if (p->capabilities & UART_CAP_EFR) {
762 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
763 serial_out(p, UART_EFR, efr);
764 serial_out(p, UART_LCR, lcr);
768 serial8250_rpm_put(p);
771 #ifdef CONFIG_SERIAL_8250_RSA
773 * Attempts to turn on the RSA FIFO. Returns zero on failure.
774 * We set the port uart clock rate if we succeed.
776 static int __enable_rsa(struct uart_8250_port *up)
781 mode = serial_in(up, UART_RSA_MSR);
782 result = mode & UART_RSA_MSR_FIFO;
785 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
786 mode = serial_in(up, UART_RSA_MSR);
787 result = mode & UART_RSA_MSR_FIFO;
791 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
796 static void enable_rsa(struct uart_8250_port *up)
798 if (up->port.type == PORT_RSA) {
799 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
800 spin_lock_irq(&up->port.lock);
802 spin_unlock_irq(&up->port.lock);
804 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
805 serial_out(up, UART_RSA_FRR, 0);
810 * Attempts to turn off the RSA FIFO. Returns zero on failure.
811 * It is unknown why interrupts were disabled in here. However,
812 * the caller is expected to preserve this behaviour by grabbing
813 * the spinlock before calling this function.
815 static void disable_rsa(struct uart_8250_port *up)
820 if (up->port.type == PORT_RSA &&
821 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
822 spin_lock_irq(&up->port.lock);
824 mode = serial_in(up, UART_RSA_MSR);
825 result = !(mode & UART_RSA_MSR_FIFO);
828 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
829 mode = serial_in(up, UART_RSA_MSR);
830 result = !(mode & UART_RSA_MSR_FIFO);
834 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
835 spin_unlock_irq(&up->port.lock);
838 #endif /* CONFIG_SERIAL_8250_RSA */
841 * This is a quickie test to see how big the FIFO is.
842 * It doesn't work at all the time, more's the pity.
844 static int size_fifo(struct uart_8250_port *up)
846 unsigned char old_fcr, old_mcr, old_lcr;
847 unsigned short old_dl;
850 old_lcr = serial_in(up, UART_LCR);
851 serial_out(up, UART_LCR, 0);
852 old_fcr = serial_in(up, UART_FCR);
853 old_mcr = serial8250_in_MCR(up);
854 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
855 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
856 serial8250_out_MCR(up, UART_MCR_LOOP);
857 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
858 old_dl = serial_dl_read(up);
859 serial_dl_write(up, 0x0001);
860 serial_out(up, UART_LCR, 0x03);
861 for (count = 0; count < 256; count++)
862 serial_out(up, UART_TX, count);
863 mdelay(20);/* FIXME - schedule_timeout */
864 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
865 (count < 256); count++)
866 serial_in(up, UART_RX);
867 serial_out(up, UART_FCR, old_fcr);
868 serial8250_out_MCR(up, old_mcr);
869 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
870 serial_dl_write(up, old_dl);
871 serial_out(up, UART_LCR, old_lcr);
877 * Read UART ID using the divisor method - set DLL and DLM to zero
878 * and the revision will be in DLL and device type in DLM. We
879 * preserve the device state across this.
881 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
883 unsigned char old_lcr;
884 unsigned int id, old_dl;
886 old_lcr = serial_in(p, UART_LCR);
887 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
888 old_dl = serial_dl_read(p);
889 serial_dl_write(p, 0);
890 id = serial_dl_read(p);
891 serial_dl_write(p, old_dl);
893 serial_out(p, UART_LCR, old_lcr);
899 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
900 * When this function is called we know it is at least a StarTech
901 * 16650 V2, but it might be one of several StarTech UARTs, or one of
902 * its clones. (We treat the broken original StarTech 16650 V1 as a
903 * 16550, and why not? Startech doesn't seem to even acknowledge its
906 * What evil have men's minds wrought...
908 static void autoconfig_has_efr(struct uart_8250_port *up)
910 unsigned int id1, id2, id3, rev;
913 * Everything with an EFR has SLEEP
915 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
918 * First we check to see if it's an Oxford Semiconductor UART.
920 * If we have to do this here because some non-National
921 * Semiconductor clone chips lock up if you try writing to the
922 * LSR register (which serial_icr_read does)
926 * Check for Oxford Semiconductor 16C950.
928 * EFR [4] must be set else this test fails.
930 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
931 * claims that it's needed for 952 dual UART's (which are not
932 * recommended for new designs).
935 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
936 serial_out(up, UART_EFR, UART_EFR_ECB);
937 serial_out(up, UART_LCR, 0x00);
938 id1 = serial_icr_read(up, UART_ID1);
939 id2 = serial_icr_read(up, UART_ID2);
940 id3 = serial_icr_read(up, UART_ID3);
941 rev = serial_icr_read(up, UART_REV);
943 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
945 if (id1 == 0x16 && id2 == 0xC9 &&
946 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
947 up->port.type = PORT_16C950;
950 * Enable work around for the Oxford Semiconductor 952 rev B
951 * chip which causes it to seriously miscalculate baud rates
954 if (id3 == 0x52 && rev == 0x01)
955 up->bugs |= UART_BUG_QUOT;
960 * We check for a XR16C850 by setting DLL and DLM to 0, and then
961 * reading back DLL and DLM. The chip type depends on the DLM
963 * 0x10 - XR16C850 and the DLL contains the chip revision.
967 id1 = autoconfig_read_divisor_id(up);
968 DEBUG_AUTOCONF("850id=%04x ", id1);
971 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
972 up->port.type = PORT_16850;
977 * It wasn't an XR16C850.
979 * We distinguish between the '654 and the '650 by counting
980 * how many bytes are in the FIFO. I'm using this for now,
981 * since that's the technique that was sent to me in the
982 * serial driver update, but I'm not convinced this works.
983 * I've had problems doing this in the past. -TYT
985 if (size_fifo(up) == 64)
986 up->port.type = PORT_16654;
988 up->port.type = PORT_16650V2;
992 * We detected a chip without a FIFO. Only two fall into
993 * this category - the original 8250 and the 16450. The
994 * 16450 has a scratch register (accessible with LCR=0)
996 static void autoconfig_8250(struct uart_8250_port *up)
998 unsigned char scratch, status1, status2;
1000 up->port.type = PORT_8250;
1002 scratch = serial_in(up, UART_SCR);
1003 serial_out(up, UART_SCR, 0xa5);
1004 status1 = serial_in(up, UART_SCR);
1005 serial_out(up, UART_SCR, 0x5a);
1006 status2 = serial_in(up, UART_SCR);
1007 serial_out(up, UART_SCR, scratch);
1009 if (status1 == 0xa5 && status2 == 0x5a)
1010 up->port.type = PORT_16450;
1013 static int broken_efr(struct uart_8250_port *up)
1016 * Exar ST16C2550 "A2" devices incorrectly detect as
1017 * having an EFR, and report an ID of 0x0201. See
1018 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1020 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
1027 * We know that the chip has FIFOs. Does it have an EFR? The
1028 * EFR is located in the same register position as the IIR and
1029 * we know the top two bits of the IIR are currently set. The
1030 * EFR should contain zero. Try to read the EFR.
1032 static void autoconfig_16550a(struct uart_8250_port *up)
1034 unsigned char status1, status2;
1035 unsigned int iersave;
1037 up->port.type = PORT_16550A;
1038 up->capabilities |= UART_CAP_FIFO;
1040 if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS))
1044 * Check for presence of the EFR when DLAB is set.
1045 * Only ST16C650V1 UARTs pass this test.
1047 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1048 if (serial_in(up, UART_EFR) == 0) {
1049 serial_out(up, UART_EFR, 0xA8);
1050 if (serial_in(up, UART_EFR) != 0) {
1051 DEBUG_AUTOCONF("EFRv1 ");
1052 up->port.type = PORT_16650;
1053 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1055 serial_out(up, UART_LCR, 0);
1056 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1058 status1 = serial_in(up, UART_IIR) >> 5;
1059 serial_out(up, UART_FCR, 0);
1060 serial_out(up, UART_LCR, 0);
1063 up->port.type = PORT_16550A_FSL64;
1065 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1067 serial_out(up, UART_EFR, 0);
1072 * Maybe it requires 0xbf to be written to the LCR.
1073 * (other ST16C650V2 UARTs, TI16C752A, etc)
1075 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1076 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1077 DEBUG_AUTOCONF("EFRv2 ");
1078 autoconfig_has_efr(up);
1083 * Check for a National Semiconductor SuperIO chip.
1084 * Attempt to switch to bank 2, read the value of the LOOP bit
1085 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1086 * switch back to bank 2, read it from EXCR1 again and check
1087 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1089 serial_out(up, UART_LCR, 0);
1090 status1 = serial8250_in_MCR(up);
1091 serial_out(up, UART_LCR, 0xE0);
1092 status2 = serial_in(up, 0x02); /* EXCR1 */
1094 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1095 serial_out(up, UART_LCR, 0);
1096 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1097 serial_out(up, UART_LCR, 0xE0);
1098 status2 = serial_in(up, 0x02); /* EXCR1 */
1099 serial_out(up, UART_LCR, 0);
1100 serial8250_out_MCR(up, status1);
1102 if ((status2 ^ status1) & UART_MCR_LOOP) {
1103 unsigned short quot;
1105 serial_out(up, UART_LCR, 0xE0);
1107 quot = serial_dl_read(up);
1110 if (ns16550a_goto_highspeed(up))
1111 serial_dl_write(up, quot);
1113 serial_out(up, UART_LCR, 0);
1115 up->port.uartclk = 921600*16;
1116 up->port.type = PORT_NS16550A;
1117 up->capabilities |= UART_NATSEMI;
1123 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1124 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1125 * Try setting it with and without DLAB set. Cheap clones
1126 * set bit 5 without DLAB set.
1128 serial_out(up, UART_LCR, 0);
1129 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1130 status1 = serial_in(up, UART_IIR) >> 5;
1131 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1132 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1133 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1134 status2 = serial_in(up, UART_IIR) >> 5;
1135 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1136 serial_out(up, UART_LCR, 0);
1138 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1140 if (status1 == 6 && status2 == 7) {
1141 up->port.type = PORT_16750;
1142 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1147 * Try writing and reading the UART_IER_UUE bit (b6).
1148 * If it works, this is probably one of the Xscale platform's
1150 * We're going to explicitly set the UUE bit to 0 before
1151 * trying to write and read a 1 just to make sure it's not
1152 * already a 1 and maybe locked there before we even start start.
1154 iersave = serial_in(up, UART_IER);
1155 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1156 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1158 * OK it's in a known zero state, try writing and reading
1159 * without disturbing the current state of the other bits.
1161 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1162 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1165 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1167 DEBUG_AUTOCONF("Xscale ");
1168 up->port.type = PORT_XSCALE;
1169 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1174 * If we got here we couldn't force the IER_UUE bit to 0.
1175 * Log it and continue.
1177 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1179 serial_out(up, UART_IER, iersave);
1182 * We distinguish between 16550A and U6 16550A by counting
1183 * how many bytes are in the FIFO.
1185 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1186 up->port.type = PORT_U6_16550A;
1187 up->capabilities |= UART_CAP_AFE;
1192 * This routine is called by rs_init() to initialize a specific serial
1193 * port. It determines what type of UART chip this serial port is
1194 * using: 8250, 16450, 16550, 16550A. The important question is
1195 * whether or not this UART is a 16550A or not, since this will
1196 * determine whether or not we can use its FIFO features or not.
1198 static void autoconfig(struct uart_8250_port *up)
1200 unsigned char status1, scratch, scratch2, scratch3;
1201 unsigned char save_lcr, save_mcr;
1202 struct uart_port *port = &up->port;
1203 unsigned long flags;
1204 unsigned int old_capabilities;
1206 if (!port->iobase && !port->mapbase && !port->membase)
1209 DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1210 port->name, port->iobase, port->membase);
1213 * We really do need global IRQs disabled here - we're going to
1214 * be frobbing the chips IRQ enable register to see if it exists.
1216 spin_lock_irqsave(&port->lock, flags);
1218 up->capabilities = 0;
1221 if (!(port->flags & UPF_BUGGY_UART)) {
1223 * Do a simple existence test first; if we fail this,
1224 * there's no point trying anything else.
1226 * 0x80 is used as a nonsense port to prevent against
1227 * false positives due to ISA bus float. The
1228 * assumption is that 0x80 is a non-existent port;
1229 * which should be safe since include/asm/io.h also
1230 * makes this assumption.
1232 * Note: this is safe as long as MCR bit 4 is clear
1233 * and the device is in "PC" mode.
1235 scratch = serial_in(up, UART_IER);
1236 serial_out(up, UART_IER, 0);
1241 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1242 * 16C754B) allow only to modify them if an EFR bit is set.
1244 scratch2 = serial_in(up, UART_IER) & 0x0f;
1245 serial_out(up, UART_IER, 0x0F);
1249 scratch3 = serial_in(up, UART_IER) & 0x0f;
1250 serial_out(up, UART_IER, scratch);
1251 if (scratch2 != 0 || scratch3 != 0x0F) {
1253 * We failed; there's nothing here
1255 spin_unlock_irqrestore(&port->lock, flags);
1256 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1257 scratch2, scratch3);
1262 save_mcr = serial8250_in_MCR(up);
1263 save_lcr = serial_in(up, UART_LCR);
1266 * Check to see if a UART is really there. Certain broken
1267 * internal modems based on the Rockwell chipset fail this
1268 * test, because they apparently don't implement the loopback
1269 * test mode. So this test is skipped on the COM 1 through
1270 * COM 4 ports. This *should* be safe, since no board
1271 * manufacturer would be stupid enough to design a board
1272 * that conflicts with COM 1-4 --- we hope!
1274 if (!(port->flags & UPF_SKIP_TEST)) {
1275 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1276 status1 = serial_in(up, UART_MSR) & 0xF0;
1277 serial8250_out_MCR(up, save_mcr);
1278 if (status1 != 0x90) {
1279 spin_unlock_irqrestore(&port->lock, flags);
1280 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1287 * We're pretty sure there's a port here. Lets find out what
1288 * type of port it is. The IIR top two bits allows us to find
1289 * out if it's 8250 or 16450, 16550, 16550A or later. This
1290 * determines what we test for next.
1292 * We also initialise the EFR (if any) to zero for later. The
1293 * EFR occupies the same register location as the FCR and IIR.
1295 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1296 serial_out(up, UART_EFR, 0);
1297 serial_out(up, UART_LCR, 0);
1299 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1300 scratch = serial_in(up, UART_IIR) >> 6;
1304 autoconfig_8250(up);
1307 port->type = PORT_UNKNOWN;
1310 port->type = PORT_16550;
1313 autoconfig_16550a(up);
1317 #ifdef CONFIG_SERIAL_8250_RSA
1319 * Only probe for RSA ports if we got the region.
1321 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1323 port->type = PORT_RSA;
1326 serial_out(up, UART_LCR, save_lcr);
1328 port->fifosize = uart_config[up->port.type].fifo_size;
1329 old_capabilities = up->capabilities;
1330 up->capabilities = uart_config[port->type].flags;
1331 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1333 if (port->type == PORT_UNKNOWN)
1339 #ifdef CONFIG_SERIAL_8250_RSA
1340 if (port->type == PORT_RSA)
1341 serial_out(up, UART_RSA_FRR, 0);
1343 serial8250_out_MCR(up, save_mcr);
1344 serial8250_clear_fifos(up);
1345 serial_in(up, UART_RX);
1346 if (up->capabilities & UART_CAP_UUE)
1347 serial_out(up, UART_IER, UART_IER_UUE);
1349 serial_out(up, UART_IER, 0);
1352 spin_unlock_irqrestore(&port->lock, flags);
1355 * Check if the device is a Fintek F81216A
1357 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1358 fintek_8250_probe(up);
1360 if (up->capabilities != old_capabilities) {
1361 dev_warn(port->dev, "detected caps %08x should be %08x\n",
1362 old_capabilities, up->capabilities);
1365 DEBUG_AUTOCONF("iir=%d ", scratch);
1366 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1369 static void autoconfig_irq(struct uart_8250_port *up)
1371 struct uart_port *port = &up->port;
1372 unsigned char save_mcr, save_ier;
1373 unsigned char save_ICP = 0;
1374 unsigned int ICP = 0;
1378 if (port->flags & UPF_FOURPORT) {
1379 ICP = (port->iobase & 0xfe0) | 0x1f;
1380 save_ICP = inb_p(ICP);
1385 if (uart_console(port))
1388 /* forget possible initially masked and pending IRQ */
1389 probe_irq_off(probe_irq_on());
1390 save_mcr = serial8250_in_MCR(up);
1391 save_ier = serial_in(up, UART_IER);
1392 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1394 irqs = probe_irq_on();
1395 serial8250_out_MCR(up, 0);
1397 if (port->flags & UPF_FOURPORT) {
1398 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1400 serial8250_out_MCR(up,
1401 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1403 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1404 serial_in(up, UART_LSR);
1405 serial_in(up, UART_RX);
1406 serial_in(up, UART_IIR);
1407 serial_in(up, UART_MSR);
1408 serial_out(up, UART_TX, 0xFF);
1410 irq = probe_irq_off(irqs);
1412 serial8250_out_MCR(up, save_mcr);
1413 serial_out(up, UART_IER, save_ier);
1415 if (port->flags & UPF_FOURPORT)
1416 outb_p(save_ICP, ICP);
1418 if (uart_console(port))
1421 port->irq = (irq > 0) ? irq : 0;
1424 static void serial8250_stop_rx(struct uart_port *port)
1426 struct uart_8250_port *up = up_to_u8250p(port);
1428 serial8250_rpm_get(up);
1430 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1431 up->port.read_status_mask &= ~UART_LSR_DR;
1432 serial_port_out(port, UART_IER, up->ier);
1434 serial8250_rpm_put(up);
1438 * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback
1439 * @p: uart 8250 port
1441 * Generic callback usable by 8250 uart drivers to stop rs485 transmission.
1443 void serial8250_em485_stop_tx(struct uart_8250_port *p)
1445 unsigned char mcr = serial8250_in_MCR(p);
1447 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
1448 mcr |= UART_MCR_RTS;
1450 mcr &= ~UART_MCR_RTS;
1451 serial8250_out_MCR(p, mcr);
1454 * Empty the RX FIFO, we are not interested in anything
1455 * received during the half-duplex transmission.
1456 * Enable previously disabled RX interrupts.
1458 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1459 serial8250_clear_and_reinit_fifos(p);
1461 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1462 serial_port_out(&p->port, UART_IER, p->ier);
1465 EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx);
1467 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1469 struct uart_8250_em485 *em485;
1470 struct uart_8250_port *p;
1471 unsigned long flags;
1473 em485 = container_of(t, struct uart_8250_em485, stop_tx_timer);
1476 serial8250_rpm_get(p);
1477 spin_lock_irqsave(&p->port.lock, flags);
1478 if (em485->active_timer == &em485->stop_tx_timer) {
1479 p->rs485_stop_tx(p);
1480 em485->active_timer = NULL;
1481 em485->tx_stopped = true;
1483 spin_unlock_irqrestore(&p->port.lock, flags);
1484 serial8250_rpm_put(p);
1485 return HRTIMER_NORESTART;
1488 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1490 long sec = msec / 1000;
1491 long nsec = (msec % 1000) * 1000000;
1492 ktime_t t = ktime_set(sec, nsec);
1494 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1497 static void __stop_tx_rs485(struct uart_8250_port *p)
1499 struct uart_8250_em485 *em485 = p->em485;
1502 * rs485_stop_tx() is going to set RTS according to config
1503 * AND flush RX FIFO if required.
1505 if (p->port.rs485.delay_rts_after_send > 0) {
1506 em485->active_timer = &em485->stop_tx_timer;
1507 start_hrtimer_ms(&em485->stop_tx_timer,
1508 p->port.rs485.delay_rts_after_send);
1510 p->rs485_stop_tx(p);
1511 em485->active_timer = NULL;
1512 em485->tx_stopped = true;
1516 static inline void __do_stop_tx(struct uart_8250_port *p)
1518 if (serial8250_clear_THRI(p))
1519 serial8250_rpm_put_tx(p);
1522 static inline void __stop_tx(struct uart_8250_port *p)
1524 struct uart_8250_em485 *em485 = p->em485;
1527 unsigned char lsr = serial_in(p, UART_LSR);
1529 * To provide required timeing and allow FIFO transfer,
1530 * __stop_tx_rs485() must be called only when both FIFO and
1531 * shift register are empty. It is for device driver to enable
1532 * interrupt on TEMT.
1534 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1542 static void serial8250_stop_tx(struct uart_port *port)
1544 struct uart_8250_port *up = up_to_u8250p(port);
1546 serial8250_rpm_get(up);
1550 * We really want to stop the transmitter from sending.
1552 if (port->type == PORT_16C950) {
1553 up->acr |= UART_ACR_TXDIS;
1554 serial_icr_write(up, UART_ACR, up->acr);
1556 serial8250_rpm_put(up);
1559 static inline void __start_tx(struct uart_port *port)
1561 struct uart_8250_port *up = up_to_u8250p(port);
1563 if (up->dma && !up->dma->tx_dma(up))
1566 if (serial8250_set_THRI(up)) {
1567 if (up->bugs & UART_BUG_TXEN) {
1570 lsr = serial_in(up, UART_LSR);
1571 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1572 if (lsr & UART_LSR_THRE)
1573 serial8250_tx_chars(up);
1578 * Re-enable the transmitter if we disabled it.
1580 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1581 up->acr &= ~UART_ACR_TXDIS;
1582 serial_icr_write(up, UART_ACR, up->acr);
1587 * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback
1588 * @up: uart 8250 port
1590 * Generic callback usable by 8250 uart drivers to start rs485 transmission.
1591 * Assumes that setting the RTS bit in the MCR register means RTS is high.
1592 * (Some chips use inverse semantics.) Further assumes that reception is
1593 * stoppable by disabling the UART_IER_RDI interrupt. (Some chips set the
1594 * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.)
1596 void serial8250_em485_start_tx(struct uart_8250_port *up)
1598 unsigned char mcr = serial8250_in_MCR(up);
1600 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1601 serial8250_stop_rx(&up->port);
1603 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1604 mcr |= UART_MCR_RTS;
1606 mcr &= ~UART_MCR_RTS;
1607 serial8250_out_MCR(up, mcr);
1609 EXPORT_SYMBOL_GPL(serial8250_em485_start_tx);
1611 static inline void start_tx_rs485(struct uart_port *port)
1613 struct uart_8250_port *up = up_to_u8250p(port);
1614 struct uart_8250_em485 *em485 = up->em485;
1616 em485->active_timer = NULL;
1618 if (em485->tx_stopped) {
1619 em485->tx_stopped = false;
1621 up->rs485_start_tx(up);
1623 if (up->port.rs485.delay_rts_before_send > 0) {
1624 em485->active_timer = &em485->start_tx_timer;
1625 start_hrtimer_ms(&em485->start_tx_timer,
1626 up->port.rs485.delay_rts_before_send);
1634 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1636 struct uart_8250_em485 *em485;
1637 struct uart_8250_port *p;
1638 unsigned long flags;
1640 em485 = container_of(t, struct uart_8250_em485, start_tx_timer);
1643 spin_lock_irqsave(&p->port.lock, flags);
1644 if (em485->active_timer == &em485->start_tx_timer) {
1645 __start_tx(&p->port);
1646 em485->active_timer = NULL;
1648 spin_unlock_irqrestore(&p->port.lock, flags);
1649 return HRTIMER_NORESTART;
1652 static void serial8250_start_tx(struct uart_port *port)
1654 struct uart_8250_port *up = up_to_u8250p(port);
1655 struct uart_8250_em485 *em485 = up->em485;
1657 serial8250_rpm_get_tx(up);
1660 em485->active_timer == &em485->start_tx_timer)
1664 start_tx_rs485(port);
1669 static void serial8250_throttle(struct uart_port *port)
1671 port->throttle(port);
1674 static void serial8250_unthrottle(struct uart_port *port)
1676 port->unthrottle(port);
1679 static void serial8250_disable_ms(struct uart_port *port)
1681 struct uart_8250_port *up = up_to_u8250p(port);
1683 /* no MSR capabilities */
1684 if (up->bugs & UART_BUG_NOMSR)
1687 mctrl_gpio_disable_ms(up->gpios);
1689 up->ier &= ~UART_IER_MSI;
1690 serial_port_out(port, UART_IER, up->ier);
1693 static void serial8250_enable_ms(struct uart_port *port)
1695 struct uart_8250_port *up = up_to_u8250p(port);
1697 /* no MSR capabilities */
1698 if (up->bugs & UART_BUG_NOMSR)
1701 mctrl_gpio_enable_ms(up->gpios);
1703 up->ier |= UART_IER_MSI;
1705 serial8250_rpm_get(up);
1706 serial_port_out(port, UART_IER, up->ier);
1707 serial8250_rpm_put(up);
1710 void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1712 struct uart_port *port = &up->port;
1714 char flag = TTY_NORMAL;
1716 if (likely(lsr & UART_LSR_DR))
1717 ch = serial_in(up, UART_RX);
1720 * Intel 82571 has a Serial Over Lan device that will
1721 * set UART_LSR_BI without setting UART_LSR_DR when
1722 * it receives a break. To avoid reading from the
1723 * receive buffer without UART_LSR_DR bit set, we
1724 * just force the read character to be 0
1730 lsr |= up->lsr_saved_flags;
1731 up->lsr_saved_flags = 0;
1733 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1734 if (lsr & UART_LSR_BI) {
1735 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1738 * We do the SysRQ and SAK checking
1739 * here because otherwise the break
1740 * may get masked by ignore_status_mask
1741 * or read_status_mask.
1743 if (uart_handle_break(port))
1745 } else if (lsr & UART_LSR_PE)
1746 port->icount.parity++;
1747 else if (lsr & UART_LSR_FE)
1748 port->icount.frame++;
1749 if (lsr & UART_LSR_OE)
1750 port->icount.overrun++;
1753 * Mask off conditions which should be ignored.
1755 lsr &= port->read_status_mask;
1757 if (lsr & UART_LSR_BI) {
1758 dev_dbg(port->dev, "handling break\n");
1760 } else if (lsr & UART_LSR_PE)
1762 else if (lsr & UART_LSR_FE)
1765 if (uart_prepare_sysrq_char(port, ch))
1768 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1770 EXPORT_SYMBOL_GPL(serial8250_read_char);
1773 * serial8250_rx_chars: processes according to the passed in LSR
1774 * value, and returns the remaining LSR bits not handled
1775 * by this Rx routine.
1777 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1779 struct uart_port *port = &up->port;
1780 int max_count = 256;
1783 serial8250_read_char(up, lsr);
1784 if (--max_count == 0)
1786 lsr = serial_in(up, UART_LSR);
1787 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1789 tty_flip_buffer_push(&port->state->port);
1792 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1794 void serial8250_tx_chars(struct uart_8250_port *up)
1796 struct uart_port *port = &up->port;
1797 struct circ_buf *xmit = &port->state->xmit;
1801 serial_out(up, UART_TX, port->x_char);
1806 if (uart_tx_stopped(port)) {
1807 serial8250_stop_tx(port);
1810 if (uart_circ_empty(xmit)) {
1815 count = up->tx_loadsz;
1817 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1818 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1820 if (uart_circ_empty(xmit))
1822 if ((up->capabilities & UART_CAP_HFIFO) &&
1823 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1825 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1826 if ((up->capabilities & UART_CAP_MINI) &&
1827 !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1829 } while (--count > 0);
1831 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1832 uart_write_wakeup(port);
1835 * With RPM enabled, we have to wait until the FIFO is empty before the
1836 * HW can go idle. So we get here once again with empty FIFO and disable
1837 * the interrupt and RPM in __stop_tx()
1839 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1842 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1844 /* Caller holds uart port lock */
1845 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1847 struct uart_port *port = &up->port;
1848 unsigned int status = serial_in(up, UART_MSR);
1850 status |= up->msr_saved_flags;
1851 up->msr_saved_flags = 0;
1852 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1853 port->state != NULL) {
1854 if (status & UART_MSR_TERI)
1856 if (status & UART_MSR_DDSR)
1858 if (status & UART_MSR_DDCD)
1859 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1860 if (status & UART_MSR_DCTS)
1861 uart_handle_cts_change(port, status & UART_MSR_CTS);
1863 wake_up_interruptible(&port->state->port.delta_msr_wait);
1868 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1870 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1872 switch (iir & 0x3f) {
1873 case UART_IIR_RX_TIMEOUT:
1874 serial8250_rx_dma_flush(up);
1879 return up->dma->rx_dma(up);
1883 * This handles the interrupt from one port.
1885 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1887 unsigned char status;
1888 unsigned long flags;
1889 struct uart_8250_port *up = up_to_u8250p(port);
1890 bool skip_rx = false;
1892 if (iir & UART_IIR_NO_INT)
1895 spin_lock_irqsave(&port->lock, flags);
1897 status = serial_port_in(port, UART_LSR);
1900 * If port is stopped and there are no error conditions in the
1901 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1902 * overflow. Not servicing, RX FIFO would trigger auto HW flow
1903 * control when FIFO occupancy reaches preset threshold, thus
1904 * halting RX. This only works when auto HW flow control is
1907 if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1908 (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1909 !(port->read_status_mask & UART_LSR_DR))
1912 if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1913 if (!up->dma || handle_rx_dma(up, iir))
1914 status = serial8250_rx_chars(up, status);
1916 serial8250_modem_status(up);
1917 if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE) &&
1918 (up->ier & UART_IER_THRI))
1919 serial8250_tx_chars(up);
1921 uart_unlock_and_check_sysrq(port, flags);
1924 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1926 static int serial8250_default_handle_irq(struct uart_port *port)
1928 struct uart_8250_port *up = up_to_u8250p(port);
1932 serial8250_rpm_get(up);
1934 iir = serial_port_in(port, UART_IIR);
1935 ret = serial8250_handle_irq(port, iir);
1937 serial8250_rpm_put(up);
1942 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1943 * have a programmable TX threshold that triggers the THRE interrupt in
1944 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1945 * has space available. Load it up with tx_loadsz bytes.
1947 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1949 unsigned long flags;
1950 unsigned int iir = serial_port_in(port, UART_IIR);
1952 /* TX Threshold IRQ triggered so load up FIFO */
1953 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1954 struct uart_8250_port *up = up_to_u8250p(port);
1956 spin_lock_irqsave(&port->lock, flags);
1957 serial8250_tx_chars(up);
1958 spin_unlock_irqrestore(&port->lock, flags);
1961 iir = serial_port_in(port, UART_IIR);
1962 return serial8250_handle_irq(port, iir);
1965 static unsigned int serial8250_tx_empty(struct uart_port *port)
1967 struct uart_8250_port *up = up_to_u8250p(port);
1968 unsigned long flags;
1971 serial8250_rpm_get(up);
1973 spin_lock_irqsave(&port->lock, flags);
1974 lsr = serial_port_in(port, UART_LSR);
1975 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1976 spin_unlock_irqrestore(&port->lock, flags);
1978 serial8250_rpm_put(up);
1980 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1983 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1985 struct uart_8250_port *up = up_to_u8250p(port);
1986 unsigned int status;
1989 serial8250_rpm_get(up);
1990 status = serial8250_modem_status(up);
1991 serial8250_rpm_put(up);
1993 val = serial8250_MSR_to_TIOCM(status);
1995 return mctrl_gpio_get(up->gpios, &val);
1999 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
2001 static unsigned int serial8250_get_mctrl(struct uart_port *port)
2003 if (port->get_mctrl)
2004 return port->get_mctrl(port);
2005 return serial8250_do_get_mctrl(port);
2008 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
2010 struct uart_8250_port *up = up_to_u8250p(port);
2013 if (port->rs485.flags & SER_RS485_ENABLED) {
2014 if (serial8250_in_MCR(up) & UART_MCR_RTS)
2017 mctrl &= ~TIOCM_RTS;
2020 mcr = serial8250_TIOCM_to_MCR(mctrl);
2022 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
2024 serial8250_out_MCR(up, mcr);
2026 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2028 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2030 if (port->set_mctrl)
2031 port->set_mctrl(port, mctrl);
2033 serial8250_do_set_mctrl(port, mctrl);
2036 static void serial8250_break_ctl(struct uart_port *port, int break_state)
2038 struct uart_8250_port *up = up_to_u8250p(port);
2039 unsigned long flags;
2041 serial8250_rpm_get(up);
2042 spin_lock_irqsave(&port->lock, flags);
2043 if (break_state == -1)
2044 up->lcr |= UART_LCR_SBC;
2046 up->lcr &= ~UART_LCR_SBC;
2047 serial_port_out(port, UART_LCR, up->lcr);
2048 spin_unlock_irqrestore(&port->lock, flags);
2049 serial8250_rpm_put(up);
2053 * Wait for transmitter & holding register to empty
2055 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2057 unsigned int status, tmout = 10000;
2059 /* Wait up to 10ms for the character(s) to be sent. */
2061 status = serial_in(up, UART_LSR);
2063 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2065 if ((status & bits) == bits)
2070 touch_nmi_watchdog();
2073 /* Wait up to 1s for flow control if necessary */
2074 if (up->port.flags & UPF_CONS_FLOW) {
2075 for (tmout = 1000000; tmout; tmout--) {
2076 unsigned int msr = serial_in(up, UART_MSR);
2077 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2078 if (msr & UART_MSR_CTS)
2081 touch_nmi_watchdog();
2086 #ifdef CONFIG_CONSOLE_POLL
2088 * Console polling routines for writing and reading from the uart while
2089 * in an interrupt or debug context.
2092 static int serial8250_get_poll_char(struct uart_port *port)
2094 struct uart_8250_port *up = up_to_u8250p(port);
2098 serial8250_rpm_get(up);
2100 lsr = serial_port_in(port, UART_LSR);
2102 if (!(lsr & UART_LSR_DR)) {
2103 status = NO_POLL_CHAR;
2107 status = serial_port_in(port, UART_RX);
2109 serial8250_rpm_put(up);
2114 static void serial8250_put_poll_char(struct uart_port *port,
2118 struct uart_8250_port *up = up_to_u8250p(port);
2120 serial8250_rpm_get(up);
2122 * First save the IER then disable the interrupts
2124 ier = serial_port_in(port, UART_IER);
2125 if (up->capabilities & UART_CAP_UUE)
2126 serial_port_out(port, UART_IER, UART_IER_UUE);
2128 serial_port_out(port, UART_IER, 0);
2130 wait_for_xmitr(up, BOTH_EMPTY);
2132 * Send the character out.
2134 serial_port_out(port, UART_TX, c);
2137 * Finally, wait for transmitter to become empty
2138 * and restore the IER
2140 wait_for_xmitr(up, BOTH_EMPTY);
2141 serial_port_out(port, UART_IER, ier);
2142 serial8250_rpm_put(up);
2145 #endif /* CONFIG_CONSOLE_POLL */
2147 int serial8250_do_startup(struct uart_port *port)
2149 struct uart_8250_port *up = up_to_u8250p(port);
2150 unsigned long flags;
2151 unsigned char lsr, iir;
2154 if (!port->fifosize)
2155 port->fifosize = uart_config[port->type].fifo_size;
2157 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2158 if (!up->capabilities)
2159 up->capabilities = uart_config[port->type].flags;
2162 if (port->iotype != up->cur_iotype)
2163 set_io_from_upio(port);
2165 serial8250_rpm_get(up);
2166 if (port->type == PORT_16C950) {
2167 /* Wake up and initialize UART */
2169 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2170 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2171 serial_port_out(port, UART_IER, 0);
2172 serial_port_out(port, UART_LCR, 0);
2173 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2174 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2175 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2176 serial_port_out(port, UART_LCR, 0);
2179 if (port->type == PORT_DA830) {
2180 /* Reset the port */
2181 serial_port_out(port, UART_IER, 0);
2182 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2185 /* Enable Tx, Rx and free run mode */
2186 serial_port_out(port, UART_DA830_PWREMU_MGMT,
2187 UART_DA830_PWREMU_MGMT_UTRST |
2188 UART_DA830_PWREMU_MGMT_URRST |
2189 UART_DA830_PWREMU_MGMT_FREE);
2192 if (port->type == PORT_NPCM) {
2194 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2195 * register). Enable it, and set TIOC (timeout interrupt
2196 * comparator) to be 0x20 for correct operation.
2198 serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2201 #ifdef CONFIG_SERIAL_8250_RSA
2203 * If this is an RSA port, see if we can kick it up to the
2204 * higher speed clock.
2210 * Clear the FIFO buffers and disable them.
2211 * (they will be reenabled in set_termios())
2213 serial8250_clear_fifos(up);
2216 * Clear the interrupt registers.
2218 serial_port_in(port, UART_LSR);
2219 serial_port_in(port, UART_RX);
2220 serial_port_in(port, UART_IIR);
2221 serial_port_in(port, UART_MSR);
2224 * At this point, there's no way the LSR could still be 0xff;
2225 * if it is, then bail out, because there's likely no UART
2228 if (!(port->flags & UPF_BUGGY_UART) &&
2229 (serial_port_in(port, UART_LSR) == 0xff)) {
2230 dev_info_ratelimited(port->dev, "LSR safety check engaged!\n");
2236 * For a XR16C850, we need to set the trigger levels
2238 if (port->type == PORT_16850) {
2241 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2243 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2244 serial_port_out(port, UART_FCTR,
2245 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2246 serial_port_out(port, UART_TRG, UART_TRG_96);
2247 serial_port_out(port, UART_FCTR,
2248 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2249 serial_port_out(port, UART_TRG, UART_TRG_96);
2251 serial_port_out(port, UART_LCR, 0);
2255 * For the Altera 16550 variants, set TX threshold trigger level.
2257 if (((port->type == PORT_ALTR_16550_F32) ||
2258 (port->type == PORT_ALTR_16550_F64) ||
2259 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2260 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2261 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2262 dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2264 serial_port_out(port, UART_ALTR_AFR,
2265 UART_ALTR_EN_TXFIFO_LW);
2266 serial_port_out(port, UART_ALTR_TX_LOW,
2267 port->fifosize - up->tx_loadsz);
2268 port->handle_irq = serial8250_tx_threshold_handle_irq;
2272 /* Check if we need to have shared IRQs */
2273 if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2274 up->port.irqflags |= IRQF_SHARED;
2276 if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2279 if (port->irqflags & IRQF_SHARED)
2280 disable_irq_nosync(port->irq);
2283 * Test for UARTs that do not reassert THRE when the
2284 * transmitter is idle and the interrupt has already
2285 * been cleared. Real 16550s should always reassert
2286 * this interrupt whenever the transmitter is idle and
2287 * the interrupt is enabled. Delays are necessary to
2288 * allow register changes to become visible.
2290 spin_lock_irqsave(&port->lock, flags);
2292 wait_for_xmitr(up, UART_LSR_THRE);
2293 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2294 udelay(1); /* allow THRE to set */
2295 iir1 = serial_port_in(port, UART_IIR);
2296 serial_port_out(port, UART_IER, 0);
2297 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2298 udelay(1); /* allow a working UART time to re-assert THRE */
2299 iir = serial_port_in(port, UART_IIR);
2300 serial_port_out(port, UART_IER, 0);
2302 spin_unlock_irqrestore(&port->lock, flags);
2304 if (port->irqflags & IRQF_SHARED)
2305 enable_irq(port->irq);
2308 * If the interrupt is not reasserted, or we otherwise
2309 * don't trust the iir, setup a timer to kick the UART
2310 * on a regular basis.
2312 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2313 up->port.flags & UPF_BUG_THRE) {
2314 up->bugs |= UART_BUG_THRE;
2318 retval = up->ops->setup_irq(up);
2323 * Now, initialize the UART
2325 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2327 spin_lock_irqsave(&port->lock, flags);
2328 if (up->port.flags & UPF_FOURPORT) {
2330 up->port.mctrl |= TIOCM_OUT1;
2333 * Most PC uarts need OUT2 raised to enable interrupts.
2336 up->port.mctrl |= TIOCM_OUT2;
2338 serial8250_set_mctrl(port, port->mctrl);
2341 * Serial over Lan (SoL) hack:
2342 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2343 * used for Serial Over Lan. Those chips take a longer time than a
2344 * normal serial device to signalize that a transmission data was
2345 * queued. Due to that, the above test generally fails. One solution
2346 * would be to delay the reading of iir. However, this is not
2347 * reliable, since the timeout is variable. So, let's just don't
2348 * test if we receive TX irq. This way, we'll never enable
2351 if (up->port.quirks & UPQ_NO_TXEN_TEST)
2352 goto dont_test_tx_en;
2355 * Do a quick test to see if we receive an interrupt when we enable
2358 serial_port_out(port, UART_IER, UART_IER_THRI);
2359 lsr = serial_port_in(port, UART_LSR);
2360 iir = serial_port_in(port, UART_IIR);
2361 serial_port_out(port, UART_IER, 0);
2363 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2364 if (!(up->bugs & UART_BUG_TXEN)) {
2365 up->bugs |= UART_BUG_TXEN;
2366 dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2369 up->bugs &= ~UART_BUG_TXEN;
2373 spin_unlock_irqrestore(&port->lock, flags);
2376 * Clear the interrupt registers again for luck, and clear the
2377 * saved flags to avoid getting false values from polling
2378 * routines or the previous session.
2380 serial_port_in(port, UART_LSR);
2381 serial_port_in(port, UART_RX);
2382 serial_port_in(port, UART_IIR);
2383 serial_port_in(port, UART_MSR);
2384 up->lsr_saved_flags = 0;
2385 up->msr_saved_flags = 0;
2388 * Request DMA channels for both RX and TX.
2391 const char *msg = NULL;
2393 if (uart_console(port))
2394 msg = "forbid DMA for kernel console";
2395 else if (serial8250_request_dma(up))
2396 msg = "failed to request DMA";
2398 dev_warn_ratelimited(port->dev, "%s\n", msg);
2404 * Set the IER shadow for rx interrupts but defer actual interrupt
2405 * enable until after the FIFOs are enabled; otherwise, an already-
2406 * active sender can swamp the interrupt handler with "too much work".
2408 up->ier = UART_IER_RLSI | UART_IER_RDI;
2410 if (port->flags & UPF_FOURPORT) {
2413 * Enable interrupts on the AST Fourport board
2415 icp = (port->iobase & 0xfe0) | 0x01f;
2421 serial8250_rpm_put(up);
2424 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2426 static int serial8250_startup(struct uart_port *port)
2429 return port->startup(port);
2430 return serial8250_do_startup(port);
2433 void serial8250_do_shutdown(struct uart_port *port)
2435 struct uart_8250_port *up = up_to_u8250p(port);
2436 unsigned long flags;
2438 serial8250_rpm_get(up);
2440 * Disable interrupts from this port
2442 spin_lock_irqsave(&port->lock, flags);
2444 serial_port_out(port, UART_IER, 0);
2445 spin_unlock_irqrestore(&port->lock, flags);
2447 synchronize_irq(port->irq);
2450 serial8250_release_dma(up);
2452 spin_lock_irqsave(&port->lock, flags);
2453 if (port->flags & UPF_FOURPORT) {
2454 /* reset interrupts on the AST Fourport board */
2455 inb((port->iobase & 0xfe0) | 0x1f);
2456 port->mctrl |= TIOCM_OUT1;
2458 port->mctrl &= ~TIOCM_OUT2;
2460 serial8250_set_mctrl(port, port->mctrl);
2461 spin_unlock_irqrestore(&port->lock, flags);
2464 * Disable break condition and FIFOs
2466 serial_port_out(port, UART_LCR,
2467 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2468 serial8250_clear_fifos(up);
2470 #ifdef CONFIG_SERIAL_8250_RSA
2472 * Reset the RSA board back to 115kbps compat mode.
2478 * Read data port to reset things, and then unlink from
2481 serial_port_in(port, UART_RX);
2482 serial8250_rpm_put(up);
2484 up->ops->release_irq(up);
2486 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2488 static void serial8250_shutdown(struct uart_port *port)
2491 port->shutdown(port);
2493 serial8250_do_shutdown(port);
2496 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2497 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2500 struct uart_port *port = &up->port;
2502 return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2505 static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2509 struct uart_8250_port *up = up_to_u8250p(port);
2513 * Handle magic divisors for baud rates above baud_base on
2514 * SMSC SuperIO chips.
2517 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2518 baud == (port->uartclk/4))
2520 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2521 baud == (port->uartclk/8))
2523 else if (up->port.type == PORT_NPCM)
2524 quot = npcm_get_divisor(up, baud);
2526 quot = uart_get_divisor(port, baud);
2529 * Oxford Semi 952 rev B workaround
2531 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2537 static unsigned int serial8250_get_divisor(struct uart_port *port,
2541 if (port->get_divisor)
2542 return port->get_divisor(port, baud, frac);
2544 return serial8250_do_get_divisor(port, baud, frac);
2547 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2552 switch (c_cflag & CSIZE) {
2554 cval = UART_LCR_WLEN5;
2557 cval = UART_LCR_WLEN6;
2560 cval = UART_LCR_WLEN7;
2564 cval = UART_LCR_WLEN8;
2568 if (c_cflag & CSTOPB)
2569 cval |= UART_LCR_STOP;
2570 if (c_cflag & PARENB) {
2571 cval |= UART_LCR_PARITY;
2572 if (up->bugs & UART_BUG_PARITY)
2573 up->fifo_bug = true;
2575 if (!(c_cflag & PARODD))
2576 cval |= UART_LCR_EPAR;
2578 if (c_cflag & CMSPAR)
2579 cval |= UART_LCR_SPAR;
2585 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2586 unsigned int quot, unsigned int quot_frac)
2588 struct uart_8250_port *up = up_to_u8250p(port);
2590 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2591 if (is_omap1510_8250(up)) {
2592 if (baud == 115200) {
2594 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2596 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2600 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2601 * otherwise just set DLAB
2603 if (up->capabilities & UART_NATSEMI)
2604 serial_port_out(port, UART_LCR, 0xe0);
2606 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2608 serial_dl_write(up, quot);
2610 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2612 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2613 unsigned int quot, unsigned int quot_frac)
2615 if (port->set_divisor)
2616 port->set_divisor(port, baud, quot, quot_frac);
2618 serial8250_do_set_divisor(port, baud, quot, quot_frac);
2621 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2622 struct ktermios *termios,
2623 struct ktermios *old)
2625 unsigned int tolerance = port->uartclk / 100;
2628 * Ask the core to calculate the divisor for us.
2629 * Allow 1% tolerance at the upper limit so uart clks marginally
2630 * slower than nominal still match standard baud rates without
2631 * causing transmission errors.
2633 return uart_get_baud_rate(port, termios, old,
2634 port->uartclk / 16 / UART_DIV_MAX,
2635 (port->uartclk + tolerance) / 16);
2639 * Note in order to avoid the tty port mutex deadlock don't use the next method
2640 * within the uart port callbacks. Primarily it's supposed to be utilized to
2641 * handle a sudden reference clock rate change.
2643 void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk)
2645 struct uart_8250_port *up = up_to_u8250p(port);
2646 unsigned int baud, quot, frac = 0;
2647 struct ktermios *termios;
2648 unsigned long flags;
2650 mutex_lock(&port->state->port.mutex);
2652 if (port->uartclk == uartclk)
2655 port->uartclk = uartclk;
2656 termios = &port->state->port.tty->termios;
2658 baud = serial8250_get_baud_rate(port, termios, NULL);
2659 quot = serial8250_get_divisor(port, baud, &frac);
2661 serial8250_rpm_get(up);
2662 spin_lock_irqsave(&port->lock, flags);
2664 uart_update_timeout(port, termios->c_cflag, baud);
2666 serial8250_set_divisor(port, baud, quot, frac);
2667 serial_port_out(port, UART_LCR, up->lcr);
2668 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
2670 spin_unlock_irqrestore(&port->lock, flags);
2671 serial8250_rpm_put(up);
2674 mutex_unlock(&port->state->port.mutex);
2676 EXPORT_SYMBOL_GPL(serial8250_update_uartclk);
2679 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2680 struct ktermios *old)
2682 struct uart_8250_port *up = up_to_u8250p(port);
2684 unsigned long flags;
2685 unsigned int baud, quot, frac = 0;
2687 if (up->capabilities & UART_CAP_MINI) {
2688 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2689 if ((termios->c_cflag & CSIZE) == CS5 ||
2690 (termios->c_cflag & CSIZE) == CS6)
2691 termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2693 cval = serial8250_compute_lcr(up, termios->c_cflag);
2695 baud = serial8250_get_baud_rate(port, termios, old);
2696 quot = serial8250_get_divisor(port, baud, &frac);
2699 * Ok, we're now changing the port state. Do it with
2700 * interrupts disabled.
2702 serial8250_rpm_get(up);
2703 spin_lock_irqsave(&port->lock, flags);
2705 up->lcr = cval; /* Save computed LCR */
2707 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2708 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2709 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2710 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2711 up->fcr |= UART_FCR_TRIGGER_1;
2716 * MCR-based auto flow control. When AFE is enabled, RTS will be
2717 * deasserted when the receive FIFO contains more characters than
2718 * the trigger, or the MCR RTS bit is cleared.
2720 if (up->capabilities & UART_CAP_AFE) {
2721 up->mcr &= ~UART_MCR_AFE;
2722 if (termios->c_cflag & CRTSCTS)
2723 up->mcr |= UART_MCR_AFE;
2727 * Update the per-port timeout.
2729 uart_update_timeout(port, termios->c_cflag, baud);
2731 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2732 if (termios->c_iflag & INPCK)
2733 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2734 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2735 port->read_status_mask |= UART_LSR_BI;
2738 * Characteres to ignore
2740 port->ignore_status_mask = 0;
2741 if (termios->c_iflag & IGNPAR)
2742 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2743 if (termios->c_iflag & IGNBRK) {
2744 port->ignore_status_mask |= UART_LSR_BI;
2746 * If we're ignoring parity and break indicators,
2747 * ignore overruns too (for real raw support).
2749 if (termios->c_iflag & IGNPAR)
2750 port->ignore_status_mask |= UART_LSR_OE;
2754 * ignore all characters if CREAD is not set
2756 if ((termios->c_cflag & CREAD) == 0)
2757 port->ignore_status_mask |= UART_LSR_DR;
2760 * CTS flow control flag and modem status interrupts
2762 up->ier &= ~UART_IER_MSI;
2763 if (!(up->bugs & UART_BUG_NOMSR) &&
2764 UART_ENABLE_MS(&up->port, termios->c_cflag))
2765 up->ier |= UART_IER_MSI;
2766 if (up->capabilities & UART_CAP_UUE)
2767 up->ier |= UART_IER_UUE;
2768 if (up->capabilities & UART_CAP_RTOIE)
2769 up->ier |= UART_IER_RTOIE;
2771 serial_port_out(port, UART_IER, up->ier);
2773 if (up->capabilities & UART_CAP_EFR) {
2774 unsigned char efr = 0;
2776 * TI16C752/Startech hardware flow control. FIXME:
2777 * - TI16C752 requires control thresholds to be set.
2778 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2780 if (termios->c_cflag & CRTSCTS)
2781 efr |= UART_EFR_CTS;
2783 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2784 if (port->flags & UPF_EXAR_EFR)
2785 serial_port_out(port, UART_XR_EFR, efr);
2787 serial_port_out(port, UART_EFR, efr);
2790 serial8250_set_divisor(port, baud, quot, frac);
2793 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2794 * is written without DLAB set, this mode will be disabled.
2796 if (port->type == PORT_16750)
2797 serial_port_out(port, UART_FCR, up->fcr);
2799 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2800 if (port->type != PORT_16750) {
2801 /* emulated UARTs (Lucent Venus 167x) need two steps */
2802 if (up->fcr & UART_FCR_ENABLE_FIFO)
2803 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2804 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2806 serial8250_set_mctrl(port, port->mctrl);
2807 spin_unlock_irqrestore(&port->lock, flags);
2808 serial8250_rpm_put(up);
2810 /* Don't rewrite B0 */
2811 if (tty_termios_baud_rate(termios))
2812 tty_termios_encode_baud_rate(termios, baud, baud);
2814 EXPORT_SYMBOL(serial8250_do_set_termios);
2817 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2818 struct ktermios *old)
2820 if (port->set_termios)
2821 port->set_termios(port, termios, old);
2823 serial8250_do_set_termios(port, termios, old);
2826 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2828 if (termios->c_line == N_PPS) {
2829 port->flags |= UPF_HARDPPS_CD;
2830 spin_lock_irq(&port->lock);
2831 serial8250_enable_ms(port);
2832 spin_unlock_irq(&port->lock);
2834 port->flags &= ~UPF_HARDPPS_CD;
2835 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2836 spin_lock_irq(&port->lock);
2837 serial8250_disable_ms(port);
2838 spin_unlock_irq(&port->lock);
2842 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2845 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2847 if (port->set_ldisc)
2848 port->set_ldisc(port, termios);
2850 serial8250_do_set_ldisc(port, termios);
2853 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2854 unsigned int oldstate)
2856 struct uart_8250_port *p = up_to_u8250p(port);
2858 serial8250_set_sleep(p, state != 0);
2860 EXPORT_SYMBOL(serial8250_do_pm);
2863 serial8250_pm(struct uart_port *port, unsigned int state,
2864 unsigned int oldstate)
2867 port->pm(port, state, oldstate);
2869 serial8250_do_pm(port, state, oldstate);
2872 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2874 if (pt->port.mapsize)
2875 return pt->port.mapsize;
2876 if (pt->port.iotype == UPIO_AU) {
2877 if (pt->port.type == PORT_RT2880)
2881 if (is_omap1_8250(pt))
2882 return 0x16 << pt->port.regshift;
2884 return 8 << pt->port.regshift;
2888 * Resource handling.
2890 static int serial8250_request_std_resource(struct uart_8250_port *up)
2892 unsigned int size = serial8250_port_size(up);
2893 struct uart_port *port = &up->port;
2896 switch (port->iotype) {
2906 if (!request_mem_region(port->mapbase, size, "serial")) {
2911 if (port->flags & UPF_IOREMAP) {
2912 port->membase = ioremap(port->mapbase, size);
2913 if (!port->membase) {
2914 release_mem_region(port->mapbase, size);
2922 if (!request_region(port->iobase, size, "serial"))
2929 static void serial8250_release_std_resource(struct uart_8250_port *up)
2931 unsigned int size = serial8250_port_size(up);
2932 struct uart_port *port = &up->port;
2934 switch (port->iotype) {
2944 if (port->flags & UPF_IOREMAP) {
2945 iounmap(port->membase);
2946 port->membase = NULL;
2949 release_mem_region(port->mapbase, size);
2954 release_region(port->iobase, size);
2959 static void serial8250_release_port(struct uart_port *port)
2961 struct uart_8250_port *up = up_to_u8250p(port);
2963 serial8250_release_std_resource(up);
2966 static int serial8250_request_port(struct uart_port *port)
2968 struct uart_8250_port *up = up_to_u8250p(port);
2970 return serial8250_request_std_resource(up);
2973 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2975 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2976 unsigned char bytes;
2978 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2980 return bytes ? bytes : -EOPNOTSUPP;
2983 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2985 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2988 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2991 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2992 if (bytes < conf_type->rxtrig_bytes[i])
2993 /* Use the nearest lower value */
2994 return (--i) << UART_FCR_R_TRIG_SHIFT;
2997 return UART_FCR_R_TRIG_11;
3000 static int do_get_rxtrig(struct tty_port *port)
3002 struct uart_state *state = container_of(port, struct uart_state, port);
3003 struct uart_port *uport = state->uart_port;
3004 struct uart_8250_port *up = up_to_u8250p(uport);
3006 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3009 return fcr_get_rxtrig_bytes(up);
3012 static int do_serial8250_get_rxtrig(struct tty_port *port)
3016 mutex_lock(&port->mutex);
3017 rxtrig_bytes = do_get_rxtrig(port);
3018 mutex_unlock(&port->mutex);
3020 return rxtrig_bytes;
3023 static ssize_t rx_trig_bytes_show(struct device *dev,
3024 struct device_attribute *attr, char *buf)
3026 struct tty_port *port = dev_get_drvdata(dev);
3029 rxtrig_bytes = do_serial8250_get_rxtrig(port);
3030 if (rxtrig_bytes < 0)
3031 return rxtrig_bytes;
3033 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
3036 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
3038 struct uart_state *state = container_of(port, struct uart_state, port);
3039 struct uart_port *uport = state->uart_port;
3040 struct uart_8250_port *up = up_to_u8250p(uport);
3043 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
3047 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3051 serial8250_clear_fifos(up);
3052 up->fcr &= ~UART_FCR_TRIGGER_MASK;
3053 up->fcr |= (unsigned char)rxtrig;
3054 serial_out(up, UART_FCR, up->fcr);
3058 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3062 mutex_lock(&port->mutex);
3063 ret = do_set_rxtrig(port, bytes);
3064 mutex_unlock(&port->mutex);
3069 static ssize_t rx_trig_bytes_store(struct device *dev,
3070 struct device_attribute *attr, const char *buf, size_t count)
3072 struct tty_port *port = dev_get_drvdata(dev);
3073 unsigned char bytes;
3079 ret = kstrtou8(buf, 10, &bytes);
3083 ret = do_serial8250_set_rxtrig(port, bytes);
3090 static DEVICE_ATTR_RW(rx_trig_bytes);
3092 static struct attribute *serial8250_dev_attrs[] = {
3093 &dev_attr_rx_trig_bytes.attr,
3097 static struct attribute_group serial8250_dev_attr_group = {
3098 .attrs = serial8250_dev_attrs,
3101 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3103 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3105 if (conf_type->rxtrig_bytes[0])
3106 up->port.attr_group = &serial8250_dev_attr_group;
3109 static void serial8250_config_port(struct uart_port *port, int flags)
3111 struct uart_8250_port *up = up_to_u8250p(port);
3115 * Find the region that we can probe for. This in turn
3116 * tells us whether we can probe for the type of port.
3118 ret = serial8250_request_std_resource(up);
3122 if (port->iotype != up->cur_iotype)
3123 set_io_from_upio(port);
3125 if (flags & UART_CONFIG_TYPE)
3128 if (port->rs485.flags & SER_RS485_ENABLED)
3129 port->rs485_config(port, &port->rs485);
3131 /* if access method is AU, it is a 16550 with a quirk */
3132 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3133 up->bugs |= UART_BUG_NOMSR;
3135 /* HW bugs may trigger IRQ while IIR == NO_INT */
3136 if (port->type == PORT_TEGRA)
3137 up->bugs |= UART_BUG_NOMSR;
3139 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3142 if (port->type == PORT_UNKNOWN)
3143 serial8250_release_std_resource(up);
3145 register_dev_spec_attr_grp(up);
3146 up->fcr = uart_config[up->port.type].fcr;
3150 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3152 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3153 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3154 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3155 ser->type == PORT_STARTECH)
3160 static const char *serial8250_type(struct uart_port *port)
3162 int type = port->type;
3164 if (type >= ARRAY_SIZE(uart_config))
3166 return uart_config[type].name;
3169 static const struct uart_ops serial8250_pops = {
3170 .tx_empty = serial8250_tx_empty,
3171 .set_mctrl = serial8250_set_mctrl,
3172 .get_mctrl = serial8250_get_mctrl,
3173 .stop_tx = serial8250_stop_tx,
3174 .start_tx = serial8250_start_tx,
3175 .throttle = serial8250_throttle,
3176 .unthrottle = serial8250_unthrottle,
3177 .stop_rx = serial8250_stop_rx,
3178 .enable_ms = serial8250_enable_ms,
3179 .break_ctl = serial8250_break_ctl,
3180 .startup = serial8250_startup,
3181 .shutdown = serial8250_shutdown,
3182 .set_termios = serial8250_set_termios,
3183 .set_ldisc = serial8250_set_ldisc,
3184 .pm = serial8250_pm,
3185 .type = serial8250_type,
3186 .release_port = serial8250_release_port,
3187 .request_port = serial8250_request_port,
3188 .config_port = serial8250_config_port,
3189 .verify_port = serial8250_verify_port,
3190 #ifdef CONFIG_CONSOLE_POLL
3191 .poll_get_char = serial8250_get_poll_char,
3192 .poll_put_char = serial8250_put_poll_char,
3196 void serial8250_init_port(struct uart_8250_port *up)
3198 struct uart_port *port = &up->port;
3200 spin_lock_init(&port->lock);
3201 port->ops = &serial8250_pops;
3202 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3204 up->cur_iotype = 0xFF;
3206 EXPORT_SYMBOL_GPL(serial8250_init_port);
3208 void serial8250_set_defaults(struct uart_8250_port *up)
3210 struct uart_port *port = &up->port;
3212 if (up->port.flags & UPF_FIXED_TYPE) {
3213 unsigned int type = up->port.type;
3215 if (!up->port.fifosize)
3216 up->port.fifosize = uart_config[type].fifo_size;
3218 up->tx_loadsz = uart_config[type].tx_loadsz;
3219 if (!up->capabilities)
3220 up->capabilities = uart_config[type].flags;
3223 set_io_from_upio(port);
3225 /* default dma handlers */
3227 if (!up->dma->tx_dma)
3228 up->dma->tx_dma = serial8250_tx_dma;
3229 if (!up->dma->rx_dma)
3230 up->dma->rx_dma = serial8250_rx_dma;
3233 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3235 #ifdef CONFIG_SERIAL_8250_CONSOLE
3237 static void serial8250_console_putchar(struct uart_port *port, int ch)
3239 struct uart_8250_port *up = up_to_u8250p(port);
3241 wait_for_xmitr(up, UART_LSR_THRE);
3242 serial_port_out(port, UART_TX, ch);
3246 * Restore serial console when h/w power-off detected
3248 static void serial8250_console_restore(struct uart_8250_port *up)
3250 struct uart_port *port = &up->port;
3251 struct ktermios termios;
3252 unsigned int baud, quot, frac = 0;
3254 termios.c_cflag = port->cons->cflag;
3255 if (port->state->port.tty && termios.c_cflag == 0)
3256 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3258 baud = serial8250_get_baud_rate(port, &termios, NULL);
3259 quot = serial8250_get_divisor(port, baud, &frac);
3261 serial8250_set_divisor(port, baud, quot, frac);
3262 serial_port_out(port, UART_LCR, up->lcr);
3263 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
3267 * Print a string to the serial port trying not to disturb
3268 * any possible real use of the port...
3270 * The console_lock must be held when we get here.
3272 * Doing runtime PM is really a bad idea for the kernel console.
3273 * Thus, we assume the function is called when device is powered up.
3275 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3278 struct uart_8250_em485 *em485 = up->em485;
3279 struct uart_port *port = &up->port;
3280 unsigned long flags;
3284 touch_nmi_watchdog();
3286 if (oops_in_progress)
3287 locked = spin_trylock_irqsave(&port->lock, flags);
3289 spin_lock_irqsave(&port->lock, flags);
3292 * First save the IER then disable the interrupts
3294 ier = serial_port_in(port, UART_IER);
3296 if (up->capabilities & UART_CAP_UUE)
3297 serial_port_out(port, UART_IER, UART_IER_UUE);
3299 serial_port_out(port, UART_IER, 0);
3301 /* check scratch reg to see if port powered off during system sleep */
3302 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3303 serial8250_console_restore(up);
3308 if (em485->tx_stopped)
3309 up->rs485_start_tx(up);
3310 mdelay(port->rs485.delay_rts_before_send);
3313 uart_console_write(port, s, count, serial8250_console_putchar);
3316 * Finally, wait for transmitter to become empty
3317 * and restore the IER
3319 wait_for_xmitr(up, BOTH_EMPTY);
3322 mdelay(port->rs485.delay_rts_after_send);
3323 if (em485->tx_stopped)
3324 up->rs485_stop_tx(up);
3327 serial_port_out(port, UART_IER, ier);
3330 * The receive handling will happen properly because the
3331 * receive ready bit will still be set; it is not cleared
3332 * on read. However, modem control will not, we must
3333 * call it if we have saved something in the saved flags
3334 * while processing with interrupts off.
3336 if (up->msr_saved_flags)
3337 serial8250_modem_status(up);
3340 spin_unlock_irqrestore(&port->lock, flags);
3343 static unsigned int probe_baud(struct uart_port *port)
3345 unsigned char lcr, dll, dlm;
3348 lcr = serial_port_in(port, UART_LCR);
3349 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3350 dll = serial_port_in(port, UART_DLL);
3351 dlm = serial_port_in(port, UART_DLM);
3352 serial_port_out(port, UART_LCR, lcr);
3354 quot = (dlm << 8) | dll;
3355 return (port->uartclk / 16) / quot;
3358 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3366 if (!port->iobase && !port->membase)
3370 uart_parse_options(options, &baud, &parity, &bits, &flow);
3372 baud = probe_baud(port);
3374 ret = uart_set_options(port, port->cons, baud, parity, bits, flow);
3379 pm_runtime_get_sync(port->dev);
3384 int serial8250_console_exit(struct uart_port *port)
3387 pm_runtime_put_sync(port->dev);
3392 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3394 MODULE_LICENSE("GPL");