1 // SPDX-License-Identifier: GPL-2.0+
3 * Base port operations for 8250/16550-type serial ports
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
8 * A note about mapbase / membase
10 * mapbase is the physical address of the IO port.
11 * membase is an 'ioremapped' cookie.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/ioport.h>
17 #include <linux/init.h>
18 #include <linux/console.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/sysrq.h>
21 #include <linux/delay.h>
22 #include <linux/platform_device.h>
23 #include <linux/tty.h>
24 #include <linux/ratelimit.h>
25 #include <linux/tty_flip.h>
26 #include <linux/serial.h>
27 #include <linux/serial_8250.h>
28 #include <linux/nmi.h>
29 #include <linux/mutex.h>
30 #include <linux/slab.h>
31 #include <linux/uaccess.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/ktime.h>
40 /* Nuvoton NPCM timeout register */
41 #define UART_NPCM_TOR 7
42 #define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */
48 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
50 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
53 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
56 * Here we define the default xmit fifo size used for each type of UART.
58 static const struct serial8250_config uart_config[] = {
83 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
84 .rxtrig_bytes = {1, 4, 8, 14},
85 .flags = UART_CAP_FIFO,
96 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
102 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
104 .rxtrig_bytes = {8, 16, 24, 28},
105 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
111 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
113 .rxtrig_bytes = {1, 16, 32, 56},
114 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
122 .name = "16C950/954",
125 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
126 .rxtrig_bytes = {16, 32, 112, 120},
127 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
128 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
134 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
136 .rxtrig_bytes = {8, 16, 56, 60},
137 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
143 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
144 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
150 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
151 .flags = UART_CAP_FIFO,
157 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
158 .flags = UART_CAP_FIFO | UART_NATSEMI,
164 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
165 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
171 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
172 .flags = UART_CAP_FIFO,
178 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
179 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
185 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
186 .flags = UART_CAP_FIFO | UART_CAP_AFE,
192 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
194 .rxtrig_bytes = {1, 4, 8, 14},
195 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
201 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
202 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
209 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
211 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
218 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
219 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
220 .flags = UART_CAP_FIFO,
222 [PORT_BRCM_TRUMANAGE] = {
226 .flags = UART_CAP_HFIFO,
231 [PORT_ALTR_16550_F32] = {
232 .name = "Altera 16550 FIFO32",
235 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
236 .rxtrig_bytes = {1, 8, 16, 30},
237 .flags = UART_CAP_FIFO | UART_CAP_AFE,
239 [PORT_ALTR_16550_F64] = {
240 .name = "Altera 16550 FIFO64",
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
244 .rxtrig_bytes = {1, 16, 32, 62},
245 .flags = UART_CAP_FIFO | UART_CAP_AFE,
247 [PORT_ALTR_16550_F128] = {
248 .name = "Altera 16550 FIFO128",
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .rxtrig_bytes = {1, 32, 64, 126},
253 .flags = UART_CAP_FIFO | UART_CAP_AFE,
256 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
257 * workaround of errata A-008006 which states that tx_loadsz should
258 * be configured less than Maximum supported fifo bytes.
260 [PORT_16550A_FSL64] = {
261 .name = "16550A_FSL64",
264 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
266 .flags = UART_CAP_FIFO | UART_CAP_NOTEMT,
269 .name = "Palmchip BK-3103",
272 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
273 .rxtrig_bytes = {1, 4, 8, 14},
274 .flags = UART_CAP_FIFO,
277 .name = "TI DA8xx/66AK2x",
280 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
282 .rxtrig_bytes = {1, 4, 8, 14},
283 .flags = UART_CAP_FIFO | UART_CAP_AFE,
286 .name = "MediaTek BTIF",
289 .fcr = UART_FCR_ENABLE_FIFO |
290 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
291 .flags = UART_CAP_FIFO,
294 .name = "Nuvoton 16550",
297 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
298 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
299 .rxtrig_bytes = {1, 4, 8, 14},
300 .flags = UART_CAP_FIFO,
306 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
307 .rxtrig_bytes = {1, 32, 64, 112},
308 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
310 [PORT_ASPEED_VUART] = {
311 .name = "ASPEED VUART",
314 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
315 .rxtrig_bytes = {1, 4, 8, 14},
316 .flags = UART_CAP_FIFO,
320 /* Uart divisor latch read */
321 static int default_serial_dl_read(struct uart_8250_port *up)
323 /* Assign these in pieces to truncate any bits above 7. */
324 unsigned char dll = serial_in(up, UART_DLL);
325 unsigned char dlm = serial_in(up, UART_DLM);
327 return dll | dlm << 8;
330 /* Uart divisor latch write */
331 static void default_serial_dl_write(struct uart_8250_port *up, int value)
333 serial_out(up, UART_DLL, value & 0xff);
334 serial_out(up, UART_DLM, value >> 8 & 0xff);
337 #ifdef CONFIG_SERIAL_8250_RT288X
339 /* Au1x00/RT288x UART hardware has a weird register layout */
340 static const s8 au_io_in_map[8] = {
348 -1, /* UART_SCR (unmapped) */
351 static const s8 au_io_out_map[8] = {
357 -1, /* UART_LSR (unmapped) */
358 -1, /* UART_MSR (unmapped) */
359 -1, /* UART_SCR (unmapped) */
362 unsigned int au_serial_in(struct uart_port *p, int offset)
364 if (offset >= ARRAY_SIZE(au_io_in_map))
366 offset = au_io_in_map[offset];
369 return __raw_readl(p->membase + (offset << p->regshift));
372 void au_serial_out(struct uart_port *p, int offset, int value)
374 if (offset >= ARRAY_SIZE(au_io_out_map))
376 offset = au_io_out_map[offset];
379 __raw_writel(value, p->membase + (offset << p->regshift));
382 /* Au1x00 haven't got a standard divisor latch */
383 static int au_serial_dl_read(struct uart_8250_port *up)
385 return __raw_readl(up->port.membase + 0x28);
388 static void au_serial_dl_write(struct uart_8250_port *up, int value)
390 __raw_writel(value, up->port.membase + 0x28);
395 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
397 offset = offset << p->regshift;
398 outb(p->hub6 - 1 + offset, p->iobase);
399 return inb(p->iobase + 1);
402 static void hub6_serial_out(struct uart_port *p, int offset, int value)
404 offset = offset << p->regshift;
405 outb(p->hub6 - 1 + offset, p->iobase);
406 outb(value, p->iobase + 1);
409 static unsigned int mem_serial_in(struct uart_port *p, int offset)
411 offset = offset << p->regshift;
412 return readb(p->membase + offset);
415 static void mem_serial_out(struct uart_port *p, int offset, int value)
417 offset = offset << p->regshift;
418 writeb(value, p->membase + offset);
421 static void mem16_serial_out(struct uart_port *p, int offset, int value)
423 offset = offset << p->regshift;
424 writew(value, p->membase + offset);
427 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
429 offset = offset << p->regshift;
430 return readw(p->membase + offset);
433 static void mem32_serial_out(struct uart_port *p, int offset, int value)
435 offset = offset << p->regshift;
436 writel(value, p->membase + offset);
439 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
441 offset = offset << p->regshift;
442 return readl(p->membase + offset);
445 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
447 offset = offset << p->regshift;
448 iowrite32be(value, p->membase + offset);
451 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
453 offset = offset << p->regshift;
454 return ioread32be(p->membase + offset);
457 static unsigned int io_serial_in(struct uart_port *p, int offset)
459 offset = offset << p->regshift;
460 return inb(p->iobase + offset);
463 static void io_serial_out(struct uart_port *p, int offset, int value)
465 offset = offset << p->regshift;
466 outb(value, p->iobase + offset);
469 static int serial8250_default_handle_irq(struct uart_port *port);
471 static void set_io_from_upio(struct uart_port *p)
473 struct uart_8250_port *up = up_to_u8250p(p);
475 up->dl_read = default_serial_dl_read;
476 up->dl_write = default_serial_dl_write;
480 p->serial_in = hub6_serial_in;
481 p->serial_out = hub6_serial_out;
485 p->serial_in = mem_serial_in;
486 p->serial_out = mem_serial_out;
490 p->serial_in = mem16_serial_in;
491 p->serial_out = mem16_serial_out;
495 p->serial_in = mem32_serial_in;
496 p->serial_out = mem32_serial_out;
500 p->serial_in = mem32be_serial_in;
501 p->serial_out = mem32be_serial_out;
504 #ifdef CONFIG_SERIAL_8250_RT288X
506 p->serial_in = au_serial_in;
507 p->serial_out = au_serial_out;
508 up->dl_read = au_serial_dl_read;
509 up->dl_write = au_serial_dl_write;
514 p->serial_in = io_serial_in;
515 p->serial_out = io_serial_out;
518 /* Remember loaded iotype */
519 up->cur_iotype = p->iotype;
520 p->handle_irq = serial8250_default_handle_irq;
524 serial_port_out_sync(struct uart_port *p, int offset, int value)
532 p->serial_out(p, offset, value);
533 p->serial_in(p, UART_LCR); /* safe, no side-effects */
536 p->serial_out(p, offset, value);
543 static void serial8250_clear_fifos(struct uart_8250_port *p)
545 if (p->capabilities & UART_CAP_FIFO) {
546 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
547 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
548 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
549 serial_out(p, UART_FCR, 0);
553 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
554 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
556 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
558 serial8250_clear_fifos(p);
559 serial_out(p, UART_FCR, p->fcr);
561 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
563 void serial8250_rpm_get(struct uart_8250_port *p)
565 if (!(p->capabilities & UART_CAP_RPM))
567 pm_runtime_get_sync(p->port.dev);
569 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
571 void serial8250_rpm_put(struct uart_8250_port *p)
573 if (!(p->capabilities & UART_CAP_RPM))
575 pm_runtime_mark_last_busy(p->port.dev);
576 pm_runtime_put_autosuspend(p->port.dev);
578 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
581 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
582 * @p: uart_8250_port port instance
584 * The function is used to start rs485 software emulating on the
585 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
586 * transmission. The function is idempotent, so it is safe to call it
589 * The caller MUST enable interrupt on empty shift register before
590 * calling serial8250_em485_init(). This interrupt is not a part of
591 * 8250 standard, but implementation defined.
593 * The function is supposed to be called from .rs485_config callback
594 * or from any other callback protected with p->port.lock spinlock.
596 * See also serial8250_em485_destroy()
598 * Return 0 - success, -errno - otherwise
600 static int serial8250_em485_init(struct uart_8250_port *p)
605 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
609 hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
611 hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
613 p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
614 p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
616 p->em485->active_timer = NULL;
617 p->em485->tx_stopped = true;
625 * serial8250_em485_destroy() - put uart_8250_port into normal state
626 * @p: uart_8250_port port instance
628 * The function is used to stop rs485 software emulating on the
629 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
630 * call it multiple times.
632 * The function is supposed to be called from .rs485_config callback
633 * or from any other callback protected with p->port.lock spinlock.
635 * See also serial8250_em485_init()
637 void serial8250_em485_destroy(struct uart_8250_port *p)
642 hrtimer_cancel(&p->em485->start_tx_timer);
643 hrtimer_cancel(&p->em485->stop_tx_timer);
648 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
651 * serial8250_em485_config() - generic ->rs485_config() callback
653 * @rs485: rs485 settings
655 * Generic callback usable by 8250 uart drivers to activate rs485 settings
656 * if the uart is incapable of driving RTS as a Transmit Enable signal in
657 * hardware, relying on software emulation instead.
659 int serial8250_em485_config(struct uart_port *port, struct serial_rs485 *rs485)
661 struct uart_8250_port *up = up_to_u8250p(port);
663 /* pick sane settings if the user hasn't */
664 if (!!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
665 !!(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
666 rs485->flags |= SER_RS485_RTS_ON_SEND;
667 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
670 /* clamp the delays to [0, 100ms] */
671 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
672 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
674 memset(rs485->padding, 0, sizeof(rs485->padding));
675 port->rs485 = *rs485;
677 gpiod_set_value(port->rs485_term_gpio,
678 rs485->flags & SER_RS485_TERMINATE_BUS);
681 * Both serial8250_em485_init() and serial8250_em485_destroy()
684 if (rs485->flags & SER_RS485_ENABLED) {
685 int ret = serial8250_em485_init(up);
688 rs485->flags &= ~SER_RS485_ENABLED;
689 port->rs485.flags &= ~SER_RS485_ENABLED;
694 serial8250_em485_destroy(up);
697 EXPORT_SYMBOL_GPL(serial8250_em485_config);
700 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
701 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
702 * empty and the HW can idle again.
704 void serial8250_rpm_get_tx(struct uart_8250_port *p)
706 unsigned char rpm_active;
708 if (!(p->capabilities & UART_CAP_RPM))
711 rpm_active = xchg(&p->rpm_tx_active, 1);
714 pm_runtime_get_sync(p->port.dev);
716 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
718 void serial8250_rpm_put_tx(struct uart_8250_port *p)
720 unsigned char rpm_active;
722 if (!(p->capabilities & UART_CAP_RPM))
725 rpm_active = xchg(&p->rpm_tx_active, 0);
728 pm_runtime_mark_last_busy(p->port.dev);
729 pm_runtime_put_autosuspend(p->port.dev);
731 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
734 * IER sleep support. UARTs which have EFRs need the "extended
735 * capability" bit enabled. Note that on XR16C850s, we need to
736 * reset LCR to write to IER.
738 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
740 unsigned char lcr = 0, efr = 0;
742 serial8250_rpm_get(p);
744 if (p->capabilities & UART_CAP_SLEEP) {
745 if (p->capabilities & UART_CAP_EFR) {
746 lcr = serial_in(p, UART_LCR);
747 efr = serial_in(p, UART_EFR);
748 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
749 serial_out(p, UART_EFR, UART_EFR_ECB);
750 serial_out(p, UART_LCR, 0);
752 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
753 if (p->capabilities & UART_CAP_EFR) {
754 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
755 serial_out(p, UART_EFR, efr);
756 serial_out(p, UART_LCR, lcr);
760 serial8250_rpm_put(p);
763 #ifdef CONFIG_SERIAL_8250_RSA
765 * Attempts to turn on the RSA FIFO. Returns zero on failure.
766 * We set the port uart clock rate if we succeed.
768 static int __enable_rsa(struct uart_8250_port *up)
773 mode = serial_in(up, UART_RSA_MSR);
774 result = mode & UART_RSA_MSR_FIFO;
777 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
778 mode = serial_in(up, UART_RSA_MSR);
779 result = mode & UART_RSA_MSR_FIFO;
783 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
788 static void enable_rsa(struct uart_8250_port *up)
790 if (up->port.type == PORT_RSA) {
791 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
792 spin_lock_irq(&up->port.lock);
794 spin_unlock_irq(&up->port.lock);
796 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
797 serial_out(up, UART_RSA_FRR, 0);
802 * Attempts to turn off the RSA FIFO. Returns zero on failure.
803 * It is unknown why interrupts were disabled in here. However,
804 * the caller is expected to preserve this behaviour by grabbing
805 * the spinlock before calling this function.
807 static void disable_rsa(struct uart_8250_port *up)
812 if (up->port.type == PORT_RSA &&
813 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
814 spin_lock_irq(&up->port.lock);
816 mode = serial_in(up, UART_RSA_MSR);
817 result = !(mode & UART_RSA_MSR_FIFO);
820 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
821 mode = serial_in(up, UART_RSA_MSR);
822 result = !(mode & UART_RSA_MSR_FIFO);
826 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
827 spin_unlock_irq(&up->port.lock);
830 #endif /* CONFIG_SERIAL_8250_RSA */
833 * This is a quickie test to see how big the FIFO is.
834 * It doesn't work at all the time, more's the pity.
836 static int size_fifo(struct uart_8250_port *up)
838 unsigned char old_fcr, old_mcr, old_lcr;
839 unsigned short old_dl;
842 old_lcr = serial_in(up, UART_LCR);
843 serial_out(up, UART_LCR, 0);
844 old_fcr = serial_in(up, UART_FCR);
845 old_mcr = serial8250_in_MCR(up);
846 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
847 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
848 serial8250_out_MCR(up, UART_MCR_LOOP);
849 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
850 old_dl = serial_dl_read(up);
851 serial_dl_write(up, 0x0001);
852 serial_out(up, UART_LCR, 0x03);
853 for (count = 0; count < 256; count++)
854 serial_out(up, UART_TX, count);
855 mdelay(20);/* FIXME - schedule_timeout */
856 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
857 (count < 256); count++)
858 serial_in(up, UART_RX);
859 serial_out(up, UART_FCR, old_fcr);
860 serial8250_out_MCR(up, old_mcr);
861 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
862 serial_dl_write(up, old_dl);
863 serial_out(up, UART_LCR, old_lcr);
869 * Read UART ID using the divisor method - set DLL and DLM to zero
870 * and the revision will be in DLL and device type in DLM. We
871 * preserve the device state across this.
873 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
875 unsigned char old_lcr;
876 unsigned int id, old_dl;
878 old_lcr = serial_in(p, UART_LCR);
879 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
880 old_dl = serial_dl_read(p);
881 serial_dl_write(p, 0);
882 id = serial_dl_read(p);
883 serial_dl_write(p, old_dl);
885 serial_out(p, UART_LCR, old_lcr);
891 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
892 * When this function is called we know it is at least a StarTech
893 * 16650 V2, but it might be one of several StarTech UARTs, or one of
894 * its clones. (We treat the broken original StarTech 16650 V1 as a
895 * 16550, and why not? Startech doesn't seem to even acknowledge its
898 * What evil have men's minds wrought...
900 static void autoconfig_has_efr(struct uart_8250_port *up)
902 unsigned int id1, id2, id3, rev;
905 * Everything with an EFR has SLEEP
907 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
910 * First we check to see if it's an Oxford Semiconductor UART.
912 * If we have to do this here because some non-National
913 * Semiconductor clone chips lock up if you try writing to the
914 * LSR register (which serial_icr_read does)
918 * Check for Oxford Semiconductor 16C950.
920 * EFR [4] must be set else this test fails.
922 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
923 * claims that it's needed for 952 dual UART's (which are not
924 * recommended for new designs).
927 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
928 serial_out(up, UART_EFR, UART_EFR_ECB);
929 serial_out(up, UART_LCR, 0x00);
930 id1 = serial_icr_read(up, UART_ID1);
931 id2 = serial_icr_read(up, UART_ID2);
932 id3 = serial_icr_read(up, UART_ID3);
933 rev = serial_icr_read(up, UART_REV);
935 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
937 if (id1 == 0x16 && id2 == 0xC9 &&
938 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
939 up->port.type = PORT_16C950;
942 * Enable work around for the Oxford Semiconductor 952 rev B
943 * chip which causes it to seriously miscalculate baud rates
946 if (id3 == 0x52 && rev == 0x01)
947 up->bugs |= UART_BUG_QUOT;
952 * We check for a XR16C850 by setting DLL and DLM to 0, and then
953 * reading back DLL and DLM. The chip type depends on the DLM
955 * 0x10 - XR16C850 and the DLL contains the chip revision.
959 id1 = autoconfig_read_divisor_id(up);
960 DEBUG_AUTOCONF("850id=%04x ", id1);
963 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
964 up->port.type = PORT_16850;
969 * It wasn't an XR16C850.
971 * We distinguish between the '654 and the '650 by counting
972 * how many bytes are in the FIFO. I'm using this for now,
973 * since that's the technique that was sent to me in the
974 * serial driver update, but I'm not convinced this works.
975 * I've had problems doing this in the past. -TYT
977 if (size_fifo(up) == 64)
978 up->port.type = PORT_16654;
980 up->port.type = PORT_16650V2;
984 * We detected a chip without a FIFO. Only two fall into
985 * this category - the original 8250 and the 16450. The
986 * 16450 has a scratch register (accessible with LCR=0)
988 static void autoconfig_8250(struct uart_8250_port *up)
990 unsigned char scratch, status1, status2;
992 up->port.type = PORT_8250;
994 scratch = serial_in(up, UART_SCR);
995 serial_out(up, UART_SCR, 0xa5);
996 status1 = serial_in(up, UART_SCR);
997 serial_out(up, UART_SCR, 0x5a);
998 status2 = serial_in(up, UART_SCR);
999 serial_out(up, UART_SCR, scratch);
1001 if (status1 == 0xa5 && status2 == 0x5a)
1002 up->port.type = PORT_16450;
1005 static int broken_efr(struct uart_8250_port *up)
1008 * Exar ST16C2550 "A2" devices incorrectly detect as
1009 * having an EFR, and report an ID of 0x0201. See
1010 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1012 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
1019 * We know that the chip has FIFOs. Does it have an EFR? The
1020 * EFR is located in the same register position as the IIR and
1021 * we know the top two bits of the IIR are currently set. The
1022 * EFR should contain zero. Try to read the EFR.
1024 static void autoconfig_16550a(struct uart_8250_port *up)
1026 unsigned char status1, status2;
1027 unsigned int iersave;
1029 up->port.type = PORT_16550A;
1030 up->capabilities |= UART_CAP_FIFO;
1032 if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS))
1036 * Check for presence of the EFR when DLAB is set.
1037 * Only ST16C650V1 UARTs pass this test.
1039 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1040 if (serial_in(up, UART_EFR) == 0) {
1041 serial_out(up, UART_EFR, 0xA8);
1042 if (serial_in(up, UART_EFR) != 0) {
1043 DEBUG_AUTOCONF("EFRv1 ");
1044 up->port.type = PORT_16650;
1045 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1047 serial_out(up, UART_LCR, 0);
1048 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1050 status1 = serial_in(up, UART_IIR) >> 5;
1051 serial_out(up, UART_FCR, 0);
1052 serial_out(up, UART_LCR, 0);
1055 up->port.type = PORT_16550A_FSL64;
1057 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1059 serial_out(up, UART_EFR, 0);
1064 * Maybe it requires 0xbf to be written to the LCR.
1065 * (other ST16C650V2 UARTs, TI16C752A, etc)
1067 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1068 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1069 DEBUG_AUTOCONF("EFRv2 ");
1070 autoconfig_has_efr(up);
1075 * Check for a National Semiconductor SuperIO chip.
1076 * Attempt to switch to bank 2, read the value of the LOOP bit
1077 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1078 * switch back to bank 2, read it from EXCR1 again and check
1079 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1081 serial_out(up, UART_LCR, 0);
1082 status1 = serial8250_in_MCR(up);
1083 serial_out(up, UART_LCR, 0xE0);
1084 status2 = serial_in(up, 0x02); /* EXCR1 */
1086 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1087 serial_out(up, UART_LCR, 0);
1088 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1089 serial_out(up, UART_LCR, 0xE0);
1090 status2 = serial_in(up, 0x02); /* EXCR1 */
1091 serial_out(up, UART_LCR, 0);
1092 serial8250_out_MCR(up, status1);
1094 if ((status2 ^ status1) & UART_MCR_LOOP) {
1095 unsigned short quot;
1097 serial_out(up, UART_LCR, 0xE0);
1099 quot = serial_dl_read(up);
1102 if (ns16550a_goto_highspeed(up))
1103 serial_dl_write(up, quot);
1105 serial_out(up, UART_LCR, 0);
1107 up->port.uartclk = 921600*16;
1108 up->port.type = PORT_NS16550A;
1109 up->capabilities |= UART_NATSEMI;
1115 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1116 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1117 * Try setting it with and without DLAB set. Cheap clones
1118 * set bit 5 without DLAB set.
1120 serial_out(up, UART_LCR, 0);
1121 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1122 status1 = serial_in(up, UART_IIR) >> 5;
1123 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1124 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1125 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1126 status2 = serial_in(up, UART_IIR) >> 5;
1127 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1128 serial_out(up, UART_LCR, 0);
1130 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1132 if (status1 == 6 && status2 == 7) {
1133 up->port.type = PORT_16750;
1134 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1139 * Try writing and reading the UART_IER_UUE bit (b6).
1140 * If it works, this is probably one of the Xscale platform's
1142 * We're going to explicitly set the UUE bit to 0 before
1143 * trying to write and read a 1 just to make sure it's not
1144 * already a 1 and maybe locked there before we even start start.
1146 iersave = serial_in(up, UART_IER);
1147 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1148 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1150 * OK it's in a known zero state, try writing and reading
1151 * without disturbing the current state of the other bits.
1153 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1154 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1157 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1159 DEBUG_AUTOCONF("Xscale ");
1160 up->port.type = PORT_XSCALE;
1161 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1166 * If we got here we couldn't force the IER_UUE bit to 0.
1167 * Log it and continue.
1169 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1171 serial_out(up, UART_IER, iersave);
1174 * We distinguish between 16550A and U6 16550A by counting
1175 * how many bytes are in the FIFO.
1177 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1178 up->port.type = PORT_U6_16550A;
1179 up->capabilities |= UART_CAP_AFE;
1184 * This routine is called by rs_init() to initialize a specific serial
1185 * port. It determines what type of UART chip this serial port is
1186 * using: 8250, 16450, 16550, 16550A. The important question is
1187 * whether or not this UART is a 16550A or not, since this will
1188 * determine whether or not we can use its FIFO features or not.
1190 static void autoconfig(struct uart_8250_port *up)
1192 unsigned char status1, scratch, scratch2, scratch3;
1193 unsigned char save_lcr, save_mcr;
1194 struct uart_port *port = &up->port;
1195 unsigned long flags;
1196 unsigned int old_capabilities;
1198 if (!port->iobase && !port->mapbase && !port->membase)
1201 DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1202 port->name, port->iobase, port->membase);
1205 * We really do need global IRQs disabled here - we're going to
1206 * be frobbing the chips IRQ enable register to see if it exists.
1208 spin_lock_irqsave(&port->lock, flags);
1210 up->capabilities = 0;
1213 if (!(port->flags & UPF_BUGGY_UART)) {
1215 * Do a simple existence test first; if we fail this,
1216 * there's no point trying anything else.
1218 * 0x80 is used as a nonsense port to prevent against
1219 * false positives due to ISA bus float. The
1220 * assumption is that 0x80 is a non-existent port;
1221 * which should be safe since include/asm/io.h also
1222 * makes this assumption.
1224 * Note: this is safe as long as MCR bit 4 is clear
1225 * and the device is in "PC" mode.
1227 scratch = serial_in(up, UART_IER);
1228 serial_out(up, UART_IER, 0);
1233 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1234 * 16C754B) allow only to modify them if an EFR bit is set.
1236 scratch2 = serial_in(up, UART_IER) & 0x0f;
1237 serial_out(up, UART_IER, 0x0F);
1241 scratch3 = serial_in(up, UART_IER) & 0x0f;
1242 serial_out(up, UART_IER, scratch);
1243 if (scratch2 != 0 || scratch3 != 0x0F) {
1245 * We failed; there's nothing here
1247 spin_unlock_irqrestore(&port->lock, flags);
1248 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1249 scratch2, scratch3);
1254 save_mcr = serial8250_in_MCR(up);
1255 save_lcr = serial_in(up, UART_LCR);
1258 * Check to see if a UART is really there. Certain broken
1259 * internal modems based on the Rockwell chipset fail this
1260 * test, because they apparently don't implement the loopback
1261 * test mode. So this test is skipped on the COM 1 through
1262 * COM 4 ports. This *should* be safe, since no board
1263 * manufacturer would be stupid enough to design a board
1264 * that conflicts with COM 1-4 --- we hope!
1266 if (!(port->flags & UPF_SKIP_TEST)) {
1267 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1268 status1 = serial_in(up, UART_MSR) & 0xF0;
1269 serial8250_out_MCR(up, save_mcr);
1270 if (status1 != 0x90) {
1271 spin_unlock_irqrestore(&port->lock, flags);
1272 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1279 * We're pretty sure there's a port here. Lets find out what
1280 * type of port it is. The IIR top two bits allows us to find
1281 * out if it's 8250 or 16450, 16550, 16550A or later. This
1282 * determines what we test for next.
1284 * We also initialise the EFR (if any) to zero for later. The
1285 * EFR occupies the same register location as the FCR and IIR.
1287 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1288 serial_out(up, UART_EFR, 0);
1289 serial_out(up, UART_LCR, 0);
1291 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1293 /* Assign this as it is to truncate any bits above 7. */
1294 scratch = serial_in(up, UART_IIR);
1296 switch (scratch >> 6) {
1298 autoconfig_8250(up);
1301 port->type = PORT_UNKNOWN;
1304 port->type = PORT_16550;
1307 autoconfig_16550a(up);
1311 #ifdef CONFIG_SERIAL_8250_RSA
1313 * Only probe for RSA ports if we got the region.
1315 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1317 port->type = PORT_RSA;
1320 serial_out(up, UART_LCR, save_lcr);
1322 port->fifosize = uart_config[up->port.type].fifo_size;
1323 old_capabilities = up->capabilities;
1324 up->capabilities = uart_config[port->type].flags;
1325 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1327 if (port->type == PORT_UNKNOWN)
1333 #ifdef CONFIG_SERIAL_8250_RSA
1334 if (port->type == PORT_RSA)
1335 serial_out(up, UART_RSA_FRR, 0);
1337 serial8250_out_MCR(up, save_mcr);
1338 serial8250_clear_fifos(up);
1339 serial_in(up, UART_RX);
1340 if (up->capabilities & UART_CAP_UUE)
1341 serial_out(up, UART_IER, UART_IER_UUE);
1343 serial_out(up, UART_IER, 0);
1346 spin_unlock_irqrestore(&port->lock, flags);
1349 * Check if the device is a Fintek F81216A
1351 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1352 fintek_8250_probe(up);
1354 if (up->capabilities != old_capabilities) {
1355 dev_warn(port->dev, "detected caps %08x should be %08x\n",
1356 old_capabilities, up->capabilities);
1359 DEBUG_AUTOCONF("iir=%d ", scratch);
1360 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1363 static void autoconfig_irq(struct uart_8250_port *up)
1365 struct uart_port *port = &up->port;
1366 unsigned char save_mcr, save_ier;
1367 unsigned char save_ICP = 0;
1368 unsigned int ICP = 0;
1372 if (port->flags & UPF_FOURPORT) {
1373 ICP = (port->iobase & 0xfe0) | 0x1f;
1374 save_ICP = inb_p(ICP);
1379 if (uart_console(port))
1382 /* forget possible initially masked and pending IRQ */
1383 probe_irq_off(probe_irq_on());
1384 save_mcr = serial8250_in_MCR(up);
1385 save_ier = serial_in(up, UART_IER);
1386 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1388 irqs = probe_irq_on();
1389 serial8250_out_MCR(up, 0);
1391 if (port->flags & UPF_FOURPORT) {
1392 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1394 serial8250_out_MCR(up,
1395 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1397 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1398 serial_in(up, UART_LSR);
1399 serial_in(up, UART_RX);
1400 serial_in(up, UART_IIR);
1401 serial_in(up, UART_MSR);
1402 serial_out(up, UART_TX, 0xFF);
1404 irq = probe_irq_off(irqs);
1406 serial8250_out_MCR(up, save_mcr);
1407 serial_out(up, UART_IER, save_ier);
1409 if (port->flags & UPF_FOURPORT)
1410 outb_p(save_ICP, ICP);
1412 if (uart_console(port))
1415 port->irq = (irq > 0) ? irq : 0;
1418 static void serial8250_stop_rx(struct uart_port *port)
1420 struct uart_8250_port *up = up_to_u8250p(port);
1422 serial8250_rpm_get(up);
1424 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1425 up->port.read_status_mask &= ~UART_LSR_DR;
1426 serial_port_out(port, UART_IER, up->ier);
1428 serial8250_rpm_put(up);
1432 * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback
1433 * @p: uart 8250 port
1435 * Generic callback usable by 8250 uart drivers to stop rs485 transmission.
1437 void serial8250_em485_stop_tx(struct uart_8250_port *p)
1439 unsigned char mcr = serial8250_in_MCR(p);
1441 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
1442 mcr |= UART_MCR_RTS;
1444 mcr &= ~UART_MCR_RTS;
1445 serial8250_out_MCR(p, mcr);
1448 * Empty the RX FIFO, we are not interested in anything
1449 * received during the half-duplex transmission.
1450 * Enable previously disabled RX interrupts.
1452 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1453 serial8250_clear_and_reinit_fifos(p);
1455 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1456 serial_port_out(&p->port, UART_IER, p->ier);
1459 EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx);
1461 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1463 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1465 struct uart_8250_port *p = em485->port;
1466 unsigned long flags;
1468 serial8250_rpm_get(p);
1469 spin_lock_irqsave(&p->port.lock, flags);
1470 if (em485->active_timer == &em485->stop_tx_timer) {
1471 p->rs485_stop_tx(p);
1472 em485->active_timer = NULL;
1473 em485->tx_stopped = true;
1475 spin_unlock_irqrestore(&p->port.lock, flags);
1476 serial8250_rpm_put(p);
1478 return HRTIMER_NORESTART;
1481 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1483 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
1486 static void __stop_tx_rs485(struct uart_8250_port *p, u64 stop_delay)
1488 struct uart_8250_em485 *em485 = p->em485;
1490 stop_delay += (u64)p->port.rs485.delay_rts_after_send * NSEC_PER_MSEC;
1493 * rs485_stop_tx() is going to set RTS according to config
1494 * AND flush RX FIFO if required.
1496 if (stop_delay > 0) {
1497 em485->active_timer = &em485->stop_tx_timer;
1498 hrtimer_start(&em485->stop_tx_timer, ns_to_ktime(stop_delay), HRTIMER_MODE_REL);
1500 p->rs485_stop_tx(p);
1501 em485->active_timer = NULL;
1502 em485->tx_stopped = true;
1506 static inline void __do_stop_tx(struct uart_8250_port *p)
1508 if (serial8250_clear_THRI(p))
1509 serial8250_rpm_put_tx(p);
1512 static inline void __stop_tx(struct uart_8250_port *p)
1514 struct uart_8250_em485 *em485 = p->em485;
1517 unsigned char lsr = serial_in(p, UART_LSR);
1520 if (!(lsr & UART_LSR_THRE))
1523 * To provide required timeing and allow FIFO transfer,
1524 * __stop_tx_rs485() must be called only when both FIFO and
1525 * shift register are empty. The device driver should either
1526 * enable interrupt on TEMT or set UART_CAP_NOTEMT that will
1527 * enlarge stop_tx_timer by the tx time of one frame to cover
1528 * for emptying of the shift register.
1530 if (!(lsr & UART_LSR_TEMT)) {
1531 if (!(p->capabilities & UART_CAP_NOTEMT))
1534 * RTS might get deasserted too early with the normal
1535 * frame timing formula. It seems to suggest THRE might
1536 * get asserted already during tx of the stop bit
1537 * rather than after it is fully sent.
1538 * Roughly estimate 1 extra bit here with / 7.
1540 stop_delay = p->port.frame_time + DIV_ROUND_UP(p->port.frame_time, 7);
1543 __stop_tx_rs485(p, stop_delay);
1548 static void serial8250_stop_tx(struct uart_port *port)
1550 struct uart_8250_port *up = up_to_u8250p(port);
1552 serial8250_rpm_get(up);
1556 * We really want to stop the transmitter from sending.
1558 if (port->type == PORT_16C950) {
1559 up->acr |= UART_ACR_TXDIS;
1560 serial_icr_write(up, UART_ACR, up->acr);
1562 serial8250_rpm_put(up);
1565 static inline void __start_tx(struct uart_port *port)
1567 struct uart_8250_port *up = up_to_u8250p(port);
1569 if (up->dma && !up->dma->tx_dma(up))
1572 if (serial8250_set_THRI(up)) {
1573 if (up->bugs & UART_BUG_TXEN) {
1576 lsr = serial_in(up, UART_LSR);
1577 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1578 if (lsr & UART_LSR_THRE)
1579 serial8250_tx_chars(up);
1584 * Re-enable the transmitter if we disabled it.
1586 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1587 up->acr &= ~UART_ACR_TXDIS;
1588 serial_icr_write(up, UART_ACR, up->acr);
1593 * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback
1594 * @up: uart 8250 port
1596 * Generic callback usable by 8250 uart drivers to start rs485 transmission.
1597 * Assumes that setting the RTS bit in the MCR register means RTS is high.
1598 * (Some chips use inverse semantics.) Further assumes that reception is
1599 * stoppable by disabling the UART_IER_RDI interrupt. (Some chips set the
1600 * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.)
1602 void serial8250_em485_start_tx(struct uart_8250_port *up)
1604 unsigned char mcr = serial8250_in_MCR(up);
1606 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1607 serial8250_stop_rx(&up->port);
1609 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1610 mcr |= UART_MCR_RTS;
1612 mcr &= ~UART_MCR_RTS;
1613 serial8250_out_MCR(up, mcr);
1615 EXPORT_SYMBOL_GPL(serial8250_em485_start_tx);
1617 static inline void start_tx_rs485(struct uart_port *port)
1619 struct uart_8250_port *up = up_to_u8250p(port);
1620 struct uart_8250_em485 *em485 = up->em485;
1623 * While serial8250_em485_handle_stop_tx() is a noop if
1624 * em485->active_timer != &em485->stop_tx_timer, it might happen that
1625 * the timer is still armed and triggers only after the current bunch of
1626 * chars is send and em485->active_timer == &em485->stop_tx_timer again.
1627 * So cancel the timer. There is still a theoretical race condition if
1628 * the timer is already running and only comes around to check for
1629 * em485->active_timer when &em485->stop_tx_timer is armed again.
1631 if (em485->active_timer == &em485->stop_tx_timer)
1632 hrtimer_try_to_cancel(&em485->stop_tx_timer);
1634 em485->active_timer = NULL;
1636 if (em485->tx_stopped) {
1637 em485->tx_stopped = false;
1639 up->rs485_start_tx(up);
1641 if (up->port.rs485.delay_rts_before_send > 0) {
1642 em485->active_timer = &em485->start_tx_timer;
1643 start_hrtimer_ms(&em485->start_tx_timer,
1644 up->port.rs485.delay_rts_before_send);
1652 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1654 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1656 struct uart_8250_port *p = em485->port;
1657 unsigned long flags;
1659 spin_lock_irqsave(&p->port.lock, flags);
1660 if (em485->active_timer == &em485->start_tx_timer) {
1661 __start_tx(&p->port);
1662 em485->active_timer = NULL;
1664 spin_unlock_irqrestore(&p->port.lock, flags);
1666 return HRTIMER_NORESTART;
1669 static void serial8250_start_tx(struct uart_port *port)
1671 struct uart_8250_port *up = up_to_u8250p(port);
1672 struct uart_8250_em485 *em485 = up->em485;
1674 if (!port->x_char && uart_circ_empty(&port->state->xmit))
1677 serial8250_rpm_get_tx(up);
1680 em485->active_timer == &em485->start_tx_timer)
1684 start_tx_rs485(port);
1689 static void serial8250_throttle(struct uart_port *port)
1691 port->throttle(port);
1694 static void serial8250_unthrottle(struct uart_port *port)
1696 port->unthrottle(port);
1699 static void serial8250_disable_ms(struct uart_port *port)
1701 struct uart_8250_port *up = up_to_u8250p(port);
1703 /* no MSR capabilities */
1704 if (up->bugs & UART_BUG_NOMSR)
1707 mctrl_gpio_disable_ms(up->gpios);
1709 up->ier &= ~UART_IER_MSI;
1710 serial_port_out(port, UART_IER, up->ier);
1713 static void serial8250_enable_ms(struct uart_port *port)
1715 struct uart_8250_port *up = up_to_u8250p(port);
1717 /* no MSR capabilities */
1718 if (up->bugs & UART_BUG_NOMSR)
1721 mctrl_gpio_enable_ms(up->gpios);
1723 up->ier |= UART_IER_MSI;
1725 serial8250_rpm_get(up);
1726 serial_port_out(port, UART_IER, up->ier);
1727 serial8250_rpm_put(up);
1730 void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1732 struct uart_port *port = &up->port;
1734 char flag = TTY_NORMAL;
1736 if (likely(lsr & UART_LSR_DR))
1737 ch = serial_in(up, UART_RX);
1740 * Intel 82571 has a Serial Over Lan device that will
1741 * set UART_LSR_BI without setting UART_LSR_DR when
1742 * it receives a break. To avoid reading from the
1743 * receive buffer without UART_LSR_DR bit set, we
1744 * just force the read character to be 0
1750 lsr |= up->lsr_saved_flags;
1751 up->lsr_saved_flags = 0;
1753 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1754 if (lsr & UART_LSR_BI) {
1755 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1758 * We do the SysRQ and SAK checking
1759 * here because otherwise the break
1760 * may get masked by ignore_status_mask
1761 * or read_status_mask.
1763 if (uart_handle_break(port))
1765 } else if (lsr & UART_LSR_PE)
1766 port->icount.parity++;
1767 else if (lsr & UART_LSR_FE)
1768 port->icount.frame++;
1769 if (lsr & UART_LSR_OE)
1770 port->icount.overrun++;
1773 * Mask off conditions which should be ignored.
1775 lsr &= port->read_status_mask;
1777 if (lsr & UART_LSR_BI) {
1778 dev_dbg(port->dev, "handling break\n");
1780 } else if (lsr & UART_LSR_PE)
1782 else if (lsr & UART_LSR_FE)
1785 if (uart_prepare_sysrq_char(port, ch))
1788 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1790 EXPORT_SYMBOL_GPL(serial8250_read_char);
1793 * serial8250_rx_chars: processes according to the passed in LSR
1794 * value, and returns the remaining LSR bits not handled
1795 * by this Rx routine.
1797 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1799 struct uart_port *port = &up->port;
1800 int max_count = 256;
1803 serial8250_read_char(up, lsr);
1804 if (--max_count == 0)
1806 lsr = serial_in(up, UART_LSR);
1807 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1809 tty_flip_buffer_push(&port->state->port);
1812 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1814 void serial8250_tx_chars(struct uart_8250_port *up)
1816 struct uart_port *port = &up->port;
1817 struct circ_buf *xmit = &port->state->xmit;
1821 uart_xchar_out(port, UART_TX);
1824 if (uart_tx_stopped(port)) {
1825 serial8250_stop_tx(port);
1828 if (uart_circ_empty(xmit)) {
1833 count = up->tx_loadsz;
1835 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1836 if (up->bugs & UART_BUG_TXRACE) {
1838 * The Aspeed BMC virtual UARTs have a bug where data
1839 * may get stuck in the BMC's Tx FIFO from bursts of
1840 * writes on the APB interface.
1842 * Delay back-to-back writes by a read cycle to avoid
1843 * stalling the VUART. Read a register that won't have
1844 * side-effects and discard the result.
1846 serial_in(up, UART_SCR);
1848 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1850 if (uart_circ_empty(xmit))
1852 if ((up->capabilities & UART_CAP_HFIFO) &&
1853 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1855 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1856 if ((up->capabilities & UART_CAP_MINI) &&
1857 !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1859 } while (--count > 0);
1861 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1862 uart_write_wakeup(port);
1865 * With RPM enabled, we have to wait until the FIFO is empty before the
1866 * HW can go idle. So we get here once again with empty FIFO and disable
1867 * the interrupt and RPM in __stop_tx()
1869 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1872 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1874 /* Caller holds uart port lock */
1875 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1877 struct uart_port *port = &up->port;
1878 unsigned int status = serial_in(up, UART_MSR);
1880 status |= up->msr_saved_flags;
1881 up->msr_saved_flags = 0;
1882 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1883 port->state != NULL) {
1884 if (status & UART_MSR_TERI)
1886 if (status & UART_MSR_DDSR)
1888 if (status & UART_MSR_DDCD)
1889 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1890 if (status & UART_MSR_DCTS)
1891 uart_handle_cts_change(port, status & UART_MSR_CTS);
1893 wake_up_interruptible(&port->state->port.delta_msr_wait);
1898 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1900 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1902 switch (iir & 0x3f) {
1903 case UART_IIR_RX_TIMEOUT:
1904 serial8250_rx_dma_flush(up);
1909 return up->dma->rx_dma(up);
1913 * This handles the interrupt from one port.
1915 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1917 unsigned char status;
1918 struct uart_8250_port *up = up_to_u8250p(port);
1919 bool skip_rx = false;
1920 unsigned long flags;
1922 if (iir & UART_IIR_NO_INT)
1925 spin_lock_irqsave(&port->lock, flags);
1927 status = serial_port_in(port, UART_LSR);
1930 * If port is stopped and there are no error conditions in the
1931 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1932 * overflow. Not servicing, RX FIFO would trigger auto HW flow
1933 * control when FIFO occupancy reaches preset threshold, thus
1934 * halting RX. This only works when auto HW flow control is
1937 if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1938 (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1939 !(port->read_status_mask & UART_LSR_DR))
1942 if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1943 if (!up->dma || handle_rx_dma(up, iir))
1944 status = serial8250_rx_chars(up, status);
1946 serial8250_modem_status(up);
1947 if ((status & UART_LSR_THRE) && (up->ier & UART_IER_THRI)) {
1948 if (!up->dma || up->dma->tx_err)
1949 serial8250_tx_chars(up);
1954 uart_unlock_and_check_sysrq_irqrestore(port, flags);
1958 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1960 static int serial8250_default_handle_irq(struct uart_port *port)
1962 struct uart_8250_port *up = up_to_u8250p(port);
1966 serial8250_rpm_get(up);
1968 iir = serial_port_in(port, UART_IIR);
1969 ret = serial8250_handle_irq(port, iir);
1971 serial8250_rpm_put(up);
1976 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1977 * have a programmable TX threshold that triggers the THRE interrupt in
1978 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1979 * has space available. Load it up with tx_loadsz bytes.
1981 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1983 unsigned long flags;
1984 unsigned int iir = serial_port_in(port, UART_IIR);
1986 /* TX Threshold IRQ triggered so load up FIFO */
1987 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1988 struct uart_8250_port *up = up_to_u8250p(port);
1990 spin_lock_irqsave(&port->lock, flags);
1991 serial8250_tx_chars(up);
1992 spin_unlock_irqrestore(&port->lock, flags);
1995 iir = serial_port_in(port, UART_IIR);
1996 return serial8250_handle_irq(port, iir);
1999 static unsigned int serial8250_tx_empty(struct uart_port *port)
2001 struct uart_8250_port *up = up_to_u8250p(port);
2002 unsigned long flags;
2005 serial8250_rpm_get(up);
2007 spin_lock_irqsave(&port->lock, flags);
2008 lsr = serial_port_in(port, UART_LSR);
2009 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
2010 spin_unlock_irqrestore(&port->lock, flags);
2012 serial8250_rpm_put(up);
2014 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
2017 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
2019 struct uart_8250_port *up = up_to_u8250p(port);
2020 unsigned int status;
2023 serial8250_rpm_get(up);
2024 status = serial8250_modem_status(up);
2025 serial8250_rpm_put(up);
2027 val = serial8250_MSR_to_TIOCM(status);
2029 return mctrl_gpio_get(up->gpios, &val);
2033 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
2035 static unsigned int serial8250_get_mctrl(struct uart_port *port)
2037 if (port->get_mctrl)
2038 return port->get_mctrl(port);
2039 return serial8250_do_get_mctrl(port);
2042 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
2044 struct uart_8250_port *up = up_to_u8250p(port);
2047 mcr = serial8250_TIOCM_to_MCR(mctrl);
2051 serial8250_out_MCR(up, mcr);
2053 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2055 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2057 if (port->set_mctrl)
2058 port->set_mctrl(port, mctrl);
2060 serial8250_do_set_mctrl(port, mctrl);
2063 static void serial8250_break_ctl(struct uart_port *port, int break_state)
2065 struct uart_8250_port *up = up_to_u8250p(port);
2066 unsigned long flags;
2068 serial8250_rpm_get(up);
2069 spin_lock_irqsave(&port->lock, flags);
2070 if (break_state == -1)
2071 up->lcr |= UART_LCR_SBC;
2073 up->lcr &= ~UART_LCR_SBC;
2074 serial_port_out(port, UART_LCR, up->lcr);
2075 spin_unlock_irqrestore(&port->lock, flags);
2076 serial8250_rpm_put(up);
2079 static void wait_for_lsr(struct uart_8250_port *up, int bits)
2081 unsigned int status, tmout = 10000;
2083 /* Wait up to 10ms for the character(s) to be sent. */
2085 status = serial_in(up, UART_LSR);
2087 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2089 if ((status & bits) == bits)
2094 touch_nmi_watchdog();
2099 * Wait for transmitter & holding register to empty
2101 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2105 wait_for_lsr(up, bits);
2107 /* Wait up to 1s for flow control if necessary */
2108 if (up->port.flags & UPF_CONS_FLOW) {
2109 for (tmout = 1000000; tmout; tmout--) {
2110 unsigned int msr = serial_in(up, UART_MSR);
2111 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2112 if (msr & UART_MSR_CTS)
2115 touch_nmi_watchdog();
2120 #ifdef CONFIG_CONSOLE_POLL
2122 * Console polling routines for writing and reading from the uart while
2123 * in an interrupt or debug context.
2126 static int serial8250_get_poll_char(struct uart_port *port)
2128 struct uart_8250_port *up = up_to_u8250p(port);
2132 serial8250_rpm_get(up);
2134 lsr = serial_port_in(port, UART_LSR);
2136 if (!(lsr & UART_LSR_DR)) {
2137 status = NO_POLL_CHAR;
2141 status = serial_port_in(port, UART_RX);
2143 serial8250_rpm_put(up);
2148 static void serial8250_put_poll_char(struct uart_port *port,
2152 struct uart_8250_port *up = up_to_u8250p(port);
2154 serial8250_rpm_get(up);
2156 * First save the IER then disable the interrupts
2158 ier = serial_port_in(port, UART_IER);
2159 if (up->capabilities & UART_CAP_UUE)
2160 serial_port_out(port, UART_IER, UART_IER_UUE);
2162 serial_port_out(port, UART_IER, 0);
2164 wait_for_xmitr(up, BOTH_EMPTY);
2166 * Send the character out.
2168 serial_port_out(port, UART_TX, c);
2171 * Finally, wait for transmitter to become empty
2172 * and restore the IER
2174 wait_for_xmitr(up, BOTH_EMPTY);
2175 serial_port_out(port, UART_IER, ier);
2176 serial8250_rpm_put(up);
2179 #endif /* CONFIG_CONSOLE_POLL */
2181 int serial8250_do_startup(struct uart_port *port)
2183 struct uart_8250_port *up = up_to_u8250p(port);
2184 unsigned long flags;
2185 unsigned char lsr, iir;
2188 if (!port->fifosize)
2189 port->fifosize = uart_config[port->type].fifo_size;
2191 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2192 if (!up->capabilities)
2193 up->capabilities = uart_config[port->type].flags;
2196 if (port->iotype != up->cur_iotype)
2197 set_io_from_upio(port);
2199 serial8250_rpm_get(up);
2200 if (port->type == PORT_16C950) {
2201 /* Wake up and initialize UART */
2203 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2204 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2205 serial_port_out(port, UART_IER, 0);
2206 serial_port_out(port, UART_LCR, 0);
2207 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2208 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2209 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2210 serial_port_out(port, UART_LCR, 0);
2213 if (port->type == PORT_DA830) {
2214 /* Reset the port */
2215 serial_port_out(port, UART_IER, 0);
2216 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2219 /* Enable Tx, Rx and free run mode */
2220 serial_port_out(port, UART_DA830_PWREMU_MGMT,
2221 UART_DA830_PWREMU_MGMT_UTRST |
2222 UART_DA830_PWREMU_MGMT_URRST |
2223 UART_DA830_PWREMU_MGMT_FREE);
2226 if (port->type == PORT_NPCM) {
2228 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2229 * register). Enable it, and set TIOC (timeout interrupt
2230 * comparator) to be 0x20 for correct operation.
2232 serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2235 #ifdef CONFIG_SERIAL_8250_RSA
2237 * If this is an RSA port, see if we can kick it up to the
2238 * higher speed clock.
2244 * Clear the FIFO buffers and disable them.
2245 * (they will be reenabled in set_termios())
2247 serial8250_clear_fifos(up);
2250 * Clear the interrupt registers.
2252 serial_port_in(port, UART_LSR);
2253 serial_port_in(port, UART_RX);
2254 serial_port_in(port, UART_IIR);
2255 serial_port_in(port, UART_MSR);
2258 * At this point, there's no way the LSR could still be 0xff;
2259 * if it is, then bail out, because there's likely no UART
2262 if (!(port->flags & UPF_BUGGY_UART) &&
2263 (serial_port_in(port, UART_LSR) == 0xff)) {
2264 dev_info_ratelimited(port->dev, "LSR safety check engaged!\n");
2270 * For a XR16C850, we need to set the trigger levels
2272 if (port->type == PORT_16850) {
2275 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2277 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2278 serial_port_out(port, UART_FCTR,
2279 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2280 serial_port_out(port, UART_TRG, UART_TRG_96);
2281 serial_port_out(port, UART_FCTR,
2282 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2283 serial_port_out(port, UART_TRG, UART_TRG_96);
2285 serial_port_out(port, UART_LCR, 0);
2289 * For the Altera 16550 variants, set TX threshold trigger level.
2291 if (((port->type == PORT_ALTR_16550_F32) ||
2292 (port->type == PORT_ALTR_16550_F64) ||
2293 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2294 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2295 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2296 dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2298 serial_port_out(port, UART_ALTR_AFR,
2299 UART_ALTR_EN_TXFIFO_LW);
2300 serial_port_out(port, UART_ALTR_TX_LOW,
2301 port->fifosize - up->tx_loadsz);
2302 port->handle_irq = serial8250_tx_threshold_handle_irq;
2306 /* Check if we need to have shared IRQs */
2307 if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2308 up->port.irqflags |= IRQF_SHARED;
2310 if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2313 if (port->irqflags & IRQF_SHARED)
2314 disable_irq_nosync(port->irq);
2317 * Test for UARTs that do not reassert THRE when the
2318 * transmitter is idle and the interrupt has already
2319 * been cleared. Real 16550s should always reassert
2320 * this interrupt whenever the transmitter is idle and
2321 * the interrupt is enabled. Delays are necessary to
2322 * allow register changes to become visible.
2324 spin_lock_irqsave(&port->lock, flags);
2326 wait_for_xmitr(up, UART_LSR_THRE);
2327 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2328 udelay(1); /* allow THRE to set */
2329 iir1 = serial_port_in(port, UART_IIR);
2330 serial_port_out(port, UART_IER, 0);
2331 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2332 udelay(1); /* allow a working UART time to re-assert THRE */
2333 iir = serial_port_in(port, UART_IIR);
2334 serial_port_out(port, UART_IER, 0);
2336 spin_unlock_irqrestore(&port->lock, flags);
2338 if (port->irqflags & IRQF_SHARED)
2339 enable_irq(port->irq);
2342 * If the interrupt is not reasserted, or we otherwise
2343 * don't trust the iir, setup a timer to kick the UART
2344 * on a regular basis.
2346 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2347 up->port.flags & UPF_BUG_THRE) {
2348 up->bugs |= UART_BUG_THRE;
2352 retval = up->ops->setup_irq(up);
2357 * Now, initialize the UART
2359 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2361 spin_lock_irqsave(&port->lock, flags);
2362 if (up->port.flags & UPF_FOURPORT) {
2364 up->port.mctrl |= TIOCM_OUT1;
2367 * Most PC uarts need OUT2 raised to enable interrupts.
2370 up->port.mctrl |= TIOCM_OUT2;
2372 serial8250_set_mctrl(port, port->mctrl);
2375 * Serial over Lan (SoL) hack:
2376 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2377 * used for Serial Over Lan. Those chips take a longer time than a
2378 * normal serial device to signalize that a transmission data was
2379 * queued. Due to that, the above test generally fails. One solution
2380 * would be to delay the reading of iir. However, this is not
2381 * reliable, since the timeout is variable. So, let's just don't
2382 * test if we receive TX irq. This way, we'll never enable
2385 if (up->port.quirks & UPQ_NO_TXEN_TEST)
2386 goto dont_test_tx_en;
2389 * Do a quick test to see if we receive an interrupt when we enable
2392 serial_port_out(port, UART_IER, UART_IER_THRI);
2393 lsr = serial_port_in(port, UART_LSR);
2394 iir = serial_port_in(port, UART_IIR);
2395 serial_port_out(port, UART_IER, 0);
2397 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2398 if (!(up->bugs & UART_BUG_TXEN)) {
2399 up->bugs |= UART_BUG_TXEN;
2400 dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2403 up->bugs &= ~UART_BUG_TXEN;
2407 spin_unlock_irqrestore(&port->lock, flags);
2410 * Clear the interrupt registers again for luck, and clear the
2411 * saved flags to avoid getting false values from polling
2412 * routines or the previous session.
2414 serial_port_in(port, UART_LSR);
2415 serial_port_in(port, UART_RX);
2416 serial_port_in(port, UART_IIR);
2417 serial_port_in(port, UART_MSR);
2418 up->lsr_saved_flags = 0;
2419 up->msr_saved_flags = 0;
2422 * Request DMA channels for both RX and TX.
2425 const char *msg = NULL;
2427 if (uart_console(port))
2428 msg = "forbid DMA for kernel console";
2429 else if (serial8250_request_dma(up))
2430 msg = "failed to request DMA";
2432 dev_warn_ratelimited(port->dev, "%s\n", msg);
2438 * Set the IER shadow for rx interrupts but defer actual interrupt
2439 * enable until after the FIFOs are enabled; otherwise, an already-
2440 * active sender can swamp the interrupt handler with "too much work".
2442 up->ier = UART_IER_RLSI | UART_IER_RDI;
2444 if (port->flags & UPF_FOURPORT) {
2447 * Enable interrupts on the AST Fourport board
2449 icp = (port->iobase & 0xfe0) | 0x01f;
2455 serial8250_rpm_put(up);
2458 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2460 static int serial8250_startup(struct uart_port *port)
2463 return port->startup(port);
2464 return serial8250_do_startup(port);
2467 void serial8250_do_shutdown(struct uart_port *port)
2469 struct uart_8250_port *up = up_to_u8250p(port);
2470 unsigned long flags;
2472 serial8250_rpm_get(up);
2474 * Disable interrupts from this port
2476 spin_lock_irqsave(&port->lock, flags);
2478 serial_port_out(port, UART_IER, 0);
2479 spin_unlock_irqrestore(&port->lock, flags);
2481 synchronize_irq(port->irq);
2484 serial8250_release_dma(up);
2486 spin_lock_irqsave(&port->lock, flags);
2487 if (port->flags & UPF_FOURPORT) {
2488 /* reset interrupts on the AST Fourport board */
2489 inb((port->iobase & 0xfe0) | 0x1f);
2490 port->mctrl |= TIOCM_OUT1;
2492 port->mctrl &= ~TIOCM_OUT2;
2494 serial8250_set_mctrl(port, port->mctrl);
2495 spin_unlock_irqrestore(&port->lock, flags);
2498 * Disable break condition and FIFOs
2500 serial_port_out(port, UART_LCR,
2501 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2502 serial8250_clear_fifos(up);
2504 #ifdef CONFIG_SERIAL_8250_RSA
2506 * Reset the RSA board back to 115kbps compat mode.
2512 * Read data port to reset things, and then unlink from
2515 serial_port_in(port, UART_RX);
2516 serial8250_rpm_put(up);
2518 up->ops->release_irq(up);
2520 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2522 static void serial8250_shutdown(struct uart_port *port)
2525 port->shutdown(port);
2527 serial8250_do_shutdown(port);
2530 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2531 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2534 struct uart_port *port = &up->port;
2536 return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2539 static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2543 upf_t magic_multiplier = port->flags & UPF_MAGIC_MULTIPLIER;
2544 struct uart_8250_port *up = up_to_u8250p(port);
2548 * Handle magic divisors for baud rates above baud_base on SMSC
2549 * Super I/O chips. We clamp custom rates from clk/6 and clk/12
2550 * up to clk/4 (0x8001) and clk/8 (0x8002) respectively. These
2551 * magic divisors actually reprogram the baud rate generator's
2552 * reference clock derived from chips's 14.318MHz clock input.
2554 * Documentation claims that with these magic divisors the base
2555 * frequencies of 7.3728MHz and 3.6864MHz are used respectively
2556 * for the extra baud rates of 460800bps and 230400bps rather
2557 * than the usual base frequency of 1.8462MHz. However empirical
2558 * evidence contradicts that.
2560 * Instead bit 7 of the DLM register (bit 15 of the divisor) is
2561 * effectively used as a clock prescaler selection bit for the
2562 * base frequency of 7.3728MHz, always used. If set to 0, then
2563 * the base frequency is divided by 4 for use by the Baud Rate
2564 * Generator, for the usual arrangement where the value of 1 of
2565 * the divisor produces the baud rate of 115200bps. Conversely,
2566 * if set to 1 and high-speed operation has been enabled with the
2567 * Serial Port Mode Register in the Device Configuration Space,
2568 * then the base frequency is supplied directly to the Baud Rate
2569 * Generator, so for the divisor values of 0x8001, 0x8002, 0x8003,
2570 * 0x8004, etc. the respective baud rates produced are 460800bps,
2571 * 230400bps, 153600bps, 115200bps, etc.
2573 * In all cases only low 15 bits of the divisor are used to divide
2574 * the baud base and therefore 32767 is the maximum divisor value
2575 * possible, even though documentation says that the programmable
2576 * Baud Rate Generator is capable of dividing the internal PLL
2577 * clock by any divisor from 1 to 65535.
2579 if (magic_multiplier && baud >= port->uartclk / 6)
2581 else if (magic_multiplier && baud >= port->uartclk / 12)
2583 else if (up->port.type == PORT_NPCM)
2584 quot = npcm_get_divisor(up, baud);
2586 quot = uart_get_divisor(port, baud);
2589 * Oxford Semi 952 rev B workaround
2591 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2597 static unsigned int serial8250_get_divisor(struct uart_port *port,
2601 if (port->get_divisor)
2602 return port->get_divisor(port, baud, frac);
2604 return serial8250_do_get_divisor(port, baud, frac);
2607 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2612 cval = UART_LCR_WLEN(tty_get_char_size(c_cflag));
2614 if (c_cflag & CSTOPB)
2615 cval |= UART_LCR_STOP;
2616 if (c_cflag & PARENB) {
2617 cval |= UART_LCR_PARITY;
2618 if (up->bugs & UART_BUG_PARITY)
2619 up->fifo_bug = true;
2621 if (!(c_cflag & PARODD))
2622 cval |= UART_LCR_EPAR;
2623 if (c_cflag & CMSPAR)
2624 cval |= UART_LCR_SPAR;
2629 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2630 unsigned int quot, unsigned int quot_frac)
2632 struct uart_8250_port *up = up_to_u8250p(port);
2634 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2635 if (is_omap1510_8250(up)) {
2636 if (baud == 115200) {
2638 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2640 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2644 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2645 * otherwise just set DLAB
2647 if (up->capabilities & UART_NATSEMI)
2648 serial_port_out(port, UART_LCR, 0xe0);
2650 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2652 serial_dl_write(up, quot);
2654 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2656 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2657 unsigned int quot, unsigned int quot_frac)
2659 if (port->set_divisor)
2660 port->set_divisor(port, baud, quot, quot_frac);
2662 serial8250_do_set_divisor(port, baud, quot, quot_frac);
2665 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2666 struct ktermios *termios,
2667 struct ktermios *old)
2669 unsigned int tolerance = port->uartclk / 100;
2674 * Handle magic divisors for baud rates above baud_base on SMSC
2675 * Super I/O chips. Enable custom rates of clk/4 and clk/8, but
2676 * disable divisor values beyond 32767, which are unavailable.
2678 if (port->flags & UPF_MAGIC_MULTIPLIER) {
2679 min = port->uartclk / 16 / UART_DIV_MAX >> 1;
2680 max = (port->uartclk + tolerance) / 4;
2682 min = port->uartclk / 16 / UART_DIV_MAX;
2683 max = (port->uartclk + tolerance) / 16;
2687 * Ask the core to calculate the divisor for us.
2688 * Allow 1% tolerance at the upper limit so uart clks marginally
2689 * slower than nominal still match standard baud rates without
2690 * causing transmission errors.
2692 return uart_get_baud_rate(port, termios, old, min, max);
2696 * Note in order to avoid the tty port mutex deadlock don't use the next method
2697 * within the uart port callbacks. Primarily it's supposed to be utilized to
2698 * handle a sudden reference clock rate change.
2700 void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk)
2702 struct uart_8250_port *up = up_to_u8250p(port);
2703 struct tty_port *tport = &port->state->port;
2704 unsigned int baud, quot, frac = 0;
2705 struct ktermios *termios;
2706 struct tty_struct *tty;
2707 unsigned long flags;
2709 tty = tty_port_tty_get(tport);
2711 mutex_lock(&tport->mutex);
2712 port->uartclk = uartclk;
2713 mutex_unlock(&tport->mutex);
2717 down_write(&tty->termios_rwsem);
2718 mutex_lock(&tport->mutex);
2720 if (port->uartclk == uartclk)
2723 port->uartclk = uartclk;
2725 if (!tty_port_initialized(tport))
2728 termios = &tty->termios;
2730 baud = serial8250_get_baud_rate(port, termios, NULL);
2731 quot = serial8250_get_divisor(port, baud, &frac);
2733 serial8250_rpm_get(up);
2734 spin_lock_irqsave(&port->lock, flags);
2736 uart_update_timeout(port, termios->c_cflag, baud);
2738 serial8250_set_divisor(port, baud, quot, frac);
2739 serial_port_out(port, UART_LCR, up->lcr);
2741 spin_unlock_irqrestore(&port->lock, flags);
2742 serial8250_rpm_put(up);
2745 mutex_unlock(&tport->mutex);
2746 up_write(&tty->termios_rwsem);
2749 EXPORT_SYMBOL_GPL(serial8250_update_uartclk);
2752 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2753 struct ktermios *old)
2755 struct uart_8250_port *up = up_to_u8250p(port);
2757 unsigned long flags;
2758 unsigned int baud, quot, frac = 0;
2760 if (up->capabilities & UART_CAP_MINI) {
2761 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2762 if ((termios->c_cflag & CSIZE) == CS5 ||
2763 (termios->c_cflag & CSIZE) == CS6)
2764 termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2766 cval = serial8250_compute_lcr(up, termios->c_cflag);
2768 baud = serial8250_get_baud_rate(port, termios, old);
2769 quot = serial8250_get_divisor(port, baud, &frac);
2772 * Ok, we're now changing the port state. Do it with
2773 * interrupts disabled.
2775 serial8250_rpm_get(up);
2776 spin_lock_irqsave(&port->lock, flags);
2778 up->lcr = cval; /* Save computed LCR */
2780 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2781 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2782 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2783 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2784 up->fcr |= UART_FCR_TRIGGER_1;
2789 * MCR-based auto flow control. When AFE is enabled, RTS will be
2790 * deasserted when the receive FIFO contains more characters than
2791 * the trigger, or the MCR RTS bit is cleared.
2793 if (up->capabilities & UART_CAP_AFE) {
2794 up->mcr &= ~UART_MCR_AFE;
2795 if (termios->c_cflag & CRTSCTS)
2796 up->mcr |= UART_MCR_AFE;
2800 * Update the per-port timeout.
2802 uart_update_timeout(port, termios->c_cflag, baud);
2804 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2805 if (termios->c_iflag & INPCK)
2806 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2807 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2808 port->read_status_mask |= UART_LSR_BI;
2811 * Characteres to ignore
2813 port->ignore_status_mask = 0;
2814 if (termios->c_iflag & IGNPAR)
2815 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2816 if (termios->c_iflag & IGNBRK) {
2817 port->ignore_status_mask |= UART_LSR_BI;
2819 * If we're ignoring parity and break indicators,
2820 * ignore overruns too (for real raw support).
2822 if (termios->c_iflag & IGNPAR)
2823 port->ignore_status_mask |= UART_LSR_OE;
2827 * ignore all characters if CREAD is not set
2829 if ((termios->c_cflag & CREAD) == 0)
2830 port->ignore_status_mask |= UART_LSR_DR;
2833 * CTS flow control flag and modem status interrupts
2835 up->ier &= ~UART_IER_MSI;
2836 if (!(up->bugs & UART_BUG_NOMSR) &&
2837 UART_ENABLE_MS(&up->port, termios->c_cflag))
2838 up->ier |= UART_IER_MSI;
2839 if (up->capabilities & UART_CAP_UUE)
2840 up->ier |= UART_IER_UUE;
2841 if (up->capabilities & UART_CAP_RTOIE)
2842 up->ier |= UART_IER_RTOIE;
2844 serial_port_out(port, UART_IER, up->ier);
2846 if (up->capabilities & UART_CAP_EFR) {
2847 unsigned char efr = 0;
2849 * TI16C752/Startech hardware flow control. FIXME:
2850 * - TI16C752 requires control thresholds to be set.
2851 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2853 if (termios->c_cflag & CRTSCTS)
2854 efr |= UART_EFR_CTS;
2856 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2857 if (port->flags & UPF_EXAR_EFR)
2858 serial_port_out(port, UART_XR_EFR, efr);
2860 serial_port_out(port, UART_EFR, efr);
2863 serial8250_set_divisor(port, baud, quot, frac);
2866 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2867 * is written without DLAB set, this mode will be disabled.
2869 if (port->type == PORT_16750)
2870 serial_port_out(port, UART_FCR, up->fcr);
2872 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2873 if (port->type != PORT_16750) {
2874 /* emulated UARTs (Lucent Venus 167x) need two steps */
2875 if (up->fcr & UART_FCR_ENABLE_FIFO)
2876 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2877 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2879 serial8250_set_mctrl(port, port->mctrl);
2880 spin_unlock_irqrestore(&port->lock, flags);
2881 serial8250_rpm_put(up);
2883 /* Don't rewrite B0 */
2884 if (tty_termios_baud_rate(termios))
2885 tty_termios_encode_baud_rate(termios, baud, baud);
2887 EXPORT_SYMBOL(serial8250_do_set_termios);
2890 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2891 struct ktermios *old)
2893 if (port->set_termios)
2894 port->set_termios(port, termios, old);
2896 serial8250_do_set_termios(port, termios, old);
2899 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2901 if (termios->c_line == N_PPS) {
2902 port->flags |= UPF_HARDPPS_CD;
2903 spin_lock_irq(&port->lock);
2904 serial8250_enable_ms(port);
2905 spin_unlock_irq(&port->lock);
2907 port->flags &= ~UPF_HARDPPS_CD;
2908 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2909 spin_lock_irq(&port->lock);
2910 serial8250_disable_ms(port);
2911 spin_unlock_irq(&port->lock);
2915 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2918 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2920 if (port->set_ldisc)
2921 port->set_ldisc(port, termios);
2923 serial8250_do_set_ldisc(port, termios);
2926 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2927 unsigned int oldstate)
2929 struct uart_8250_port *p = up_to_u8250p(port);
2931 serial8250_set_sleep(p, state != 0);
2933 EXPORT_SYMBOL(serial8250_do_pm);
2936 serial8250_pm(struct uart_port *port, unsigned int state,
2937 unsigned int oldstate)
2940 port->pm(port, state, oldstate);
2942 serial8250_do_pm(port, state, oldstate);
2945 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2947 if (pt->port.mapsize)
2948 return pt->port.mapsize;
2949 if (pt->port.iotype == UPIO_AU) {
2950 if (pt->port.type == PORT_RT2880)
2954 if (is_omap1_8250(pt))
2955 return 0x16 << pt->port.regshift;
2957 return 8 << pt->port.regshift;
2961 * Resource handling.
2963 static int serial8250_request_std_resource(struct uart_8250_port *up)
2965 unsigned int size = serial8250_port_size(up);
2966 struct uart_port *port = &up->port;
2969 switch (port->iotype) {
2979 if (!request_mem_region(port->mapbase, size, "serial")) {
2984 if (port->flags & UPF_IOREMAP) {
2985 port->membase = ioremap(port->mapbase, size);
2986 if (!port->membase) {
2987 release_mem_region(port->mapbase, size);
2995 if (!request_region(port->iobase, size, "serial"))
3002 static void serial8250_release_std_resource(struct uart_8250_port *up)
3004 unsigned int size = serial8250_port_size(up);
3005 struct uart_port *port = &up->port;
3007 switch (port->iotype) {
3017 if (port->flags & UPF_IOREMAP) {
3018 iounmap(port->membase);
3019 port->membase = NULL;
3022 release_mem_region(port->mapbase, size);
3027 release_region(port->iobase, size);
3032 static void serial8250_release_port(struct uart_port *port)
3034 struct uart_8250_port *up = up_to_u8250p(port);
3036 serial8250_release_std_resource(up);
3039 static int serial8250_request_port(struct uart_port *port)
3041 struct uart_8250_port *up = up_to_u8250p(port);
3043 return serial8250_request_std_resource(up);
3046 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
3048 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3049 unsigned char bytes;
3051 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
3053 return bytes ? bytes : -EOPNOTSUPP;
3056 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
3058 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3061 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
3064 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
3065 if (bytes < conf_type->rxtrig_bytes[i])
3066 /* Use the nearest lower value */
3067 return (--i) << UART_FCR_R_TRIG_SHIFT;
3070 return UART_FCR_R_TRIG_11;
3073 static int do_get_rxtrig(struct tty_port *port)
3075 struct uart_state *state = container_of(port, struct uart_state, port);
3076 struct uart_port *uport = state->uart_port;
3077 struct uart_8250_port *up = up_to_u8250p(uport);
3079 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3082 return fcr_get_rxtrig_bytes(up);
3085 static int do_serial8250_get_rxtrig(struct tty_port *port)
3089 mutex_lock(&port->mutex);
3090 rxtrig_bytes = do_get_rxtrig(port);
3091 mutex_unlock(&port->mutex);
3093 return rxtrig_bytes;
3096 static ssize_t rx_trig_bytes_show(struct device *dev,
3097 struct device_attribute *attr, char *buf)
3099 struct tty_port *port = dev_get_drvdata(dev);
3102 rxtrig_bytes = do_serial8250_get_rxtrig(port);
3103 if (rxtrig_bytes < 0)
3104 return rxtrig_bytes;
3106 return sysfs_emit(buf, "%d\n", rxtrig_bytes);
3109 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
3111 struct uart_state *state = container_of(port, struct uart_state, port);
3112 struct uart_port *uport = state->uart_port;
3113 struct uart_8250_port *up = up_to_u8250p(uport);
3116 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
3120 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3124 serial8250_clear_fifos(up);
3125 up->fcr &= ~UART_FCR_TRIGGER_MASK;
3126 up->fcr |= (unsigned char)rxtrig;
3127 serial_out(up, UART_FCR, up->fcr);
3131 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3135 mutex_lock(&port->mutex);
3136 ret = do_set_rxtrig(port, bytes);
3137 mutex_unlock(&port->mutex);
3142 static ssize_t rx_trig_bytes_store(struct device *dev,
3143 struct device_attribute *attr, const char *buf, size_t count)
3145 struct tty_port *port = dev_get_drvdata(dev);
3146 unsigned char bytes;
3152 ret = kstrtou8(buf, 10, &bytes);
3156 ret = do_serial8250_set_rxtrig(port, bytes);
3163 static DEVICE_ATTR_RW(rx_trig_bytes);
3165 static struct attribute *serial8250_dev_attrs[] = {
3166 &dev_attr_rx_trig_bytes.attr,
3170 static struct attribute_group serial8250_dev_attr_group = {
3171 .attrs = serial8250_dev_attrs,
3174 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3176 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3178 if (conf_type->rxtrig_bytes[0])
3179 up->port.attr_group = &serial8250_dev_attr_group;
3182 static void serial8250_config_port(struct uart_port *port, int flags)
3184 struct uart_8250_port *up = up_to_u8250p(port);
3188 * Find the region that we can probe for. This in turn
3189 * tells us whether we can probe for the type of port.
3191 ret = serial8250_request_std_resource(up);
3195 if (port->iotype != up->cur_iotype)
3196 set_io_from_upio(port);
3198 if (flags & UART_CONFIG_TYPE)
3201 if (port->rs485.flags & SER_RS485_ENABLED)
3202 port->rs485_config(port, &port->rs485);
3204 /* if access method is AU, it is a 16550 with a quirk */
3205 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3206 up->bugs |= UART_BUG_NOMSR;
3208 /* HW bugs may trigger IRQ while IIR == NO_INT */
3209 if (port->type == PORT_TEGRA)
3210 up->bugs |= UART_BUG_NOMSR;
3212 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3215 if (port->type == PORT_UNKNOWN)
3216 serial8250_release_std_resource(up);
3218 register_dev_spec_attr_grp(up);
3219 up->fcr = uart_config[up->port.type].fcr;
3223 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3225 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3226 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3227 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3228 ser->type == PORT_STARTECH)
3233 static const char *serial8250_type(struct uart_port *port)
3235 int type = port->type;
3237 if (type >= ARRAY_SIZE(uart_config))
3239 return uart_config[type].name;
3242 static const struct uart_ops serial8250_pops = {
3243 .tx_empty = serial8250_tx_empty,
3244 .set_mctrl = serial8250_set_mctrl,
3245 .get_mctrl = serial8250_get_mctrl,
3246 .stop_tx = serial8250_stop_tx,
3247 .start_tx = serial8250_start_tx,
3248 .throttle = serial8250_throttle,
3249 .unthrottle = serial8250_unthrottle,
3250 .stop_rx = serial8250_stop_rx,
3251 .enable_ms = serial8250_enable_ms,
3252 .break_ctl = serial8250_break_ctl,
3253 .startup = serial8250_startup,
3254 .shutdown = serial8250_shutdown,
3255 .set_termios = serial8250_set_termios,
3256 .set_ldisc = serial8250_set_ldisc,
3257 .pm = serial8250_pm,
3258 .type = serial8250_type,
3259 .release_port = serial8250_release_port,
3260 .request_port = serial8250_request_port,
3261 .config_port = serial8250_config_port,
3262 .verify_port = serial8250_verify_port,
3263 #ifdef CONFIG_CONSOLE_POLL
3264 .poll_get_char = serial8250_get_poll_char,
3265 .poll_put_char = serial8250_put_poll_char,
3269 void serial8250_init_port(struct uart_8250_port *up)
3271 struct uart_port *port = &up->port;
3273 spin_lock_init(&port->lock);
3274 port->ops = &serial8250_pops;
3275 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3277 up->cur_iotype = 0xFF;
3279 EXPORT_SYMBOL_GPL(serial8250_init_port);
3281 void serial8250_set_defaults(struct uart_8250_port *up)
3283 struct uart_port *port = &up->port;
3285 if (up->port.flags & UPF_FIXED_TYPE) {
3286 unsigned int type = up->port.type;
3288 if (!up->port.fifosize)
3289 up->port.fifosize = uart_config[type].fifo_size;
3291 up->tx_loadsz = uart_config[type].tx_loadsz;
3292 if (!up->capabilities)
3293 up->capabilities = uart_config[type].flags;
3296 set_io_from_upio(port);
3298 /* default dma handlers */
3300 if (!up->dma->tx_dma)
3301 up->dma->tx_dma = serial8250_tx_dma;
3302 if (!up->dma->rx_dma)
3303 up->dma->rx_dma = serial8250_rx_dma;
3306 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3308 #ifdef CONFIG_SERIAL_8250_CONSOLE
3310 static void serial8250_console_putchar(struct uart_port *port, unsigned char ch)
3312 struct uart_8250_port *up = up_to_u8250p(port);
3314 wait_for_xmitr(up, UART_LSR_THRE);
3315 serial_port_out(port, UART_TX, ch);
3319 * Restore serial console when h/w power-off detected
3321 static void serial8250_console_restore(struct uart_8250_port *up)
3323 struct uart_port *port = &up->port;
3324 struct ktermios termios;
3325 unsigned int baud, quot, frac = 0;
3327 termios.c_cflag = port->cons->cflag;
3328 if (port->state->port.tty && termios.c_cflag == 0)
3329 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3331 baud = serial8250_get_baud_rate(port, &termios, NULL);
3332 quot = serial8250_get_divisor(port, baud, &frac);
3334 serial8250_set_divisor(port, baud, quot, frac);
3335 serial_port_out(port, UART_LCR, up->lcr);
3336 serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS);
3340 * Print a string to the serial port using the device FIFO
3342 * It sends fifosize bytes and then waits for the fifo
3345 static void serial8250_console_fifo_write(struct uart_8250_port *up,
3346 const char *s, unsigned int count)
3349 const char *end = s + count;
3350 unsigned int fifosize = up->tx_loadsz;
3351 bool cr_sent = false;
3354 wait_for_lsr(up, UART_LSR_THRE);
3356 for (i = 0; i < fifosize && s != end; ++i) {
3357 if (*s == '\n' && !cr_sent) {
3358 serial_out(up, UART_TX, '\r');
3361 serial_out(up, UART_TX, *s++);
3369 * Print a string to the serial port trying not to disturb
3370 * any possible real use of the port...
3372 * The console_lock must be held when we get here.
3374 * Doing runtime PM is really a bad idea for the kernel console.
3375 * Thus, we assume the function is called when device is powered up.
3377 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3380 struct uart_8250_em485 *em485 = up->em485;
3381 struct uart_port *port = &up->port;
3382 unsigned long flags;
3383 unsigned int ier, use_fifo;
3386 touch_nmi_watchdog();
3388 if (oops_in_progress)
3389 locked = spin_trylock_irqsave(&port->lock, flags);
3391 spin_lock_irqsave(&port->lock, flags);
3394 * First save the IER then disable the interrupts
3396 ier = serial_port_in(port, UART_IER);
3398 if (up->capabilities & UART_CAP_UUE)
3399 serial_port_out(port, UART_IER, UART_IER_UUE);
3401 serial_port_out(port, UART_IER, 0);
3403 /* check scratch reg to see if port powered off during system sleep */
3404 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3405 serial8250_console_restore(up);
3410 if (em485->tx_stopped)
3411 up->rs485_start_tx(up);
3412 mdelay(port->rs485.delay_rts_before_send);
3415 use_fifo = (up->capabilities & UART_CAP_FIFO) &&
3417 * BCM283x requires to check the fifo
3420 !(up->capabilities & UART_CAP_MINI) &&
3422 * tx_loadsz contains the transmit fifo size
3424 up->tx_loadsz > 1 &&
3425 (up->fcr & UART_FCR_ENABLE_FIFO) &&
3427 test_bit(TTY_PORT_INITIALIZED, &port->state->port.iflags) &&
3429 * After we put a data in the fifo, the controller will send
3430 * it regardless of the CTS state. Therefore, only use fifo
3431 * if we don't use control flow.
3433 !(up->port.flags & UPF_CONS_FLOW);
3435 if (likely(use_fifo))
3436 serial8250_console_fifo_write(up, s, count);
3438 uart_console_write(port, s, count, serial8250_console_putchar);
3441 * Finally, wait for transmitter to become empty
3442 * and restore the IER
3444 wait_for_xmitr(up, BOTH_EMPTY);
3447 mdelay(port->rs485.delay_rts_after_send);
3448 if (em485->tx_stopped)
3449 up->rs485_stop_tx(up);
3452 serial_port_out(port, UART_IER, ier);
3455 * The receive handling will happen properly because the
3456 * receive ready bit will still be set; it is not cleared
3457 * on read. However, modem control will not, we must
3458 * call it if we have saved something in the saved flags
3459 * while processing with interrupts off.
3461 if (up->msr_saved_flags)
3462 serial8250_modem_status(up);
3465 spin_unlock_irqrestore(&port->lock, flags);
3468 static unsigned int probe_baud(struct uart_port *port)
3470 unsigned char lcr, dll, dlm;
3473 lcr = serial_port_in(port, UART_LCR);
3474 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3475 dll = serial_port_in(port, UART_DLL);
3476 dlm = serial_port_in(port, UART_DLM);
3477 serial_port_out(port, UART_LCR, lcr);
3479 quot = (dlm << 8) | dll;
3480 return (port->uartclk / 16) / quot;
3483 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3491 if (!port->iobase && !port->membase)
3495 uart_parse_options(options, &baud, &parity, &bits, &flow);
3497 baud = probe_baud(port);
3499 ret = uart_set_options(port, port->cons, baud, parity, bits, flow);
3504 pm_runtime_get_sync(port->dev);
3509 int serial8250_console_exit(struct uart_port *port)
3512 pm_runtime_put_sync(port->dev);
3517 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3519 MODULE_LICENSE("GPL");