1 // SPDX-License-Identifier: GPL-2.0+
3 * Base port operations for 8250/16550-type serial ports
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
8 * A note about mapbase / membase
10 * mapbase is the physical address of the IO port.
11 * membase is an 'ioremapped' cookie.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/ioport.h>
17 #include <linux/init.h>
18 #include <linux/console.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/sysrq.h>
21 #include <linux/delay.h>
22 #include <linux/platform_device.h>
23 #include <linux/tty.h>
24 #include <linux/ratelimit.h>
25 #include <linux/tty_flip.h>
26 #include <linux/serial.h>
27 #include <linux/serial_8250.h>
28 #include <linux/nmi.h>
29 #include <linux/mutex.h>
30 #include <linux/slab.h>
31 #include <linux/uaccess.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/ktime.h>
40 /* Nuvoton NPCM timeout register */
41 #define UART_NPCM_TOR 7
42 #define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */
48 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
50 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
53 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
56 * Here we define the default xmit fifo size used for each type of UART.
58 static const struct serial8250_config uart_config[] = {
83 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
84 .rxtrig_bytes = {1, 4, 8, 14},
85 .flags = UART_CAP_FIFO,
96 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
102 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
104 .rxtrig_bytes = {8, 16, 24, 28},
105 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
111 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
113 .rxtrig_bytes = {1, 16, 32, 56},
114 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
122 .name = "16C950/954",
125 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
126 .rxtrig_bytes = {16, 32, 112, 120},
127 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
128 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
134 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
136 .rxtrig_bytes = {8, 16, 56, 60},
137 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
143 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
144 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
150 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
151 .flags = UART_CAP_FIFO,
157 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
158 .flags = UART_CAP_FIFO | UART_NATSEMI,
164 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
165 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
171 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
172 .flags = UART_CAP_FIFO,
178 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
179 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
185 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
186 .flags = UART_CAP_FIFO | UART_CAP_AFE,
192 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
194 .rxtrig_bytes = {1, 4, 8, 14},
195 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
201 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
202 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
209 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
211 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
218 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
219 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
220 .flags = UART_CAP_FIFO,
222 [PORT_BRCM_TRUMANAGE] = {
226 .flags = UART_CAP_HFIFO,
231 [PORT_ALTR_16550_F32] = {
232 .name = "Altera 16550 FIFO32",
235 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
236 .rxtrig_bytes = {1, 8, 16, 30},
237 .flags = UART_CAP_FIFO | UART_CAP_AFE,
239 [PORT_ALTR_16550_F64] = {
240 .name = "Altera 16550 FIFO64",
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
244 .rxtrig_bytes = {1, 16, 32, 62},
245 .flags = UART_CAP_FIFO | UART_CAP_AFE,
247 [PORT_ALTR_16550_F128] = {
248 .name = "Altera 16550 FIFO128",
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .rxtrig_bytes = {1, 32, 64, 126},
253 .flags = UART_CAP_FIFO | UART_CAP_AFE,
256 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
257 * workaround of errata A-008006 which states that tx_loadsz should
258 * be configured less than Maximum supported fifo bytes.
260 [PORT_16550A_FSL64] = {
261 .name = "16550A_FSL64",
264 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
266 .flags = UART_CAP_FIFO,
269 .name = "Palmchip BK-3103",
272 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
273 .rxtrig_bytes = {1, 4, 8, 14},
274 .flags = UART_CAP_FIFO,
277 .name = "TI DA8xx/66AK2x",
280 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
282 .rxtrig_bytes = {1, 4, 8, 14},
283 .flags = UART_CAP_FIFO | UART_CAP_AFE,
286 .name = "MediaTek BTIF",
289 .fcr = UART_FCR_ENABLE_FIFO |
290 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
291 .flags = UART_CAP_FIFO,
294 .name = "Nuvoton 16550",
297 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
298 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
299 .rxtrig_bytes = {1, 4, 8, 14},
300 .flags = UART_CAP_FIFO,
306 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
307 .rxtrig_bytes = {1, 32, 64, 112},
308 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
310 [PORT_ASPEED_VUART] = {
311 .name = "ASPEED VUART",
314 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
315 .rxtrig_bytes = {1, 4, 8, 14},
316 .flags = UART_CAP_FIFO,
320 /* Uart divisor latch read */
321 static int default_serial_dl_read(struct uart_8250_port *up)
323 /* Assign these in pieces to truncate any bits above 7. */
324 unsigned char dll = serial_in(up, UART_DLL);
325 unsigned char dlm = serial_in(up, UART_DLM);
327 return dll | dlm << 8;
330 /* Uart divisor latch write */
331 static void default_serial_dl_write(struct uart_8250_port *up, int value)
333 serial_out(up, UART_DLL, value & 0xff);
334 serial_out(up, UART_DLM, value >> 8 & 0xff);
337 #ifdef CONFIG_SERIAL_8250_RT288X
339 /* Au1x00/RT288x UART hardware has a weird register layout */
340 static const s8 au_io_in_map[8] = {
348 -1, /* UART_SCR (unmapped) */
351 static const s8 au_io_out_map[8] = {
357 -1, /* UART_LSR (unmapped) */
358 -1, /* UART_MSR (unmapped) */
359 -1, /* UART_SCR (unmapped) */
362 unsigned int au_serial_in(struct uart_port *p, int offset)
364 if (offset >= ARRAY_SIZE(au_io_in_map))
366 offset = au_io_in_map[offset];
369 return __raw_readl(p->membase + (offset << p->regshift));
372 void au_serial_out(struct uart_port *p, int offset, int value)
374 if (offset >= ARRAY_SIZE(au_io_out_map))
376 offset = au_io_out_map[offset];
379 __raw_writel(value, p->membase + (offset << p->regshift));
382 /* Au1x00 haven't got a standard divisor latch */
383 static int au_serial_dl_read(struct uart_8250_port *up)
385 return __raw_readl(up->port.membase + 0x28);
388 static void au_serial_dl_write(struct uart_8250_port *up, int value)
390 __raw_writel(value, up->port.membase + 0x28);
395 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
397 offset = offset << p->regshift;
398 outb(p->hub6 - 1 + offset, p->iobase);
399 return inb(p->iobase + 1);
402 static void hub6_serial_out(struct uart_port *p, int offset, int value)
404 offset = offset << p->regshift;
405 outb(p->hub6 - 1 + offset, p->iobase);
406 outb(value, p->iobase + 1);
409 static unsigned int mem_serial_in(struct uart_port *p, int offset)
411 offset = offset << p->regshift;
412 return readb(p->membase + offset);
415 static void mem_serial_out(struct uart_port *p, int offset, int value)
417 offset = offset << p->regshift;
418 writeb(value, p->membase + offset);
421 static void mem16_serial_out(struct uart_port *p, int offset, int value)
423 offset = offset << p->regshift;
424 writew(value, p->membase + offset);
427 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
429 offset = offset << p->regshift;
430 return readw(p->membase + offset);
433 static void mem32_serial_out(struct uart_port *p, int offset, int value)
435 offset = offset << p->regshift;
436 writel(value, p->membase + offset);
439 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
441 offset = offset << p->regshift;
442 return readl(p->membase + offset);
445 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
447 offset = offset << p->regshift;
448 iowrite32be(value, p->membase + offset);
451 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
453 offset = offset << p->regshift;
454 return ioread32be(p->membase + offset);
457 static unsigned int io_serial_in(struct uart_port *p, int offset)
459 offset = offset << p->regshift;
460 return inb(p->iobase + offset);
463 static void io_serial_out(struct uart_port *p, int offset, int value)
465 offset = offset << p->regshift;
466 outb(value, p->iobase + offset);
469 static int serial8250_default_handle_irq(struct uart_port *port);
471 static void set_io_from_upio(struct uart_port *p)
473 struct uart_8250_port *up = up_to_u8250p(p);
475 up->dl_read = default_serial_dl_read;
476 up->dl_write = default_serial_dl_write;
480 p->serial_in = hub6_serial_in;
481 p->serial_out = hub6_serial_out;
485 p->serial_in = mem_serial_in;
486 p->serial_out = mem_serial_out;
490 p->serial_in = mem16_serial_in;
491 p->serial_out = mem16_serial_out;
495 p->serial_in = mem32_serial_in;
496 p->serial_out = mem32_serial_out;
500 p->serial_in = mem32be_serial_in;
501 p->serial_out = mem32be_serial_out;
504 #ifdef CONFIG_SERIAL_8250_RT288X
506 p->serial_in = au_serial_in;
507 p->serial_out = au_serial_out;
508 up->dl_read = au_serial_dl_read;
509 up->dl_write = au_serial_dl_write;
514 p->serial_in = io_serial_in;
515 p->serial_out = io_serial_out;
518 /* Remember loaded iotype */
519 up->cur_iotype = p->iotype;
520 p->handle_irq = serial8250_default_handle_irq;
524 serial_port_out_sync(struct uart_port *p, int offset, int value)
532 p->serial_out(p, offset, value);
533 p->serial_in(p, UART_LCR); /* safe, no side-effects */
536 p->serial_out(p, offset, value);
543 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
545 serial_out(up, UART_SCR, offset);
546 serial_out(up, UART_ICR, value);
549 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
553 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
554 serial_out(up, UART_SCR, offset);
555 value = serial_in(up, UART_ICR);
556 serial_icr_write(up, UART_ACR, up->acr);
564 static void serial8250_clear_fifos(struct uart_8250_port *p)
566 if (p->capabilities & UART_CAP_FIFO) {
567 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
568 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
569 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
570 serial_out(p, UART_FCR, 0);
574 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
575 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
577 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
579 serial8250_clear_fifos(p);
580 serial_out(p, UART_FCR, p->fcr);
582 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
584 void serial8250_rpm_get(struct uart_8250_port *p)
586 if (!(p->capabilities & UART_CAP_RPM))
588 pm_runtime_get_sync(p->port.dev);
590 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
592 void serial8250_rpm_put(struct uart_8250_port *p)
594 if (!(p->capabilities & UART_CAP_RPM))
596 pm_runtime_mark_last_busy(p->port.dev);
597 pm_runtime_put_autosuspend(p->port.dev);
599 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
602 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
603 * @p: uart_8250_port port instance
605 * The function is used to start rs485 software emulating on the
606 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
607 * transmission. The function is idempotent, so it is safe to call it
610 * The caller MUST enable interrupt on empty shift register before
611 * calling serial8250_em485_init(). This interrupt is not a part of
612 * 8250 standard, but implementation defined.
614 * The function is supposed to be called from .rs485_config callback
615 * or from any other callback protected with p->port.lock spinlock.
617 * See also serial8250_em485_destroy()
619 * Return 0 - success, -errno - otherwise
621 static int serial8250_em485_init(struct uart_8250_port *p)
626 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
630 hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
632 hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
634 p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
635 p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
637 p->em485->active_timer = NULL;
638 p->em485->tx_stopped = true;
646 * serial8250_em485_destroy() - put uart_8250_port into normal state
647 * @p: uart_8250_port port instance
649 * The function is used to stop rs485 software emulating on the
650 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
651 * call it multiple times.
653 * The function is supposed to be called from .rs485_config callback
654 * or from any other callback protected with p->port.lock spinlock.
656 * See also serial8250_em485_init()
658 void serial8250_em485_destroy(struct uart_8250_port *p)
663 hrtimer_cancel(&p->em485->start_tx_timer);
664 hrtimer_cancel(&p->em485->stop_tx_timer);
669 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
672 * serial8250_em485_config() - generic ->rs485_config() callback
674 * @rs485: rs485 settings
676 * Generic callback usable by 8250 uart drivers to activate rs485 settings
677 * if the uart is incapable of driving RTS as a Transmit Enable signal in
678 * hardware, relying on software emulation instead.
680 int serial8250_em485_config(struct uart_port *port, struct serial_rs485 *rs485)
682 struct uart_8250_port *up = up_to_u8250p(port);
684 /* pick sane settings if the user hasn't */
685 if (!!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
686 !!(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
687 rs485->flags |= SER_RS485_RTS_ON_SEND;
688 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
691 /* clamp the delays to [0, 100ms] */
692 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
693 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
695 memset(rs485->padding, 0, sizeof(rs485->padding));
696 port->rs485 = *rs485;
698 gpiod_set_value(port->rs485_term_gpio,
699 rs485->flags & SER_RS485_TERMINATE_BUS);
702 * Both serial8250_em485_init() and serial8250_em485_destroy()
705 if (rs485->flags & SER_RS485_ENABLED) {
706 int ret = serial8250_em485_init(up);
709 rs485->flags &= ~SER_RS485_ENABLED;
710 port->rs485.flags &= ~SER_RS485_ENABLED;
715 serial8250_em485_destroy(up);
718 EXPORT_SYMBOL_GPL(serial8250_em485_config);
721 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
722 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
723 * empty and the HW can idle again.
725 void serial8250_rpm_get_tx(struct uart_8250_port *p)
727 unsigned char rpm_active;
729 if (!(p->capabilities & UART_CAP_RPM))
732 rpm_active = xchg(&p->rpm_tx_active, 1);
735 pm_runtime_get_sync(p->port.dev);
737 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
739 void serial8250_rpm_put_tx(struct uart_8250_port *p)
741 unsigned char rpm_active;
743 if (!(p->capabilities & UART_CAP_RPM))
746 rpm_active = xchg(&p->rpm_tx_active, 0);
749 pm_runtime_mark_last_busy(p->port.dev);
750 pm_runtime_put_autosuspend(p->port.dev);
752 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
755 * IER sleep support. UARTs which have EFRs need the "extended
756 * capability" bit enabled. Note that on XR16C850s, we need to
757 * reset LCR to write to IER.
759 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
761 unsigned char lcr = 0, efr = 0;
763 serial8250_rpm_get(p);
765 if (p->capabilities & UART_CAP_SLEEP) {
766 if (p->capabilities & UART_CAP_EFR) {
767 lcr = serial_in(p, UART_LCR);
768 efr = serial_in(p, UART_EFR);
769 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
770 serial_out(p, UART_EFR, UART_EFR_ECB);
771 serial_out(p, UART_LCR, 0);
773 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
774 if (p->capabilities & UART_CAP_EFR) {
775 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
776 serial_out(p, UART_EFR, efr);
777 serial_out(p, UART_LCR, lcr);
781 serial8250_rpm_put(p);
784 #ifdef CONFIG_SERIAL_8250_RSA
786 * Attempts to turn on the RSA FIFO. Returns zero on failure.
787 * We set the port uart clock rate if we succeed.
789 static int __enable_rsa(struct uart_8250_port *up)
794 mode = serial_in(up, UART_RSA_MSR);
795 result = mode & UART_RSA_MSR_FIFO;
798 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
799 mode = serial_in(up, UART_RSA_MSR);
800 result = mode & UART_RSA_MSR_FIFO;
804 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
809 static void enable_rsa(struct uart_8250_port *up)
811 if (up->port.type == PORT_RSA) {
812 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
813 spin_lock_irq(&up->port.lock);
815 spin_unlock_irq(&up->port.lock);
817 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
818 serial_out(up, UART_RSA_FRR, 0);
823 * Attempts to turn off the RSA FIFO. Returns zero on failure.
824 * It is unknown why interrupts were disabled in here. However,
825 * the caller is expected to preserve this behaviour by grabbing
826 * the spinlock before calling this function.
828 static void disable_rsa(struct uart_8250_port *up)
833 if (up->port.type == PORT_RSA &&
834 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
835 spin_lock_irq(&up->port.lock);
837 mode = serial_in(up, UART_RSA_MSR);
838 result = !(mode & UART_RSA_MSR_FIFO);
841 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
842 mode = serial_in(up, UART_RSA_MSR);
843 result = !(mode & UART_RSA_MSR_FIFO);
847 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
848 spin_unlock_irq(&up->port.lock);
851 #endif /* CONFIG_SERIAL_8250_RSA */
854 * This is a quickie test to see how big the FIFO is.
855 * It doesn't work at all the time, more's the pity.
857 static int size_fifo(struct uart_8250_port *up)
859 unsigned char old_fcr, old_mcr, old_lcr;
860 unsigned short old_dl;
863 old_lcr = serial_in(up, UART_LCR);
864 serial_out(up, UART_LCR, 0);
865 old_fcr = serial_in(up, UART_FCR);
866 old_mcr = serial8250_in_MCR(up);
867 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
868 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
869 serial8250_out_MCR(up, UART_MCR_LOOP);
870 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
871 old_dl = serial_dl_read(up);
872 serial_dl_write(up, 0x0001);
873 serial_out(up, UART_LCR, 0x03);
874 for (count = 0; count < 256; count++)
875 serial_out(up, UART_TX, count);
876 mdelay(20);/* FIXME - schedule_timeout */
877 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
878 (count < 256); count++)
879 serial_in(up, UART_RX);
880 serial_out(up, UART_FCR, old_fcr);
881 serial8250_out_MCR(up, old_mcr);
882 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
883 serial_dl_write(up, old_dl);
884 serial_out(up, UART_LCR, old_lcr);
890 * Read UART ID using the divisor method - set DLL and DLM to zero
891 * and the revision will be in DLL and device type in DLM. We
892 * preserve the device state across this.
894 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
896 unsigned char old_lcr;
897 unsigned int id, old_dl;
899 old_lcr = serial_in(p, UART_LCR);
900 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
901 old_dl = serial_dl_read(p);
902 serial_dl_write(p, 0);
903 id = serial_dl_read(p);
904 serial_dl_write(p, old_dl);
906 serial_out(p, UART_LCR, old_lcr);
912 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
913 * When this function is called we know it is at least a StarTech
914 * 16650 V2, but it might be one of several StarTech UARTs, or one of
915 * its clones. (We treat the broken original StarTech 16650 V1 as a
916 * 16550, and why not? Startech doesn't seem to even acknowledge its
919 * What evil have men's minds wrought...
921 static void autoconfig_has_efr(struct uart_8250_port *up)
923 unsigned int id1, id2, id3, rev;
926 * Everything with an EFR has SLEEP
928 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
931 * First we check to see if it's an Oxford Semiconductor UART.
933 * If we have to do this here because some non-National
934 * Semiconductor clone chips lock up if you try writing to the
935 * LSR register (which serial_icr_read does)
939 * Check for Oxford Semiconductor 16C950.
941 * EFR [4] must be set else this test fails.
943 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
944 * claims that it's needed for 952 dual UART's (which are not
945 * recommended for new designs).
948 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
949 serial_out(up, UART_EFR, UART_EFR_ECB);
950 serial_out(up, UART_LCR, 0x00);
951 id1 = serial_icr_read(up, UART_ID1);
952 id2 = serial_icr_read(up, UART_ID2);
953 id3 = serial_icr_read(up, UART_ID3);
954 rev = serial_icr_read(up, UART_REV);
956 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
958 if (id1 == 0x16 && id2 == 0xC9 &&
959 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
960 up->port.type = PORT_16C950;
963 * Enable work around for the Oxford Semiconductor 952 rev B
964 * chip which causes it to seriously miscalculate baud rates
967 if (id3 == 0x52 && rev == 0x01)
968 up->bugs |= UART_BUG_QUOT;
973 * We check for a XR16C850 by setting DLL and DLM to 0, and then
974 * reading back DLL and DLM. The chip type depends on the DLM
976 * 0x10 - XR16C850 and the DLL contains the chip revision.
980 id1 = autoconfig_read_divisor_id(up);
981 DEBUG_AUTOCONF("850id=%04x ", id1);
984 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
985 up->port.type = PORT_16850;
990 * It wasn't an XR16C850.
992 * We distinguish between the '654 and the '650 by counting
993 * how many bytes are in the FIFO. I'm using this for now,
994 * since that's the technique that was sent to me in the
995 * serial driver update, but I'm not convinced this works.
996 * I've had problems doing this in the past. -TYT
998 if (size_fifo(up) == 64)
999 up->port.type = PORT_16654;
1001 up->port.type = PORT_16650V2;
1005 * We detected a chip without a FIFO. Only two fall into
1006 * this category - the original 8250 and the 16450. The
1007 * 16450 has a scratch register (accessible with LCR=0)
1009 static void autoconfig_8250(struct uart_8250_port *up)
1011 unsigned char scratch, status1, status2;
1013 up->port.type = PORT_8250;
1015 scratch = serial_in(up, UART_SCR);
1016 serial_out(up, UART_SCR, 0xa5);
1017 status1 = serial_in(up, UART_SCR);
1018 serial_out(up, UART_SCR, 0x5a);
1019 status2 = serial_in(up, UART_SCR);
1020 serial_out(up, UART_SCR, scratch);
1022 if (status1 == 0xa5 && status2 == 0x5a)
1023 up->port.type = PORT_16450;
1026 static int broken_efr(struct uart_8250_port *up)
1029 * Exar ST16C2550 "A2" devices incorrectly detect as
1030 * having an EFR, and report an ID of 0x0201. See
1031 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1033 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
1040 * We know that the chip has FIFOs. Does it have an EFR? The
1041 * EFR is located in the same register position as the IIR and
1042 * we know the top two bits of the IIR are currently set. The
1043 * EFR should contain zero. Try to read the EFR.
1045 static void autoconfig_16550a(struct uart_8250_port *up)
1047 unsigned char status1, status2;
1048 unsigned int iersave;
1050 up->port.type = PORT_16550A;
1051 up->capabilities |= UART_CAP_FIFO;
1053 if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS))
1057 * Check for presence of the EFR when DLAB is set.
1058 * Only ST16C650V1 UARTs pass this test.
1060 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1061 if (serial_in(up, UART_EFR) == 0) {
1062 serial_out(up, UART_EFR, 0xA8);
1063 if (serial_in(up, UART_EFR) != 0) {
1064 DEBUG_AUTOCONF("EFRv1 ");
1065 up->port.type = PORT_16650;
1066 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1068 serial_out(up, UART_LCR, 0);
1069 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1071 status1 = serial_in(up, UART_IIR) >> 5;
1072 serial_out(up, UART_FCR, 0);
1073 serial_out(up, UART_LCR, 0);
1076 up->port.type = PORT_16550A_FSL64;
1078 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1080 serial_out(up, UART_EFR, 0);
1085 * Maybe it requires 0xbf to be written to the LCR.
1086 * (other ST16C650V2 UARTs, TI16C752A, etc)
1088 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1089 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1090 DEBUG_AUTOCONF("EFRv2 ");
1091 autoconfig_has_efr(up);
1096 * Check for a National Semiconductor SuperIO chip.
1097 * Attempt to switch to bank 2, read the value of the LOOP bit
1098 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1099 * switch back to bank 2, read it from EXCR1 again and check
1100 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1102 serial_out(up, UART_LCR, 0);
1103 status1 = serial8250_in_MCR(up);
1104 serial_out(up, UART_LCR, 0xE0);
1105 status2 = serial_in(up, 0x02); /* EXCR1 */
1107 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1108 serial_out(up, UART_LCR, 0);
1109 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1110 serial_out(up, UART_LCR, 0xE0);
1111 status2 = serial_in(up, 0x02); /* EXCR1 */
1112 serial_out(up, UART_LCR, 0);
1113 serial8250_out_MCR(up, status1);
1115 if ((status2 ^ status1) & UART_MCR_LOOP) {
1116 unsigned short quot;
1118 serial_out(up, UART_LCR, 0xE0);
1120 quot = serial_dl_read(up);
1123 if (ns16550a_goto_highspeed(up))
1124 serial_dl_write(up, quot);
1126 serial_out(up, UART_LCR, 0);
1128 up->port.uartclk = 921600*16;
1129 up->port.type = PORT_NS16550A;
1130 up->capabilities |= UART_NATSEMI;
1136 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1137 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1138 * Try setting it with and without DLAB set. Cheap clones
1139 * set bit 5 without DLAB set.
1141 serial_out(up, UART_LCR, 0);
1142 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1143 status1 = serial_in(up, UART_IIR) >> 5;
1144 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1145 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1146 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1147 status2 = serial_in(up, UART_IIR) >> 5;
1148 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1149 serial_out(up, UART_LCR, 0);
1151 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1153 if (status1 == 6 && status2 == 7) {
1154 up->port.type = PORT_16750;
1155 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1160 * Try writing and reading the UART_IER_UUE bit (b6).
1161 * If it works, this is probably one of the Xscale platform's
1163 * We're going to explicitly set the UUE bit to 0 before
1164 * trying to write and read a 1 just to make sure it's not
1165 * already a 1 and maybe locked there before we even start start.
1167 iersave = serial_in(up, UART_IER);
1168 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1169 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1171 * OK it's in a known zero state, try writing and reading
1172 * without disturbing the current state of the other bits.
1174 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1175 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1178 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1180 DEBUG_AUTOCONF("Xscale ");
1181 up->port.type = PORT_XSCALE;
1182 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1187 * If we got here we couldn't force the IER_UUE bit to 0.
1188 * Log it and continue.
1190 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1192 serial_out(up, UART_IER, iersave);
1195 * We distinguish between 16550A and U6 16550A by counting
1196 * how many bytes are in the FIFO.
1198 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1199 up->port.type = PORT_U6_16550A;
1200 up->capabilities |= UART_CAP_AFE;
1205 * This routine is called by rs_init() to initialize a specific serial
1206 * port. It determines what type of UART chip this serial port is
1207 * using: 8250, 16450, 16550, 16550A. The important question is
1208 * whether or not this UART is a 16550A or not, since this will
1209 * determine whether or not we can use its FIFO features or not.
1211 static void autoconfig(struct uart_8250_port *up)
1213 unsigned char status1, scratch, scratch2, scratch3;
1214 unsigned char save_lcr, save_mcr;
1215 struct uart_port *port = &up->port;
1216 unsigned long flags;
1217 unsigned int old_capabilities;
1219 if (!port->iobase && !port->mapbase && !port->membase)
1222 DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1223 port->name, port->iobase, port->membase);
1226 * We really do need global IRQs disabled here - we're going to
1227 * be frobbing the chips IRQ enable register to see if it exists.
1229 spin_lock_irqsave(&port->lock, flags);
1231 up->capabilities = 0;
1234 if (!(port->flags & UPF_BUGGY_UART)) {
1236 * Do a simple existence test first; if we fail this,
1237 * there's no point trying anything else.
1239 * 0x80 is used as a nonsense port to prevent against
1240 * false positives due to ISA bus float. The
1241 * assumption is that 0x80 is a non-existent port;
1242 * which should be safe since include/asm/io.h also
1243 * makes this assumption.
1245 * Note: this is safe as long as MCR bit 4 is clear
1246 * and the device is in "PC" mode.
1248 scratch = serial_in(up, UART_IER);
1249 serial_out(up, UART_IER, 0);
1254 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1255 * 16C754B) allow only to modify them if an EFR bit is set.
1257 scratch2 = serial_in(up, UART_IER) & 0x0f;
1258 serial_out(up, UART_IER, 0x0F);
1262 scratch3 = serial_in(up, UART_IER) & 0x0f;
1263 serial_out(up, UART_IER, scratch);
1264 if (scratch2 != 0 || scratch3 != 0x0F) {
1266 * We failed; there's nothing here
1268 spin_unlock_irqrestore(&port->lock, flags);
1269 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1270 scratch2, scratch3);
1275 save_mcr = serial8250_in_MCR(up);
1276 save_lcr = serial_in(up, UART_LCR);
1279 * Check to see if a UART is really there. Certain broken
1280 * internal modems based on the Rockwell chipset fail this
1281 * test, because they apparently don't implement the loopback
1282 * test mode. So this test is skipped on the COM 1 through
1283 * COM 4 ports. This *should* be safe, since no board
1284 * manufacturer would be stupid enough to design a board
1285 * that conflicts with COM 1-4 --- we hope!
1287 if (!(port->flags & UPF_SKIP_TEST)) {
1288 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1289 status1 = serial_in(up, UART_MSR) & 0xF0;
1290 serial8250_out_MCR(up, save_mcr);
1291 if (status1 != 0x90) {
1292 spin_unlock_irqrestore(&port->lock, flags);
1293 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1300 * We're pretty sure there's a port here. Lets find out what
1301 * type of port it is. The IIR top two bits allows us to find
1302 * out if it's 8250 or 16450, 16550, 16550A or later. This
1303 * determines what we test for next.
1305 * We also initialise the EFR (if any) to zero for later. The
1306 * EFR occupies the same register location as the FCR and IIR.
1308 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1309 serial_out(up, UART_EFR, 0);
1310 serial_out(up, UART_LCR, 0);
1312 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1314 /* Assign this as it is to truncate any bits above 7. */
1315 scratch = serial_in(up, UART_IIR);
1317 switch (scratch >> 6) {
1319 autoconfig_8250(up);
1322 port->type = PORT_UNKNOWN;
1325 port->type = PORT_16550;
1328 autoconfig_16550a(up);
1332 #ifdef CONFIG_SERIAL_8250_RSA
1334 * Only probe for RSA ports if we got the region.
1336 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1338 port->type = PORT_RSA;
1341 serial_out(up, UART_LCR, save_lcr);
1343 port->fifosize = uart_config[up->port.type].fifo_size;
1344 old_capabilities = up->capabilities;
1345 up->capabilities = uart_config[port->type].flags;
1346 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1348 if (port->type == PORT_UNKNOWN)
1354 #ifdef CONFIG_SERIAL_8250_RSA
1355 if (port->type == PORT_RSA)
1356 serial_out(up, UART_RSA_FRR, 0);
1358 serial8250_out_MCR(up, save_mcr);
1359 serial8250_clear_fifos(up);
1360 serial_in(up, UART_RX);
1361 if (up->capabilities & UART_CAP_UUE)
1362 serial_out(up, UART_IER, UART_IER_UUE);
1364 serial_out(up, UART_IER, 0);
1367 spin_unlock_irqrestore(&port->lock, flags);
1370 * Check if the device is a Fintek F81216A
1372 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1373 fintek_8250_probe(up);
1375 if (up->capabilities != old_capabilities) {
1376 dev_warn(port->dev, "detected caps %08x should be %08x\n",
1377 old_capabilities, up->capabilities);
1380 DEBUG_AUTOCONF("iir=%d ", scratch);
1381 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1384 static void autoconfig_irq(struct uart_8250_port *up)
1386 struct uart_port *port = &up->port;
1387 unsigned char save_mcr, save_ier;
1388 unsigned char save_ICP = 0;
1389 unsigned int ICP = 0;
1393 if (port->flags & UPF_FOURPORT) {
1394 ICP = (port->iobase & 0xfe0) | 0x1f;
1395 save_ICP = inb_p(ICP);
1400 if (uart_console(port))
1403 /* forget possible initially masked and pending IRQ */
1404 probe_irq_off(probe_irq_on());
1405 save_mcr = serial8250_in_MCR(up);
1406 save_ier = serial_in(up, UART_IER);
1407 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1409 irqs = probe_irq_on();
1410 serial8250_out_MCR(up, 0);
1412 if (port->flags & UPF_FOURPORT) {
1413 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1415 serial8250_out_MCR(up,
1416 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1418 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1419 serial_in(up, UART_LSR);
1420 serial_in(up, UART_RX);
1421 serial_in(up, UART_IIR);
1422 serial_in(up, UART_MSR);
1423 serial_out(up, UART_TX, 0xFF);
1425 irq = probe_irq_off(irqs);
1427 serial8250_out_MCR(up, save_mcr);
1428 serial_out(up, UART_IER, save_ier);
1430 if (port->flags & UPF_FOURPORT)
1431 outb_p(save_ICP, ICP);
1433 if (uart_console(port))
1436 port->irq = (irq > 0) ? irq : 0;
1439 static void serial8250_stop_rx(struct uart_port *port)
1441 struct uart_8250_port *up = up_to_u8250p(port);
1443 serial8250_rpm_get(up);
1445 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1446 up->port.read_status_mask &= ~UART_LSR_DR;
1447 serial_port_out(port, UART_IER, up->ier);
1449 serial8250_rpm_put(up);
1453 * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback
1454 * @p: uart 8250 port
1456 * Generic callback usable by 8250 uart drivers to stop rs485 transmission.
1458 void serial8250_em485_stop_tx(struct uart_8250_port *p)
1460 unsigned char mcr = serial8250_in_MCR(p);
1462 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
1463 mcr |= UART_MCR_RTS;
1465 mcr &= ~UART_MCR_RTS;
1466 serial8250_out_MCR(p, mcr);
1469 * Empty the RX FIFO, we are not interested in anything
1470 * received during the half-duplex transmission.
1471 * Enable previously disabled RX interrupts.
1473 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1474 serial8250_clear_and_reinit_fifos(p);
1476 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1477 serial_port_out(&p->port, UART_IER, p->ier);
1480 EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx);
1482 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1484 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1486 struct uart_8250_port *p = em485->port;
1487 unsigned long flags;
1489 serial8250_rpm_get(p);
1490 spin_lock_irqsave(&p->port.lock, flags);
1491 if (em485->active_timer == &em485->stop_tx_timer) {
1492 p->rs485_stop_tx(p);
1493 em485->active_timer = NULL;
1494 em485->tx_stopped = true;
1496 spin_unlock_irqrestore(&p->port.lock, flags);
1497 serial8250_rpm_put(p);
1499 return HRTIMER_NORESTART;
1502 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1504 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
1507 static void __stop_tx_rs485(struct uart_8250_port *p)
1509 struct uart_8250_em485 *em485 = p->em485;
1512 * rs485_stop_tx() is going to set RTS according to config
1513 * AND flush RX FIFO if required.
1515 if (p->port.rs485.delay_rts_after_send > 0) {
1516 em485->active_timer = &em485->stop_tx_timer;
1517 start_hrtimer_ms(&em485->stop_tx_timer,
1518 p->port.rs485.delay_rts_after_send);
1520 p->rs485_stop_tx(p);
1521 em485->active_timer = NULL;
1522 em485->tx_stopped = true;
1526 static inline void __do_stop_tx(struct uart_8250_port *p)
1528 if (serial8250_clear_THRI(p))
1529 serial8250_rpm_put_tx(p);
1532 static inline void __stop_tx(struct uart_8250_port *p)
1534 struct uart_8250_em485 *em485 = p->em485;
1537 unsigned char lsr = serial_in(p, UART_LSR);
1539 * To provide required timeing and allow FIFO transfer,
1540 * __stop_tx_rs485() must be called only when both FIFO and
1541 * shift register are empty. It is for device driver to enable
1542 * interrupt on TEMT.
1544 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1552 static void serial8250_stop_tx(struct uart_port *port)
1554 struct uart_8250_port *up = up_to_u8250p(port);
1556 serial8250_rpm_get(up);
1560 * We really want to stop the transmitter from sending.
1562 if (port->type == PORT_16C950) {
1563 up->acr |= UART_ACR_TXDIS;
1564 serial_icr_write(up, UART_ACR, up->acr);
1566 serial8250_rpm_put(up);
1569 static inline void __start_tx(struct uart_port *port)
1571 struct uart_8250_port *up = up_to_u8250p(port);
1573 if (up->dma && !up->dma->tx_dma(up))
1576 if (serial8250_set_THRI(up)) {
1577 if (up->bugs & UART_BUG_TXEN) {
1580 lsr = serial_in(up, UART_LSR);
1581 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1582 if (lsr & UART_LSR_THRE)
1583 serial8250_tx_chars(up);
1588 * Re-enable the transmitter if we disabled it.
1590 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1591 up->acr &= ~UART_ACR_TXDIS;
1592 serial_icr_write(up, UART_ACR, up->acr);
1597 * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback
1598 * @up: uart 8250 port
1600 * Generic callback usable by 8250 uart drivers to start rs485 transmission.
1601 * Assumes that setting the RTS bit in the MCR register means RTS is high.
1602 * (Some chips use inverse semantics.) Further assumes that reception is
1603 * stoppable by disabling the UART_IER_RDI interrupt. (Some chips set the
1604 * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.)
1606 void serial8250_em485_start_tx(struct uart_8250_port *up)
1608 unsigned char mcr = serial8250_in_MCR(up);
1610 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1611 serial8250_stop_rx(&up->port);
1613 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1614 mcr |= UART_MCR_RTS;
1616 mcr &= ~UART_MCR_RTS;
1617 serial8250_out_MCR(up, mcr);
1619 EXPORT_SYMBOL_GPL(serial8250_em485_start_tx);
1621 static inline void start_tx_rs485(struct uart_port *port)
1623 struct uart_8250_port *up = up_to_u8250p(port);
1624 struct uart_8250_em485 *em485 = up->em485;
1627 * While serial8250_em485_handle_stop_tx() is a noop if
1628 * em485->active_timer != &em485->stop_tx_timer, it might happen that
1629 * the timer is still armed and triggers only after the current bunch of
1630 * chars is send and em485->active_timer == &em485->stop_tx_timer again.
1631 * So cancel the timer. There is still a theoretical race condition if
1632 * the timer is already running and only comes around to check for
1633 * em485->active_timer when &em485->stop_tx_timer is armed again.
1635 if (em485->active_timer == &em485->stop_tx_timer)
1636 hrtimer_try_to_cancel(&em485->stop_tx_timer);
1638 em485->active_timer = NULL;
1640 if (em485->tx_stopped) {
1641 em485->tx_stopped = false;
1643 up->rs485_start_tx(up);
1645 if (up->port.rs485.delay_rts_before_send > 0) {
1646 em485->active_timer = &em485->start_tx_timer;
1647 start_hrtimer_ms(&em485->start_tx_timer,
1648 up->port.rs485.delay_rts_before_send);
1656 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1658 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1660 struct uart_8250_port *p = em485->port;
1661 unsigned long flags;
1663 spin_lock_irqsave(&p->port.lock, flags);
1664 if (em485->active_timer == &em485->start_tx_timer) {
1665 __start_tx(&p->port);
1666 em485->active_timer = NULL;
1668 spin_unlock_irqrestore(&p->port.lock, flags);
1670 return HRTIMER_NORESTART;
1673 static void serial8250_start_tx(struct uart_port *port)
1675 struct uart_8250_port *up = up_to_u8250p(port);
1676 struct uart_8250_em485 *em485 = up->em485;
1678 serial8250_rpm_get_tx(up);
1680 if (!port->x_char && uart_circ_empty(&port->state->xmit))
1684 em485->active_timer == &em485->start_tx_timer)
1688 start_tx_rs485(port);
1693 static void serial8250_throttle(struct uart_port *port)
1695 port->throttle(port);
1698 static void serial8250_unthrottle(struct uart_port *port)
1700 port->unthrottle(port);
1703 static void serial8250_disable_ms(struct uart_port *port)
1705 struct uart_8250_port *up = up_to_u8250p(port);
1707 /* no MSR capabilities */
1708 if (up->bugs & UART_BUG_NOMSR)
1711 mctrl_gpio_disable_ms(up->gpios);
1713 up->ier &= ~UART_IER_MSI;
1714 serial_port_out(port, UART_IER, up->ier);
1717 static void serial8250_enable_ms(struct uart_port *port)
1719 struct uart_8250_port *up = up_to_u8250p(port);
1721 /* no MSR capabilities */
1722 if (up->bugs & UART_BUG_NOMSR)
1725 mctrl_gpio_enable_ms(up->gpios);
1727 up->ier |= UART_IER_MSI;
1729 serial8250_rpm_get(up);
1730 serial_port_out(port, UART_IER, up->ier);
1731 serial8250_rpm_put(up);
1734 void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1736 struct uart_port *port = &up->port;
1738 char flag = TTY_NORMAL;
1740 if (likely(lsr & UART_LSR_DR))
1741 ch = serial_in(up, UART_RX);
1744 * Intel 82571 has a Serial Over Lan device that will
1745 * set UART_LSR_BI without setting UART_LSR_DR when
1746 * it receives a break. To avoid reading from the
1747 * receive buffer without UART_LSR_DR bit set, we
1748 * just force the read character to be 0
1754 lsr |= up->lsr_saved_flags;
1755 up->lsr_saved_flags = 0;
1757 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1758 if (lsr & UART_LSR_BI) {
1759 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1762 * We do the SysRQ and SAK checking
1763 * here because otherwise the break
1764 * may get masked by ignore_status_mask
1765 * or read_status_mask.
1767 if (uart_handle_break(port))
1769 } else if (lsr & UART_LSR_PE)
1770 port->icount.parity++;
1771 else if (lsr & UART_LSR_FE)
1772 port->icount.frame++;
1773 if (lsr & UART_LSR_OE)
1774 port->icount.overrun++;
1777 * Mask off conditions which should be ignored.
1779 lsr &= port->read_status_mask;
1781 if (lsr & UART_LSR_BI) {
1782 dev_dbg(port->dev, "handling break\n");
1784 } else if (lsr & UART_LSR_PE)
1786 else if (lsr & UART_LSR_FE)
1789 if (uart_prepare_sysrq_char(port, ch))
1792 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1794 EXPORT_SYMBOL_GPL(serial8250_read_char);
1797 * serial8250_rx_chars: processes according to the passed in LSR
1798 * value, and returns the remaining LSR bits not handled
1799 * by this Rx routine.
1801 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1803 struct uart_port *port = &up->port;
1804 int max_count = 256;
1807 serial8250_read_char(up, lsr);
1808 if (--max_count == 0)
1810 lsr = serial_in(up, UART_LSR);
1811 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1813 tty_flip_buffer_push(&port->state->port);
1816 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1818 void serial8250_tx_chars(struct uart_8250_port *up)
1820 struct uart_port *port = &up->port;
1821 struct circ_buf *xmit = &port->state->xmit;
1825 uart_xchar_out(port, UART_TX);
1828 if (uart_tx_stopped(port)) {
1829 serial8250_stop_tx(port);
1832 if (uart_circ_empty(xmit)) {
1837 count = up->tx_loadsz;
1839 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1840 if (up->bugs & UART_BUG_TXRACE) {
1842 * The Aspeed BMC virtual UARTs have a bug where data
1843 * may get stuck in the BMC's Tx FIFO from bursts of
1844 * writes on the APB interface.
1846 * Delay back-to-back writes by a read cycle to avoid
1847 * stalling the VUART. Read a register that won't have
1848 * side-effects and discard the result.
1850 serial_in(up, UART_SCR);
1852 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1854 if (uart_circ_empty(xmit))
1856 if ((up->capabilities & UART_CAP_HFIFO) &&
1857 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1859 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1860 if ((up->capabilities & UART_CAP_MINI) &&
1861 !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1863 } while (--count > 0);
1865 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1866 uart_write_wakeup(port);
1869 * With RPM enabled, we have to wait until the FIFO is empty before the
1870 * HW can go idle. So we get here once again with empty FIFO and disable
1871 * the interrupt and RPM in __stop_tx()
1873 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1876 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1878 /* Caller holds uart port lock */
1879 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1881 struct uart_port *port = &up->port;
1882 unsigned int status = serial_in(up, UART_MSR);
1884 status |= up->msr_saved_flags;
1885 up->msr_saved_flags = 0;
1886 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1887 port->state != NULL) {
1888 if (status & UART_MSR_TERI)
1890 if (status & UART_MSR_DDSR)
1892 if (status & UART_MSR_DDCD)
1893 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1894 if (status & UART_MSR_DCTS)
1895 uart_handle_cts_change(port, status & UART_MSR_CTS);
1897 wake_up_interruptible(&port->state->port.delta_msr_wait);
1902 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1904 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1906 switch (iir & 0x3f) {
1907 case UART_IIR_RX_TIMEOUT:
1908 serial8250_rx_dma_flush(up);
1913 return up->dma->rx_dma(up);
1917 * This handles the interrupt from one port.
1919 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1921 unsigned char status;
1922 struct uart_8250_port *up = up_to_u8250p(port);
1923 bool skip_rx = false;
1924 unsigned long flags;
1926 if (iir & UART_IIR_NO_INT)
1929 spin_lock_irqsave(&port->lock, flags);
1931 status = serial_port_in(port, UART_LSR);
1934 * If port is stopped and there are no error conditions in the
1935 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1936 * overflow. Not servicing, RX FIFO would trigger auto HW flow
1937 * control when FIFO occupancy reaches preset threshold, thus
1938 * halting RX. This only works when auto HW flow control is
1941 if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1942 (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1943 !(port->read_status_mask & UART_LSR_DR))
1946 if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1947 if (!up->dma || handle_rx_dma(up, iir))
1948 status = serial8250_rx_chars(up, status);
1950 serial8250_modem_status(up);
1951 if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE) &&
1952 (up->ier & UART_IER_THRI))
1953 serial8250_tx_chars(up);
1955 uart_unlock_and_check_sysrq_irqrestore(port, flags);
1959 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1961 static int serial8250_default_handle_irq(struct uart_port *port)
1963 struct uart_8250_port *up = up_to_u8250p(port);
1967 serial8250_rpm_get(up);
1969 iir = serial_port_in(port, UART_IIR);
1970 ret = serial8250_handle_irq(port, iir);
1972 serial8250_rpm_put(up);
1977 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1978 * have a programmable TX threshold that triggers the THRE interrupt in
1979 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1980 * has space available. Load it up with tx_loadsz bytes.
1982 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1984 unsigned long flags;
1985 unsigned int iir = serial_port_in(port, UART_IIR);
1987 /* TX Threshold IRQ triggered so load up FIFO */
1988 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1989 struct uart_8250_port *up = up_to_u8250p(port);
1991 spin_lock_irqsave(&port->lock, flags);
1992 serial8250_tx_chars(up);
1993 spin_unlock_irqrestore(&port->lock, flags);
1996 iir = serial_port_in(port, UART_IIR);
1997 return serial8250_handle_irq(port, iir);
2000 static unsigned int serial8250_tx_empty(struct uart_port *port)
2002 struct uart_8250_port *up = up_to_u8250p(port);
2003 unsigned long flags;
2006 serial8250_rpm_get(up);
2008 spin_lock_irqsave(&port->lock, flags);
2009 lsr = serial_port_in(port, UART_LSR);
2010 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
2011 spin_unlock_irqrestore(&port->lock, flags);
2013 serial8250_rpm_put(up);
2015 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
2018 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
2020 struct uart_8250_port *up = up_to_u8250p(port);
2021 unsigned int status;
2024 serial8250_rpm_get(up);
2025 status = serial8250_modem_status(up);
2026 serial8250_rpm_put(up);
2028 val = serial8250_MSR_to_TIOCM(status);
2030 return mctrl_gpio_get(up->gpios, &val);
2034 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
2036 static unsigned int serial8250_get_mctrl(struct uart_port *port)
2038 if (port->get_mctrl)
2039 return port->get_mctrl(port);
2040 return serial8250_do_get_mctrl(port);
2043 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
2045 struct uart_8250_port *up = up_to_u8250p(port);
2048 mcr = serial8250_TIOCM_to_MCR(mctrl);
2052 serial8250_out_MCR(up, mcr);
2054 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2056 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2058 if (port->set_mctrl)
2059 port->set_mctrl(port, mctrl);
2061 serial8250_do_set_mctrl(port, mctrl);
2064 static void serial8250_break_ctl(struct uart_port *port, int break_state)
2066 struct uart_8250_port *up = up_to_u8250p(port);
2067 unsigned long flags;
2069 serial8250_rpm_get(up);
2070 spin_lock_irqsave(&port->lock, flags);
2071 if (break_state == -1)
2072 up->lcr |= UART_LCR_SBC;
2074 up->lcr &= ~UART_LCR_SBC;
2075 serial_port_out(port, UART_LCR, up->lcr);
2076 spin_unlock_irqrestore(&port->lock, flags);
2077 serial8250_rpm_put(up);
2081 * Wait for transmitter & holding register to empty
2083 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2085 unsigned int status, tmout = 10000;
2087 /* Wait up to 10ms for the character(s) to be sent. */
2089 status = serial_in(up, UART_LSR);
2091 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2093 if ((status & bits) == bits)
2098 touch_nmi_watchdog();
2101 /* Wait up to 1s for flow control if necessary */
2102 if (up->port.flags & UPF_CONS_FLOW) {
2103 for (tmout = 1000000; tmout; tmout--) {
2104 unsigned int msr = serial_in(up, UART_MSR);
2105 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2106 if (msr & UART_MSR_CTS)
2109 touch_nmi_watchdog();
2114 #ifdef CONFIG_CONSOLE_POLL
2116 * Console polling routines for writing and reading from the uart while
2117 * in an interrupt or debug context.
2120 static int serial8250_get_poll_char(struct uart_port *port)
2122 struct uart_8250_port *up = up_to_u8250p(port);
2126 serial8250_rpm_get(up);
2128 lsr = serial_port_in(port, UART_LSR);
2130 if (!(lsr & UART_LSR_DR)) {
2131 status = NO_POLL_CHAR;
2135 status = serial_port_in(port, UART_RX);
2137 serial8250_rpm_put(up);
2142 static void serial8250_put_poll_char(struct uart_port *port,
2146 struct uart_8250_port *up = up_to_u8250p(port);
2148 serial8250_rpm_get(up);
2150 * First save the IER then disable the interrupts
2152 ier = serial_port_in(port, UART_IER);
2153 if (up->capabilities & UART_CAP_UUE)
2154 serial_port_out(port, UART_IER, UART_IER_UUE);
2156 serial_port_out(port, UART_IER, 0);
2158 wait_for_xmitr(up, BOTH_EMPTY);
2160 * Send the character out.
2162 serial_port_out(port, UART_TX, c);
2165 * Finally, wait for transmitter to become empty
2166 * and restore the IER
2168 wait_for_xmitr(up, BOTH_EMPTY);
2169 serial_port_out(port, UART_IER, ier);
2170 serial8250_rpm_put(up);
2173 #endif /* CONFIG_CONSOLE_POLL */
2175 int serial8250_do_startup(struct uart_port *port)
2177 struct uart_8250_port *up = up_to_u8250p(port);
2178 unsigned long flags;
2179 unsigned char lsr, iir;
2182 if (!port->fifosize)
2183 port->fifosize = uart_config[port->type].fifo_size;
2185 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2186 if (!up->capabilities)
2187 up->capabilities = uart_config[port->type].flags;
2190 if (port->iotype != up->cur_iotype)
2191 set_io_from_upio(port);
2193 serial8250_rpm_get(up);
2194 if (port->type == PORT_16C950) {
2195 /* Wake up and initialize UART */
2197 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2198 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2199 serial_port_out(port, UART_IER, 0);
2200 serial_port_out(port, UART_LCR, 0);
2201 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2202 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2203 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2204 serial_port_out(port, UART_LCR, 0);
2207 if (port->type == PORT_DA830) {
2208 /* Reset the port */
2209 serial_port_out(port, UART_IER, 0);
2210 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2213 /* Enable Tx, Rx and free run mode */
2214 serial_port_out(port, UART_DA830_PWREMU_MGMT,
2215 UART_DA830_PWREMU_MGMT_UTRST |
2216 UART_DA830_PWREMU_MGMT_URRST |
2217 UART_DA830_PWREMU_MGMT_FREE);
2220 if (port->type == PORT_NPCM) {
2222 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2223 * register). Enable it, and set TIOC (timeout interrupt
2224 * comparator) to be 0x20 for correct operation.
2226 serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2229 #ifdef CONFIG_SERIAL_8250_RSA
2231 * If this is an RSA port, see if we can kick it up to the
2232 * higher speed clock.
2238 * Clear the FIFO buffers and disable them.
2239 * (they will be reenabled in set_termios())
2241 serial8250_clear_fifos(up);
2244 * Clear the interrupt registers.
2246 serial_port_in(port, UART_LSR);
2247 serial_port_in(port, UART_RX);
2248 serial_port_in(port, UART_IIR);
2249 serial_port_in(port, UART_MSR);
2252 * At this point, there's no way the LSR could still be 0xff;
2253 * if it is, then bail out, because there's likely no UART
2256 if (!(port->flags & UPF_BUGGY_UART) &&
2257 (serial_port_in(port, UART_LSR) == 0xff)) {
2258 dev_info_ratelimited(port->dev, "LSR safety check engaged!\n");
2264 * For a XR16C850, we need to set the trigger levels
2266 if (port->type == PORT_16850) {
2269 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2271 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2272 serial_port_out(port, UART_FCTR,
2273 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2274 serial_port_out(port, UART_TRG, UART_TRG_96);
2275 serial_port_out(port, UART_FCTR,
2276 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2277 serial_port_out(port, UART_TRG, UART_TRG_96);
2279 serial_port_out(port, UART_LCR, 0);
2283 * For the Altera 16550 variants, set TX threshold trigger level.
2285 if (((port->type == PORT_ALTR_16550_F32) ||
2286 (port->type == PORT_ALTR_16550_F64) ||
2287 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2288 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2289 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2290 dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2292 serial_port_out(port, UART_ALTR_AFR,
2293 UART_ALTR_EN_TXFIFO_LW);
2294 serial_port_out(port, UART_ALTR_TX_LOW,
2295 port->fifosize - up->tx_loadsz);
2296 port->handle_irq = serial8250_tx_threshold_handle_irq;
2300 /* Check if we need to have shared IRQs */
2301 if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2302 up->port.irqflags |= IRQF_SHARED;
2304 if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2307 if (port->irqflags & IRQF_SHARED)
2308 disable_irq_nosync(port->irq);
2311 * Test for UARTs that do not reassert THRE when the
2312 * transmitter is idle and the interrupt has already
2313 * been cleared. Real 16550s should always reassert
2314 * this interrupt whenever the transmitter is idle and
2315 * the interrupt is enabled. Delays are necessary to
2316 * allow register changes to become visible.
2318 spin_lock_irqsave(&port->lock, flags);
2320 wait_for_xmitr(up, UART_LSR_THRE);
2321 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2322 udelay(1); /* allow THRE to set */
2323 iir1 = serial_port_in(port, UART_IIR);
2324 serial_port_out(port, UART_IER, 0);
2325 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2326 udelay(1); /* allow a working UART time to re-assert THRE */
2327 iir = serial_port_in(port, UART_IIR);
2328 serial_port_out(port, UART_IER, 0);
2330 spin_unlock_irqrestore(&port->lock, flags);
2332 if (port->irqflags & IRQF_SHARED)
2333 enable_irq(port->irq);
2336 * If the interrupt is not reasserted, or we otherwise
2337 * don't trust the iir, setup a timer to kick the UART
2338 * on a regular basis.
2340 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2341 up->port.flags & UPF_BUG_THRE) {
2342 up->bugs |= UART_BUG_THRE;
2346 retval = up->ops->setup_irq(up);
2351 * Now, initialize the UART
2353 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2355 spin_lock_irqsave(&port->lock, flags);
2356 if (up->port.flags & UPF_FOURPORT) {
2358 up->port.mctrl |= TIOCM_OUT1;
2361 * Most PC uarts need OUT2 raised to enable interrupts.
2364 up->port.mctrl |= TIOCM_OUT2;
2366 serial8250_set_mctrl(port, port->mctrl);
2369 * Serial over Lan (SoL) hack:
2370 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2371 * used for Serial Over Lan. Those chips take a longer time than a
2372 * normal serial device to signalize that a transmission data was
2373 * queued. Due to that, the above test generally fails. One solution
2374 * would be to delay the reading of iir. However, this is not
2375 * reliable, since the timeout is variable. So, let's just don't
2376 * test if we receive TX irq. This way, we'll never enable
2379 if (up->port.quirks & UPQ_NO_TXEN_TEST)
2380 goto dont_test_tx_en;
2383 * Do a quick test to see if we receive an interrupt when we enable
2386 serial_port_out(port, UART_IER, UART_IER_THRI);
2387 lsr = serial_port_in(port, UART_LSR);
2388 iir = serial_port_in(port, UART_IIR);
2389 serial_port_out(port, UART_IER, 0);
2391 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2392 if (!(up->bugs & UART_BUG_TXEN)) {
2393 up->bugs |= UART_BUG_TXEN;
2394 dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2397 up->bugs &= ~UART_BUG_TXEN;
2401 spin_unlock_irqrestore(&port->lock, flags);
2404 * Clear the interrupt registers again for luck, and clear the
2405 * saved flags to avoid getting false values from polling
2406 * routines or the previous session.
2408 serial_port_in(port, UART_LSR);
2409 serial_port_in(port, UART_RX);
2410 serial_port_in(port, UART_IIR);
2411 serial_port_in(port, UART_MSR);
2412 up->lsr_saved_flags = 0;
2413 up->msr_saved_flags = 0;
2416 * Request DMA channels for both RX and TX.
2419 const char *msg = NULL;
2421 if (uart_console(port))
2422 msg = "forbid DMA for kernel console";
2423 else if (serial8250_request_dma(up))
2424 msg = "failed to request DMA";
2426 dev_warn_ratelimited(port->dev, "%s\n", msg);
2432 * Set the IER shadow for rx interrupts but defer actual interrupt
2433 * enable until after the FIFOs are enabled; otherwise, an already-
2434 * active sender can swamp the interrupt handler with "too much work".
2436 up->ier = UART_IER_RLSI | UART_IER_RDI;
2438 if (port->flags & UPF_FOURPORT) {
2441 * Enable interrupts on the AST Fourport board
2443 icp = (port->iobase & 0xfe0) | 0x01f;
2449 serial8250_rpm_put(up);
2452 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2454 static int serial8250_startup(struct uart_port *port)
2457 return port->startup(port);
2458 return serial8250_do_startup(port);
2461 void serial8250_do_shutdown(struct uart_port *port)
2463 struct uart_8250_port *up = up_to_u8250p(port);
2464 unsigned long flags;
2466 serial8250_rpm_get(up);
2468 * Disable interrupts from this port
2470 spin_lock_irqsave(&port->lock, flags);
2472 serial_port_out(port, UART_IER, 0);
2473 spin_unlock_irqrestore(&port->lock, flags);
2475 synchronize_irq(port->irq);
2478 serial8250_release_dma(up);
2480 spin_lock_irqsave(&port->lock, flags);
2481 if (port->flags & UPF_FOURPORT) {
2482 /* reset interrupts on the AST Fourport board */
2483 inb((port->iobase & 0xfe0) | 0x1f);
2484 port->mctrl |= TIOCM_OUT1;
2486 port->mctrl &= ~TIOCM_OUT2;
2488 serial8250_set_mctrl(port, port->mctrl);
2489 spin_unlock_irqrestore(&port->lock, flags);
2492 * Disable break condition and FIFOs
2494 serial_port_out(port, UART_LCR,
2495 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2496 serial8250_clear_fifos(up);
2498 #ifdef CONFIG_SERIAL_8250_RSA
2500 * Reset the RSA board back to 115kbps compat mode.
2506 * Read data port to reset things, and then unlink from
2509 serial_port_in(port, UART_RX);
2510 serial8250_rpm_put(up);
2512 up->ops->release_irq(up);
2514 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2516 static void serial8250_shutdown(struct uart_port *port)
2519 port->shutdown(port);
2521 serial8250_do_shutdown(port);
2524 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2525 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2528 struct uart_port *port = &up->port;
2530 return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2533 static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2537 upf_t magic_multiplier = port->flags & UPF_MAGIC_MULTIPLIER;
2538 struct uart_8250_port *up = up_to_u8250p(port);
2542 * Handle magic divisors for baud rates above baud_base on SMSC
2543 * Super I/O chips. We clamp custom rates from clk/6 and clk/12
2544 * up to clk/4 (0x8001) and clk/8 (0x8002) respectively. These
2545 * magic divisors actually reprogram the baud rate generator's
2546 * reference clock derived from chips's 14.318MHz clock input.
2548 * Documentation claims that with these magic divisors the base
2549 * frequencies of 7.3728MHz and 3.6864MHz are used respectively
2550 * for the extra baud rates of 460800bps and 230400bps rather
2551 * than the usual base frequency of 1.8462MHz. However empirical
2552 * evidence contradicts that.
2554 * Instead bit 7 of the DLM register (bit 15 of the divisor) is
2555 * effectively used as a clock prescaler selection bit for the
2556 * base frequency of 7.3728MHz, always used. If set to 0, then
2557 * the base frequency is divided by 4 for use by the Baud Rate
2558 * Generator, for the usual arrangement where the value of 1 of
2559 * the divisor produces the baud rate of 115200bps. Conversely,
2560 * if set to 1 and high-speed operation has been enabled with the
2561 * Serial Port Mode Register in the Device Configuration Space,
2562 * then the base frequency is supplied directly to the Baud Rate
2563 * Generator, so for the divisor values of 0x8001, 0x8002, 0x8003,
2564 * 0x8004, etc. the respective baud rates produced are 460800bps,
2565 * 230400bps, 153600bps, 115200bps, etc.
2567 * In all cases only low 15 bits of the divisor are used to divide
2568 * the baud base and therefore 32767 is the maximum divisor value
2569 * possible, even though documentation says that the programmable
2570 * Baud Rate Generator is capable of dividing the internal PLL
2571 * clock by any divisor from 1 to 65535.
2573 if (magic_multiplier && baud >= port->uartclk / 6)
2575 else if (magic_multiplier && baud >= port->uartclk / 12)
2577 else if (up->port.type == PORT_NPCM)
2578 quot = npcm_get_divisor(up, baud);
2580 quot = uart_get_divisor(port, baud);
2583 * Oxford Semi 952 rev B workaround
2585 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2591 static unsigned int serial8250_get_divisor(struct uart_port *port,
2595 if (port->get_divisor)
2596 return port->get_divisor(port, baud, frac);
2598 return serial8250_do_get_divisor(port, baud, frac);
2601 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2606 cval = UART_LCR_WLEN(tty_get_char_size(c_cflag));
2608 if (c_cflag & CSTOPB)
2609 cval |= UART_LCR_STOP;
2610 if (c_cflag & PARENB) {
2611 cval |= UART_LCR_PARITY;
2612 if (up->bugs & UART_BUG_PARITY)
2613 up->fifo_bug = true;
2615 if (!(c_cflag & PARODD))
2616 cval |= UART_LCR_EPAR;
2618 if (c_cflag & CMSPAR)
2619 cval |= UART_LCR_SPAR;
2625 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2626 unsigned int quot, unsigned int quot_frac)
2628 struct uart_8250_port *up = up_to_u8250p(port);
2630 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2631 if (is_omap1510_8250(up)) {
2632 if (baud == 115200) {
2634 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2636 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2640 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2641 * otherwise just set DLAB
2643 if (up->capabilities & UART_NATSEMI)
2644 serial_port_out(port, UART_LCR, 0xe0);
2646 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2648 serial_dl_write(up, quot);
2650 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2652 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2653 unsigned int quot, unsigned int quot_frac)
2655 if (port->set_divisor)
2656 port->set_divisor(port, baud, quot, quot_frac);
2658 serial8250_do_set_divisor(port, baud, quot, quot_frac);
2661 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2662 struct ktermios *termios,
2663 struct ktermios *old)
2665 unsigned int tolerance = port->uartclk / 100;
2670 * Handle magic divisors for baud rates above baud_base on SMSC
2671 * Super I/O chips. Enable custom rates of clk/4 and clk/8, but
2672 * disable divisor values beyond 32767, which are unavailable.
2674 if (port->flags & UPF_MAGIC_MULTIPLIER) {
2675 min = port->uartclk / 16 / UART_DIV_MAX >> 1;
2676 max = (port->uartclk + tolerance) / 4;
2678 min = port->uartclk / 16 / UART_DIV_MAX;
2679 max = (port->uartclk + tolerance) / 16;
2683 * Ask the core to calculate the divisor for us.
2684 * Allow 1% tolerance at the upper limit so uart clks marginally
2685 * slower than nominal still match standard baud rates without
2686 * causing transmission errors.
2688 return uart_get_baud_rate(port, termios, old, min, max);
2692 * Note in order to avoid the tty port mutex deadlock don't use the next method
2693 * within the uart port callbacks. Primarily it's supposed to be utilized to
2694 * handle a sudden reference clock rate change.
2696 void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk)
2698 struct uart_8250_port *up = up_to_u8250p(port);
2699 struct tty_port *tport = &port->state->port;
2700 unsigned int baud, quot, frac = 0;
2701 struct ktermios *termios;
2702 struct tty_struct *tty;
2703 unsigned long flags;
2705 tty = tty_port_tty_get(tport);
2707 mutex_lock(&tport->mutex);
2708 port->uartclk = uartclk;
2709 mutex_unlock(&tport->mutex);
2713 down_write(&tty->termios_rwsem);
2714 mutex_lock(&tport->mutex);
2716 if (port->uartclk == uartclk)
2719 port->uartclk = uartclk;
2721 if (!tty_port_initialized(tport))
2724 termios = &tty->termios;
2726 baud = serial8250_get_baud_rate(port, termios, NULL);
2727 quot = serial8250_get_divisor(port, baud, &frac);
2729 serial8250_rpm_get(up);
2730 spin_lock_irqsave(&port->lock, flags);
2732 uart_update_timeout(port, termios->c_cflag, baud);
2734 serial8250_set_divisor(port, baud, quot, frac);
2735 serial_port_out(port, UART_LCR, up->lcr);
2737 spin_unlock_irqrestore(&port->lock, flags);
2738 serial8250_rpm_put(up);
2741 mutex_unlock(&tport->mutex);
2742 up_write(&tty->termios_rwsem);
2745 EXPORT_SYMBOL_GPL(serial8250_update_uartclk);
2748 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2749 struct ktermios *old)
2751 struct uart_8250_port *up = up_to_u8250p(port);
2753 unsigned long flags;
2754 unsigned int baud, quot, frac = 0;
2756 if (up->capabilities & UART_CAP_MINI) {
2757 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2758 if ((termios->c_cflag & CSIZE) == CS5 ||
2759 (termios->c_cflag & CSIZE) == CS6)
2760 termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2762 cval = serial8250_compute_lcr(up, termios->c_cflag);
2764 baud = serial8250_get_baud_rate(port, termios, old);
2765 quot = serial8250_get_divisor(port, baud, &frac);
2768 * Ok, we're now changing the port state. Do it with
2769 * interrupts disabled.
2771 serial8250_rpm_get(up);
2772 spin_lock_irqsave(&port->lock, flags);
2774 up->lcr = cval; /* Save computed LCR */
2776 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2777 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2778 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2779 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2780 up->fcr |= UART_FCR_TRIGGER_1;
2785 * MCR-based auto flow control. When AFE is enabled, RTS will be
2786 * deasserted when the receive FIFO contains more characters than
2787 * the trigger, or the MCR RTS bit is cleared.
2789 if (up->capabilities & UART_CAP_AFE) {
2790 up->mcr &= ~UART_MCR_AFE;
2791 if (termios->c_cflag & CRTSCTS)
2792 up->mcr |= UART_MCR_AFE;
2796 * Update the per-port timeout.
2798 uart_update_timeout(port, termios->c_cflag, baud);
2800 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2801 if (termios->c_iflag & INPCK)
2802 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2803 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2804 port->read_status_mask |= UART_LSR_BI;
2807 * Characteres to ignore
2809 port->ignore_status_mask = 0;
2810 if (termios->c_iflag & IGNPAR)
2811 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2812 if (termios->c_iflag & IGNBRK) {
2813 port->ignore_status_mask |= UART_LSR_BI;
2815 * If we're ignoring parity and break indicators,
2816 * ignore overruns too (for real raw support).
2818 if (termios->c_iflag & IGNPAR)
2819 port->ignore_status_mask |= UART_LSR_OE;
2823 * ignore all characters if CREAD is not set
2825 if ((termios->c_cflag & CREAD) == 0)
2826 port->ignore_status_mask |= UART_LSR_DR;
2829 * CTS flow control flag and modem status interrupts
2831 up->ier &= ~UART_IER_MSI;
2832 if (!(up->bugs & UART_BUG_NOMSR) &&
2833 UART_ENABLE_MS(&up->port, termios->c_cflag))
2834 up->ier |= UART_IER_MSI;
2835 if (up->capabilities & UART_CAP_UUE)
2836 up->ier |= UART_IER_UUE;
2837 if (up->capabilities & UART_CAP_RTOIE)
2838 up->ier |= UART_IER_RTOIE;
2840 serial_port_out(port, UART_IER, up->ier);
2842 if (up->capabilities & UART_CAP_EFR) {
2843 unsigned char efr = 0;
2845 * TI16C752/Startech hardware flow control. FIXME:
2846 * - TI16C752 requires control thresholds to be set.
2847 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2849 if (termios->c_cflag & CRTSCTS)
2850 efr |= UART_EFR_CTS;
2852 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2853 if (port->flags & UPF_EXAR_EFR)
2854 serial_port_out(port, UART_XR_EFR, efr);
2856 serial_port_out(port, UART_EFR, efr);
2859 serial8250_set_divisor(port, baud, quot, frac);
2862 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2863 * is written without DLAB set, this mode will be disabled.
2865 if (port->type == PORT_16750)
2866 serial_port_out(port, UART_FCR, up->fcr);
2868 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2869 if (port->type != PORT_16750) {
2870 /* emulated UARTs (Lucent Venus 167x) need two steps */
2871 if (up->fcr & UART_FCR_ENABLE_FIFO)
2872 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2873 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2875 serial8250_set_mctrl(port, port->mctrl);
2876 spin_unlock_irqrestore(&port->lock, flags);
2877 serial8250_rpm_put(up);
2879 /* Don't rewrite B0 */
2880 if (tty_termios_baud_rate(termios))
2881 tty_termios_encode_baud_rate(termios, baud, baud);
2883 EXPORT_SYMBOL(serial8250_do_set_termios);
2886 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2887 struct ktermios *old)
2889 if (port->set_termios)
2890 port->set_termios(port, termios, old);
2892 serial8250_do_set_termios(port, termios, old);
2895 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2897 if (termios->c_line == N_PPS) {
2898 port->flags |= UPF_HARDPPS_CD;
2899 spin_lock_irq(&port->lock);
2900 serial8250_enable_ms(port);
2901 spin_unlock_irq(&port->lock);
2903 port->flags &= ~UPF_HARDPPS_CD;
2904 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2905 spin_lock_irq(&port->lock);
2906 serial8250_disable_ms(port);
2907 spin_unlock_irq(&port->lock);
2911 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2914 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2916 if (port->set_ldisc)
2917 port->set_ldisc(port, termios);
2919 serial8250_do_set_ldisc(port, termios);
2922 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2923 unsigned int oldstate)
2925 struct uart_8250_port *p = up_to_u8250p(port);
2927 serial8250_set_sleep(p, state != 0);
2929 EXPORT_SYMBOL(serial8250_do_pm);
2932 serial8250_pm(struct uart_port *port, unsigned int state,
2933 unsigned int oldstate)
2936 port->pm(port, state, oldstate);
2938 serial8250_do_pm(port, state, oldstate);
2941 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2943 if (pt->port.mapsize)
2944 return pt->port.mapsize;
2945 if (pt->port.iotype == UPIO_AU) {
2946 if (pt->port.type == PORT_RT2880)
2950 if (is_omap1_8250(pt))
2951 return 0x16 << pt->port.regshift;
2953 return 8 << pt->port.regshift;
2957 * Resource handling.
2959 static int serial8250_request_std_resource(struct uart_8250_port *up)
2961 unsigned int size = serial8250_port_size(up);
2962 struct uart_port *port = &up->port;
2965 switch (port->iotype) {
2975 if (!request_mem_region(port->mapbase, size, "serial")) {
2980 if (port->flags & UPF_IOREMAP) {
2981 port->membase = ioremap(port->mapbase, size);
2982 if (!port->membase) {
2983 release_mem_region(port->mapbase, size);
2991 if (!request_region(port->iobase, size, "serial"))
2998 static void serial8250_release_std_resource(struct uart_8250_port *up)
3000 unsigned int size = serial8250_port_size(up);
3001 struct uart_port *port = &up->port;
3003 switch (port->iotype) {
3013 if (port->flags & UPF_IOREMAP) {
3014 iounmap(port->membase);
3015 port->membase = NULL;
3018 release_mem_region(port->mapbase, size);
3023 release_region(port->iobase, size);
3028 static void serial8250_release_port(struct uart_port *port)
3030 struct uart_8250_port *up = up_to_u8250p(port);
3032 serial8250_release_std_resource(up);
3035 static int serial8250_request_port(struct uart_port *port)
3037 struct uart_8250_port *up = up_to_u8250p(port);
3039 return serial8250_request_std_resource(up);
3042 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
3044 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3045 unsigned char bytes;
3047 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
3049 return bytes ? bytes : -EOPNOTSUPP;
3052 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
3054 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3057 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
3060 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
3061 if (bytes < conf_type->rxtrig_bytes[i])
3062 /* Use the nearest lower value */
3063 return (--i) << UART_FCR_R_TRIG_SHIFT;
3066 return UART_FCR_R_TRIG_11;
3069 static int do_get_rxtrig(struct tty_port *port)
3071 struct uart_state *state = container_of(port, struct uart_state, port);
3072 struct uart_port *uport = state->uart_port;
3073 struct uart_8250_port *up = up_to_u8250p(uport);
3075 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3078 return fcr_get_rxtrig_bytes(up);
3081 static int do_serial8250_get_rxtrig(struct tty_port *port)
3085 mutex_lock(&port->mutex);
3086 rxtrig_bytes = do_get_rxtrig(port);
3087 mutex_unlock(&port->mutex);
3089 return rxtrig_bytes;
3092 static ssize_t rx_trig_bytes_show(struct device *dev,
3093 struct device_attribute *attr, char *buf)
3095 struct tty_port *port = dev_get_drvdata(dev);
3098 rxtrig_bytes = do_serial8250_get_rxtrig(port);
3099 if (rxtrig_bytes < 0)
3100 return rxtrig_bytes;
3102 return sysfs_emit(buf, "%d\n", rxtrig_bytes);
3105 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
3107 struct uart_state *state = container_of(port, struct uart_state, port);
3108 struct uart_port *uport = state->uart_port;
3109 struct uart_8250_port *up = up_to_u8250p(uport);
3112 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
3116 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3120 serial8250_clear_fifos(up);
3121 up->fcr &= ~UART_FCR_TRIGGER_MASK;
3122 up->fcr |= (unsigned char)rxtrig;
3123 serial_out(up, UART_FCR, up->fcr);
3127 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3131 mutex_lock(&port->mutex);
3132 ret = do_set_rxtrig(port, bytes);
3133 mutex_unlock(&port->mutex);
3138 static ssize_t rx_trig_bytes_store(struct device *dev,
3139 struct device_attribute *attr, const char *buf, size_t count)
3141 struct tty_port *port = dev_get_drvdata(dev);
3142 unsigned char bytes;
3148 ret = kstrtou8(buf, 10, &bytes);
3152 ret = do_serial8250_set_rxtrig(port, bytes);
3159 static DEVICE_ATTR_RW(rx_trig_bytes);
3161 static struct attribute *serial8250_dev_attrs[] = {
3162 &dev_attr_rx_trig_bytes.attr,
3166 static struct attribute_group serial8250_dev_attr_group = {
3167 .attrs = serial8250_dev_attrs,
3170 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3172 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3174 if (conf_type->rxtrig_bytes[0])
3175 up->port.attr_group = &serial8250_dev_attr_group;
3178 static void serial8250_config_port(struct uart_port *port, int flags)
3180 struct uart_8250_port *up = up_to_u8250p(port);
3184 * Find the region that we can probe for. This in turn
3185 * tells us whether we can probe for the type of port.
3187 ret = serial8250_request_std_resource(up);
3191 if (port->iotype != up->cur_iotype)
3192 set_io_from_upio(port);
3194 if (flags & UART_CONFIG_TYPE)
3197 if (port->rs485.flags & SER_RS485_ENABLED)
3198 port->rs485_config(port, &port->rs485);
3200 /* if access method is AU, it is a 16550 with a quirk */
3201 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3202 up->bugs |= UART_BUG_NOMSR;
3204 /* HW bugs may trigger IRQ while IIR == NO_INT */
3205 if (port->type == PORT_TEGRA)
3206 up->bugs |= UART_BUG_NOMSR;
3208 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3211 if (port->type == PORT_UNKNOWN)
3212 serial8250_release_std_resource(up);
3214 register_dev_spec_attr_grp(up);
3215 up->fcr = uart_config[up->port.type].fcr;
3219 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3221 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3222 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3223 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3224 ser->type == PORT_STARTECH)
3229 static const char *serial8250_type(struct uart_port *port)
3231 int type = port->type;
3233 if (type >= ARRAY_SIZE(uart_config))
3235 return uart_config[type].name;
3238 static const struct uart_ops serial8250_pops = {
3239 .tx_empty = serial8250_tx_empty,
3240 .set_mctrl = serial8250_set_mctrl,
3241 .get_mctrl = serial8250_get_mctrl,
3242 .stop_tx = serial8250_stop_tx,
3243 .start_tx = serial8250_start_tx,
3244 .throttle = serial8250_throttle,
3245 .unthrottle = serial8250_unthrottle,
3246 .stop_rx = serial8250_stop_rx,
3247 .enable_ms = serial8250_enable_ms,
3248 .break_ctl = serial8250_break_ctl,
3249 .startup = serial8250_startup,
3250 .shutdown = serial8250_shutdown,
3251 .set_termios = serial8250_set_termios,
3252 .set_ldisc = serial8250_set_ldisc,
3253 .pm = serial8250_pm,
3254 .type = serial8250_type,
3255 .release_port = serial8250_release_port,
3256 .request_port = serial8250_request_port,
3257 .config_port = serial8250_config_port,
3258 .verify_port = serial8250_verify_port,
3259 #ifdef CONFIG_CONSOLE_POLL
3260 .poll_get_char = serial8250_get_poll_char,
3261 .poll_put_char = serial8250_put_poll_char,
3265 void serial8250_init_port(struct uart_8250_port *up)
3267 struct uart_port *port = &up->port;
3269 spin_lock_init(&port->lock);
3270 port->ops = &serial8250_pops;
3271 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3273 up->cur_iotype = 0xFF;
3275 EXPORT_SYMBOL_GPL(serial8250_init_port);
3277 void serial8250_set_defaults(struct uart_8250_port *up)
3279 struct uart_port *port = &up->port;
3281 if (up->port.flags & UPF_FIXED_TYPE) {
3282 unsigned int type = up->port.type;
3284 if (!up->port.fifosize)
3285 up->port.fifosize = uart_config[type].fifo_size;
3287 up->tx_loadsz = uart_config[type].tx_loadsz;
3288 if (!up->capabilities)
3289 up->capabilities = uart_config[type].flags;
3292 set_io_from_upio(port);
3294 /* default dma handlers */
3296 if (!up->dma->tx_dma)
3297 up->dma->tx_dma = serial8250_tx_dma;
3298 if (!up->dma->rx_dma)
3299 up->dma->rx_dma = serial8250_rx_dma;
3302 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3304 #ifdef CONFIG_SERIAL_8250_CONSOLE
3306 static void serial8250_console_putchar(struct uart_port *port, unsigned char ch)
3308 struct uart_8250_port *up = up_to_u8250p(port);
3310 wait_for_xmitr(up, UART_LSR_THRE);
3311 serial_port_out(port, UART_TX, ch);
3315 * Restore serial console when h/w power-off detected
3317 static void serial8250_console_restore(struct uart_8250_port *up)
3319 struct uart_port *port = &up->port;
3320 struct ktermios termios;
3321 unsigned int baud, quot, frac = 0;
3323 termios.c_cflag = port->cons->cflag;
3324 if (port->state->port.tty && termios.c_cflag == 0)
3325 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3327 baud = serial8250_get_baud_rate(port, &termios, NULL);
3328 quot = serial8250_get_divisor(port, baud, &frac);
3330 serial8250_set_divisor(port, baud, quot, frac);
3331 serial_port_out(port, UART_LCR, up->lcr);
3332 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
3336 * Print a string to the serial port trying not to disturb
3337 * any possible real use of the port...
3339 * The console_lock must be held when we get here.
3341 * Doing runtime PM is really a bad idea for the kernel console.
3342 * Thus, we assume the function is called when device is powered up.
3344 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3347 struct uart_8250_em485 *em485 = up->em485;
3348 struct uart_port *port = &up->port;
3349 unsigned long flags;
3353 touch_nmi_watchdog();
3355 if (oops_in_progress)
3356 locked = spin_trylock_irqsave(&port->lock, flags);
3358 spin_lock_irqsave(&port->lock, flags);
3361 * First save the IER then disable the interrupts
3363 ier = serial_port_in(port, UART_IER);
3365 if (up->capabilities & UART_CAP_UUE)
3366 serial_port_out(port, UART_IER, UART_IER_UUE);
3368 serial_port_out(port, UART_IER, 0);
3370 /* check scratch reg to see if port powered off during system sleep */
3371 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3372 serial8250_console_restore(up);
3377 if (em485->tx_stopped)
3378 up->rs485_start_tx(up);
3379 mdelay(port->rs485.delay_rts_before_send);
3382 uart_console_write(port, s, count, serial8250_console_putchar);
3385 * Finally, wait for transmitter to become empty
3386 * and restore the IER
3388 wait_for_xmitr(up, BOTH_EMPTY);
3391 mdelay(port->rs485.delay_rts_after_send);
3392 if (em485->tx_stopped)
3393 up->rs485_stop_tx(up);
3396 serial_port_out(port, UART_IER, ier);
3399 * The receive handling will happen properly because the
3400 * receive ready bit will still be set; it is not cleared
3401 * on read. However, modem control will not, we must
3402 * call it if we have saved something in the saved flags
3403 * while processing with interrupts off.
3405 if (up->msr_saved_flags)
3406 serial8250_modem_status(up);
3409 spin_unlock_irqrestore(&port->lock, flags);
3412 static unsigned int probe_baud(struct uart_port *port)
3414 unsigned char lcr, dll, dlm;
3417 lcr = serial_port_in(port, UART_LCR);
3418 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3419 dll = serial_port_in(port, UART_DLL);
3420 dlm = serial_port_in(port, UART_DLM);
3421 serial_port_out(port, UART_LCR, lcr);
3423 quot = (dlm << 8) | dll;
3424 return (port->uartclk / 16) / quot;
3427 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3435 if (!port->iobase && !port->membase)
3439 uart_parse_options(options, &baud, &parity, &bits, &flow);
3441 baud = probe_baud(port);
3443 ret = uart_set_options(port, port->cons, baud, parity, bits, flow);
3448 pm_runtime_get_sync(port->dev);
3453 int serial8250_console_exit(struct uart_port *port)
3456 pm_runtime_put_sync(port->dev);
3461 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3463 MODULE_LICENSE("GPL");