1 // SPDX-License-Identifier: GPL-2.0+
3 * Base port operations for 8250/16550-type serial ports
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
8 * A note about mapbase / membase
10 * mapbase is the physical address of the IO port.
11 * membase is an 'ioremapped' cookie.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/ioport.h>
17 #include <linux/init.h>
18 #include <linux/console.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/sysrq.h>
21 #include <linux/delay.h>
22 #include <linux/platform_device.h>
23 #include <linux/tty.h>
24 #include <linux/ratelimit.h>
25 #include <linux/tty_flip.h>
26 #include <linux/serial.h>
27 #include <linux/serial_8250.h>
28 #include <linux/nmi.h>
29 #include <linux/mutex.h>
30 #include <linux/slab.h>
31 #include <linux/uaccess.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/ktime.h>
40 /* Nuvoton NPCM timeout register */
41 #define UART_NPCM_TOR 7
42 #define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */
48 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
50 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
53 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
56 * Here we define the default xmit fifo size used for each type of UART.
58 static const struct serial8250_config uart_config[] = {
83 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
84 .rxtrig_bytes = {1, 4, 8, 14},
85 .flags = UART_CAP_FIFO,
96 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
102 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
104 .rxtrig_bytes = {8, 16, 24, 28},
105 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
111 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
113 .rxtrig_bytes = {1, 16, 32, 56},
114 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
122 .name = "16C950/954",
125 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
126 .rxtrig_bytes = {16, 32, 112, 120},
127 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
128 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
134 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
136 .rxtrig_bytes = {8, 16, 56, 60},
137 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
143 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
144 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
150 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
151 .flags = UART_CAP_FIFO,
157 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
158 .flags = UART_CAP_FIFO | UART_NATSEMI,
164 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
165 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
171 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
172 .flags = UART_CAP_FIFO,
178 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
179 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
185 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
186 .flags = UART_CAP_FIFO | UART_CAP_AFE,
192 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
194 .rxtrig_bytes = {1, 4, 8, 14},
195 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
201 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
202 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
209 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
211 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
218 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
219 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
220 .flags = UART_CAP_FIFO,
222 [PORT_BRCM_TRUMANAGE] = {
226 .flags = UART_CAP_HFIFO,
231 [PORT_ALTR_16550_F32] = {
232 .name = "Altera 16550 FIFO32",
235 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
236 .rxtrig_bytes = {1, 8, 16, 30},
237 .flags = UART_CAP_FIFO | UART_CAP_AFE,
239 [PORT_ALTR_16550_F64] = {
240 .name = "Altera 16550 FIFO64",
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
244 .rxtrig_bytes = {1, 16, 32, 62},
245 .flags = UART_CAP_FIFO | UART_CAP_AFE,
247 [PORT_ALTR_16550_F128] = {
248 .name = "Altera 16550 FIFO128",
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .rxtrig_bytes = {1, 32, 64, 126},
253 .flags = UART_CAP_FIFO | UART_CAP_AFE,
256 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
257 * workaround of errata A-008006 which states that tx_loadsz should
258 * be configured less than Maximum supported fifo bytes.
260 [PORT_16550A_FSL64] = {
261 .name = "16550A_FSL64",
264 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
266 .flags = UART_CAP_FIFO,
269 .name = "Palmchip BK-3103",
272 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
273 .rxtrig_bytes = {1, 4, 8, 14},
274 .flags = UART_CAP_FIFO,
277 .name = "TI DA8xx/66AK2x",
280 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
282 .rxtrig_bytes = {1, 4, 8, 14},
283 .flags = UART_CAP_FIFO | UART_CAP_AFE,
286 .name = "MediaTek BTIF",
289 .fcr = UART_FCR_ENABLE_FIFO |
290 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
291 .flags = UART_CAP_FIFO,
294 .name = "Nuvoton 16550",
297 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
298 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
299 .rxtrig_bytes = {1, 4, 8, 14},
300 .flags = UART_CAP_FIFO,
306 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
307 .rxtrig_bytes = {1, 32, 64, 112},
308 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
310 [PORT_ASPEED_VUART] = {
311 .name = "ASPEED VUART",
314 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
315 .rxtrig_bytes = {1, 4, 8, 14},
316 .flags = UART_CAP_FIFO,
320 /* Uart divisor latch read */
321 static int default_serial_dl_read(struct uart_8250_port *up)
323 /* Assign these in pieces to truncate any bits above 7. */
324 unsigned char dll = serial_in(up, UART_DLL);
325 unsigned char dlm = serial_in(up, UART_DLM);
327 return dll | dlm << 8;
330 /* Uart divisor latch write */
331 static void default_serial_dl_write(struct uart_8250_port *up, int value)
333 serial_out(up, UART_DLL, value & 0xff);
334 serial_out(up, UART_DLM, value >> 8 & 0xff);
337 #ifdef CONFIG_SERIAL_8250_RT288X
339 /* Au1x00/RT288x UART hardware has a weird register layout */
340 static const s8 au_io_in_map[8] = {
348 -1, /* UART_SCR (unmapped) */
351 static const s8 au_io_out_map[8] = {
357 -1, /* UART_LSR (unmapped) */
358 -1, /* UART_MSR (unmapped) */
359 -1, /* UART_SCR (unmapped) */
362 unsigned int au_serial_in(struct uart_port *p, int offset)
364 if (offset >= ARRAY_SIZE(au_io_in_map))
366 offset = au_io_in_map[offset];
369 return __raw_readl(p->membase + (offset << p->regshift));
372 void au_serial_out(struct uart_port *p, int offset, int value)
374 if (offset >= ARRAY_SIZE(au_io_out_map))
376 offset = au_io_out_map[offset];
379 __raw_writel(value, p->membase + (offset << p->regshift));
382 /* Au1x00 haven't got a standard divisor latch */
383 static int au_serial_dl_read(struct uart_8250_port *up)
385 return __raw_readl(up->port.membase + 0x28);
388 static void au_serial_dl_write(struct uart_8250_port *up, int value)
390 __raw_writel(value, up->port.membase + 0x28);
395 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
397 offset = offset << p->regshift;
398 outb(p->hub6 - 1 + offset, p->iobase);
399 return inb(p->iobase + 1);
402 static void hub6_serial_out(struct uart_port *p, int offset, int value)
404 offset = offset << p->regshift;
405 outb(p->hub6 - 1 + offset, p->iobase);
406 outb(value, p->iobase + 1);
409 static unsigned int mem_serial_in(struct uart_port *p, int offset)
411 offset = offset << p->regshift;
412 return readb(p->membase + offset);
415 static void mem_serial_out(struct uart_port *p, int offset, int value)
417 offset = offset << p->regshift;
418 writeb(value, p->membase + offset);
421 static void mem16_serial_out(struct uart_port *p, int offset, int value)
423 offset = offset << p->regshift;
424 writew(value, p->membase + offset);
427 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
429 offset = offset << p->regshift;
430 return readw(p->membase + offset);
433 static void mem32_serial_out(struct uart_port *p, int offset, int value)
435 offset = offset << p->regshift;
436 writel(value, p->membase + offset);
439 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
441 offset = offset << p->regshift;
442 return readl(p->membase + offset);
445 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
447 offset = offset << p->regshift;
448 iowrite32be(value, p->membase + offset);
451 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
453 offset = offset << p->regshift;
454 return ioread32be(p->membase + offset);
457 static unsigned int io_serial_in(struct uart_port *p, int offset)
459 offset = offset << p->regshift;
460 return inb(p->iobase + offset);
463 static void io_serial_out(struct uart_port *p, int offset, int value)
465 offset = offset << p->regshift;
466 outb(value, p->iobase + offset);
469 static int serial8250_default_handle_irq(struct uart_port *port);
471 static void set_io_from_upio(struct uart_port *p)
473 struct uart_8250_port *up = up_to_u8250p(p);
475 up->dl_read = default_serial_dl_read;
476 up->dl_write = default_serial_dl_write;
480 p->serial_in = hub6_serial_in;
481 p->serial_out = hub6_serial_out;
485 p->serial_in = mem_serial_in;
486 p->serial_out = mem_serial_out;
490 p->serial_in = mem16_serial_in;
491 p->serial_out = mem16_serial_out;
495 p->serial_in = mem32_serial_in;
496 p->serial_out = mem32_serial_out;
500 p->serial_in = mem32be_serial_in;
501 p->serial_out = mem32be_serial_out;
504 #ifdef CONFIG_SERIAL_8250_RT288X
506 p->serial_in = au_serial_in;
507 p->serial_out = au_serial_out;
508 up->dl_read = au_serial_dl_read;
509 up->dl_write = au_serial_dl_write;
514 p->serial_in = io_serial_in;
515 p->serial_out = io_serial_out;
518 /* Remember loaded iotype */
519 up->cur_iotype = p->iotype;
520 p->handle_irq = serial8250_default_handle_irq;
524 serial_port_out_sync(struct uart_port *p, int offset, int value)
532 p->serial_out(p, offset, value);
533 p->serial_in(p, UART_LCR); /* safe, no side-effects */
536 p->serial_out(p, offset, value);
543 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
545 serial_out(up, UART_SCR, offset);
546 serial_out(up, UART_ICR, value);
549 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
553 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
554 serial_out(up, UART_SCR, offset);
555 value = serial_in(up, UART_ICR);
556 serial_icr_write(up, UART_ACR, up->acr);
564 static void serial8250_clear_fifos(struct uart_8250_port *p)
566 if (p->capabilities & UART_CAP_FIFO) {
567 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
568 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
569 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
570 serial_out(p, UART_FCR, 0);
574 static inline void serial8250_em485_update_temt_delay(struct uart_8250_port *p,
575 unsigned int cflag, unsigned int baud)
582 bits = tty_get_frame_size(cflag);
583 p->em485->no_temt_delay = DIV_ROUND_UP(bits * NSEC_PER_SEC, baud);
586 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
587 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
588 static enum hrtimer_restart serial8250_em485_handle_no_temt(struct hrtimer *t);
590 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
592 serial8250_clear_fifos(p);
593 serial_out(p, UART_FCR, p->fcr);
595 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
597 void serial8250_rpm_get(struct uart_8250_port *p)
599 if (!(p->capabilities & UART_CAP_RPM))
601 pm_runtime_get_sync(p->port.dev);
603 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
605 void serial8250_rpm_put(struct uart_8250_port *p)
607 if (!(p->capabilities & UART_CAP_RPM))
609 pm_runtime_mark_last_busy(p->port.dev);
610 pm_runtime_put_autosuspend(p->port.dev);
612 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
615 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
616 * @p: uart_8250_port port instance
618 * The function is used to start rs485 software emulating on the
619 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
620 * transmission. The function is idempotent, so it is safe to call it
623 * The caller MUST enable interrupt on empty shift register before
624 * calling serial8250_em485_init(). This interrupt is not a part of
625 * 8250 standard, but implementation defined.
627 * The function is supposed to be called from .rs485_config callback
628 * or from any other callback protected with p->port.lock spinlock.
630 * See also serial8250_em485_destroy()
632 * Return 0 - success, -errno - otherwise
634 static int serial8250_em485_init(struct uart_8250_port *p)
639 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
643 hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
645 hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
648 if (p->capabilities & UART_CAP_NOTEMT) {
649 struct tty_struct *tty = p->port.state->port.tty;
651 serial8250_em485_update_temt_delay(p, tty->termios.c_cflag,
652 tty_get_baud_rate(tty));
653 hrtimer_init(&p->em485->no_temt_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
654 p->em485->no_temt_timer.function = &serial8250_em485_handle_no_temt;
657 p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
658 p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
660 p->em485->active_timer = NULL;
661 p->em485->tx_stopped = true;
669 * serial8250_em485_destroy() - put uart_8250_port into normal state
670 * @p: uart_8250_port port instance
672 * The function is used to stop rs485 software emulating on the
673 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
674 * call it multiple times.
676 * The function is supposed to be called from .rs485_config callback
677 * or from any other callback protected with p->port.lock spinlock.
679 * See also serial8250_em485_init()
681 void serial8250_em485_destroy(struct uart_8250_port *p)
686 hrtimer_cancel(&p->em485->start_tx_timer);
687 hrtimer_cancel(&p->em485->stop_tx_timer);
688 hrtimer_cancel(&p->em485->no_temt_timer);
693 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
696 * serial8250_em485_config() - generic ->rs485_config() callback
698 * @rs485: rs485 settings
700 * Generic callback usable by 8250 uart drivers to activate rs485 settings
701 * if the uart is incapable of driving RTS as a Transmit Enable signal in
702 * hardware, relying on software emulation instead.
704 int serial8250_em485_config(struct uart_port *port, struct serial_rs485 *rs485)
706 struct uart_8250_port *up = up_to_u8250p(port);
708 /* pick sane settings if the user hasn't */
709 if (!!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
710 !!(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
711 rs485->flags |= SER_RS485_RTS_ON_SEND;
712 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
715 /* clamp the delays to [0, 100ms] */
716 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
717 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
719 memset(rs485->padding, 0, sizeof(rs485->padding));
720 port->rs485 = *rs485;
722 gpiod_set_value(port->rs485_term_gpio,
723 rs485->flags & SER_RS485_TERMINATE_BUS);
726 * Both serial8250_em485_init() and serial8250_em485_destroy()
729 if (rs485->flags & SER_RS485_ENABLED) {
730 int ret = serial8250_em485_init(up);
733 rs485->flags &= ~SER_RS485_ENABLED;
734 port->rs485.flags &= ~SER_RS485_ENABLED;
739 serial8250_em485_destroy(up);
742 EXPORT_SYMBOL_GPL(serial8250_em485_config);
745 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
746 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
747 * empty and the HW can idle again.
749 void serial8250_rpm_get_tx(struct uart_8250_port *p)
751 unsigned char rpm_active;
753 if (!(p->capabilities & UART_CAP_RPM))
756 rpm_active = xchg(&p->rpm_tx_active, 1);
759 pm_runtime_get_sync(p->port.dev);
761 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
763 void serial8250_rpm_put_tx(struct uart_8250_port *p)
765 unsigned char rpm_active;
767 if (!(p->capabilities & UART_CAP_RPM))
770 rpm_active = xchg(&p->rpm_tx_active, 0);
773 pm_runtime_mark_last_busy(p->port.dev);
774 pm_runtime_put_autosuspend(p->port.dev);
776 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
779 * IER sleep support. UARTs which have EFRs need the "extended
780 * capability" bit enabled. Note that on XR16C850s, we need to
781 * reset LCR to write to IER.
783 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
785 unsigned char lcr = 0, efr = 0;
787 serial8250_rpm_get(p);
789 if (p->capabilities & UART_CAP_SLEEP) {
790 if (p->capabilities & UART_CAP_EFR) {
791 lcr = serial_in(p, UART_LCR);
792 efr = serial_in(p, UART_EFR);
793 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
794 serial_out(p, UART_EFR, UART_EFR_ECB);
795 serial_out(p, UART_LCR, 0);
797 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
798 if (p->capabilities & UART_CAP_EFR) {
799 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
800 serial_out(p, UART_EFR, efr);
801 serial_out(p, UART_LCR, lcr);
805 serial8250_rpm_put(p);
808 #ifdef CONFIG_SERIAL_8250_RSA
810 * Attempts to turn on the RSA FIFO. Returns zero on failure.
811 * We set the port uart clock rate if we succeed.
813 static int __enable_rsa(struct uart_8250_port *up)
818 mode = serial_in(up, UART_RSA_MSR);
819 result = mode & UART_RSA_MSR_FIFO;
822 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
823 mode = serial_in(up, UART_RSA_MSR);
824 result = mode & UART_RSA_MSR_FIFO;
828 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
833 static void enable_rsa(struct uart_8250_port *up)
835 if (up->port.type == PORT_RSA) {
836 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
837 spin_lock_irq(&up->port.lock);
839 spin_unlock_irq(&up->port.lock);
841 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
842 serial_out(up, UART_RSA_FRR, 0);
847 * Attempts to turn off the RSA FIFO. Returns zero on failure.
848 * It is unknown why interrupts were disabled in here. However,
849 * the caller is expected to preserve this behaviour by grabbing
850 * the spinlock before calling this function.
852 static void disable_rsa(struct uart_8250_port *up)
857 if (up->port.type == PORT_RSA &&
858 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
859 spin_lock_irq(&up->port.lock);
861 mode = serial_in(up, UART_RSA_MSR);
862 result = !(mode & UART_RSA_MSR_FIFO);
865 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
866 mode = serial_in(up, UART_RSA_MSR);
867 result = !(mode & UART_RSA_MSR_FIFO);
871 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
872 spin_unlock_irq(&up->port.lock);
875 #endif /* CONFIG_SERIAL_8250_RSA */
878 * This is a quickie test to see how big the FIFO is.
879 * It doesn't work at all the time, more's the pity.
881 static int size_fifo(struct uart_8250_port *up)
883 unsigned char old_fcr, old_mcr, old_lcr;
884 unsigned short old_dl;
887 old_lcr = serial_in(up, UART_LCR);
888 serial_out(up, UART_LCR, 0);
889 old_fcr = serial_in(up, UART_FCR);
890 old_mcr = serial8250_in_MCR(up);
891 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
892 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
893 serial8250_out_MCR(up, UART_MCR_LOOP);
894 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
895 old_dl = serial_dl_read(up);
896 serial_dl_write(up, 0x0001);
897 serial_out(up, UART_LCR, 0x03);
898 for (count = 0; count < 256; count++)
899 serial_out(up, UART_TX, count);
900 mdelay(20);/* FIXME - schedule_timeout */
901 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
902 (count < 256); count++)
903 serial_in(up, UART_RX);
904 serial_out(up, UART_FCR, old_fcr);
905 serial8250_out_MCR(up, old_mcr);
906 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
907 serial_dl_write(up, old_dl);
908 serial_out(up, UART_LCR, old_lcr);
914 * Read UART ID using the divisor method - set DLL and DLM to zero
915 * and the revision will be in DLL and device type in DLM. We
916 * preserve the device state across this.
918 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
920 unsigned char old_lcr;
921 unsigned int id, old_dl;
923 old_lcr = serial_in(p, UART_LCR);
924 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
925 old_dl = serial_dl_read(p);
926 serial_dl_write(p, 0);
927 id = serial_dl_read(p);
928 serial_dl_write(p, old_dl);
930 serial_out(p, UART_LCR, old_lcr);
936 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
937 * When this function is called we know it is at least a StarTech
938 * 16650 V2, but it might be one of several StarTech UARTs, or one of
939 * its clones. (We treat the broken original StarTech 16650 V1 as a
940 * 16550, and why not? Startech doesn't seem to even acknowledge its
943 * What evil have men's minds wrought...
945 static void autoconfig_has_efr(struct uart_8250_port *up)
947 unsigned int id1, id2, id3, rev;
950 * Everything with an EFR has SLEEP
952 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
955 * First we check to see if it's an Oxford Semiconductor UART.
957 * If we have to do this here because some non-National
958 * Semiconductor clone chips lock up if you try writing to the
959 * LSR register (which serial_icr_read does)
963 * Check for Oxford Semiconductor 16C950.
965 * EFR [4] must be set else this test fails.
967 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
968 * claims that it's needed for 952 dual UART's (which are not
969 * recommended for new designs).
972 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
973 serial_out(up, UART_EFR, UART_EFR_ECB);
974 serial_out(up, UART_LCR, 0x00);
975 id1 = serial_icr_read(up, UART_ID1);
976 id2 = serial_icr_read(up, UART_ID2);
977 id3 = serial_icr_read(up, UART_ID3);
978 rev = serial_icr_read(up, UART_REV);
980 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
982 if (id1 == 0x16 && id2 == 0xC9 &&
983 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
984 up->port.type = PORT_16C950;
987 * Enable work around for the Oxford Semiconductor 952 rev B
988 * chip which causes it to seriously miscalculate baud rates
991 if (id3 == 0x52 && rev == 0x01)
992 up->bugs |= UART_BUG_QUOT;
997 * We check for a XR16C850 by setting DLL and DLM to 0, and then
998 * reading back DLL and DLM. The chip type depends on the DLM
1000 * 0x10 - XR16C850 and the DLL contains the chip revision.
1004 id1 = autoconfig_read_divisor_id(up);
1005 DEBUG_AUTOCONF("850id=%04x ", id1);
1008 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1009 up->port.type = PORT_16850;
1014 * It wasn't an XR16C850.
1016 * We distinguish between the '654 and the '650 by counting
1017 * how many bytes are in the FIFO. I'm using this for now,
1018 * since that's the technique that was sent to me in the
1019 * serial driver update, but I'm not convinced this works.
1020 * I've had problems doing this in the past. -TYT
1022 if (size_fifo(up) == 64)
1023 up->port.type = PORT_16654;
1025 up->port.type = PORT_16650V2;
1029 * We detected a chip without a FIFO. Only two fall into
1030 * this category - the original 8250 and the 16450. The
1031 * 16450 has a scratch register (accessible with LCR=0)
1033 static void autoconfig_8250(struct uart_8250_port *up)
1035 unsigned char scratch, status1, status2;
1037 up->port.type = PORT_8250;
1039 scratch = serial_in(up, UART_SCR);
1040 serial_out(up, UART_SCR, 0xa5);
1041 status1 = serial_in(up, UART_SCR);
1042 serial_out(up, UART_SCR, 0x5a);
1043 status2 = serial_in(up, UART_SCR);
1044 serial_out(up, UART_SCR, scratch);
1046 if (status1 == 0xa5 && status2 == 0x5a)
1047 up->port.type = PORT_16450;
1050 static int broken_efr(struct uart_8250_port *up)
1053 * Exar ST16C2550 "A2" devices incorrectly detect as
1054 * having an EFR, and report an ID of 0x0201. See
1055 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1057 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
1064 * We know that the chip has FIFOs. Does it have an EFR? The
1065 * EFR is located in the same register position as the IIR and
1066 * we know the top two bits of the IIR are currently set. The
1067 * EFR should contain zero. Try to read the EFR.
1069 static void autoconfig_16550a(struct uart_8250_port *up)
1071 unsigned char status1, status2;
1072 unsigned int iersave;
1074 up->port.type = PORT_16550A;
1075 up->capabilities |= UART_CAP_FIFO;
1077 if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS))
1081 * Check for presence of the EFR when DLAB is set.
1082 * Only ST16C650V1 UARTs pass this test.
1084 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1085 if (serial_in(up, UART_EFR) == 0) {
1086 serial_out(up, UART_EFR, 0xA8);
1087 if (serial_in(up, UART_EFR) != 0) {
1088 DEBUG_AUTOCONF("EFRv1 ");
1089 up->port.type = PORT_16650;
1090 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1092 serial_out(up, UART_LCR, 0);
1093 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1095 status1 = serial_in(up, UART_IIR) >> 5;
1096 serial_out(up, UART_FCR, 0);
1097 serial_out(up, UART_LCR, 0);
1100 up->port.type = PORT_16550A_FSL64;
1102 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1104 serial_out(up, UART_EFR, 0);
1109 * Maybe it requires 0xbf to be written to the LCR.
1110 * (other ST16C650V2 UARTs, TI16C752A, etc)
1112 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1113 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1114 DEBUG_AUTOCONF("EFRv2 ");
1115 autoconfig_has_efr(up);
1120 * Check for a National Semiconductor SuperIO chip.
1121 * Attempt to switch to bank 2, read the value of the LOOP bit
1122 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1123 * switch back to bank 2, read it from EXCR1 again and check
1124 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1126 serial_out(up, UART_LCR, 0);
1127 status1 = serial8250_in_MCR(up);
1128 serial_out(up, UART_LCR, 0xE0);
1129 status2 = serial_in(up, 0x02); /* EXCR1 */
1131 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1132 serial_out(up, UART_LCR, 0);
1133 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1134 serial_out(up, UART_LCR, 0xE0);
1135 status2 = serial_in(up, 0x02); /* EXCR1 */
1136 serial_out(up, UART_LCR, 0);
1137 serial8250_out_MCR(up, status1);
1139 if ((status2 ^ status1) & UART_MCR_LOOP) {
1140 unsigned short quot;
1142 serial_out(up, UART_LCR, 0xE0);
1144 quot = serial_dl_read(up);
1147 if (ns16550a_goto_highspeed(up))
1148 serial_dl_write(up, quot);
1150 serial_out(up, UART_LCR, 0);
1152 up->port.uartclk = 921600*16;
1153 up->port.type = PORT_NS16550A;
1154 up->capabilities |= UART_NATSEMI;
1160 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1161 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1162 * Try setting it with and without DLAB set. Cheap clones
1163 * set bit 5 without DLAB set.
1165 serial_out(up, UART_LCR, 0);
1166 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1167 status1 = serial_in(up, UART_IIR) >> 5;
1168 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1169 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1170 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1171 status2 = serial_in(up, UART_IIR) >> 5;
1172 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1173 serial_out(up, UART_LCR, 0);
1175 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1177 if (status1 == 6 && status2 == 7) {
1178 up->port.type = PORT_16750;
1179 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1184 * Try writing and reading the UART_IER_UUE bit (b6).
1185 * If it works, this is probably one of the Xscale platform's
1187 * We're going to explicitly set the UUE bit to 0 before
1188 * trying to write and read a 1 just to make sure it's not
1189 * already a 1 and maybe locked there before we even start start.
1191 iersave = serial_in(up, UART_IER);
1192 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1193 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1195 * OK it's in a known zero state, try writing and reading
1196 * without disturbing the current state of the other bits.
1198 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1199 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1202 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1204 DEBUG_AUTOCONF("Xscale ");
1205 up->port.type = PORT_XSCALE;
1206 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1211 * If we got here we couldn't force the IER_UUE bit to 0.
1212 * Log it and continue.
1214 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1216 serial_out(up, UART_IER, iersave);
1219 * We distinguish between 16550A and U6 16550A by counting
1220 * how many bytes are in the FIFO.
1222 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1223 up->port.type = PORT_U6_16550A;
1224 up->capabilities |= UART_CAP_AFE;
1229 * This routine is called by rs_init() to initialize a specific serial
1230 * port. It determines what type of UART chip this serial port is
1231 * using: 8250, 16450, 16550, 16550A. The important question is
1232 * whether or not this UART is a 16550A or not, since this will
1233 * determine whether or not we can use its FIFO features or not.
1235 static void autoconfig(struct uart_8250_port *up)
1237 unsigned char status1, scratch, scratch2, scratch3;
1238 unsigned char save_lcr, save_mcr;
1239 struct uart_port *port = &up->port;
1240 unsigned long flags;
1241 unsigned int old_capabilities;
1243 if (!port->iobase && !port->mapbase && !port->membase)
1246 DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1247 port->name, port->iobase, port->membase);
1250 * We really do need global IRQs disabled here - we're going to
1251 * be frobbing the chips IRQ enable register to see if it exists.
1253 spin_lock_irqsave(&port->lock, flags);
1255 up->capabilities = 0;
1258 if (!(port->flags & UPF_BUGGY_UART)) {
1260 * Do a simple existence test first; if we fail this,
1261 * there's no point trying anything else.
1263 * 0x80 is used as a nonsense port to prevent against
1264 * false positives due to ISA bus float. The
1265 * assumption is that 0x80 is a non-existent port;
1266 * which should be safe since include/asm/io.h also
1267 * makes this assumption.
1269 * Note: this is safe as long as MCR bit 4 is clear
1270 * and the device is in "PC" mode.
1272 scratch = serial_in(up, UART_IER);
1273 serial_out(up, UART_IER, 0);
1278 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1279 * 16C754B) allow only to modify them if an EFR bit is set.
1281 scratch2 = serial_in(up, UART_IER) & 0x0f;
1282 serial_out(up, UART_IER, 0x0F);
1286 scratch3 = serial_in(up, UART_IER) & 0x0f;
1287 serial_out(up, UART_IER, scratch);
1288 if (scratch2 != 0 || scratch3 != 0x0F) {
1290 * We failed; there's nothing here
1292 spin_unlock_irqrestore(&port->lock, flags);
1293 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1294 scratch2, scratch3);
1299 save_mcr = serial8250_in_MCR(up);
1300 save_lcr = serial_in(up, UART_LCR);
1303 * Check to see if a UART is really there. Certain broken
1304 * internal modems based on the Rockwell chipset fail this
1305 * test, because they apparently don't implement the loopback
1306 * test mode. So this test is skipped on the COM 1 through
1307 * COM 4 ports. This *should* be safe, since no board
1308 * manufacturer would be stupid enough to design a board
1309 * that conflicts with COM 1-4 --- we hope!
1311 if (!(port->flags & UPF_SKIP_TEST)) {
1312 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1313 status1 = serial_in(up, UART_MSR) & 0xF0;
1314 serial8250_out_MCR(up, save_mcr);
1315 if (status1 != 0x90) {
1316 spin_unlock_irqrestore(&port->lock, flags);
1317 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1324 * We're pretty sure there's a port here. Lets find out what
1325 * type of port it is. The IIR top two bits allows us to find
1326 * out if it's 8250 or 16450, 16550, 16550A or later. This
1327 * determines what we test for next.
1329 * We also initialise the EFR (if any) to zero for later. The
1330 * EFR occupies the same register location as the FCR and IIR.
1332 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1333 serial_out(up, UART_EFR, 0);
1334 serial_out(up, UART_LCR, 0);
1336 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1338 /* Assign this as it is to truncate any bits above 7. */
1339 scratch = serial_in(up, UART_IIR);
1341 switch (scratch >> 6) {
1343 autoconfig_8250(up);
1346 port->type = PORT_UNKNOWN;
1349 port->type = PORT_16550;
1352 autoconfig_16550a(up);
1356 #ifdef CONFIG_SERIAL_8250_RSA
1358 * Only probe for RSA ports if we got the region.
1360 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1362 port->type = PORT_RSA;
1365 serial_out(up, UART_LCR, save_lcr);
1367 port->fifosize = uart_config[up->port.type].fifo_size;
1368 old_capabilities = up->capabilities;
1369 up->capabilities = uart_config[port->type].flags;
1370 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1372 if (port->type == PORT_UNKNOWN)
1378 #ifdef CONFIG_SERIAL_8250_RSA
1379 if (port->type == PORT_RSA)
1380 serial_out(up, UART_RSA_FRR, 0);
1382 serial8250_out_MCR(up, save_mcr);
1383 serial8250_clear_fifos(up);
1384 serial_in(up, UART_RX);
1385 if (up->capabilities & UART_CAP_UUE)
1386 serial_out(up, UART_IER, UART_IER_UUE);
1388 serial_out(up, UART_IER, 0);
1391 spin_unlock_irqrestore(&port->lock, flags);
1394 * Check if the device is a Fintek F81216A
1396 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1397 fintek_8250_probe(up);
1399 if (up->capabilities != old_capabilities) {
1400 dev_warn(port->dev, "detected caps %08x should be %08x\n",
1401 old_capabilities, up->capabilities);
1404 DEBUG_AUTOCONF("iir=%d ", scratch);
1405 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1408 static void autoconfig_irq(struct uart_8250_port *up)
1410 struct uart_port *port = &up->port;
1411 unsigned char save_mcr, save_ier;
1412 unsigned char save_ICP = 0;
1413 unsigned int ICP = 0;
1417 if (port->flags & UPF_FOURPORT) {
1418 ICP = (port->iobase & 0xfe0) | 0x1f;
1419 save_ICP = inb_p(ICP);
1424 if (uart_console(port))
1427 /* forget possible initially masked and pending IRQ */
1428 probe_irq_off(probe_irq_on());
1429 save_mcr = serial8250_in_MCR(up);
1430 save_ier = serial_in(up, UART_IER);
1431 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1433 irqs = probe_irq_on();
1434 serial8250_out_MCR(up, 0);
1436 if (port->flags & UPF_FOURPORT) {
1437 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1439 serial8250_out_MCR(up,
1440 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1442 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1443 serial_in(up, UART_LSR);
1444 serial_in(up, UART_RX);
1445 serial_in(up, UART_IIR);
1446 serial_in(up, UART_MSR);
1447 serial_out(up, UART_TX, 0xFF);
1449 irq = probe_irq_off(irqs);
1451 serial8250_out_MCR(up, save_mcr);
1452 serial_out(up, UART_IER, save_ier);
1454 if (port->flags & UPF_FOURPORT)
1455 outb_p(save_ICP, ICP);
1457 if (uart_console(port))
1460 port->irq = (irq > 0) ? irq : 0;
1463 static void serial8250_stop_rx(struct uart_port *port)
1465 struct uart_8250_port *up = up_to_u8250p(port);
1467 serial8250_rpm_get(up);
1469 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1470 up->port.read_status_mask &= ~UART_LSR_DR;
1471 serial_port_out(port, UART_IER, up->ier);
1473 serial8250_rpm_put(up);
1477 * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback
1478 * @p: uart 8250 port
1480 * Generic callback usable by 8250 uart drivers to stop rs485 transmission.
1482 void serial8250_em485_stop_tx(struct uart_8250_port *p)
1484 unsigned char mcr = serial8250_in_MCR(p);
1486 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
1487 mcr |= UART_MCR_RTS;
1489 mcr &= ~UART_MCR_RTS;
1490 serial8250_out_MCR(p, mcr);
1493 * Empty the RX FIFO, we are not interested in anything
1494 * received during the half-duplex transmission.
1495 * Enable previously disabled RX interrupts.
1497 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1498 serial8250_clear_and_reinit_fifos(p);
1500 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1501 serial_port_out(&p->port, UART_IER, p->ier);
1504 EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx);
1506 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1508 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1510 struct uart_8250_port *p = em485->port;
1511 unsigned long flags;
1513 serial8250_rpm_get(p);
1514 spin_lock_irqsave(&p->port.lock, flags);
1515 if (em485->active_timer == &em485->stop_tx_timer) {
1516 p->rs485_stop_tx(p);
1517 em485->active_timer = NULL;
1518 em485->tx_stopped = true;
1520 spin_unlock_irqrestore(&p->port.lock, flags);
1521 serial8250_rpm_put(p);
1523 return HRTIMER_NORESTART;
1526 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1528 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
1531 static void start_hrtimer_ns(struct hrtimer *hrt, unsigned long nsec)
1533 hrtimer_start(hrt, ns_to_ktime(nsec), HRTIMER_MODE_REL);
1536 static void __stop_tx_rs485(struct uart_8250_port *p)
1538 struct uart_8250_em485 *em485 = p->em485;
1541 * rs485_stop_tx() is going to set RTS according to config
1542 * AND flush RX FIFO if required.
1544 if (p->port.rs485.delay_rts_after_send > 0) {
1545 em485->active_timer = &em485->stop_tx_timer;
1546 start_hrtimer_ms(&em485->stop_tx_timer,
1547 p->port.rs485.delay_rts_after_send);
1549 p->rs485_stop_tx(p);
1550 em485->active_timer = NULL;
1551 em485->tx_stopped = true;
1555 static inline void __do_stop_tx(struct uart_8250_port *p)
1557 if (serial8250_clear_THRI(p))
1558 serial8250_rpm_put_tx(p);
1561 static inline void __stop_tx(struct uart_8250_port *p)
1563 struct uart_8250_em485 *em485 = p->em485;
1566 unsigned char lsr = serial_in(p, UART_LSR);
1568 p->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1571 * To provide required timing and allow FIFO transfer,
1572 * __stop_tx_rs485() must be called only when both FIFO and
1573 * shift register are empty. It is for device driver to enable
1574 * interrupt on TEMT.
1576 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY) {
1577 if (!(p->capabilities & UART_CAP_NOTEMT))
1578 /* __stop_tx will be called again once TEMT triggers */
1581 if (!(lsr & UART_LSR_THRE))
1582 /* __stop_tx will be called again once THRE triggers */
1586 * On devices with no TEMT interrupt available, start
1587 * a timer for a byte time. The timer will recall
1590 em485->active_timer = &em485->no_temt_timer;
1591 start_hrtimer_ns(&em485->no_temt_timer, em485->no_temt_delay);
1600 static void serial8250_stop_tx(struct uart_port *port)
1602 struct uart_8250_port *up = up_to_u8250p(port);
1604 serial8250_rpm_get(up);
1608 * We really want to stop the transmitter from sending.
1610 if (port->type == PORT_16C950) {
1611 up->acr |= UART_ACR_TXDIS;
1612 serial_icr_write(up, UART_ACR, up->acr);
1614 serial8250_rpm_put(up);
1617 static inline void __start_tx(struct uart_port *port)
1619 struct uart_8250_port *up = up_to_u8250p(port);
1621 if (up->dma && !up->dma->tx_dma(up))
1624 if (serial8250_set_THRI(up)) {
1625 if (up->bugs & UART_BUG_TXEN) {
1628 lsr = serial_in(up, UART_LSR);
1629 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1630 if (lsr & UART_LSR_THRE)
1631 serial8250_tx_chars(up);
1636 * Re-enable the transmitter if we disabled it.
1638 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1639 up->acr &= ~UART_ACR_TXDIS;
1640 serial_icr_write(up, UART_ACR, up->acr);
1645 * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback
1646 * @up: uart 8250 port
1648 * Generic callback usable by 8250 uart drivers to start rs485 transmission.
1649 * Assumes that setting the RTS bit in the MCR register means RTS is high.
1650 * (Some chips use inverse semantics.) Further assumes that reception is
1651 * stoppable by disabling the UART_IER_RDI interrupt. (Some chips set the
1652 * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.)
1654 void serial8250_em485_start_tx(struct uart_8250_port *up)
1656 unsigned char mcr = serial8250_in_MCR(up);
1658 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1659 serial8250_stop_rx(&up->port);
1661 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1662 mcr |= UART_MCR_RTS;
1664 mcr &= ~UART_MCR_RTS;
1665 serial8250_out_MCR(up, mcr);
1667 EXPORT_SYMBOL_GPL(serial8250_em485_start_tx);
1669 static inline void start_tx_rs485(struct uart_port *port)
1671 struct uart_8250_port *up = up_to_u8250p(port);
1672 struct uart_8250_em485 *em485 = up->em485;
1675 * While serial8250_em485_handle_stop_tx() is a noop if
1676 * em485->active_timer != &em485->stop_tx_timer, it might happen that
1677 * the timer is still armed and triggers only after the current bunch of
1678 * chars is send and em485->active_timer == &em485->stop_tx_timer again.
1679 * So cancel the timer. There is still a theoretical race condition if
1680 * the timer is already running and only comes around to check for
1681 * em485->active_timer when &em485->stop_tx_timer is armed again.
1683 if (em485->active_timer == &em485->stop_tx_timer)
1684 hrtimer_try_to_cancel(&em485->stop_tx_timer);
1686 em485->active_timer = NULL;
1688 if (em485->tx_stopped) {
1689 em485->tx_stopped = false;
1691 up->rs485_start_tx(up);
1693 if (up->port.rs485.delay_rts_before_send > 0) {
1694 em485->active_timer = &em485->start_tx_timer;
1695 start_hrtimer_ms(&em485->start_tx_timer,
1696 up->port.rs485.delay_rts_before_send);
1704 static enum hrtimer_restart serial8250_em485_handle_no_temt(struct hrtimer *t)
1706 struct uart_8250_em485 *em485;
1707 struct uart_8250_port *p;
1708 unsigned long flags;
1710 em485 = container_of(t, struct uart_8250_em485, no_temt_timer);
1713 serial8250_rpm_get(p);
1714 spin_lock_irqsave(&p->port.lock, flags);
1715 if (em485->active_timer == &em485->no_temt_timer) {
1716 em485->active_timer = NULL;
1720 spin_unlock_irqrestore(&p->port.lock, flags);
1721 serial8250_rpm_put(p);
1722 return HRTIMER_NORESTART;
1725 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1727 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1729 struct uart_8250_port *p = em485->port;
1730 unsigned long flags;
1732 spin_lock_irqsave(&p->port.lock, flags);
1733 if (em485->active_timer == &em485->start_tx_timer) {
1734 __start_tx(&p->port);
1735 em485->active_timer = NULL;
1737 spin_unlock_irqrestore(&p->port.lock, flags);
1739 return HRTIMER_NORESTART;
1742 static void serial8250_start_tx(struct uart_port *port)
1744 struct uart_8250_port *up = up_to_u8250p(port);
1745 struct uart_8250_em485 *em485 = up->em485;
1747 serial8250_rpm_get_tx(up);
1749 if (!port->x_char && uart_circ_empty(&port->state->xmit))
1753 em485->active_timer == &em485->start_tx_timer)
1757 start_tx_rs485(port);
1762 static void serial8250_throttle(struct uart_port *port)
1764 port->throttle(port);
1767 static void serial8250_unthrottle(struct uart_port *port)
1769 port->unthrottle(port);
1772 static void serial8250_disable_ms(struct uart_port *port)
1774 struct uart_8250_port *up = up_to_u8250p(port);
1776 /* no MSR capabilities */
1777 if (up->bugs & UART_BUG_NOMSR)
1780 mctrl_gpio_disable_ms(up->gpios);
1782 up->ier &= ~UART_IER_MSI;
1783 serial_port_out(port, UART_IER, up->ier);
1786 static void serial8250_enable_ms(struct uart_port *port)
1788 struct uart_8250_port *up = up_to_u8250p(port);
1790 /* no MSR capabilities */
1791 if (up->bugs & UART_BUG_NOMSR)
1794 mctrl_gpio_enable_ms(up->gpios);
1796 up->ier |= UART_IER_MSI;
1798 serial8250_rpm_get(up);
1799 serial_port_out(port, UART_IER, up->ier);
1800 serial8250_rpm_put(up);
1803 void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1805 struct uart_port *port = &up->port;
1807 char flag = TTY_NORMAL;
1809 if (likely(lsr & UART_LSR_DR))
1810 ch = serial_in(up, UART_RX);
1813 * Intel 82571 has a Serial Over Lan device that will
1814 * set UART_LSR_BI without setting UART_LSR_DR when
1815 * it receives a break. To avoid reading from the
1816 * receive buffer without UART_LSR_DR bit set, we
1817 * just force the read character to be 0
1823 lsr |= up->lsr_saved_flags;
1824 up->lsr_saved_flags = 0;
1826 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1827 if (lsr & UART_LSR_BI) {
1828 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1831 * We do the SysRQ and SAK checking
1832 * here because otherwise the break
1833 * may get masked by ignore_status_mask
1834 * or read_status_mask.
1836 if (uart_handle_break(port))
1838 } else if (lsr & UART_LSR_PE)
1839 port->icount.parity++;
1840 else if (lsr & UART_LSR_FE)
1841 port->icount.frame++;
1842 if (lsr & UART_LSR_OE)
1843 port->icount.overrun++;
1846 * Mask off conditions which should be ignored.
1848 lsr &= port->read_status_mask;
1850 if (lsr & UART_LSR_BI) {
1851 dev_dbg(port->dev, "handling break\n");
1853 } else if (lsr & UART_LSR_PE)
1855 else if (lsr & UART_LSR_FE)
1858 if (uart_prepare_sysrq_char(port, ch))
1861 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1863 EXPORT_SYMBOL_GPL(serial8250_read_char);
1866 * serial8250_rx_chars: processes according to the passed in LSR
1867 * value, and returns the remaining LSR bits not handled
1868 * by this Rx routine.
1870 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1872 struct uart_port *port = &up->port;
1873 int max_count = 256;
1876 serial8250_read_char(up, lsr);
1877 if (--max_count == 0)
1879 lsr = serial_in(up, UART_LSR);
1880 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1882 tty_flip_buffer_push(&port->state->port);
1885 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1887 void serial8250_tx_chars(struct uart_8250_port *up)
1889 struct uart_port *port = &up->port;
1890 struct circ_buf *xmit = &port->state->xmit;
1894 uart_xchar_out(port, UART_TX);
1897 if (uart_tx_stopped(port)) {
1898 serial8250_stop_tx(port);
1901 if (uart_circ_empty(xmit)) {
1906 count = up->tx_loadsz;
1908 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1909 if (up->bugs & UART_BUG_TXRACE) {
1911 * The Aspeed BMC virtual UARTs have a bug where data
1912 * may get stuck in the BMC's Tx FIFO from bursts of
1913 * writes on the APB interface.
1915 * Delay back-to-back writes by a read cycle to avoid
1916 * stalling the VUART. Read a register that won't have
1917 * side-effects and discard the result.
1919 serial_in(up, UART_SCR);
1921 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1923 if (uart_circ_empty(xmit))
1925 if ((up->capabilities & UART_CAP_HFIFO) &&
1926 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1928 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1929 if ((up->capabilities & UART_CAP_MINI) &&
1930 !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1932 } while (--count > 0);
1934 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1935 uart_write_wakeup(port);
1938 * With RPM enabled, we have to wait until the FIFO is empty before the
1939 * HW can go idle. So we get here once again with empty FIFO and disable
1940 * the interrupt and RPM in __stop_tx()
1942 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1945 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1947 /* Caller holds uart port lock */
1948 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1950 struct uart_port *port = &up->port;
1951 unsigned int status = serial_in(up, UART_MSR);
1953 status |= up->msr_saved_flags;
1954 up->msr_saved_flags = 0;
1955 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1956 port->state != NULL) {
1957 if (status & UART_MSR_TERI)
1959 if (status & UART_MSR_DDSR)
1961 if (status & UART_MSR_DDCD)
1962 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1963 if (status & UART_MSR_DCTS)
1964 uart_handle_cts_change(port, status & UART_MSR_CTS);
1966 wake_up_interruptible(&port->state->port.delta_msr_wait);
1971 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1973 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1975 switch (iir & 0x3f) {
1976 case UART_IIR_RX_TIMEOUT:
1977 serial8250_rx_dma_flush(up);
1982 return up->dma->rx_dma(up);
1986 * This handles the interrupt from one port.
1988 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1990 unsigned char status;
1991 struct uart_8250_port *up = up_to_u8250p(port);
1992 bool skip_rx = false;
1993 unsigned long flags;
1995 if (iir & UART_IIR_NO_INT)
1998 spin_lock_irqsave(&port->lock, flags);
2000 status = serial_port_in(port, UART_LSR);
2003 * If port is stopped and there are no error conditions in the
2004 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
2005 * overflow. Not servicing, RX FIFO would trigger auto HW flow
2006 * control when FIFO occupancy reaches preset threshold, thus
2007 * halting RX. This only works when auto HW flow control is
2010 if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
2011 (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
2012 !(port->read_status_mask & UART_LSR_DR))
2015 if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
2016 if (!up->dma || handle_rx_dma(up, iir))
2017 status = serial8250_rx_chars(up, status);
2019 serial8250_modem_status(up);
2020 if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE) &&
2021 (up->ier & UART_IER_THRI))
2022 serial8250_tx_chars(up);
2024 uart_unlock_and_check_sysrq_irqrestore(port, flags);
2028 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
2030 static int serial8250_default_handle_irq(struct uart_port *port)
2032 struct uart_8250_port *up = up_to_u8250p(port);
2036 serial8250_rpm_get(up);
2038 iir = serial_port_in(port, UART_IIR);
2039 ret = serial8250_handle_irq(port, iir);
2041 serial8250_rpm_put(up);
2046 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
2047 * have a programmable TX threshold that triggers the THRE interrupt in
2048 * the IIR register. In this case, the THRE interrupt indicates the FIFO
2049 * has space available. Load it up with tx_loadsz bytes.
2051 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
2053 unsigned long flags;
2054 unsigned int iir = serial_port_in(port, UART_IIR);
2056 /* TX Threshold IRQ triggered so load up FIFO */
2057 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
2058 struct uart_8250_port *up = up_to_u8250p(port);
2060 spin_lock_irqsave(&port->lock, flags);
2061 serial8250_tx_chars(up);
2062 spin_unlock_irqrestore(&port->lock, flags);
2065 iir = serial_port_in(port, UART_IIR);
2066 return serial8250_handle_irq(port, iir);
2069 static unsigned int serial8250_tx_empty(struct uart_port *port)
2071 struct uart_8250_port *up = up_to_u8250p(port);
2072 unsigned long flags;
2075 serial8250_rpm_get(up);
2077 spin_lock_irqsave(&port->lock, flags);
2078 lsr = serial_port_in(port, UART_LSR);
2079 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
2080 spin_unlock_irqrestore(&port->lock, flags);
2082 serial8250_rpm_put(up);
2084 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
2087 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
2089 struct uart_8250_port *up = up_to_u8250p(port);
2090 unsigned int status;
2093 serial8250_rpm_get(up);
2094 status = serial8250_modem_status(up);
2095 serial8250_rpm_put(up);
2097 val = serial8250_MSR_to_TIOCM(status);
2099 return mctrl_gpio_get(up->gpios, &val);
2103 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
2105 static unsigned int serial8250_get_mctrl(struct uart_port *port)
2107 if (port->get_mctrl)
2108 return port->get_mctrl(port);
2109 return serial8250_do_get_mctrl(port);
2112 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
2114 struct uart_8250_port *up = up_to_u8250p(port);
2117 mcr = serial8250_TIOCM_to_MCR(mctrl);
2121 serial8250_out_MCR(up, mcr);
2123 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2125 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2127 if (port->set_mctrl)
2128 port->set_mctrl(port, mctrl);
2130 serial8250_do_set_mctrl(port, mctrl);
2133 static void serial8250_break_ctl(struct uart_port *port, int break_state)
2135 struct uart_8250_port *up = up_to_u8250p(port);
2136 unsigned long flags;
2138 serial8250_rpm_get(up);
2139 spin_lock_irqsave(&port->lock, flags);
2140 if (break_state == -1)
2141 up->lcr |= UART_LCR_SBC;
2143 up->lcr &= ~UART_LCR_SBC;
2144 serial_port_out(port, UART_LCR, up->lcr);
2145 spin_unlock_irqrestore(&port->lock, flags);
2146 serial8250_rpm_put(up);
2150 * Wait for transmitter & holding register to empty
2152 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2154 unsigned int status, tmout = 10000;
2156 /* Wait up to 10ms for the character(s) to be sent. */
2158 status = serial_in(up, UART_LSR);
2160 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2162 if ((status & bits) == bits)
2167 touch_nmi_watchdog();
2170 /* Wait up to 1s for flow control if necessary */
2171 if (up->port.flags & UPF_CONS_FLOW) {
2172 for (tmout = 1000000; tmout; tmout--) {
2173 unsigned int msr = serial_in(up, UART_MSR);
2174 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2175 if (msr & UART_MSR_CTS)
2178 touch_nmi_watchdog();
2183 #ifdef CONFIG_CONSOLE_POLL
2185 * Console polling routines for writing and reading from the uart while
2186 * in an interrupt or debug context.
2189 static int serial8250_get_poll_char(struct uart_port *port)
2191 struct uart_8250_port *up = up_to_u8250p(port);
2195 serial8250_rpm_get(up);
2197 lsr = serial_port_in(port, UART_LSR);
2199 if (!(lsr & UART_LSR_DR)) {
2200 status = NO_POLL_CHAR;
2204 status = serial_port_in(port, UART_RX);
2206 serial8250_rpm_put(up);
2211 static void serial8250_put_poll_char(struct uart_port *port,
2215 struct uart_8250_port *up = up_to_u8250p(port);
2217 serial8250_rpm_get(up);
2219 * First save the IER then disable the interrupts
2221 ier = serial_port_in(port, UART_IER);
2222 if (up->capabilities & UART_CAP_UUE)
2223 serial_port_out(port, UART_IER, UART_IER_UUE);
2225 serial_port_out(port, UART_IER, 0);
2227 wait_for_xmitr(up, BOTH_EMPTY);
2229 * Send the character out.
2231 serial_port_out(port, UART_TX, c);
2234 * Finally, wait for transmitter to become empty
2235 * and restore the IER
2237 wait_for_xmitr(up, BOTH_EMPTY);
2238 serial_port_out(port, UART_IER, ier);
2239 serial8250_rpm_put(up);
2242 #endif /* CONFIG_CONSOLE_POLL */
2244 int serial8250_do_startup(struct uart_port *port)
2246 struct uart_8250_port *up = up_to_u8250p(port);
2247 unsigned long flags;
2248 unsigned char lsr, iir;
2251 if (!port->fifosize)
2252 port->fifosize = uart_config[port->type].fifo_size;
2254 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2255 if (!up->capabilities)
2256 up->capabilities = uart_config[port->type].flags;
2259 if (port->iotype != up->cur_iotype)
2260 set_io_from_upio(port);
2262 serial8250_rpm_get(up);
2263 if (port->type == PORT_16C950) {
2264 /* Wake up and initialize UART */
2266 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2267 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2268 serial_port_out(port, UART_IER, 0);
2269 serial_port_out(port, UART_LCR, 0);
2270 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2271 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2272 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2273 serial_port_out(port, UART_LCR, 0);
2276 if (port->type == PORT_DA830) {
2277 /* Reset the port */
2278 serial_port_out(port, UART_IER, 0);
2279 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2282 /* Enable Tx, Rx and free run mode */
2283 serial_port_out(port, UART_DA830_PWREMU_MGMT,
2284 UART_DA830_PWREMU_MGMT_UTRST |
2285 UART_DA830_PWREMU_MGMT_URRST |
2286 UART_DA830_PWREMU_MGMT_FREE);
2289 if (port->type == PORT_NPCM) {
2291 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2292 * register). Enable it, and set TIOC (timeout interrupt
2293 * comparator) to be 0x20 for correct operation.
2295 serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2298 #ifdef CONFIG_SERIAL_8250_RSA
2300 * If this is an RSA port, see if we can kick it up to the
2301 * higher speed clock.
2307 * Clear the FIFO buffers and disable them.
2308 * (they will be reenabled in set_termios())
2310 serial8250_clear_fifos(up);
2313 * Clear the interrupt registers.
2315 serial_port_in(port, UART_LSR);
2316 serial_port_in(port, UART_RX);
2317 serial_port_in(port, UART_IIR);
2318 serial_port_in(port, UART_MSR);
2321 * At this point, there's no way the LSR could still be 0xff;
2322 * if it is, then bail out, because there's likely no UART
2325 if (!(port->flags & UPF_BUGGY_UART) &&
2326 (serial_port_in(port, UART_LSR) == 0xff)) {
2327 dev_info_ratelimited(port->dev, "LSR safety check engaged!\n");
2333 * For a XR16C850, we need to set the trigger levels
2335 if (port->type == PORT_16850) {
2338 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2340 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2341 serial_port_out(port, UART_FCTR,
2342 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2343 serial_port_out(port, UART_TRG, UART_TRG_96);
2344 serial_port_out(port, UART_FCTR,
2345 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2346 serial_port_out(port, UART_TRG, UART_TRG_96);
2348 serial_port_out(port, UART_LCR, 0);
2352 * For the Altera 16550 variants, set TX threshold trigger level.
2354 if (((port->type == PORT_ALTR_16550_F32) ||
2355 (port->type == PORT_ALTR_16550_F64) ||
2356 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2357 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2358 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2359 dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2361 serial_port_out(port, UART_ALTR_AFR,
2362 UART_ALTR_EN_TXFIFO_LW);
2363 serial_port_out(port, UART_ALTR_TX_LOW,
2364 port->fifosize - up->tx_loadsz);
2365 port->handle_irq = serial8250_tx_threshold_handle_irq;
2369 /* Check if we need to have shared IRQs */
2370 if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2371 up->port.irqflags |= IRQF_SHARED;
2373 if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2376 if (port->irqflags & IRQF_SHARED)
2377 disable_irq_nosync(port->irq);
2380 * Test for UARTs that do not reassert THRE when the
2381 * transmitter is idle and the interrupt has already
2382 * been cleared. Real 16550s should always reassert
2383 * this interrupt whenever the transmitter is idle and
2384 * the interrupt is enabled. Delays are necessary to
2385 * allow register changes to become visible.
2387 spin_lock_irqsave(&port->lock, flags);
2389 wait_for_xmitr(up, UART_LSR_THRE);
2390 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2391 udelay(1); /* allow THRE to set */
2392 iir1 = serial_port_in(port, UART_IIR);
2393 serial_port_out(port, UART_IER, 0);
2394 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2395 udelay(1); /* allow a working UART time to re-assert THRE */
2396 iir = serial_port_in(port, UART_IIR);
2397 serial_port_out(port, UART_IER, 0);
2399 spin_unlock_irqrestore(&port->lock, flags);
2401 if (port->irqflags & IRQF_SHARED)
2402 enable_irq(port->irq);
2405 * If the interrupt is not reasserted, or we otherwise
2406 * don't trust the iir, setup a timer to kick the UART
2407 * on a regular basis.
2409 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2410 up->port.flags & UPF_BUG_THRE) {
2411 up->bugs |= UART_BUG_THRE;
2415 retval = up->ops->setup_irq(up);
2420 * Now, initialize the UART
2422 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2424 spin_lock_irqsave(&port->lock, flags);
2425 if (up->port.flags & UPF_FOURPORT) {
2427 up->port.mctrl |= TIOCM_OUT1;
2430 * Most PC uarts need OUT2 raised to enable interrupts.
2433 up->port.mctrl |= TIOCM_OUT2;
2435 serial8250_set_mctrl(port, port->mctrl);
2438 * Serial over Lan (SoL) hack:
2439 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2440 * used for Serial Over Lan. Those chips take a longer time than a
2441 * normal serial device to signalize that a transmission data was
2442 * queued. Due to that, the above test generally fails. One solution
2443 * would be to delay the reading of iir. However, this is not
2444 * reliable, since the timeout is variable. So, let's just don't
2445 * test if we receive TX irq. This way, we'll never enable
2448 if (up->port.quirks & UPQ_NO_TXEN_TEST)
2449 goto dont_test_tx_en;
2452 * Do a quick test to see if we receive an interrupt when we enable
2455 serial_port_out(port, UART_IER, UART_IER_THRI);
2456 lsr = serial_port_in(port, UART_LSR);
2457 iir = serial_port_in(port, UART_IIR);
2458 serial_port_out(port, UART_IER, 0);
2460 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2461 if (!(up->bugs & UART_BUG_TXEN)) {
2462 up->bugs |= UART_BUG_TXEN;
2463 dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2466 up->bugs &= ~UART_BUG_TXEN;
2470 spin_unlock_irqrestore(&port->lock, flags);
2473 * Clear the interrupt registers again for luck, and clear the
2474 * saved flags to avoid getting false values from polling
2475 * routines or the previous session.
2477 serial_port_in(port, UART_LSR);
2478 serial_port_in(port, UART_RX);
2479 serial_port_in(port, UART_IIR);
2480 serial_port_in(port, UART_MSR);
2481 up->lsr_saved_flags = 0;
2482 up->msr_saved_flags = 0;
2485 * Request DMA channels for both RX and TX.
2488 const char *msg = NULL;
2490 if (uart_console(port))
2491 msg = "forbid DMA for kernel console";
2492 else if (serial8250_request_dma(up))
2493 msg = "failed to request DMA";
2495 dev_warn_ratelimited(port->dev, "%s\n", msg);
2501 * Set the IER shadow for rx interrupts but defer actual interrupt
2502 * enable until after the FIFOs are enabled; otherwise, an already-
2503 * active sender can swamp the interrupt handler with "too much work".
2505 up->ier = UART_IER_RLSI | UART_IER_RDI;
2507 if (port->flags & UPF_FOURPORT) {
2510 * Enable interrupts on the AST Fourport board
2512 icp = (port->iobase & 0xfe0) | 0x01f;
2518 serial8250_rpm_put(up);
2521 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2523 static int serial8250_startup(struct uart_port *port)
2526 return port->startup(port);
2527 return serial8250_do_startup(port);
2530 void serial8250_do_shutdown(struct uart_port *port)
2532 struct uart_8250_port *up = up_to_u8250p(port);
2533 unsigned long flags;
2535 serial8250_rpm_get(up);
2537 * Disable interrupts from this port
2539 spin_lock_irqsave(&port->lock, flags);
2541 serial_port_out(port, UART_IER, 0);
2542 spin_unlock_irqrestore(&port->lock, flags);
2544 synchronize_irq(port->irq);
2547 serial8250_release_dma(up);
2549 spin_lock_irqsave(&port->lock, flags);
2550 if (port->flags & UPF_FOURPORT) {
2551 /* reset interrupts on the AST Fourport board */
2552 inb((port->iobase & 0xfe0) | 0x1f);
2553 port->mctrl |= TIOCM_OUT1;
2555 port->mctrl &= ~TIOCM_OUT2;
2557 serial8250_set_mctrl(port, port->mctrl);
2558 spin_unlock_irqrestore(&port->lock, flags);
2561 * Disable break condition and FIFOs
2563 serial_port_out(port, UART_LCR,
2564 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2565 serial8250_clear_fifos(up);
2567 #ifdef CONFIG_SERIAL_8250_RSA
2569 * Reset the RSA board back to 115kbps compat mode.
2575 * Read data port to reset things, and then unlink from
2578 serial_port_in(port, UART_RX);
2579 serial8250_rpm_put(up);
2581 up->ops->release_irq(up);
2583 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2585 static void serial8250_shutdown(struct uart_port *port)
2588 port->shutdown(port);
2590 serial8250_do_shutdown(port);
2593 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2594 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2597 struct uart_port *port = &up->port;
2599 return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2602 static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2606 upf_t magic_multiplier = port->flags & UPF_MAGIC_MULTIPLIER;
2607 struct uart_8250_port *up = up_to_u8250p(port);
2611 * Handle magic divisors for baud rates above baud_base on SMSC
2612 * Super I/O chips. We clamp custom rates from clk/6 and clk/12
2613 * up to clk/4 (0x8001) and clk/8 (0x8002) respectively. These
2614 * magic divisors actually reprogram the baud rate generator's
2615 * reference clock derived from chips's 14.318MHz clock input.
2617 * Documentation claims that with these magic divisors the base
2618 * frequencies of 7.3728MHz and 3.6864MHz are used respectively
2619 * for the extra baud rates of 460800bps and 230400bps rather
2620 * than the usual base frequency of 1.8462MHz. However empirical
2621 * evidence contradicts that.
2623 * Instead bit 7 of the DLM register (bit 15 of the divisor) is
2624 * effectively used as a clock prescaler selection bit for the
2625 * base frequency of 7.3728MHz, always used. If set to 0, then
2626 * the base frequency is divided by 4 for use by the Baud Rate
2627 * Generator, for the usual arrangement where the value of 1 of
2628 * the divisor produces the baud rate of 115200bps. Conversely,
2629 * if set to 1 and high-speed operation has been enabled with the
2630 * Serial Port Mode Register in the Device Configuration Space,
2631 * then the base frequency is supplied directly to the Baud Rate
2632 * Generator, so for the divisor values of 0x8001, 0x8002, 0x8003,
2633 * 0x8004, etc. the respective baud rates produced are 460800bps,
2634 * 230400bps, 153600bps, 115200bps, etc.
2636 * In all cases only low 15 bits of the divisor are used to divide
2637 * the baud base and therefore 32767 is the maximum divisor value
2638 * possible, even though documentation says that the programmable
2639 * Baud Rate Generator is capable of dividing the internal PLL
2640 * clock by any divisor from 1 to 65535.
2642 if (magic_multiplier && baud >= port->uartclk / 6)
2644 else if (magic_multiplier && baud >= port->uartclk / 12)
2646 else if (up->port.type == PORT_NPCM)
2647 quot = npcm_get_divisor(up, baud);
2649 quot = uart_get_divisor(port, baud);
2652 * Oxford Semi 952 rev B workaround
2654 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2660 static unsigned int serial8250_get_divisor(struct uart_port *port,
2664 if (port->get_divisor)
2665 return port->get_divisor(port, baud, frac);
2667 return serial8250_do_get_divisor(port, baud, frac);
2670 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2675 cval = UART_LCR_WLEN(tty_get_char_size(c_cflag));
2677 if (c_cflag & CSTOPB)
2678 cval |= UART_LCR_STOP;
2679 if (c_cflag & PARENB) {
2680 cval |= UART_LCR_PARITY;
2681 if (up->bugs & UART_BUG_PARITY)
2682 up->fifo_bug = true;
2684 if (!(c_cflag & PARODD))
2685 cval |= UART_LCR_EPAR;
2687 if (c_cflag & CMSPAR)
2688 cval |= UART_LCR_SPAR;
2694 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2695 unsigned int quot, unsigned int quot_frac)
2697 struct uart_8250_port *up = up_to_u8250p(port);
2699 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2700 if (is_omap1510_8250(up)) {
2701 if (baud == 115200) {
2703 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2705 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2709 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2710 * otherwise just set DLAB
2712 if (up->capabilities & UART_NATSEMI)
2713 serial_port_out(port, UART_LCR, 0xe0);
2715 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2717 serial_dl_write(up, quot);
2719 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2721 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2722 unsigned int quot, unsigned int quot_frac)
2724 if (port->set_divisor)
2725 port->set_divisor(port, baud, quot, quot_frac);
2727 serial8250_do_set_divisor(port, baud, quot, quot_frac);
2730 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2731 struct ktermios *termios,
2732 struct ktermios *old)
2734 unsigned int tolerance = port->uartclk / 100;
2739 * Handle magic divisors for baud rates above baud_base on SMSC
2740 * Super I/O chips. Enable custom rates of clk/4 and clk/8, but
2741 * disable divisor values beyond 32767, which are unavailable.
2743 if (port->flags & UPF_MAGIC_MULTIPLIER) {
2744 min = port->uartclk / 16 / UART_DIV_MAX >> 1;
2745 max = (port->uartclk + tolerance) / 4;
2747 min = port->uartclk / 16 / UART_DIV_MAX;
2748 max = (port->uartclk + tolerance) / 16;
2752 * Ask the core to calculate the divisor for us.
2753 * Allow 1% tolerance at the upper limit so uart clks marginally
2754 * slower than nominal still match standard baud rates without
2755 * causing transmission errors.
2757 return uart_get_baud_rate(port, termios, old, min, max);
2761 * Note in order to avoid the tty port mutex deadlock don't use the next method
2762 * within the uart port callbacks. Primarily it's supposed to be utilized to
2763 * handle a sudden reference clock rate change.
2765 void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk)
2767 struct uart_8250_port *up = up_to_u8250p(port);
2768 struct tty_port *tport = &port->state->port;
2769 unsigned int baud, quot, frac = 0;
2770 struct ktermios *termios;
2771 struct tty_struct *tty;
2772 unsigned long flags;
2774 tty = tty_port_tty_get(tport);
2776 mutex_lock(&tport->mutex);
2777 port->uartclk = uartclk;
2778 mutex_unlock(&tport->mutex);
2782 down_write(&tty->termios_rwsem);
2783 mutex_lock(&tport->mutex);
2785 if (port->uartclk == uartclk)
2788 port->uartclk = uartclk;
2790 if (!tty_port_initialized(tport))
2793 termios = &tty->termios;
2795 baud = serial8250_get_baud_rate(port, termios, NULL);
2796 quot = serial8250_get_divisor(port, baud, &frac);
2798 serial8250_rpm_get(up);
2799 spin_lock_irqsave(&port->lock, flags);
2801 uart_update_timeout(port, termios->c_cflag, baud);
2803 serial8250_set_divisor(port, baud, quot, frac);
2804 serial_port_out(port, UART_LCR, up->lcr);
2806 spin_unlock_irqrestore(&port->lock, flags);
2807 serial8250_rpm_put(up);
2810 mutex_unlock(&tport->mutex);
2811 up_write(&tty->termios_rwsem);
2814 EXPORT_SYMBOL_GPL(serial8250_update_uartclk);
2817 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2818 struct ktermios *old)
2820 struct uart_8250_port *up = up_to_u8250p(port);
2822 unsigned long flags;
2823 unsigned int baud, quot, frac = 0;
2825 if (up->capabilities & UART_CAP_MINI) {
2826 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2827 if ((termios->c_cflag & CSIZE) == CS5 ||
2828 (termios->c_cflag & CSIZE) == CS6)
2829 termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2831 cval = serial8250_compute_lcr(up, termios->c_cflag);
2833 baud = serial8250_get_baud_rate(port, termios, old);
2834 quot = serial8250_get_divisor(port, baud, &frac);
2837 * Ok, we're now changing the port state. Do it with
2838 * interrupts disabled.
2840 serial8250_rpm_get(up);
2841 spin_lock_irqsave(&port->lock, flags);
2843 up->lcr = cval; /* Save computed LCR */
2845 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2846 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2847 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2848 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2849 up->fcr |= UART_FCR_TRIGGER_1;
2854 * MCR-based auto flow control. When AFE is enabled, RTS will be
2855 * deasserted when the receive FIFO contains more characters than
2856 * the trigger, or the MCR RTS bit is cleared.
2858 if (up->capabilities & UART_CAP_AFE) {
2859 up->mcr &= ~UART_MCR_AFE;
2860 if (termios->c_cflag & CRTSCTS)
2861 up->mcr |= UART_MCR_AFE;
2865 * Update the per-port timeout.
2867 uart_update_timeout(port, termios->c_cflag, baud);
2869 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2870 if (termios->c_iflag & INPCK)
2871 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2872 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2873 port->read_status_mask |= UART_LSR_BI;
2876 * Characteres to ignore
2878 port->ignore_status_mask = 0;
2879 if (termios->c_iflag & IGNPAR)
2880 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2881 if (termios->c_iflag & IGNBRK) {
2882 port->ignore_status_mask |= UART_LSR_BI;
2884 * If we're ignoring parity and break indicators,
2885 * ignore overruns too (for real raw support).
2887 if (termios->c_iflag & IGNPAR)
2888 port->ignore_status_mask |= UART_LSR_OE;
2892 * ignore all characters if CREAD is not set
2894 if ((termios->c_cflag & CREAD) == 0)
2895 port->ignore_status_mask |= UART_LSR_DR;
2898 * CTS flow control flag and modem status interrupts
2900 up->ier &= ~UART_IER_MSI;
2901 if (!(up->bugs & UART_BUG_NOMSR) &&
2902 UART_ENABLE_MS(&up->port, termios->c_cflag))
2903 up->ier |= UART_IER_MSI;
2904 if (up->capabilities & UART_CAP_UUE)
2905 up->ier |= UART_IER_UUE;
2906 if (up->capabilities & UART_CAP_RTOIE)
2907 up->ier |= UART_IER_RTOIE;
2909 serial_port_out(port, UART_IER, up->ier);
2911 if (up->capabilities & UART_CAP_EFR) {
2912 unsigned char efr = 0;
2914 * TI16C752/Startech hardware flow control. FIXME:
2915 * - TI16C752 requires control thresholds to be set.
2916 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2918 if (termios->c_cflag & CRTSCTS)
2919 efr |= UART_EFR_CTS;
2921 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2922 if (port->flags & UPF_EXAR_EFR)
2923 serial_port_out(port, UART_XR_EFR, efr);
2925 serial_port_out(port, UART_EFR, efr);
2928 serial8250_set_divisor(port, baud, quot, frac);
2930 if (up->capabilities & UART_CAP_NOTEMT)
2931 serial8250_em485_update_temt_delay(up, termios->c_cflag, baud);
2934 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2935 * is written without DLAB set, this mode will be disabled.
2937 if (port->type == PORT_16750)
2938 serial_port_out(port, UART_FCR, up->fcr);
2940 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2941 if (port->type != PORT_16750) {
2942 /* emulated UARTs (Lucent Venus 167x) need two steps */
2943 if (up->fcr & UART_FCR_ENABLE_FIFO)
2944 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2945 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2947 serial8250_set_mctrl(port, port->mctrl);
2948 spin_unlock_irqrestore(&port->lock, flags);
2949 serial8250_rpm_put(up);
2951 /* Don't rewrite B0 */
2952 if (tty_termios_baud_rate(termios))
2953 tty_termios_encode_baud_rate(termios, baud, baud);
2955 EXPORT_SYMBOL(serial8250_do_set_termios);
2958 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2959 struct ktermios *old)
2961 if (port->set_termios)
2962 port->set_termios(port, termios, old);
2964 serial8250_do_set_termios(port, termios, old);
2967 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2969 if (termios->c_line == N_PPS) {
2970 port->flags |= UPF_HARDPPS_CD;
2971 spin_lock_irq(&port->lock);
2972 serial8250_enable_ms(port);
2973 spin_unlock_irq(&port->lock);
2975 port->flags &= ~UPF_HARDPPS_CD;
2976 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2977 spin_lock_irq(&port->lock);
2978 serial8250_disable_ms(port);
2979 spin_unlock_irq(&port->lock);
2983 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2986 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2988 if (port->set_ldisc)
2989 port->set_ldisc(port, termios);
2991 serial8250_do_set_ldisc(port, termios);
2994 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2995 unsigned int oldstate)
2997 struct uart_8250_port *p = up_to_u8250p(port);
2999 serial8250_set_sleep(p, state != 0);
3001 EXPORT_SYMBOL(serial8250_do_pm);
3004 serial8250_pm(struct uart_port *port, unsigned int state,
3005 unsigned int oldstate)
3008 port->pm(port, state, oldstate);
3010 serial8250_do_pm(port, state, oldstate);
3013 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
3015 if (pt->port.mapsize)
3016 return pt->port.mapsize;
3017 if (pt->port.iotype == UPIO_AU) {
3018 if (pt->port.type == PORT_RT2880)
3022 if (is_omap1_8250(pt))
3023 return 0x16 << pt->port.regshift;
3025 return 8 << pt->port.regshift;
3029 * Resource handling.
3031 static int serial8250_request_std_resource(struct uart_8250_port *up)
3033 unsigned int size = serial8250_port_size(up);
3034 struct uart_port *port = &up->port;
3037 switch (port->iotype) {
3047 if (!request_mem_region(port->mapbase, size, "serial")) {
3052 if (port->flags & UPF_IOREMAP) {
3053 port->membase = ioremap(port->mapbase, size);
3054 if (!port->membase) {
3055 release_mem_region(port->mapbase, size);
3063 if (!request_region(port->iobase, size, "serial"))
3070 static void serial8250_release_std_resource(struct uart_8250_port *up)
3072 unsigned int size = serial8250_port_size(up);
3073 struct uart_port *port = &up->port;
3075 switch (port->iotype) {
3085 if (port->flags & UPF_IOREMAP) {
3086 iounmap(port->membase);
3087 port->membase = NULL;
3090 release_mem_region(port->mapbase, size);
3095 release_region(port->iobase, size);
3100 static void serial8250_release_port(struct uart_port *port)
3102 struct uart_8250_port *up = up_to_u8250p(port);
3104 serial8250_release_std_resource(up);
3107 static int serial8250_request_port(struct uart_port *port)
3109 struct uart_8250_port *up = up_to_u8250p(port);
3111 return serial8250_request_std_resource(up);
3114 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
3116 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3117 unsigned char bytes;
3119 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
3121 return bytes ? bytes : -EOPNOTSUPP;
3124 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
3126 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3129 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
3132 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
3133 if (bytes < conf_type->rxtrig_bytes[i])
3134 /* Use the nearest lower value */
3135 return (--i) << UART_FCR_R_TRIG_SHIFT;
3138 return UART_FCR_R_TRIG_11;
3141 static int do_get_rxtrig(struct tty_port *port)
3143 struct uart_state *state = container_of(port, struct uart_state, port);
3144 struct uart_port *uport = state->uart_port;
3145 struct uart_8250_port *up = up_to_u8250p(uport);
3147 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3150 return fcr_get_rxtrig_bytes(up);
3153 static int do_serial8250_get_rxtrig(struct tty_port *port)
3157 mutex_lock(&port->mutex);
3158 rxtrig_bytes = do_get_rxtrig(port);
3159 mutex_unlock(&port->mutex);
3161 return rxtrig_bytes;
3164 static ssize_t rx_trig_bytes_show(struct device *dev,
3165 struct device_attribute *attr, char *buf)
3167 struct tty_port *port = dev_get_drvdata(dev);
3170 rxtrig_bytes = do_serial8250_get_rxtrig(port);
3171 if (rxtrig_bytes < 0)
3172 return rxtrig_bytes;
3174 return sysfs_emit(buf, "%d\n", rxtrig_bytes);
3177 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
3179 struct uart_state *state = container_of(port, struct uart_state, port);
3180 struct uart_port *uport = state->uart_port;
3181 struct uart_8250_port *up = up_to_u8250p(uport);
3184 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
3188 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3192 serial8250_clear_fifos(up);
3193 up->fcr &= ~UART_FCR_TRIGGER_MASK;
3194 up->fcr |= (unsigned char)rxtrig;
3195 serial_out(up, UART_FCR, up->fcr);
3199 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3203 mutex_lock(&port->mutex);
3204 ret = do_set_rxtrig(port, bytes);
3205 mutex_unlock(&port->mutex);
3210 static ssize_t rx_trig_bytes_store(struct device *dev,
3211 struct device_attribute *attr, const char *buf, size_t count)
3213 struct tty_port *port = dev_get_drvdata(dev);
3214 unsigned char bytes;
3220 ret = kstrtou8(buf, 10, &bytes);
3224 ret = do_serial8250_set_rxtrig(port, bytes);
3231 static DEVICE_ATTR_RW(rx_trig_bytes);
3233 static struct attribute *serial8250_dev_attrs[] = {
3234 &dev_attr_rx_trig_bytes.attr,
3238 static struct attribute_group serial8250_dev_attr_group = {
3239 .attrs = serial8250_dev_attrs,
3242 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3244 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3246 if (conf_type->rxtrig_bytes[0])
3247 up->port.attr_group = &serial8250_dev_attr_group;
3250 static void serial8250_config_port(struct uart_port *port, int flags)
3252 struct uart_8250_port *up = up_to_u8250p(port);
3256 * Find the region that we can probe for. This in turn
3257 * tells us whether we can probe for the type of port.
3259 ret = serial8250_request_std_resource(up);
3263 if (port->iotype != up->cur_iotype)
3264 set_io_from_upio(port);
3266 if (flags & UART_CONFIG_TYPE)
3269 if (port->rs485.flags & SER_RS485_ENABLED)
3270 port->rs485_config(port, &port->rs485);
3272 /* if access method is AU, it is a 16550 with a quirk */
3273 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3274 up->bugs |= UART_BUG_NOMSR;
3276 /* HW bugs may trigger IRQ while IIR == NO_INT */
3277 if (port->type == PORT_TEGRA)
3278 up->bugs |= UART_BUG_NOMSR;
3280 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3283 if (port->type == PORT_UNKNOWN)
3284 serial8250_release_std_resource(up);
3286 register_dev_spec_attr_grp(up);
3287 up->fcr = uart_config[up->port.type].fcr;
3291 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3293 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3294 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3295 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3296 ser->type == PORT_STARTECH)
3301 static const char *serial8250_type(struct uart_port *port)
3303 int type = port->type;
3305 if (type >= ARRAY_SIZE(uart_config))
3307 return uart_config[type].name;
3310 static const struct uart_ops serial8250_pops = {
3311 .tx_empty = serial8250_tx_empty,
3312 .set_mctrl = serial8250_set_mctrl,
3313 .get_mctrl = serial8250_get_mctrl,
3314 .stop_tx = serial8250_stop_tx,
3315 .start_tx = serial8250_start_tx,
3316 .throttle = serial8250_throttle,
3317 .unthrottle = serial8250_unthrottle,
3318 .stop_rx = serial8250_stop_rx,
3319 .enable_ms = serial8250_enable_ms,
3320 .break_ctl = serial8250_break_ctl,
3321 .startup = serial8250_startup,
3322 .shutdown = serial8250_shutdown,
3323 .set_termios = serial8250_set_termios,
3324 .set_ldisc = serial8250_set_ldisc,
3325 .pm = serial8250_pm,
3326 .type = serial8250_type,
3327 .release_port = serial8250_release_port,
3328 .request_port = serial8250_request_port,
3329 .config_port = serial8250_config_port,
3330 .verify_port = serial8250_verify_port,
3331 #ifdef CONFIG_CONSOLE_POLL
3332 .poll_get_char = serial8250_get_poll_char,
3333 .poll_put_char = serial8250_put_poll_char,
3337 void serial8250_init_port(struct uart_8250_port *up)
3339 struct uart_port *port = &up->port;
3341 spin_lock_init(&port->lock);
3342 port->ops = &serial8250_pops;
3343 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3345 up->cur_iotype = 0xFF;
3347 EXPORT_SYMBOL_GPL(serial8250_init_port);
3349 void serial8250_set_defaults(struct uart_8250_port *up)
3351 struct uart_port *port = &up->port;
3353 if (up->port.flags & UPF_FIXED_TYPE) {
3354 unsigned int type = up->port.type;
3356 if (!up->port.fifosize)
3357 up->port.fifosize = uart_config[type].fifo_size;
3359 up->tx_loadsz = uart_config[type].tx_loadsz;
3360 if (!up->capabilities)
3361 up->capabilities = uart_config[type].flags;
3364 set_io_from_upio(port);
3366 /* default dma handlers */
3368 if (!up->dma->tx_dma)
3369 up->dma->tx_dma = serial8250_tx_dma;
3370 if (!up->dma->rx_dma)
3371 up->dma->rx_dma = serial8250_rx_dma;
3374 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3376 #ifdef CONFIG_SERIAL_8250_CONSOLE
3378 static void serial8250_console_putchar(struct uart_port *port, unsigned char ch)
3380 struct uart_8250_port *up = up_to_u8250p(port);
3382 wait_for_xmitr(up, UART_LSR_THRE);
3383 serial_port_out(port, UART_TX, ch);
3387 * Restore serial console when h/w power-off detected
3389 static void serial8250_console_restore(struct uart_8250_port *up)
3391 struct uart_port *port = &up->port;
3392 struct ktermios termios;
3393 unsigned int baud, quot, frac = 0;
3395 termios.c_cflag = port->cons->cflag;
3396 if (port->state->port.tty && termios.c_cflag == 0)
3397 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3399 baud = serial8250_get_baud_rate(port, &termios, NULL);
3400 quot = serial8250_get_divisor(port, baud, &frac);
3402 serial8250_set_divisor(port, baud, quot, frac);
3403 serial_port_out(port, UART_LCR, up->lcr);
3404 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
3408 * Print a string to the serial port trying not to disturb
3409 * any possible real use of the port...
3411 * The console_lock must be held when we get here.
3413 * Doing runtime PM is really a bad idea for the kernel console.
3414 * Thus, we assume the function is called when device is powered up.
3416 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3419 struct uart_8250_em485 *em485 = up->em485;
3420 struct uart_port *port = &up->port;
3421 unsigned long flags;
3425 touch_nmi_watchdog();
3427 if (oops_in_progress)
3428 locked = spin_trylock_irqsave(&port->lock, flags);
3430 spin_lock_irqsave(&port->lock, flags);
3433 * First save the IER then disable the interrupts
3435 ier = serial_port_in(port, UART_IER);
3437 if (up->capabilities & UART_CAP_UUE)
3438 serial_port_out(port, UART_IER, UART_IER_UUE);
3440 serial_port_out(port, UART_IER, 0);
3442 /* check scratch reg to see if port powered off during system sleep */
3443 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3444 serial8250_console_restore(up);
3449 if (em485->tx_stopped)
3450 up->rs485_start_tx(up);
3451 mdelay(port->rs485.delay_rts_before_send);
3454 uart_console_write(port, s, count, serial8250_console_putchar);
3457 * Finally, wait for transmitter to become empty
3458 * and restore the IER
3460 wait_for_xmitr(up, BOTH_EMPTY);
3463 mdelay(port->rs485.delay_rts_after_send);
3464 if (em485->tx_stopped)
3465 up->rs485_stop_tx(up);
3468 serial_port_out(port, UART_IER, ier);
3471 * The receive handling will happen properly because the
3472 * receive ready bit will still be set; it is not cleared
3473 * on read. However, modem control will not, we must
3474 * call it if we have saved something in the saved flags
3475 * while processing with interrupts off.
3477 if (up->msr_saved_flags)
3478 serial8250_modem_status(up);
3481 spin_unlock_irqrestore(&port->lock, flags);
3484 static unsigned int probe_baud(struct uart_port *port)
3486 unsigned char lcr, dll, dlm;
3489 lcr = serial_port_in(port, UART_LCR);
3490 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3491 dll = serial_port_in(port, UART_DLL);
3492 dlm = serial_port_in(port, UART_DLM);
3493 serial_port_out(port, UART_LCR, lcr);
3495 quot = (dlm << 8) | dll;
3496 return (port->uartclk / 16) / quot;
3499 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3507 if (!port->iobase && !port->membase)
3511 uart_parse_options(options, &baud, &parity, &bits, &flow);
3513 baud = probe_baud(port);
3515 ret = uart_set_options(port, port->cons, baud, parity, bits, flow);
3520 pm_runtime_get_sync(port->dev);
3525 int serial8250_console_exit(struct uart_port *port)
3528 pm_runtime_put_sync(port->dev);
3533 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3535 MODULE_LICENSE("GPL");