1 // SPDX-License-Identifier: GPL-2.0+
3 * Base port operations for 8250/16550-type serial ports
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
8 * A note about mapbase / membase
10 * mapbase is the physical address of the IO port.
11 * membase is an 'ioremapped' cookie.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/ioport.h>
17 #include <linux/init.h>
18 #include <linux/console.h>
19 #include <linux/sysrq.h>
20 #include <linux/delay.h>
21 #include <linux/platform_device.h>
22 #include <linux/tty.h>
23 #include <linux/ratelimit.h>
24 #include <linux/tty_flip.h>
25 #include <linux/serial.h>
26 #include <linux/serial_8250.h>
27 #include <linux/nmi.h>
28 #include <linux/mutex.h>
29 #include <linux/slab.h>
30 #include <linux/uaccess.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/ktime.h>
39 /* Nuvoton NPCM timeout register */
40 #define UART_NPCM_TOR 7
41 #define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */
47 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
49 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
52 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
55 * Here we define the default xmit fifo size used for each type of UART.
57 static const struct serial8250_config uart_config[] = {
82 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
83 .rxtrig_bytes = {1, 4, 8, 14},
84 .flags = UART_CAP_FIFO,
95 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
101 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
103 .rxtrig_bytes = {8, 16, 24, 28},
104 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
110 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
112 .rxtrig_bytes = {1, 16, 32, 56},
113 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
121 .name = "16C950/954",
124 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
125 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
126 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
132 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
134 .rxtrig_bytes = {8, 16, 56, 60},
135 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
141 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
142 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
148 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
149 .flags = UART_CAP_FIFO,
155 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
156 .flags = UART_CAP_FIFO | UART_NATSEMI,
162 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
163 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
169 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
170 .flags = UART_CAP_FIFO,
176 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
177 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
183 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
184 .flags = UART_CAP_FIFO | UART_CAP_AFE,
190 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
192 .rxtrig_bytes = {1, 4, 8, 14},
193 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
199 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
200 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
207 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
209 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
216 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
217 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
218 .flags = UART_CAP_FIFO,
220 [PORT_BRCM_TRUMANAGE] = {
224 .flags = UART_CAP_HFIFO,
229 [PORT_ALTR_16550_F32] = {
230 .name = "Altera 16550 FIFO32",
233 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
234 .rxtrig_bytes = {1, 8, 16, 30},
235 .flags = UART_CAP_FIFO | UART_CAP_AFE,
237 [PORT_ALTR_16550_F64] = {
238 .name = "Altera 16550 FIFO64",
241 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
242 .rxtrig_bytes = {1, 16, 32, 62},
243 .flags = UART_CAP_FIFO | UART_CAP_AFE,
245 [PORT_ALTR_16550_F128] = {
246 .name = "Altera 16550 FIFO128",
249 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
250 .rxtrig_bytes = {1, 32, 64, 126},
251 .flags = UART_CAP_FIFO | UART_CAP_AFE,
254 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
255 * workaround of errata A-008006 which states that tx_loadsz should
256 * be configured less than Maximum supported fifo bytes.
258 [PORT_16550A_FSL64] = {
259 .name = "16550A_FSL64",
262 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
264 .flags = UART_CAP_FIFO,
267 .name = "Palmchip BK-3103",
270 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
271 .rxtrig_bytes = {1, 4, 8, 14},
272 .flags = UART_CAP_FIFO,
275 .name = "TI DA8xx/66AK2x",
278 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
280 .rxtrig_bytes = {1, 4, 8, 14},
281 .flags = UART_CAP_FIFO | UART_CAP_AFE,
284 .name = "MediaTek BTIF",
287 .fcr = UART_FCR_ENABLE_FIFO |
288 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
289 .flags = UART_CAP_FIFO,
292 .name = "Nuvoton 16550",
295 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
296 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
297 .rxtrig_bytes = {1, 4, 8, 14},
298 .flags = UART_CAP_FIFO,
304 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
305 .rxtrig_bytes = {1, 32, 64, 112},
306 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
310 /* Uart divisor latch read */
311 static int default_serial_dl_read(struct uart_8250_port *up)
313 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
316 /* Uart divisor latch write */
317 static void default_serial_dl_write(struct uart_8250_port *up, int value)
319 serial_out(up, UART_DLL, value & 0xff);
320 serial_out(up, UART_DLM, value >> 8 & 0xff);
323 #ifdef CONFIG_SERIAL_8250_RT288X
325 /* Au1x00/RT288x UART hardware has a weird register layout */
326 static const s8 au_io_in_map[8] = {
334 -1, /* UART_SCR (unmapped) */
337 static const s8 au_io_out_map[8] = {
343 -1, /* UART_LSR (unmapped) */
344 -1, /* UART_MSR (unmapped) */
345 -1, /* UART_SCR (unmapped) */
348 unsigned int au_serial_in(struct uart_port *p, int offset)
350 if (offset >= ARRAY_SIZE(au_io_in_map))
352 offset = au_io_in_map[offset];
355 return __raw_readl(p->membase + (offset << p->regshift));
358 void au_serial_out(struct uart_port *p, int offset, int value)
360 if (offset >= ARRAY_SIZE(au_io_out_map))
362 offset = au_io_out_map[offset];
365 __raw_writel(value, p->membase + (offset << p->regshift));
368 /* Au1x00 haven't got a standard divisor latch */
369 static int au_serial_dl_read(struct uart_8250_port *up)
371 return __raw_readl(up->port.membase + 0x28);
374 static void au_serial_dl_write(struct uart_8250_port *up, int value)
376 __raw_writel(value, up->port.membase + 0x28);
381 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
383 offset = offset << p->regshift;
384 outb(p->hub6 - 1 + offset, p->iobase);
385 return inb(p->iobase + 1);
388 static void hub6_serial_out(struct uart_port *p, int offset, int value)
390 offset = offset << p->regshift;
391 outb(p->hub6 - 1 + offset, p->iobase);
392 outb(value, p->iobase + 1);
395 static unsigned int mem_serial_in(struct uart_port *p, int offset)
397 offset = offset << p->regshift;
398 return readb(p->membase + offset);
401 static void mem_serial_out(struct uart_port *p, int offset, int value)
403 offset = offset << p->regshift;
404 writeb(value, p->membase + offset);
407 static void mem16_serial_out(struct uart_port *p, int offset, int value)
409 offset = offset << p->regshift;
410 writew(value, p->membase + offset);
413 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
415 offset = offset << p->regshift;
416 return readw(p->membase + offset);
419 static void mem32_serial_out(struct uart_port *p, int offset, int value)
421 offset = offset << p->regshift;
422 writel(value, p->membase + offset);
425 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
427 offset = offset << p->regshift;
428 return readl(p->membase + offset);
431 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
433 offset = offset << p->regshift;
434 iowrite32be(value, p->membase + offset);
437 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
439 offset = offset << p->regshift;
440 return ioread32be(p->membase + offset);
443 static unsigned int io_serial_in(struct uart_port *p, int offset)
445 offset = offset << p->regshift;
446 return inb(p->iobase + offset);
449 static void io_serial_out(struct uart_port *p, int offset, int value)
451 offset = offset << p->regshift;
452 outb(value, p->iobase + offset);
455 static int serial8250_default_handle_irq(struct uart_port *port);
457 static void set_io_from_upio(struct uart_port *p)
459 struct uart_8250_port *up = up_to_u8250p(p);
461 up->dl_read = default_serial_dl_read;
462 up->dl_write = default_serial_dl_write;
466 p->serial_in = hub6_serial_in;
467 p->serial_out = hub6_serial_out;
471 p->serial_in = mem_serial_in;
472 p->serial_out = mem_serial_out;
476 p->serial_in = mem16_serial_in;
477 p->serial_out = mem16_serial_out;
481 p->serial_in = mem32_serial_in;
482 p->serial_out = mem32_serial_out;
486 p->serial_in = mem32be_serial_in;
487 p->serial_out = mem32be_serial_out;
490 #ifdef CONFIG_SERIAL_8250_RT288X
492 p->serial_in = au_serial_in;
493 p->serial_out = au_serial_out;
494 up->dl_read = au_serial_dl_read;
495 up->dl_write = au_serial_dl_write;
500 p->serial_in = io_serial_in;
501 p->serial_out = io_serial_out;
504 /* Remember loaded iotype */
505 up->cur_iotype = p->iotype;
506 p->handle_irq = serial8250_default_handle_irq;
510 serial_port_out_sync(struct uart_port *p, int offset, int value)
518 p->serial_out(p, offset, value);
519 p->serial_in(p, UART_LCR); /* safe, no side-effects */
522 p->serial_out(p, offset, value);
529 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
531 serial_out(up, UART_SCR, offset);
532 serial_out(up, UART_ICR, value);
535 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
539 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
540 serial_out(up, UART_SCR, offset);
541 value = serial_in(up, UART_ICR);
542 serial_icr_write(up, UART_ACR, up->acr);
550 static void serial8250_clear_fifos(struct uart_8250_port *p)
552 if (p->capabilities & UART_CAP_FIFO) {
553 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
554 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
555 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
556 serial_out(p, UART_FCR, 0);
560 static inline void serial8250_em485_rts_after_send(struct uart_8250_port *p)
562 unsigned char mcr = serial8250_in_MCR(p);
564 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
567 mcr &= ~UART_MCR_RTS;
568 serial8250_out_MCR(p, mcr);
571 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
572 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
574 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
576 serial8250_clear_fifos(p);
577 serial_out(p, UART_FCR, p->fcr);
579 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
581 void serial8250_rpm_get(struct uart_8250_port *p)
583 if (!(p->capabilities & UART_CAP_RPM))
585 pm_runtime_get_sync(p->port.dev);
587 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
589 void serial8250_rpm_put(struct uart_8250_port *p)
591 if (!(p->capabilities & UART_CAP_RPM))
593 pm_runtime_mark_last_busy(p->port.dev);
594 pm_runtime_put_autosuspend(p->port.dev);
596 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
599 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
600 * @p: uart_8250_port port instance
602 * The function is used to start rs485 software emulating on the
603 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
604 * transmission. The function is idempotent, so it is safe to call it
607 * The caller MUST enable interrupt on empty shift register before
608 * calling serial8250_em485_init(). This interrupt is not a part of
609 * 8250 standard, but implementation defined.
611 * The function is supposed to be called from .rs485_config callback
612 * or from any other callback protected with p->port.lock spinlock.
614 * See also serial8250_em485_destroy()
616 * Return 0 - success, -errno - otherwise
618 int serial8250_em485_init(struct uart_8250_port *p)
623 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
627 hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
629 hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
631 p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
632 p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
634 p->em485->active_timer = NULL;
635 serial8250_em485_rts_after_send(p);
639 EXPORT_SYMBOL_GPL(serial8250_em485_init);
642 * serial8250_em485_destroy() - put uart_8250_port into normal state
643 * @p: uart_8250_port port instance
645 * The function is used to stop rs485 software emulating on the
646 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
647 * call it multiple times.
649 * The function is supposed to be called from .rs485_config callback
650 * or from any other callback protected with p->port.lock spinlock.
652 * See also serial8250_em485_init()
654 void serial8250_em485_destroy(struct uart_8250_port *p)
659 hrtimer_cancel(&p->em485->start_tx_timer);
660 hrtimer_cancel(&p->em485->stop_tx_timer);
665 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
668 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
669 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
670 * empty and the HW can idle again.
672 void serial8250_rpm_get_tx(struct uart_8250_port *p)
674 unsigned char rpm_active;
676 if (!(p->capabilities & UART_CAP_RPM))
679 rpm_active = xchg(&p->rpm_tx_active, 1);
682 pm_runtime_get_sync(p->port.dev);
684 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
686 void serial8250_rpm_put_tx(struct uart_8250_port *p)
688 unsigned char rpm_active;
690 if (!(p->capabilities & UART_CAP_RPM))
693 rpm_active = xchg(&p->rpm_tx_active, 0);
696 pm_runtime_mark_last_busy(p->port.dev);
697 pm_runtime_put_autosuspend(p->port.dev);
699 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
702 * IER sleep support. UARTs which have EFRs need the "extended
703 * capability" bit enabled. Note that on XR16C850s, we need to
704 * reset LCR to write to IER.
706 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
708 unsigned char lcr = 0, efr = 0;
710 serial8250_rpm_get(p);
712 if (p->capabilities & UART_CAP_SLEEP) {
713 if (p->capabilities & UART_CAP_EFR) {
714 lcr = serial_in(p, UART_LCR);
715 efr = serial_in(p, UART_EFR);
716 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
717 serial_out(p, UART_EFR, UART_EFR_ECB);
718 serial_out(p, UART_LCR, 0);
720 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
721 if (p->capabilities & UART_CAP_EFR) {
722 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
723 serial_out(p, UART_EFR, efr);
724 serial_out(p, UART_LCR, lcr);
728 serial8250_rpm_put(p);
731 #ifdef CONFIG_SERIAL_8250_RSA
733 * Attempts to turn on the RSA FIFO. Returns zero on failure.
734 * We set the port uart clock rate if we succeed.
736 static int __enable_rsa(struct uart_8250_port *up)
741 mode = serial_in(up, UART_RSA_MSR);
742 result = mode & UART_RSA_MSR_FIFO;
745 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
746 mode = serial_in(up, UART_RSA_MSR);
747 result = mode & UART_RSA_MSR_FIFO;
751 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
756 static void enable_rsa(struct uart_8250_port *up)
758 if (up->port.type == PORT_RSA) {
759 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
760 spin_lock_irq(&up->port.lock);
762 spin_unlock_irq(&up->port.lock);
764 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
765 serial_out(up, UART_RSA_FRR, 0);
770 * Attempts to turn off the RSA FIFO. Returns zero on failure.
771 * It is unknown why interrupts were disabled in here. However,
772 * the caller is expected to preserve this behaviour by grabbing
773 * the spinlock before calling this function.
775 static void disable_rsa(struct uart_8250_port *up)
780 if (up->port.type == PORT_RSA &&
781 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
782 spin_lock_irq(&up->port.lock);
784 mode = serial_in(up, UART_RSA_MSR);
785 result = !(mode & UART_RSA_MSR_FIFO);
788 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
789 mode = serial_in(up, UART_RSA_MSR);
790 result = !(mode & UART_RSA_MSR_FIFO);
794 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
795 spin_unlock_irq(&up->port.lock);
798 #endif /* CONFIG_SERIAL_8250_RSA */
801 * This is a quickie test to see how big the FIFO is.
802 * It doesn't work at all the time, more's the pity.
804 static int size_fifo(struct uart_8250_port *up)
806 unsigned char old_fcr, old_mcr, old_lcr;
807 unsigned short old_dl;
810 old_lcr = serial_in(up, UART_LCR);
811 serial_out(up, UART_LCR, 0);
812 old_fcr = serial_in(up, UART_FCR);
813 old_mcr = serial8250_in_MCR(up);
814 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
815 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
816 serial8250_out_MCR(up, UART_MCR_LOOP);
817 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
818 old_dl = serial_dl_read(up);
819 serial_dl_write(up, 0x0001);
820 serial_out(up, UART_LCR, 0x03);
821 for (count = 0; count < 256; count++)
822 serial_out(up, UART_TX, count);
823 mdelay(20);/* FIXME - schedule_timeout */
824 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
825 (count < 256); count++)
826 serial_in(up, UART_RX);
827 serial_out(up, UART_FCR, old_fcr);
828 serial8250_out_MCR(up, old_mcr);
829 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
830 serial_dl_write(up, old_dl);
831 serial_out(up, UART_LCR, old_lcr);
837 * Read UART ID using the divisor method - set DLL and DLM to zero
838 * and the revision will be in DLL and device type in DLM. We
839 * preserve the device state across this.
841 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
843 unsigned char old_lcr;
844 unsigned int id, old_dl;
846 old_lcr = serial_in(p, UART_LCR);
847 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
848 old_dl = serial_dl_read(p);
849 serial_dl_write(p, 0);
850 id = serial_dl_read(p);
851 serial_dl_write(p, old_dl);
853 serial_out(p, UART_LCR, old_lcr);
859 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
860 * When this function is called we know it is at least a StarTech
861 * 16650 V2, but it might be one of several StarTech UARTs, or one of
862 * its clones. (We treat the broken original StarTech 16650 V1 as a
863 * 16550, and why not? Startech doesn't seem to even acknowledge its
866 * What evil have men's minds wrought...
868 static void autoconfig_has_efr(struct uart_8250_port *up)
870 unsigned int id1, id2, id3, rev;
873 * Everything with an EFR has SLEEP
875 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
878 * First we check to see if it's an Oxford Semiconductor UART.
880 * If we have to do this here because some non-National
881 * Semiconductor clone chips lock up if you try writing to the
882 * LSR register (which serial_icr_read does)
886 * Check for Oxford Semiconductor 16C950.
888 * EFR [4] must be set else this test fails.
890 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
891 * claims that it's needed for 952 dual UART's (which are not
892 * recommended for new designs).
895 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
896 serial_out(up, UART_EFR, UART_EFR_ECB);
897 serial_out(up, UART_LCR, 0x00);
898 id1 = serial_icr_read(up, UART_ID1);
899 id2 = serial_icr_read(up, UART_ID2);
900 id3 = serial_icr_read(up, UART_ID3);
901 rev = serial_icr_read(up, UART_REV);
903 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
905 if (id1 == 0x16 && id2 == 0xC9 &&
906 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
907 up->port.type = PORT_16C950;
910 * Enable work around for the Oxford Semiconductor 952 rev B
911 * chip which causes it to seriously miscalculate baud rates
914 if (id3 == 0x52 && rev == 0x01)
915 up->bugs |= UART_BUG_QUOT;
920 * We check for a XR16C850 by setting DLL and DLM to 0, and then
921 * reading back DLL and DLM. The chip type depends on the DLM
923 * 0x10 - XR16C850 and the DLL contains the chip revision.
927 id1 = autoconfig_read_divisor_id(up);
928 DEBUG_AUTOCONF("850id=%04x ", id1);
931 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
932 up->port.type = PORT_16850;
937 * It wasn't an XR16C850.
939 * We distinguish between the '654 and the '650 by counting
940 * how many bytes are in the FIFO. I'm using this for now,
941 * since that's the technique that was sent to me in the
942 * serial driver update, but I'm not convinced this works.
943 * I've had problems doing this in the past. -TYT
945 if (size_fifo(up) == 64)
946 up->port.type = PORT_16654;
948 up->port.type = PORT_16650V2;
952 * We detected a chip without a FIFO. Only two fall into
953 * this category - the original 8250 and the 16450. The
954 * 16450 has a scratch register (accessible with LCR=0)
956 static void autoconfig_8250(struct uart_8250_port *up)
958 unsigned char scratch, status1, status2;
960 up->port.type = PORT_8250;
962 scratch = serial_in(up, UART_SCR);
963 serial_out(up, UART_SCR, 0xa5);
964 status1 = serial_in(up, UART_SCR);
965 serial_out(up, UART_SCR, 0x5a);
966 status2 = serial_in(up, UART_SCR);
967 serial_out(up, UART_SCR, scratch);
969 if (status1 == 0xa5 && status2 == 0x5a)
970 up->port.type = PORT_16450;
973 static int broken_efr(struct uart_8250_port *up)
976 * Exar ST16C2550 "A2" devices incorrectly detect as
977 * having an EFR, and report an ID of 0x0201. See
978 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
980 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
987 * We know that the chip has FIFOs. Does it have an EFR? The
988 * EFR is located in the same register position as the IIR and
989 * we know the top two bits of the IIR are currently set. The
990 * EFR should contain zero. Try to read the EFR.
992 static void autoconfig_16550a(struct uart_8250_port *up)
994 unsigned char status1, status2;
995 unsigned int iersave;
997 up->port.type = PORT_16550A;
998 up->capabilities |= UART_CAP_FIFO;
1000 if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS))
1004 * Check for presence of the EFR when DLAB is set.
1005 * Only ST16C650V1 UARTs pass this test.
1007 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1008 if (serial_in(up, UART_EFR) == 0) {
1009 serial_out(up, UART_EFR, 0xA8);
1010 if (serial_in(up, UART_EFR) != 0) {
1011 DEBUG_AUTOCONF("EFRv1 ");
1012 up->port.type = PORT_16650;
1013 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1015 serial_out(up, UART_LCR, 0);
1016 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1018 status1 = serial_in(up, UART_IIR) >> 5;
1019 serial_out(up, UART_FCR, 0);
1020 serial_out(up, UART_LCR, 0);
1023 up->port.type = PORT_16550A_FSL64;
1025 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1027 serial_out(up, UART_EFR, 0);
1032 * Maybe it requires 0xbf to be written to the LCR.
1033 * (other ST16C650V2 UARTs, TI16C752A, etc)
1035 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1036 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1037 DEBUG_AUTOCONF("EFRv2 ");
1038 autoconfig_has_efr(up);
1043 * Check for a National Semiconductor SuperIO chip.
1044 * Attempt to switch to bank 2, read the value of the LOOP bit
1045 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1046 * switch back to bank 2, read it from EXCR1 again and check
1047 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1049 serial_out(up, UART_LCR, 0);
1050 status1 = serial8250_in_MCR(up);
1051 serial_out(up, UART_LCR, 0xE0);
1052 status2 = serial_in(up, 0x02); /* EXCR1 */
1054 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1055 serial_out(up, UART_LCR, 0);
1056 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1057 serial_out(up, UART_LCR, 0xE0);
1058 status2 = serial_in(up, 0x02); /* EXCR1 */
1059 serial_out(up, UART_LCR, 0);
1060 serial8250_out_MCR(up, status1);
1062 if ((status2 ^ status1) & UART_MCR_LOOP) {
1063 unsigned short quot;
1065 serial_out(up, UART_LCR, 0xE0);
1067 quot = serial_dl_read(up);
1070 if (ns16550a_goto_highspeed(up))
1071 serial_dl_write(up, quot);
1073 serial_out(up, UART_LCR, 0);
1075 up->port.uartclk = 921600*16;
1076 up->port.type = PORT_NS16550A;
1077 up->capabilities |= UART_NATSEMI;
1083 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1084 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1085 * Try setting it with and without DLAB set. Cheap clones
1086 * set bit 5 without DLAB set.
1088 serial_out(up, UART_LCR, 0);
1089 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1090 status1 = serial_in(up, UART_IIR) >> 5;
1091 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1092 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1093 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1094 status2 = serial_in(up, UART_IIR) >> 5;
1095 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1096 serial_out(up, UART_LCR, 0);
1098 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1100 if (status1 == 6 && status2 == 7) {
1101 up->port.type = PORT_16750;
1102 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1107 * Try writing and reading the UART_IER_UUE bit (b6).
1108 * If it works, this is probably one of the Xscale platform's
1110 * We're going to explicitly set the UUE bit to 0 before
1111 * trying to write and read a 1 just to make sure it's not
1112 * already a 1 and maybe locked there before we even start start.
1114 iersave = serial_in(up, UART_IER);
1115 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1116 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1118 * OK it's in a known zero state, try writing and reading
1119 * without disturbing the current state of the other bits.
1121 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1122 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1125 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1127 DEBUG_AUTOCONF("Xscale ");
1128 up->port.type = PORT_XSCALE;
1129 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1134 * If we got here we couldn't force the IER_UUE bit to 0.
1135 * Log it and continue.
1137 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1139 serial_out(up, UART_IER, iersave);
1142 * We distinguish between 16550A and U6 16550A by counting
1143 * how many bytes are in the FIFO.
1145 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1146 up->port.type = PORT_U6_16550A;
1147 up->capabilities |= UART_CAP_AFE;
1152 * This routine is called by rs_init() to initialize a specific serial
1153 * port. It determines what type of UART chip this serial port is
1154 * using: 8250, 16450, 16550, 16550A. The important question is
1155 * whether or not this UART is a 16550A or not, since this will
1156 * determine whether or not we can use its FIFO features or not.
1158 static void autoconfig(struct uart_8250_port *up)
1160 unsigned char status1, scratch, scratch2, scratch3;
1161 unsigned char save_lcr, save_mcr;
1162 struct uart_port *port = &up->port;
1163 unsigned long flags;
1164 unsigned int old_capabilities;
1166 if (!port->iobase && !port->mapbase && !port->membase)
1169 DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1170 port->name, port->iobase, port->membase);
1173 * We really do need global IRQs disabled here - we're going to
1174 * be frobbing the chips IRQ enable register to see if it exists.
1176 spin_lock_irqsave(&port->lock, flags);
1178 up->capabilities = 0;
1181 if (!(port->flags & UPF_BUGGY_UART)) {
1183 * Do a simple existence test first; if we fail this,
1184 * there's no point trying anything else.
1186 * 0x80 is used as a nonsense port to prevent against
1187 * false positives due to ISA bus float. The
1188 * assumption is that 0x80 is a non-existent port;
1189 * which should be safe since include/asm/io.h also
1190 * makes this assumption.
1192 * Note: this is safe as long as MCR bit 4 is clear
1193 * and the device is in "PC" mode.
1195 scratch = serial_in(up, UART_IER);
1196 serial_out(up, UART_IER, 0);
1201 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1202 * 16C754B) allow only to modify them if an EFR bit is set.
1204 scratch2 = serial_in(up, UART_IER) & 0x0f;
1205 serial_out(up, UART_IER, 0x0F);
1209 scratch3 = serial_in(up, UART_IER) & 0x0f;
1210 serial_out(up, UART_IER, scratch);
1211 if (scratch2 != 0 || scratch3 != 0x0F) {
1213 * We failed; there's nothing here
1215 spin_unlock_irqrestore(&port->lock, flags);
1216 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1217 scratch2, scratch3);
1222 save_mcr = serial8250_in_MCR(up);
1223 save_lcr = serial_in(up, UART_LCR);
1226 * Check to see if a UART is really there. Certain broken
1227 * internal modems based on the Rockwell chipset fail this
1228 * test, because they apparently don't implement the loopback
1229 * test mode. So this test is skipped on the COM 1 through
1230 * COM 4 ports. This *should* be safe, since no board
1231 * manufacturer would be stupid enough to design a board
1232 * that conflicts with COM 1-4 --- we hope!
1234 if (!(port->flags & UPF_SKIP_TEST)) {
1235 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1236 status1 = serial_in(up, UART_MSR) & 0xF0;
1237 serial8250_out_MCR(up, save_mcr);
1238 if (status1 != 0x90) {
1239 spin_unlock_irqrestore(&port->lock, flags);
1240 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1247 * We're pretty sure there's a port here. Lets find out what
1248 * type of port it is. The IIR top two bits allows us to find
1249 * out if it's 8250 or 16450, 16550, 16550A or later. This
1250 * determines what we test for next.
1252 * We also initialise the EFR (if any) to zero for later. The
1253 * EFR occupies the same register location as the FCR and IIR.
1255 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1256 serial_out(up, UART_EFR, 0);
1257 serial_out(up, UART_LCR, 0);
1259 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1260 scratch = serial_in(up, UART_IIR) >> 6;
1264 autoconfig_8250(up);
1267 port->type = PORT_UNKNOWN;
1270 port->type = PORT_16550;
1273 autoconfig_16550a(up);
1277 #ifdef CONFIG_SERIAL_8250_RSA
1279 * Only probe for RSA ports if we got the region.
1281 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1283 port->type = PORT_RSA;
1286 serial_out(up, UART_LCR, save_lcr);
1288 port->fifosize = uart_config[up->port.type].fifo_size;
1289 old_capabilities = up->capabilities;
1290 up->capabilities = uart_config[port->type].flags;
1291 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1293 if (port->type == PORT_UNKNOWN)
1299 #ifdef CONFIG_SERIAL_8250_RSA
1300 if (port->type == PORT_RSA)
1301 serial_out(up, UART_RSA_FRR, 0);
1303 serial8250_out_MCR(up, save_mcr);
1304 serial8250_clear_fifos(up);
1305 serial_in(up, UART_RX);
1306 if (up->capabilities & UART_CAP_UUE)
1307 serial_out(up, UART_IER, UART_IER_UUE);
1309 serial_out(up, UART_IER, 0);
1312 spin_unlock_irqrestore(&port->lock, flags);
1315 * Check if the device is a Fintek F81216A
1317 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1318 fintek_8250_probe(up);
1320 if (up->capabilities != old_capabilities) {
1321 pr_warn("%s: detected caps %08x should be %08x\n",
1322 port->name, old_capabilities, up->capabilities);
1325 DEBUG_AUTOCONF("iir=%d ", scratch);
1326 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1329 static void autoconfig_irq(struct uart_8250_port *up)
1331 struct uart_port *port = &up->port;
1332 unsigned char save_mcr, save_ier;
1333 unsigned char save_ICP = 0;
1334 unsigned int ICP = 0;
1338 if (port->flags & UPF_FOURPORT) {
1339 ICP = (port->iobase & 0xfe0) | 0x1f;
1340 save_ICP = inb_p(ICP);
1345 if (uart_console(port))
1348 /* forget possible initially masked and pending IRQ */
1349 probe_irq_off(probe_irq_on());
1350 save_mcr = serial8250_in_MCR(up);
1351 save_ier = serial_in(up, UART_IER);
1352 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1354 irqs = probe_irq_on();
1355 serial8250_out_MCR(up, 0);
1357 if (port->flags & UPF_FOURPORT) {
1358 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1360 serial8250_out_MCR(up,
1361 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1363 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1364 serial_in(up, UART_LSR);
1365 serial_in(up, UART_RX);
1366 serial_in(up, UART_IIR);
1367 serial_in(up, UART_MSR);
1368 serial_out(up, UART_TX, 0xFF);
1370 irq = probe_irq_off(irqs);
1372 serial8250_out_MCR(up, save_mcr);
1373 serial_out(up, UART_IER, save_ier);
1375 if (port->flags & UPF_FOURPORT)
1376 outb_p(save_ICP, ICP);
1378 if (uart_console(port))
1381 port->irq = (irq > 0) ? irq : 0;
1384 static void serial8250_stop_rx(struct uart_port *port)
1386 struct uart_8250_port *up = up_to_u8250p(port);
1388 serial8250_rpm_get(up);
1390 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1391 up->port.read_status_mask &= ~UART_LSR_DR;
1392 serial_port_out(port, UART_IER, up->ier);
1394 serial8250_rpm_put(up);
1397 static void __do_stop_tx_rs485(struct uart_8250_port *p)
1399 serial8250_em485_rts_after_send(p);
1402 * Empty the RX FIFO, we are not interested in anything
1403 * received during the half-duplex transmission.
1404 * Enable previously disabled RX interrupts.
1406 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1407 serial8250_clear_and_reinit_fifos(p);
1409 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1410 serial_port_out(&p->port, UART_IER, p->ier);
1413 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1415 struct uart_8250_em485 *em485;
1416 struct uart_8250_port *p;
1417 unsigned long flags;
1419 em485 = container_of(t, struct uart_8250_em485, stop_tx_timer);
1422 serial8250_rpm_get(p);
1423 spin_lock_irqsave(&p->port.lock, flags);
1424 if (em485->active_timer == &em485->stop_tx_timer) {
1425 __do_stop_tx_rs485(p);
1426 em485->active_timer = NULL;
1428 spin_unlock_irqrestore(&p->port.lock, flags);
1429 serial8250_rpm_put(p);
1430 return HRTIMER_NORESTART;
1433 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1435 long sec = msec / 1000;
1436 long nsec = (msec % 1000) * 1000000;
1437 ktime_t t = ktime_set(sec, nsec);
1439 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1442 static void __stop_tx_rs485(struct uart_8250_port *p)
1444 struct uart_8250_em485 *em485 = p->em485;
1447 * __do_stop_tx_rs485 is going to set RTS according to config
1448 * AND flush RX FIFO if required.
1450 if (p->port.rs485.delay_rts_after_send > 0) {
1451 em485->active_timer = &em485->stop_tx_timer;
1452 start_hrtimer_ms(&em485->stop_tx_timer,
1453 p->port.rs485.delay_rts_after_send);
1455 __do_stop_tx_rs485(p);
1459 static inline void __do_stop_tx(struct uart_8250_port *p)
1461 if (serial8250_clear_THRI(p))
1462 serial8250_rpm_put_tx(p);
1465 static inline void __stop_tx(struct uart_8250_port *p)
1467 struct uart_8250_em485 *em485 = p->em485;
1470 unsigned char lsr = serial_in(p, UART_LSR);
1472 * To provide required timeing and allow FIFO transfer,
1473 * __stop_tx_rs485() must be called only when both FIFO and
1474 * shift register are empty. It is for device driver to enable
1475 * interrupt on TEMT.
1477 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1480 em485->active_timer = NULL;
1487 static void serial8250_stop_tx(struct uart_port *port)
1489 struct uart_8250_port *up = up_to_u8250p(port);
1491 serial8250_rpm_get(up);
1495 * We really want to stop the transmitter from sending.
1497 if (port->type == PORT_16C950) {
1498 up->acr |= UART_ACR_TXDIS;
1499 serial_icr_write(up, UART_ACR, up->acr);
1501 serial8250_rpm_put(up);
1504 static inline void __start_tx(struct uart_port *port)
1506 struct uart_8250_port *up = up_to_u8250p(port);
1508 if (up->dma && !up->dma->tx_dma(up))
1511 if (serial8250_set_THRI(up)) {
1512 if (up->bugs & UART_BUG_TXEN) {
1515 lsr = serial_in(up, UART_LSR);
1516 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1517 if (lsr & UART_LSR_THRE)
1518 serial8250_tx_chars(up);
1523 * Re-enable the transmitter if we disabled it.
1525 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1526 up->acr &= ~UART_ACR_TXDIS;
1527 serial_icr_write(up, UART_ACR, up->acr);
1531 static inline void start_tx_rs485(struct uart_port *port)
1533 struct uart_8250_port *up = up_to_u8250p(port);
1534 struct uart_8250_em485 *em485 = up->em485;
1537 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1538 serial8250_stop_rx(&up->port);
1540 em485->active_timer = NULL;
1542 mcr = serial8250_in_MCR(up);
1543 if (!!(up->port.rs485.flags & SER_RS485_RTS_ON_SEND) !=
1544 !!(mcr & UART_MCR_RTS)) {
1545 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1546 mcr |= UART_MCR_RTS;
1548 mcr &= ~UART_MCR_RTS;
1549 serial8250_out_MCR(up, mcr);
1551 if (up->port.rs485.delay_rts_before_send > 0) {
1552 em485->active_timer = &em485->start_tx_timer;
1553 start_hrtimer_ms(&em485->start_tx_timer,
1554 up->port.rs485.delay_rts_before_send);
1562 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1564 struct uart_8250_em485 *em485;
1565 struct uart_8250_port *p;
1566 unsigned long flags;
1568 em485 = container_of(t, struct uart_8250_em485, start_tx_timer);
1571 spin_lock_irqsave(&p->port.lock, flags);
1572 if (em485->active_timer == &em485->start_tx_timer) {
1573 __start_tx(&p->port);
1574 em485->active_timer = NULL;
1576 spin_unlock_irqrestore(&p->port.lock, flags);
1577 return HRTIMER_NORESTART;
1580 static void serial8250_start_tx(struct uart_port *port)
1582 struct uart_8250_port *up = up_to_u8250p(port);
1583 struct uart_8250_em485 *em485 = up->em485;
1585 serial8250_rpm_get_tx(up);
1588 em485->active_timer == &em485->start_tx_timer)
1592 start_tx_rs485(port);
1597 static void serial8250_throttle(struct uart_port *port)
1599 port->throttle(port);
1602 static void serial8250_unthrottle(struct uart_port *port)
1604 port->unthrottle(port);
1607 static void serial8250_disable_ms(struct uart_port *port)
1609 struct uart_8250_port *up = up_to_u8250p(port);
1611 /* no MSR capabilities */
1612 if (up->bugs & UART_BUG_NOMSR)
1615 mctrl_gpio_disable_ms(up->gpios);
1617 up->ier &= ~UART_IER_MSI;
1618 serial_port_out(port, UART_IER, up->ier);
1621 static void serial8250_enable_ms(struct uart_port *port)
1623 struct uart_8250_port *up = up_to_u8250p(port);
1625 /* no MSR capabilities */
1626 if (up->bugs & UART_BUG_NOMSR)
1629 mctrl_gpio_enable_ms(up->gpios);
1631 up->ier |= UART_IER_MSI;
1633 serial8250_rpm_get(up);
1634 serial_port_out(port, UART_IER, up->ier);
1635 serial8250_rpm_put(up);
1638 void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1640 struct uart_port *port = &up->port;
1642 char flag = TTY_NORMAL;
1644 if (likely(lsr & UART_LSR_DR))
1645 ch = serial_in(up, UART_RX);
1648 * Intel 82571 has a Serial Over Lan device that will
1649 * set UART_LSR_BI without setting UART_LSR_DR when
1650 * it receives a break. To avoid reading from the
1651 * receive buffer without UART_LSR_DR bit set, we
1652 * just force the read character to be 0
1658 lsr |= up->lsr_saved_flags;
1659 up->lsr_saved_flags = 0;
1661 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1662 if (lsr & UART_LSR_BI) {
1663 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1666 * We do the SysRQ and SAK checking
1667 * here because otherwise the break
1668 * may get masked by ignore_status_mask
1669 * or read_status_mask.
1671 if (uart_handle_break(port))
1673 } else if (lsr & UART_LSR_PE)
1674 port->icount.parity++;
1675 else if (lsr & UART_LSR_FE)
1676 port->icount.frame++;
1677 if (lsr & UART_LSR_OE)
1678 port->icount.overrun++;
1681 * Mask off conditions which should be ignored.
1683 lsr &= port->read_status_mask;
1685 if (lsr & UART_LSR_BI) {
1686 pr_debug("%s: handling break\n", __func__);
1688 } else if (lsr & UART_LSR_PE)
1690 else if (lsr & UART_LSR_FE)
1693 if (uart_prepare_sysrq_char(port, ch))
1696 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1698 EXPORT_SYMBOL_GPL(serial8250_read_char);
1701 * serial8250_rx_chars: processes according to the passed in LSR
1702 * value, and returns the remaining LSR bits not handled
1703 * by this Rx routine.
1705 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1707 struct uart_port *port = &up->port;
1708 int max_count = 256;
1711 serial8250_read_char(up, lsr);
1712 if (--max_count == 0)
1714 lsr = serial_in(up, UART_LSR);
1715 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1717 tty_flip_buffer_push(&port->state->port);
1720 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1722 void serial8250_tx_chars(struct uart_8250_port *up)
1724 struct uart_port *port = &up->port;
1725 struct circ_buf *xmit = &port->state->xmit;
1729 serial_out(up, UART_TX, port->x_char);
1734 if (uart_tx_stopped(port)) {
1735 serial8250_stop_tx(port);
1738 if (uart_circ_empty(xmit)) {
1743 count = up->tx_loadsz;
1745 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1746 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1748 if (uart_circ_empty(xmit))
1750 if ((up->capabilities & UART_CAP_HFIFO) &&
1751 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1753 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1754 if ((up->capabilities & UART_CAP_MINI) &&
1755 !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1757 } while (--count > 0);
1759 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1760 uart_write_wakeup(port);
1763 * With RPM enabled, we have to wait until the FIFO is empty before the
1764 * HW can go idle. So we get here once again with empty FIFO and disable
1765 * the interrupt and RPM in __stop_tx()
1767 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1770 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1772 /* Caller holds uart port lock */
1773 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1775 struct uart_port *port = &up->port;
1776 unsigned int status = serial_in(up, UART_MSR);
1778 status |= up->msr_saved_flags;
1779 up->msr_saved_flags = 0;
1780 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1781 port->state != NULL) {
1782 if (status & UART_MSR_TERI)
1784 if (status & UART_MSR_DDSR)
1786 if (status & UART_MSR_DDCD)
1787 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1788 if (status & UART_MSR_DCTS)
1789 uart_handle_cts_change(port, status & UART_MSR_CTS);
1791 wake_up_interruptible(&port->state->port.delta_msr_wait);
1796 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1798 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1800 switch (iir & 0x3f) {
1801 case UART_IIR_RX_TIMEOUT:
1802 serial8250_rx_dma_flush(up);
1807 return up->dma->rx_dma(up);
1811 * This handles the interrupt from one port.
1813 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1815 unsigned char status;
1816 unsigned long flags;
1817 struct uart_8250_port *up = up_to_u8250p(port);
1819 if (iir & UART_IIR_NO_INT)
1822 spin_lock_irqsave(&port->lock, flags);
1824 status = serial_port_in(port, UART_LSR);
1826 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1827 if (!up->dma || handle_rx_dma(up, iir))
1828 status = serial8250_rx_chars(up, status);
1830 serial8250_modem_status(up);
1831 if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE) &&
1832 (up->ier & UART_IER_THRI))
1833 serial8250_tx_chars(up);
1835 uart_unlock_and_check_sysrq(port, flags);
1838 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1840 static int serial8250_default_handle_irq(struct uart_port *port)
1842 struct uart_8250_port *up = up_to_u8250p(port);
1846 serial8250_rpm_get(up);
1848 iir = serial_port_in(port, UART_IIR);
1849 ret = serial8250_handle_irq(port, iir);
1851 serial8250_rpm_put(up);
1856 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1857 * have a programmable TX threshold that triggers the THRE interrupt in
1858 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1859 * has space available. Load it up with tx_loadsz bytes.
1861 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1863 unsigned long flags;
1864 unsigned int iir = serial_port_in(port, UART_IIR);
1866 /* TX Threshold IRQ triggered so load up FIFO */
1867 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1868 struct uart_8250_port *up = up_to_u8250p(port);
1870 spin_lock_irqsave(&port->lock, flags);
1871 serial8250_tx_chars(up);
1872 spin_unlock_irqrestore(&port->lock, flags);
1875 iir = serial_port_in(port, UART_IIR);
1876 return serial8250_handle_irq(port, iir);
1879 static unsigned int serial8250_tx_empty(struct uart_port *port)
1881 struct uart_8250_port *up = up_to_u8250p(port);
1882 unsigned long flags;
1885 serial8250_rpm_get(up);
1887 spin_lock_irqsave(&port->lock, flags);
1888 lsr = serial_port_in(port, UART_LSR);
1889 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1890 spin_unlock_irqrestore(&port->lock, flags);
1892 serial8250_rpm_put(up);
1894 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1897 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1899 struct uart_8250_port *up = up_to_u8250p(port);
1900 unsigned int status;
1903 serial8250_rpm_get(up);
1904 status = serial8250_modem_status(up);
1905 serial8250_rpm_put(up);
1907 val = serial8250_MSR_to_TIOCM(status);
1909 return mctrl_gpio_get(up->gpios, &val);
1913 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
1915 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1917 if (port->get_mctrl)
1918 return port->get_mctrl(port);
1919 return serial8250_do_get_mctrl(port);
1922 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1924 struct uart_8250_port *up = up_to_u8250p(port);
1927 mcr = serial8250_TIOCM_to_MCR(mctrl);
1929 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1931 serial8250_out_MCR(up, mcr);
1933 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1935 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1937 if (port->set_mctrl)
1938 port->set_mctrl(port, mctrl);
1940 serial8250_do_set_mctrl(port, mctrl);
1943 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1945 struct uart_8250_port *up = up_to_u8250p(port);
1946 unsigned long flags;
1948 serial8250_rpm_get(up);
1949 spin_lock_irqsave(&port->lock, flags);
1950 if (break_state == -1)
1951 up->lcr |= UART_LCR_SBC;
1953 up->lcr &= ~UART_LCR_SBC;
1954 serial_port_out(port, UART_LCR, up->lcr);
1955 spin_unlock_irqrestore(&port->lock, flags);
1956 serial8250_rpm_put(up);
1960 * Wait for transmitter & holding register to empty
1962 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1964 unsigned int status, tmout = 10000;
1966 /* Wait up to 10ms for the character(s) to be sent. */
1968 status = serial_in(up, UART_LSR);
1970 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1972 if ((status & bits) == bits)
1977 touch_nmi_watchdog();
1980 /* Wait up to 1s for flow control if necessary */
1981 if (up->port.flags & UPF_CONS_FLOW) {
1982 for (tmout = 1000000; tmout; tmout--) {
1983 unsigned int msr = serial_in(up, UART_MSR);
1984 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1985 if (msr & UART_MSR_CTS)
1988 touch_nmi_watchdog();
1993 #ifdef CONFIG_CONSOLE_POLL
1995 * Console polling routines for writing and reading from the uart while
1996 * in an interrupt or debug context.
1999 static int serial8250_get_poll_char(struct uart_port *port)
2001 struct uart_8250_port *up = up_to_u8250p(port);
2005 serial8250_rpm_get(up);
2007 lsr = serial_port_in(port, UART_LSR);
2009 if (!(lsr & UART_LSR_DR)) {
2010 status = NO_POLL_CHAR;
2014 status = serial_port_in(port, UART_RX);
2016 serial8250_rpm_put(up);
2021 static void serial8250_put_poll_char(struct uart_port *port,
2025 struct uart_8250_port *up = up_to_u8250p(port);
2027 serial8250_rpm_get(up);
2029 * First save the IER then disable the interrupts
2031 ier = serial_port_in(port, UART_IER);
2032 if (up->capabilities & UART_CAP_UUE)
2033 serial_port_out(port, UART_IER, UART_IER_UUE);
2035 serial_port_out(port, UART_IER, 0);
2037 wait_for_xmitr(up, BOTH_EMPTY);
2039 * Send the character out.
2041 serial_port_out(port, UART_TX, c);
2044 * Finally, wait for transmitter to become empty
2045 * and restore the IER
2047 wait_for_xmitr(up, BOTH_EMPTY);
2048 serial_port_out(port, UART_IER, ier);
2049 serial8250_rpm_put(up);
2052 #endif /* CONFIG_CONSOLE_POLL */
2054 int serial8250_do_startup(struct uart_port *port)
2056 struct uart_8250_port *up = up_to_u8250p(port);
2057 unsigned long flags;
2058 unsigned char lsr, iir;
2061 if (!port->fifosize)
2062 port->fifosize = uart_config[port->type].fifo_size;
2064 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2065 if (!up->capabilities)
2066 up->capabilities = uart_config[port->type].flags;
2069 if (port->iotype != up->cur_iotype)
2070 set_io_from_upio(port);
2072 serial8250_rpm_get(up);
2073 if (port->type == PORT_16C950) {
2074 /* Wake up and initialize UART */
2076 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2077 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2078 serial_port_out(port, UART_IER, 0);
2079 serial_port_out(port, UART_LCR, 0);
2080 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2081 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2082 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2083 serial_port_out(port, UART_LCR, 0);
2086 if (port->type == PORT_DA830) {
2087 /* Reset the port */
2088 serial_port_out(port, UART_IER, 0);
2089 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2092 /* Enable Tx, Rx and free run mode */
2093 serial_port_out(port, UART_DA830_PWREMU_MGMT,
2094 UART_DA830_PWREMU_MGMT_UTRST |
2095 UART_DA830_PWREMU_MGMT_URRST |
2096 UART_DA830_PWREMU_MGMT_FREE);
2099 if (port->type == PORT_NPCM) {
2101 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2102 * register). Enable it, and set TIOC (timeout interrupt
2103 * comparator) to be 0x20 for correct operation.
2105 serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2108 #ifdef CONFIG_SERIAL_8250_RSA
2110 * If this is an RSA port, see if we can kick it up to the
2111 * higher speed clock.
2117 * Clear the FIFO buffers and disable them.
2118 * (they will be reenabled in set_termios())
2120 serial8250_clear_fifos(up);
2123 * Clear the interrupt registers.
2125 serial_port_in(port, UART_LSR);
2126 serial_port_in(port, UART_RX);
2127 serial_port_in(port, UART_IIR);
2128 serial_port_in(port, UART_MSR);
2131 * At this point, there's no way the LSR could still be 0xff;
2132 * if it is, then bail out, because there's likely no UART
2135 if (!(port->flags & UPF_BUGGY_UART) &&
2136 (serial_port_in(port, UART_LSR) == 0xff)) {
2137 pr_info_ratelimited("%s: LSR safety check engaged!\n", port->name);
2143 * For a XR16C850, we need to set the trigger levels
2145 if (port->type == PORT_16850) {
2148 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2150 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2151 serial_port_out(port, UART_FCTR,
2152 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2153 serial_port_out(port, UART_TRG, UART_TRG_96);
2154 serial_port_out(port, UART_FCTR,
2155 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2156 serial_port_out(port, UART_TRG, UART_TRG_96);
2158 serial_port_out(port, UART_LCR, 0);
2162 * For the Altera 16550 variants, set TX threshold trigger level.
2164 if (((port->type == PORT_ALTR_16550_F32) ||
2165 (port->type == PORT_ALTR_16550_F64) ||
2166 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2167 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2168 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2169 pr_err("%s TX FIFO Threshold errors, skipping\n",
2172 serial_port_out(port, UART_ALTR_AFR,
2173 UART_ALTR_EN_TXFIFO_LW);
2174 serial_port_out(port, UART_ALTR_TX_LOW,
2175 port->fifosize - up->tx_loadsz);
2176 port->handle_irq = serial8250_tx_threshold_handle_irq;
2180 /* Check if we need to have shared IRQs */
2181 if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2182 up->port.irqflags |= IRQF_SHARED;
2184 if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2187 * Test for UARTs that do not reassert THRE when the
2188 * transmitter is idle and the interrupt has already
2189 * been cleared. Real 16550s should always reassert
2190 * this interrupt whenever the transmitter is idle and
2191 * the interrupt is enabled. Delays are necessary to
2192 * allow register changes to become visible.
2194 spin_lock_irqsave(&port->lock, flags);
2195 if (up->port.irqflags & IRQF_SHARED)
2196 disable_irq_nosync(port->irq);
2198 wait_for_xmitr(up, UART_LSR_THRE);
2199 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2200 udelay(1); /* allow THRE to set */
2201 iir1 = serial_port_in(port, UART_IIR);
2202 serial_port_out(port, UART_IER, 0);
2203 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2204 udelay(1); /* allow a working UART time to re-assert THRE */
2205 iir = serial_port_in(port, UART_IIR);
2206 serial_port_out(port, UART_IER, 0);
2208 if (port->irqflags & IRQF_SHARED)
2209 enable_irq(port->irq);
2210 spin_unlock_irqrestore(&port->lock, flags);
2213 * If the interrupt is not reasserted, or we otherwise
2214 * don't trust the iir, setup a timer to kick the UART
2215 * on a regular basis.
2217 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2218 up->port.flags & UPF_BUG_THRE) {
2219 up->bugs |= UART_BUG_THRE;
2223 retval = up->ops->setup_irq(up);
2228 * Now, initialize the UART
2230 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2232 spin_lock_irqsave(&port->lock, flags);
2233 if (up->port.flags & UPF_FOURPORT) {
2235 up->port.mctrl |= TIOCM_OUT1;
2238 * Most PC uarts need OUT2 raised to enable interrupts.
2241 up->port.mctrl |= TIOCM_OUT2;
2243 serial8250_set_mctrl(port, port->mctrl);
2246 * Serial over Lan (SoL) hack:
2247 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2248 * used for Serial Over Lan. Those chips take a longer time than a
2249 * normal serial device to signalize that a transmission data was
2250 * queued. Due to that, the above test generally fails. One solution
2251 * would be to delay the reading of iir. However, this is not
2252 * reliable, since the timeout is variable. So, let's just don't
2253 * test if we receive TX irq. This way, we'll never enable
2256 if (up->port.quirks & UPQ_NO_TXEN_TEST)
2257 goto dont_test_tx_en;
2260 * Do a quick test to see if we receive an interrupt when we enable
2263 serial_port_out(port, UART_IER, UART_IER_THRI);
2264 lsr = serial_port_in(port, UART_LSR);
2265 iir = serial_port_in(port, UART_IIR);
2266 serial_port_out(port, UART_IER, 0);
2268 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2269 if (!(up->bugs & UART_BUG_TXEN)) {
2270 up->bugs |= UART_BUG_TXEN;
2271 pr_debug("%s - enabling bad tx status workarounds\n",
2275 up->bugs &= ~UART_BUG_TXEN;
2279 spin_unlock_irqrestore(&port->lock, flags);
2282 * Clear the interrupt registers again for luck, and clear the
2283 * saved flags to avoid getting false values from polling
2284 * routines or the previous session.
2286 serial_port_in(port, UART_LSR);
2287 serial_port_in(port, UART_RX);
2288 serial_port_in(port, UART_IIR);
2289 serial_port_in(port, UART_MSR);
2290 up->lsr_saved_flags = 0;
2291 up->msr_saved_flags = 0;
2294 * Request DMA channels for both RX and TX.
2297 retval = serial8250_request_dma(up);
2299 pr_warn_ratelimited("%s - failed to request DMA\n",
2306 * Set the IER shadow for rx interrupts but defer actual interrupt
2307 * enable until after the FIFOs are enabled; otherwise, an already-
2308 * active sender can swamp the interrupt handler with "too much work".
2310 up->ier = UART_IER_RLSI | UART_IER_RDI;
2312 if (port->flags & UPF_FOURPORT) {
2315 * Enable interrupts on the AST Fourport board
2317 icp = (port->iobase & 0xfe0) | 0x01f;
2323 serial8250_rpm_put(up);
2326 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2328 static int serial8250_startup(struct uart_port *port)
2331 return port->startup(port);
2332 return serial8250_do_startup(port);
2335 void serial8250_do_shutdown(struct uart_port *port)
2337 struct uart_8250_port *up = up_to_u8250p(port);
2338 unsigned long flags;
2340 serial8250_rpm_get(up);
2342 * Disable interrupts from this port
2344 spin_lock_irqsave(&port->lock, flags);
2346 serial_port_out(port, UART_IER, 0);
2347 spin_unlock_irqrestore(&port->lock, flags);
2349 synchronize_irq(port->irq);
2352 serial8250_release_dma(up);
2354 spin_lock_irqsave(&port->lock, flags);
2355 if (port->flags & UPF_FOURPORT) {
2356 /* reset interrupts on the AST Fourport board */
2357 inb((port->iobase & 0xfe0) | 0x1f);
2358 port->mctrl |= TIOCM_OUT1;
2360 port->mctrl &= ~TIOCM_OUT2;
2362 serial8250_set_mctrl(port, port->mctrl);
2363 spin_unlock_irqrestore(&port->lock, flags);
2366 * Disable break condition and FIFOs
2368 serial_port_out(port, UART_LCR,
2369 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2370 serial8250_clear_fifos(up);
2372 #ifdef CONFIG_SERIAL_8250_RSA
2374 * Reset the RSA board back to 115kbps compat mode.
2380 * Read data port to reset things, and then unlink from
2383 serial_port_in(port, UART_RX);
2384 serial8250_rpm_put(up);
2386 up->ops->release_irq(up);
2388 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2390 static void serial8250_shutdown(struct uart_port *port)
2393 port->shutdown(port);
2395 serial8250_do_shutdown(port);
2398 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2399 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2402 struct uart_port *port = &up->port;
2404 return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2407 static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2411 struct uart_8250_port *up = up_to_u8250p(port);
2415 * Handle magic divisors for baud rates above baud_base on
2416 * SMSC SuperIO chips.
2419 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2420 baud == (port->uartclk/4))
2422 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2423 baud == (port->uartclk/8))
2425 else if (up->port.type == PORT_NPCM)
2426 quot = npcm_get_divisor(up, baud);
2428 quot = uart_get_divisor(port, baud);
2431 * Oxford Semi 952 rev B workaround
2433 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2439 static unsigned int serial8250_get_divisor(struct uart_port *port,
2443 if (port->get_divisor)
2444 return port->get_divisor(port, baud, frac);
2446 return serial8250_do_get_divisor(port, baud, frac);
2449 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2454 switch (c_cflag & CSIZE) {
2456 cval = UART_LCR_WLEN5;
2459 cval = UART_LCR_WLEN6;
2462 cval = UART_LCR_WLEN7;
2466 cval = UART_LCR_WLEN8;
2470 if (c_cflag & CSTOPB)
2471 cval |= UART_LCR_STOP;
2472 if (c_cflag & PARENB) {
2473 cval |= UART_LCR_PARITY;
2474 if (up->bugs & UART_BUG_PARITY)
2475 up->fifo_bug = true;
2477 if (!(c_cflag & PARODD))
2478 cval |= UART_LCR_EPAR;
2480 if (c_cflag & CMSPAR)
2481 cval |= UART_LCR_SPAR;
2487 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2488 unsigned int quot, unsigned int quot_frac)
2490 struct uart_8250_port *up = up_to_u8250p(port);
2492 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2493 if (is_omap1510_8250(up)) {
2494 if (baud == 115200) {
2496 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2498 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2502 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2503 * otherwise just set DLAB
2505 if (up->capabilities & UART_NATSEMI)
2506 serial_port_out(port, UART_LCR, 0xe0);
2508 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2510 serial_dl_write(up, quot);
2512 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2514 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2515 unsigned int quot, unsigned int quot_frac)
2517 if (port->set_divisor)
2518 port->set_divisor(port, baud, quot, quot_frac);
2520 serial8250_do_set_divisor(port, baud, quot, quot_frac);
2523 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2524 struct ktermios *termios,
2525 struct ktermios *old)
2528 * Ask the core to calculate the divisor for us.
2529 * Allow 1% tolerance at the upper limit so uart clks marginally
2530 * slower than nominal still match standard baud rates without
2531 * causing transmission errors.
2533 return uart_get_baud_rate(port, termios, old,
2534 port->uartclk / 16 / UART_DIV_MAX,
2539 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2540 struct ktermios *old)
2542 struct uart_8250_port *up = up_to_u8250p(port);
2544 unsigned long flags;
2545 unsigned int baud, quot, frac = 0;
2547 if (up->capabilities & UART_CAP_MINI) {
2548 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2549 if ((termios->c_cflag & CSIZE) == CS5 ||
2550 (termios->c_cflag & CSIZE) == CS6)
2551 termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2553 cval = serial8250_compute_lcr(up, termios->c_cflag);
2555 baud = serial8250_get_baud_rate(port, termios, old);
2556 quot = serial8250_get_divisor(port, baud, &frac);
2559 * Ok, we're now changing the port state. Do it with
2560 * interrupts disabled.
2562 serial8250_rpm_get(up);
2563 spin_lock_irqsave(&port->lock, flags);
2565 up->lcr = cval; /* Save computed LCR */
2567 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2568 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2569 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2570 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2571 up->fcr |= UART_FCR_TRIGGER_1;
2576 * MCR-based auto flow control. When AFE is enabled, RTS will be
2577 * deasserted when the receive FIFO contains more characters than
2578 * the trigger, or the MCR RTS bit is cleared.
2580 if (up->capabilities & UART_CAP_AFE) {
2581 up->mcr &= ~UART_MCR_AFE;
2582 if (termios->c_cflag & CRTSCTS)
2583 up->mcr |= UART_MCR_AFE;
2587 * Update the per-port timeout.
2589 uart_update_timeout(port, termios->c_cflag, baud);
2591 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2592 if (termios->c_iflag & INPCK)
2593 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2594 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2595 port->read_status_mask |= UART_LSR_BI;
2598 * Characteres to ignore
2600 port->ignore_status_mask = 0;
2601 if (termios->c_iflag & IGNPAR)
2602 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2603 if (termios->c_iflag & IGNBRK) {
2604 port->ignore_status_mask |= UART_LSR_BI;
2606 * If we're ignoring parity and break indicators,
2607 * ignore overruns too (for real raw support).
2609 if (termios->c_iflag & IGNPAR)
2610 port->ignore_status_mask |= UART_LSR_OE;
2614 * ignore all characters if CREAD is not set
2616 if ((termios->c_cflag & CREAD) == 0)
2617 port->ignore_status_mask |= UART_LSR_DR;
2620 * CTS flow control flag and modem status interrupts
2622 up->ier &= ~UART_IER_MSI;
2623 if (!(up->bugs & UART_BUG_NOMSR) &&
2624 UART_ENABLE_MS(&up->port, termios->c_cflag))
2625 up->ier |= UART_IER_MSI;
2626 if (up->capabilities & UART_CAP_UUE)
2627 up->ier |= UART_IER_UUE;
2628 if (up->capabilities & UART_CAP_RTOIE)
2629 up->ier |= UART_IER_RTOIE;
2631 serial_port_out(port, UART_IER, up->ier);
2633 if (up->capabilities & UART_CAP_EFR) {
2634 unsigned char efr = 0;
2636 * TI16C752/Startech hardware flow control. FIXME:
2637 * - TI16C752 requires control thresholds to be set.
2638 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2640 if (termios->c_cflag & CRTSCTS)
2641 efr |= UART_EFR_CTS;
2643 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2644 if (port->flags & UPF_EXAR_EFR)
2645 serial_port_out(port, UART_XR_EFR, efr);
2647 serial_port_out(port, UART_EFR, efr);
2650 serial8250_set_divisor(port, baud, quot, frac);
2653 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2654 * is written without DLAB set, this mode will be disabled.
2656 if (port->type == PORT_16750)
2657 serial_port_out(port, UART_FCR, up->fcr);
2659 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2660 if (port->type != PORT_16750) {
2661 /* emulated UARTs (Lucent Venus 167x) need two steps */
2662 if (up->fcr & UART_FCR_ENABLE_FIFO)
2663 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2664 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2666 serial8250_set_mctrl(port, port->mctrl);
2667 spin_unlock_irqrestore(&port->lock, flags);
2668 serial8250_rpm_put(up);
2670 /* Don't rewrite B0 */
2671 if (tty_termios_baud_rate(termios))
2672 tty_termios_encode_baud_rate(termios, baud, baud);
2674 EXPORT_SYMBOL(serial8250_do_set_termios);
2677 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2678 struct ktermios *old)
2680 if (port->set_termios)
2681 port->set_termios(port, termios, old);
2683 serial8250_do_set_termios(port, termios, old);
2686 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2688 if (termios->c_line == N_PPS) {
2689 port->flags |= UPF_HARDPPS_CD;
2690 spin_lock_irq(&port->lock);
2691 serial8250_enable_ms(port);
2692 spin_unlock_irq(&port->lock);
2694 port->flags &= ~UPF_HARDPPS_CD;
2695 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2696 spin_lock_irq(&port->lock);
2697 serial8250_disable_ms(port);
2698 spin_unlock_irq(&port->lock);
2702 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2705 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2707 if (port->set_ldisc)
2708 port->set_ldisc(port, termios);
2710 serial8250_do_set_ldisc(port, termios);
2713 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2714 unsigned int oldstate)
2716 struct uart_8250_port *p = up_to_u8250p(port);
2718 serial8250_set_sleep(p, state != 0);
2720 EXPORT_SYMBOL(serial8250_do_pm);
2723 serial8250_pm(struct uart_port *port, unsigned int state,
2724 unsigned int oldstate)
2727 port->pm(port, state, oldstate);
2729 serial8250_do_pm(port, state, oldstate);
2732 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2734 if (pt->port.mapsize)
2735 return pt->port.mapsize;
2736 if (pt->port.iotype == UPIO_AU) {
2737 if (pt->port.type == PORT_RT2880)
2741 if (is_omap1_8250(pt))
2742 return 0x16 << pt->port.regshift;
2744 return 8 << pt->port.regshift;
2748 * Resource handling.
2750 static int serial8250_request_std_resource(struct uart_8250_port *up)
2752 unsigned int size = serial8250_port_size(up);
2753 struct uart_port *port = &up->port;
2756 switch (port->iotype) {
2766 if (!request_mem_region(port->mapbase, size, "serial")) {
2771 if (port->flags & UPF_IOREMAP) {
2772 port->membase = ioremap(port->mapbase, size);
2773 if (!port->membase) {
2774 release_mem_region(port->mapbase, size);
2782 if (!request_region(port->iobase, size, "serial"))
2789 static void serial8250_release_std_resource(struct uart_8250_port *up)
2791 unsigned int size = serial8250_port_size(up);
2792 struct uart_port *port = &up->port;
2794 switch (port->iotype) {
2804 if (port->flags & UPF_IOREMAP) {
2805 iounmap(port->membase);
2806 port->membase = NULL;
2809 release_mem_region(port->mapbase, size);
2814 release_region(port->iobase, size);
2819 static void serial8250_release_port(struct uart_port *port)
2821 struct uart_8250_port *up = up_to_u8250p(port);
2823 serial8250_release_std_resource(up);
2826 static int serial8250_request_port(struct uart_port *port)
2828 struct uart_8250_port *up = up_to_u8250p(port);
2830 return serial8250_request_std_resource(up);
2833 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2835 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2836 unsigned char bytes;
2838 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2840 return bytes ? bytes : -EOPNOTSUPP;
2843 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2845 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2848 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2851 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2852 if (bytes < conf_type->rxtrig_bytes[i])
2853 /* Use the nearest lower value */
2854 return (--i) << UART_FCR_R_TRIG_SHIFT;
2857 return UART_FCR_R_TRIG_11;
2860 static int do_get_rxtrig(struct tty_port *port)
2862 struct uart_state *state = container_of(port, struct uart_state, port);
2863 struct uart_port *uport = state->uart_port;
2864 struct uart_8250_port *up = up_to_u8250p(uport);
2866 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2869 return fcr_get_rxtrig_bytes(up);
2872 static int do_serial8250_get_rxtrig(struct tty_port *port)
2876 mutex_lock(&port->mutex);
2877 rxtrig_bytes = do_get_rxtrig(port);
2878 mutex_unlock(&port->mutex);
2880 return rxtrig_bytes;
2883 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2884 struct device_attribute *attr, char *buf)
2886 struct tty_port *port = dev_get_drvdata(dev);
2889 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2890 if (rxtrig_bytes < 0)
2891 return rxtrig_bytes;
2893 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2896 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2898 struct uart_state *state = container_of(port, struct uart_state, port);
2899 struct uart_port *uport = state->uart_port;
2900 struct uart_8250_port *up = up_to_u8250p(uport);
2903 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2907 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2911 serial8250_clear_fifos(up);
2912 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2913 up->fcr |= (unsigned char)rxtrig;
2914 serial_out(up, UART_FCR, up->fcr);
2918 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2922 mutex_lock(&port->mutex);
2923 ret = do_set_rxtrig(port, bytes);
2924 mutex_unlock(&port->mutex);
2929 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2930 struct device_attribute *attr, const char *buf, size_t count)
2932 struct tty_port *port = dev_get_drvdata(dev);
2933 unsigned char bytes;
2939 ret = kstrtou8(buf, 10, &bytes);
2943 ret = do_serial8250_set_rxtrig(port, bytes);
2950 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2951 serial8250_get_attr_rx_trig_bytes,
2952 serial8250_set_attr_rx_trig_bytes);
2954 static struct attribute *serial8250_dev_attrs[] = {
2955 &dev_attr_rx_trig_bytes.attr,
2959 static struct attribute_group serial8250_dev_attr_group = {
2960 .attrs = serial8250_dev_attrs,
2963 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
2965 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2967 if (conf_type->rxtrig_bytes[0])
2968 up->port.attr_group = &serial8250_dev_attr_group;
2971 static void serial8250_config_port(struct uart_port *port, int flags)
2973 struct uart_8250_port *up = up_to_u8250p(port);
2977 * Find the region that we can probe for. This in turn
2978 * tells us whether we can probe for the type of port.
2980 ret = serial8250_request_std_resource(up);
2984 if (port->iotype != up->cur_iotype)
2985 set_io_from_upio(port);
2987 if (flags & UART_CONFIG_TYPE)
2990 /* if access method is AU, it is a 16550 with a quirk */
2991 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2992 up->bugs |= UART_BUG_NOMSR;
2994 /* HW bugs may trigger IRQ while IIR == NO_INT */
2995 if (port->type == PORT_TEGRA)
2996 up->bugs |= UART_BUG_NOMSR;
2998 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3001 if (port->type == PORT_UNKNOWN)
3002 serial8250_release_std_resource(up);
3004 register_dev_spec_attr_grp(up);
3005 up->fcr = uart_config[up->port.type].fcr;
3009 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3011 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3012 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3013 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3014 ser->type == PORT_STARTECH)
3019 static const char *serial8250_type(struct uart_port *port)
3021 int type = port->type;
3023 if (type >= ARRAY_SIZE(uart_config))
3025 return uart_config[type].name;
3028 static const struct uart_ops serial8250_pops = {
3029 .tx_empty = serial8250_tx_empty,
3030 .set_mctrl = serial8250_set_mctrl,
3031 .get_mctrl = serial8250_get_mctrl,
3032 .stop_tx = serial8250_stop_tx,
3033 .start_tx = serial8250_start_tx,
3034 .throttle = serial8250_throttle,
3035 .unthrottle = serial8250_unthrottle,
3036 .stop_rx = serial8250_stop_rx,
3037 .enable_ms = serial8250_enable_ms,
3038 .break_ctl = serial8250_break_ctl,
3039 .startup = serial8250_startup,
3040 .shutdown = serial8250_shutdown,
3041 .set_termios = serial8250_set_termios,
3042 .set_ldisc = serial8250_set_ldisc,
3043 .pm = serial8250_pm,
3044 .type = serial8250_type,
3045 .release_port = serial8250_release_port,
3046 .request_port = serial8250_request_port,
3047 .config_port = serial8250_config_port,
3048 .verify_port = serial8250_verify_port,
3049 #ifdef CONFIG_CONSOLE_POLL
3050 .poll_get_char = serial8250_get_poll_char,
3051 .poll_put_char = serial8250_put_poll_char,
3055 void serial8250_init_port(struct uart_8250_port *up)
3057 struct uart_port *port = &up->port;
3059 spin_lock_init(&port->lock);
3060 port->ops = &serial8250_pops;
3061 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3063 up->cur_iotype = 0xFF;
3065 EXPORT_SYMBOL_GPL(serial8250_init_port);
3067 void serial8250_set_defaults(struct uart_8250_port *up)
3069 struct uart_port *port = &up->port;
3071 if (up->port.flags & UPF_FIXED_TYPE) {
3072 unsigned int type = up->port.type;
3074 if (!up->port.fifosize)
3075 up->port.fifosize = uart_config[type].fifo_size;
3077 up->tx_loadsz = uart_config[type].tx_loadsz;
3078 if (!up->capabilities)
3079 up->capabilities = uart_config[type].flags;
3082 set_io_from_upio(port);
3084 /* default dma handlers */
3086 if (!up->dma->tx_dma)
3087 up->dma->tx_dma = serial8250_tx_dma;
3088 if (!up->dma->rx_dma)
3089 up->dma->rx_dma = serial8250_rx_dma;
3092 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3094 #ifdef CONFIG_SERIAL_8250_CONSOLE
3096 static void serial8250_console_putchar(struct uart_port *port, int ch)
3098 struct uart_8250_port *up = up_to_u8250p(port);
3100 wait_for_xmitr(up, UART_LSR_THRE);
3101 serial_port_out(port, UART_TX, ch);
3105 * Restore serial console when h/w power-off detected
3107 static void serial8250_console_restore(struct uart_8250_port *up)
3109 struct uart_port *port = &up->port;
3110 struct ktermios termios;
3111 unsigned int baud, quot, frac = 0;
3113 termios.c_cflag = port->cons->cflag;
3114 if (port->state->port.tty && termios.c_cflag == 0)
3115 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3117 baud = serial8250_get_baud_rate(port, &termios, NULL);
3118 quot = serial8250_get_divisor(port, baud, &frac);
3120 serial8250_set_divisor(port, baud, quot, frac);
3121 serial_port_out(port, UART_LCR, up->lcr);
3122 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
3126 * Print a string to the serial port trying not to disturb
3127 * any possible real use of the port...
3129 * The console_lock must be held when we get here.
3131 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3134 struct uart_port *port = &up->port;
3135 unsigned long flags;
3139 touch_nmi_watchdog();
3141 serial8250_rpm_get(up);
3143 if (oops_in_progress)
3144 locked = spin_trylock_irqsave(&port->lock, flags);
3146 spin_lock_irqsave(&port->lock, flags);
3149 * First save the IER then disable the interrupts
3151 ier = serial_port_in(port, UART_IER);
3153 if (up->capabilities & UART_CAP_UUE)
3154 serial_port_out(port, UART_IER, UART_IER_UUE);
3156 serial_port_out(port, UART_IER, 0);
3158 /* check scratch reg to see if port powered off during system sleep */
3159 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3160 serial8250_console_restore(up);
3164 uart_console_write(port, s, count, serial8250_console_putchar);
3167 * Finally, wait for transmitter to become empty
3168 * and restore the IER
3170 wait_for_xmitr(up, BOTH_EMPTY);
3171 serial_port_out(port, UART_IER, ier);
3174 * The receive handling will happen properly because the
3175 * receive ready bit will still be set; it is not cleared
3176 * on read. However, modem control will not, we must
3177 * call it if we have saved something in the saved flags
3178 * while processing with interrupts off.
3180 if (up->msr_saved_flags)
3181 serial8250_modem_status(up);
3184 spin_unlock_irqrestore(&port->lock, flags);
3185 serial8250_rpm_put(up);
3188 static unsigned int probe_baud(struct uart_port *port)
3190 unsigned char lcr, dll, dlm;
3193 lcr = serial_port_in(port, UART_LCR);
3194 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3195 dll = serial_port_in(port, UART_DLL);
3196 dlm = serial_port_in(port, UART_DLM);
3197 serial_port_out(port, UART_LCR, lcr);
3199 quot = (dlm << 8) | dll;
3200 return (port->uartclk / 16) / quot;
3203 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3210 if (!port->iobase && !port->membase)
3214 uart_parse_options(options, &baud, &parity, &bits, &flow);
3216 baud = probe_baud(port);
3218 return uart_set_options(port, port->cons, baud, parity, bits, flow);
3221 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3223 MODULE_LICENSE("GPL");