2 * Probe module for 8250/16550-type PCI serial ports.
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
25 #include <asm/byteorder.h>
28 #include <linux/dmaengine.h>
29 #include <linux/platform_data/dma-dw.h>
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
39 struct pci_serial_quirk {
44 int (*probe)(struct pci_dev *dev);
45 int (*init)(struct pci_dev *dev);
46 int (*setup)(struct serial_private *,
47 const struct pciserial_board *,
48 struct uart_8250_port *, int);
49 void (*exit)(struct pci_dev *dev);
52 #define PCI_NUM_BAR_RESOURCES 6
54 struct serial_private {
57 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
58 struct pci_serial_quirk *quirk;
62 static int pci_default_setup(struct serial_private*,
63 const struct pciserial_board*, struct uart_8250_port *, int);
65 static void moan_device(const char *str, struct pci_dev *dev)
69 "Please send the output of lspci -vv, this\n"
70 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
71 "manufacturer and name of serial board or\n"
72 "modem board to rmk+serial@arm.linux.org.uk.\n",
73 pci_name(dev), str, dev->vendor, dev->device,
74 dev->subsystem_vendor, dev->subsystem_device);
78 setup_port(struct serial_private *priv, struct uart_8250_port *port,
79 int bar, int offset, int regshift)
81 struct pci_dev *dev = priv->dev;
83 if (bar >= PCI_NUM_BAR_RESOURCES)
86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
87 if (!priv->remapped_bar[bar])
88 priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar);
89 if (!priv->remapped_bar[bar])
92 port->port.iotype = UPIO_MEM;
93 port->port.iobase = 0;
94 port->port.mapbase = pci_resource_start(dev, bar) + offset;
95 port->port.membase = priv->remapped_bar[bar] + offset;
96 port->port.regshift = regshift;
98 port->port.iotype = UPIO_PORT;
99 port->port.iobase = pci_resource_start(dev, bar) + offset;
100 port->port.mapbase = 0;
101 port->port.membase = NULL;
102 port->port.regshift = 0;
108 * ADDI-DATA GmbH communication cards <info@addi-data.com>
110 static int addidata_apci7800_setup(struct serial_private *priv,
111 const struct pciserial_board *board,
112 struct uart_8250_port *port, int idx)
114 unsigned int bar = 0, offset = board->first_offset;
115 bar = FL_GET_BASE(board->flags);
118 offset += idx * board->uart_offset;
119 } else if ((idx >= 2) && (idx < 4)) {
121 offset += ((idx - 2) * board->uart_offset);
122 } else if ((idx >= 4) && (idx < 6)) {
124 offset += ((idx - 4) * board->uart_offset);
125 } else if (idx >= 6) {
127 offset += ((idx - 6) * board->uart_offset);
130 return setup_port(priv, port, bar, offset, board->reg_shift);
134 * AFAVLAB uses a different mixture of BARs and offsets
135 * Not that ugly ;) -- HW
138 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
139 struct uart_8250_port *port, int idx)
141 unsigned int bar, offset = board->first_offset;
143 bar = FL_GET_BASE(board->flags);
148 offset += (idx - 4) * board->uart_offset;
151 return setup_port(priv, port, bar, offset, board->reg_shift);
155 * HP's Remote Management Console. The Diva chip came in several
156 * different versions. N-class, L2000 and A500 have two Diva chips, each
157 * with 3 UARTs (the third UART on the second chip is unused). Superdome
158 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
159 * one Diva chip, but it has been expanded to 5 UARTs.
161 static int pci_hp_diva_init(struct pci_dev *dev)
165 switch (dev->subsystem_device) {
166 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
167 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
168 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
169 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
172 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
175 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
178 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
179 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
188 * HP's Diva chip puts the 4th/5th serial port further out, and
189 * some serial ports are supposed to be hidden on certain models.
192 pci_hp_diva_setup(struct serial_private *priv,
193 const struct pciserial_board *board,
194 struct uart_8250_port *port, int idx)
196 unsigned int offset = board->first_offset;
197 unsigned int bar = FL_GET_BASE(board->flags);
199 switch (priv->dev->subsystem_device) {
200 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
204 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
214 offset += idx * board->uart_offset;
216 return setup_port(priv, port, bar, offset, board->reg_shift);
220 * Added for EKF Intel i960 serial boards
222 static int pci_inteli960ni_init(struct pci_dev *dev)
224 unsigned long oldval;
226 if (!(dev->subsystem_device & 0x1000))
229 /* is firmware started? */
230 pci_read_config_dword(dev, 0x44, (void *)&oldval);
231 if (oldval == 0x00001000L) { /* RESET value */
232 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
239 * Some PCI serial cards using the PLX 9050 PCI interface chip require
240 * that the card interrupt be explicitly enabled or disabled. This
241 * seems to be mainly needed on card using the PLX which also use I/O
244 static int pci_plx9050_init(struct pci_dev *dev)
249 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
250 moan_device("no memory in bar 0", dev);
255 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
256 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
259 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
260 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
262 * As the megawolf cards have the int pins active
263 * high, and have 2 UART chips, both ints must be
264 * enabled on the 9050. Also, the UARTS are set in
265 * 16450 mode by default, so we have to enable the
266 * 16C950 'enhanced' mode so that we can use the
271 * enable/disable interrupts
273 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
276 writel(irq_config, p + 0x4c);
279 * Read the register back to ensure that it took effect.
287 static void pci_plx9050_exit(struct pci_dev *dev)
291 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
297 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
302 * Read the register back to ensure that it took effect.
309 #define NI8420_INT_ENABLE_REG 0x38
310 #define NI8420_INT_ENABLE_BIT 0x2000
312 static void pci_ni8420_exit(struct pci_dev *dev)
315 unsigned int bar = 0;
317 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
318 moan_device("no memory in bar", dev);
322 p = pci_ioremap_bar(dev, bar);
326 /* Disable the CPU Interrupt */
327 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
328 p + NI8420_INT_ENABLE_REG);
334 #define MITE_IOWBSR1 0xc4
335 #define MITE_IOWCR1 0xf4
336 #define MITE_LCIMR1 0x08
337 #define MITE_LCIMR2 0x10
339 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
341 static void pci_ni8430_exit(struct pci_dev *dev)
344 unsigned int bar = 0;
346 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
347 moan_device("no memory in bar", dev);
351 p = pci_ioremap_bar(dev, bar);
355 /* Disable the CPU Interrupt */
356 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
360 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
362 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
363 struct uart_8250_port *port, int idx)
365 unsigned int bar, offset = board->first_offset;
370 /* first four channels map to 0, 0x100, 0x200, 0x300 */
371 offset += idx * board->uart_offset;
372 } else if (idx < 8) {
373 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
374 offset += idx * board->uart_offset + 0xC00;
375 } else /* we have only 8 ports on PMC-OCTALPRO */
378 return setup_port(priv, port, bar, offset, board->reg_shift);
382 * This does initialization for PMC OCTALPRO cards:
383 * maps the device memory, resets the UARTs (needed, bc
384 * if the module is removed and inserted again, the card
385 * is in the sleep mode) and enables global interrupt.
388 /* global control register offset for SBS PMC-OctalPro */
389 #define OCT_REG_CR_OFF 0x500
391 static int sbs_init(struct pci_dev *dev)
395 p = pci_ioremap_bar(dev, 0);
399 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
400 writeb(0x10, p + OCT_REG_CR_OFF);
402 writeb(0x0, p + OCT_REG_CR_OFF);
404 /* Set bit-2 (INTENABLE) of Control Register */
405 writeb(0x4, p + OCT_REG_CR_OFF);
412 * Disables the global interrupt of PMC-OctalPro
415 static void sbs_exit(struct pci_dev *dev)
419 p = pci_ioremap_bar(dev, 0);
420 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
422 writeb(0, p + OCT_REG_CR_OFF);
427 * SIIG serial cards have an PCI interface chip which also controls
428 * the UART clocking frequency. Each UART can be clocked independently
429 * (except cards equipped with 4 UARTs) and initial clocking settings
430 * are stored in the EEPROM chip. It can cause problems because this
431 * version of serial driver doesn't support differently clocked UART's
432 * on single PCI card. To prevent this, initialization functions set
433 * high frequency clocking for all UART's on given card. It is safe (I
434 * hope) because it doesn't touch EEPROM settings to prevent conflicts
435 * with other OSes (like M$ DOS).
437 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
439 * There is two family of SIIG serial cards with different PCI
440 * interface chip and different configuration methods:
441 * - 10x cards have control registers in IO and/or memory space;
442 * - 20x cards have control registers in standard PCI configuration space.
444 * Note: all 10x cards have PCI device ids 0x10..
445 * all 20x cards have PCI device ids 0x20..
447 * There are also Quartet Serial cards which use Oxford Semiconductor
448 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
450 * Note: some SIIG cards are probed by the parport_serial object.
453 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
454 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
456 static int pci_siig10x_init(struct pci_dev *dev)
461 switch (dev->device & 0xfff8) {
462 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
465 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
468 default: /* 1S1P, 4S */
473 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
477 writew(readw(p + 0x28) & data, p + 0x28);
483 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
484 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
486 static int pci_siig20x_init(struct pci_dev *dev)
490 /* Change clock frequency for the first UART. */
491 pci_read_config_byte(dev, 0x6f, &data);
492 pci_write_config_byte(dev, 0x6f, data & 0xef);
494 /* If this card has 2 UART, we have to do the same with second UART. */
495 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
496 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
497 pci_read_config_byte(dev, 0x73, &data);
498 pci_write_config_byte(dev, 0x73, data & 0xef);
503 static int pci_siig_init(struct pci_dev *dev)
505 unsigned int type = dev->device & 0xff00;
508 return pci_siig10x_init(dev);
509 else if (type == 0x2000)
510 return pci_siig20x_init(dev);
512 moan_device("Unknown SIIG card", dev);
516 static int pci_siig_setup(struct serial_private *priv,
517 const struct pciserial_board *board,
518 struct uart_8250_port *port, int idx)
520 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
524 offset = (idx - 4) * 8;
527 return setup_port(priv, port, bar, offset, 0);
531 * Timedia has an explosion of boards, and to avoid the PCI table from
532 * growing *huge*, we use this function to collapse some 70 entries
533 * in the PCI table into one, for sanity's and compactness's sake.
535 static const unsigned short timedia_single_port[] = {
536 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
539 static const unsigned short timedia_dual_port[] = {
540 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
541 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
542 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
543 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
547 static const unsigned short timedia_quad_port[] = {
548 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
549 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
550 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
554 static const unsigned short timedia_eight_port[] = {
555 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
556 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
559 static const struct timedia_struct {
561 const unsigned short *ids;
563 { 1, timedia_single_port },
564 { 2, timedia_dual_port },
565 { 4, timedia_quad_port },
566 { 8, timedia_eight_port }
570 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
571 * listing them individually, this driver merely grabs them all with
572 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
573 * and should be left free to be claimed by parport_serial instead.
575 static int pci_timedia_probe(struct pci_dev *dev)
578 * Check the third digit of the subdevice ID
579 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
581 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
583 "ignoring Timedia subdevice %04x for parport_serial\n",
584 dev->subsystem_device);
591 static int pci_timedia_init(struct pci_dev *dev)
593 const unsigned short *ids;
596 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
597 ids = timedia_data[i].ids;
598 for (j = 0; ids[j]; j++)
599 if (dev->subsystem_device == ids[j])
600 return timedia_data[i].num;
606 * Timedia/SUNIX uses a mixture of BARs and offsets
607 * Ugh, this is ugly as all hell --- TYT
610 pci_timedia_setup(struct serial_private *priv,
611 const struct pciserial_board *board,
612 struct uart_8250_port *port, int idx)
614 unsigned int bar = 0, offset = board->first_offset;
621 offset = board->uart_offset;
628 offset = board->uart_offset;
637 return setup_port(priv, port, bar, offset, board->reg_shift);
641 * Some Titan cards are also a little weird
644 titan_400l_800l_setup(struct serial_private *priv,
645 const struct pciserial_board *board,
646 struct uart_8250_port *port, int idx)
648 unsigned int bar, offset = board->first_offset;
659 offset = (idx - 2) * board->uart_offset;
662 return setup_port(priv, port, bar, offset, board->reg_shift);
665 static int pci_xircom_init(struct pci_dev *dev)
671 static int pci_ni8420_init(struct pci_dev *dev)
674 unsigned int bar = 0;
676 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
677 moan_device("no memory in bar", dev);
681 p = pci_ioremap_bar(dev, bar);
685 /* Enable CPU Interrupt */
686 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
687 p + NI8420_INT_ENABLE_REG);
693 #define MITE_IOWBSR1_WSIZE 0xa
694 #define MITE_IOWBSR1_WIN_OFFSET 0x800
695 #define MITE_IOWBSR1_WENAB (1 << 7)
696 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
697 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
698 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
700 static int pci_ni8430_init(struct pci_dev *dev)
703 struct pci_bus_region region;
705 unsigned int bar = 0;
707 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
708 moan_device("no memory in bar", dev);
712 p = pci_ioremap_bar(dev, bar);
717 * Set device window address and size in BAR0, while acknowledging that
718 * the resource structure may contain a translated address that differs
719 * from the address the device responds to.
721 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
722 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
723 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
724 writel(device_window, p + MITE_IOWBSR1);
726 /* Set window access to go to RAMSEL IO address space */
727 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
730 /* Enable IO Bus Interrupt 0 */
731 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
733 /* Enable CPU Interrupt */
734 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
740 /* UART Port Control Register */
741 #define NI8430_PORTCON 0x0f
742 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
745 pci_ni8430_setup(struct serial_private *priv,
746 const struct pciserial_board *board,
747 struct uart_8250_port *port, int idx)
749 struct pci_dev *dev = priv->dev;
751 unsigned int bar, offset = board->first_offset;
753 if (idx >= board->num_ports)
756 bar = FL_GET_BASE(board->flags);
757 offset += idx * board->uart_offset;
759 p = pci_ioremap_bar(dev, bar);
763 /* enable the transceiver */
764 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
765 p + offset + NI8430_PORTCON);
769 return setup_port(priv, port, bar, offset, board->reg_shift);
772 static int pci_netmos_9900_setup(struct serial_private *priv,
773 const struct pciserial_board *board,
774 struct uart_8250_port *port, int idx)
778 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
779 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
780 /* netmos apparently orders BARs by datasheet layout, so serial
781 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
785 return setup_port(priv, port, bar, 0, board->reg_shift);
787 return pci_default_setup(priv, board, port, idx);
791 /* the 99xx series comes with a range of device IDs and a variety
794 * 9900 has varying capabilities and can cascade to sub-controllers
795 * (cascading should be purely internal)
796 * 9904 is hardwired with 4 serial ports
797 * 9912 and 9922 are hardwired with 2 serial ports
799 static int pci_netmos_9900_numports(struct pci_dev *dev)
801 unsigned int c = dev->class;
803 unsigned short sub_serports;
809 } else if ((pi == 0) &&
810 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
811 /* two possibilities: 0x30ps encodes number of parallel and
812 * serial ports, or 0x1000 indicates *something*. This is not
813 * immediately obvious, since the 2s1p+4s configuration seems
814 * to offer all functionality on functions 0..2, while still
815 * advertising the same function 3 as the 4s+2s1p config.
817 sub_serports = dev->subsystem_device & 0xf;
818 if (sub_serports > 0) {
821 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
826 moan_device("unknown NetMos/Mostech program interface", dev);
830 static int pci_netmos_init(struct pci_dev *dev)
832 /* subdevice 0x00PS means <P> parallel, <S> serial */
833 unsigned int num_serial = dev->subsystem_device & 0xf;
835 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
836 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
839 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
840 dev->subsystem_device == 0x0299)
843 switch (dev->device) { /* FALLTHROUGH on all */
844 case PCI_DEVICE_ID_NETMOS_9904:
845 case PCI_DEVICE_ID_NETMOS_9912:
846 case PCI_DEVICE_ID_NETMOS_9922:
847 case PCI_DEVICE_ID_NETMOS_9900:
848 num_serial = pci_netmos_9900_numports(dev);
852 if (num_serial == 0 ) {
853 moan_device("unknown NetMos/Mostech device", dev);
864 * These chips are available with optionally one parallel port and up to
865 * two serial ports. Unfortunately they all have the same product id.
867 * Basic configuration is done over a region of 32 I/O ports. The base
868 * ioport is called INTA or INTC, depending on docs/other drivers.
870 * The region of the 32 I/O ports is configured in POSIO0R...
874 #define ITE_887x_MISCR 0x9c
875 #define ITE_887x_INTCBAR 0x78
876 #define ITE_887x_UARTBAR 0x7c
877 #define ITE_887x_PS0BAR 0x10
878 #define ITE_887x_POSIO0 0x60
881 #define ITE_887x_IOSIZE 32
882 /* I/O space size (bits 26-24; 8 bytes = 011b) */
883 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
884 /* I/O space size (bits 26-24; 32 bytes = 101b) */
885 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
886 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
887 #define ITE_887x_POSIO_SPEED (3 << 29)
888 /* enable IO_Space bit */
889 #define ITE_887x_POSIO_ENABLE (1 << 31)
891 static int pci_ite887x_init(struct pci_dev *dev)
893 /* inta_addr are the configuration addresses of the ITE */
894 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
897 struct resource *iobase = NULL;
898 u32 miscr, uartbar, ioport;
900 /* search for the base-ioport */
902 while (inta_addr[i] && iobase == NULL) {
903 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
905 if (iobase != NULL) {
906 /* write POSIO0R - speed | size | ioport */
907 pci_write_config_dword(dev, ITE_887x_POSIO0,
908 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
909 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
910 /* write INTCBAR - ioport */
911 pci_write_config_dword(dev, ITE_887x_INTCBAR,
913 ret = inb(inta_addr[i]);
915 /* ioport connected */
918 release_region(iobase->start, ITE_887x_IOSIZE);
925 dev_err(&dev->dev, "ite887x: could not find iobase\n");
929 /* start of undocumented type checking (see parport_pc.c) */
930 type = inb(iobase->start + 0x18) & 0x0f;
933 case 0x2: /* ITE8871 (1P) */
934 case 0xa: /* ITE8875 (1P) */
937 case 0xe: /* ITE8872 (2S1P) */
940 case 0x6: /* ITE8873 (1S) */
943 case 0x8: /* ITE8874 (2S) */
947 moan_device("Unknown ITE887x", dev);
951 /* configure all serial ports */
952 for (i = 0; i < ret; i++) {
953 /* read the I/O port from the device */
954 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
956 ioport &= 0x0000FF00; /* the actual base address */
957 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
958 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
959 ITE_887x_POSIO_IOSIZE_8 | ioport);
961 /* write the ioport to the UARTBAR */
962 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
963 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
964 uartbar |= (ioport << (16 * i)); /* set the ioport */
965 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
967 /* get current config */
968 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
969 /* disable interrupts (UARTx_Routing[3:0]) */
970 miscr &= ~(0xf << (12 - 4 * i));
971 /* activate the UART (UARTx_En) */
972 miscr |= 1 << (23 - i);
973 /* write new config with activated UART */
974 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
978 /* the device has no UARTs if we get here */
979 release_region(iobase->start, ITE_887x_IOSIZE);
985 static void pci_ite887x_exit(struct pci_dev *dev)
988 /* the ioport is bit 0-15 in POSIO0R */
989 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
991 release_region(ioport, ITE_887x_IOSIZE);
995 * EndRun Technologies.
996 * Determine the number of ports available on the device.
998 #define PCI_VENDOR_ID_ENDRUN 0x7401
999 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1001 static int pci_endrun_init(struct pci_dev *dev)
1004 unsigned long deviceID;
1005 unsigned int number_uarts = 0;
1007 /* EndRun device is all 0xexxx */
1008 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1009 (dev->device & 0xf000) != 0xe000)
1012 p = pci_iomap(dev, 0, 5);
1016 deviceID = ioread32(p);
1018 if (deviceID == 0x07000200) {
1019 number_uarts = ioread8(p + 4);
1021 "%d ports detected on EndRun PCI Express device\n",
1024 pci_iounmap(dev, p);
1025 return number_uarts;
1029 * Oxford Semiconductor Inc.
1030 * Check that device is part of the Tornado range of devices, then determine
1031 * the number of ports available on the device.
1033 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1036 unsigned long deviceID;
1037 unsigned int number_uarts = 0;
1039 /* OxSemi Tornado devices are all 0xCxxx */
1040 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1041 (dev->device & 0xF000) != 0xC000)
1044 p = pci_iomap(dev, 0, 5);
1048 deviceID = ioread32(p);
1049 /* Tornado device */
1050 if (deviceID == 0x07000200) {
1051 number_uarts = ioread8(p + 4);
1053 "%d ports detected on Oxford PCI Express device\n",
1056 pci_iounmap(dev, p);
1057 return number_uarts;
1060 static int pci_asix_setup(struct serial_private *priv,
1061 const struct pciserial_board *board,
1062 struct uart_8250_port *port, int idx)
1064 port->bugs |= UART_BUG_PARITY;
1065 return pci_default_setup(priv, board, port, idx);
1068 /* Quatech devices have their own extra interface features */
1070 struct quatech_feature {
1075 #define QPCR_TEST_FOR1 0x3F
1076 #define QPCR_TEST_GET1 0x00
1077 #define QPCR_TEST_FOR2 0x40
1078 #define QPCR_TEST_GET2 0x40
1079 #define QPCR_TEST_FOR3 0x80
1080 #define QPCR_TEST_GET3 0x40
1081 #define QPCR_TEST_FOR4 0xC0
1082 #define QPCR_TEST_GET4 0x80
1084 #define QOPR_CLOCK_X1 0x0000
1085 #define QOPR_CLOCK_X2 0x0001
1086 #define QOPR_CLOCK_X4 0x0002
1087 #define QOPR_CLOCK_X8 0x0003
1088 #define QOPR_CLOCK_RATE_MASK 0x0003
1091 static struct quatech_feature quatech_cards[] = {
1092 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1093 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1094 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1095 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1096 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1097 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1098 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1099 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1100 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1101 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1102 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1103 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1104 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1105 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1106 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1107 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1108 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1109 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1110 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1114 static int pci_quatech_amcc(u16 devid)
1116 struct quatech_feature *qf = &quatech_cards[0];
1118 if (qf->devid == devid)
1122 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1126 static int pci_quatech_rqopr(struct uart_8250_port *port)
1128 unsigned long base = port->port.iobase;
1131 LCR = inb(base + UART_LCR);
1132 outb(0xBF, base + UART_LCR);
1133 val = inb(base + UART_SCR);
1134 outb(LCR, base + UART_LCR);
1138 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1140 unsigned long base = port->port.iobase;
1143 LCR = inb(base + UART_LCR);
1144 outb(0xBF, base + UART_LCR);
1145 val = inb(base + UART_SCR);
1146 outb(qopr, base + UART_SCR);
1147 outb(LCR, base + UART_LCR);
1150 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1152 unsigned long base = port->port.iobase;
1155 LCR = inb(base + UART_LCR);
1156 outb(0xBF, base + UART_LCR);
1157 val = inb(base + UART_SCR);
1158 outb(val | 0x10, base + UART_SCR);
1159 qmcr = inb(base + UART_MCR);
1160 outb(val, base + UART_SCR);
1161 outb(LCR, base + UART_LCR);
1166 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1168 unsigned long base = port->port.iobase;
1171 LCR = inb(base + UART_LCR);
1172 outb(0xBF, base + UART_LCR);
1173 val = inb(base + UART_SCR);
1174 outb(val | 0x10, base + UART_SCR);
1175 outb(qmcr, base + UART_MCR);
1176 outb(val, base + UART_SCR);
1177 outb(LCR, base + UART_LCR);
1180 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1182 unsigned long base = port->port.iobase;
1185 LCR = inb(base + UART_LCR);
1186 outb(0xBF, base + UART_LCR);
1187 val = inb(base + UART_SCR);
1189 outb(0x80, UART_LCR);
1190 if (!(inb(UART_SCR) & 0x20)) {
1191 outb(LCR, base + UART_LCR);
1198 static int pci_quatech_test(struct uart_8250_port *port)
1201 u8 qopr = pci_quatech_rqopr(port);
1202 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1203 reg = pci_quatech_rqopr(port) & 0xC0;
1204 if (reg != QPCR_TEST_GET1)
1206 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1207 reg = pci_quatech_rqopr(port) & 0xC0;
1208 if (reg != QPCR_TEST_GET2)
1210 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1211 reg = pci_quatech_rqopr(port) & 0xC0;
1212 if (reg != QPCR_TEST_GET3)
1214 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1215 reg = pci_quatech_rqopr(port) & 0xC0;
1216 if (reg != QPCR_TEST_GET4)
1219 pci_quatech_wqopr(port, qopr);
1223 static int pci_quatech_clock(struct uart_8250_port *port)
1226 unsigned long clock;
1228 if (pci_quatech_test(port) < 0)
1231 qopr = pci_quatech_rqopr(port);
1233 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1234 reg = pci_quatech_rqopr(port);
1235 if (reg & QOPR_CLOCK_X8) {
1239 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1240 reg = pci_quatech_rqopr(port);
1241 if (!(reg & QOPR_CLOCK_X8)) {
1245 reg &= QOPR_CLOCK_X8;
1246 if (reg == QOPR_CLOCK_X2) {
1248 set = QOPR_CLOCK_X2;
1249 } else if (reg == QOPR_CLOCK_X4) {
1251 set = QOPR_CLOCK_X4;
1252 } else if (reg == QOPR_CLOCK_X8) {
1254 set = QOPR_CLOCK_X8;
1257 set = QOPR_CLOCK_X1;
1259 qopr &= ~QOPR_CLOCK_RATE_MASK;
1263 pci_quatech_wqopr(port, qopr);
1267 static int pci_quatech_rs422(struct uart_8250_port *port)
1272 if (!pci_quatech_has_qmcr(port))
1274 qmcr = pci_quatech_rqmcr(port);
1275 pci_quatech_wqmcr(port, 0xFF);
1276 if (pci_quatech_rqmcr(port))
1278 pci_quatech_wqmcr(port, qmcr);
1282 static int pci_quatech_init(struct pci_dev *dev)
1284 if (pci_quatech_amcc(dev->device)) {
1285 unsigned long base = pci_resource_start(dev, 0);
1288 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1289 tmp = inl(base + 0x3c);
1290 outl(tmp | 0x01000000, base + 0x3c);
1291 outl(tmp &= ~0x01000000, base + 0x3c);
1297 static int pci_quatech_setup(struct serial_private *priv,
1298 const struct pciserial_board *board,
1299 struct uart_8250_port *port, int idx)
1301 /* Needed by pci_quatech calls below */
1302 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1303 /* Set up the clocking */
1304 port->port.uartclk = pci_quatech_clock(port);
1305 /* For now just warn about RS422 */
1306 if (pci_quatech_rs422(port))
1307 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1308 return pci_default_setup(priv, board, port, idx);
1311 static void pci_quatech_exit(struct pci_dev *dev)
1315 static int pci_default_setup(struct serial_private *priv,
1316 const struct pciserial_board *board,
1317 struct uart_8250_port *port, int idx)
1319 unsigned int bar, offset = board->first_offset, maxnr;
1321 bar = FL_GET_BASE(board->flags);
1322 if (board->flags & FL_BASE_BARS)
1325 offset += idx * board->uart_offset;
1327 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1328 (board->reg_shift + 3);
1330 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1333 return setup_port(priv, port, bar, offset, board->reg_shift);
1336 static int pci_pericom_setup(struct serial_private *priv,
1337 const struct pciserial_board *board,
1338 struct uart_8250_port *port, int idx)
1340 unsigned int bar, offset = board->first_offset, maxnr;
1342 bar = FL_GET_BASE(board->flags);
1343 if (board->flags & FL_BASE_BARS)
1346 offset += idx * board->uart_offset;
1348 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1349 (board->reg_shift + 3);
1351 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1354 port->port.uartclk = 14745600;
1356 return setup_port(priv, port, bar, offset, board->reg_shift);
1360 ce4100_serial_setup(struct serial_private *priv,
1361 const struct pciserial_board *board,
1362 struct uart_8250_port *port, int idx)
1366 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1367 port->port.iotype = UPIO_MEM32;
1368 port->port.type = PORT_XSCALE;
1369 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1370 port->port.regshift = 2;
1375 #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1376 #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1378 #define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
1379 #define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
1381 #define BYT_PRV_CLK 0x800
1382 #define BYT_PRV_CLK_EN (1 << 0)
1383 #define BYT_PRV_CLK_M_VAL_SHIFT 1
1384 #define BYT_PRV_CLK_N_VAL_SHIFT 16
1385 #define BYT_PRV_CLK_UPDATE (1 << 31)
1387 #define BYT_TX_OVF_INT 0x820
1388 #define BYT_TX_OVF_INT_MASK (1 << 1)
1391 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1392 struct ktermios *old)
1394 unsigned int baud = tty_termios_baud_rate(termios);
1399 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1400 * dividers must be adjusted.
1402 * uartclk = (m / n) * 100 MHz, where m <= n
1411 p->uartclk = 64000000;
1416 p->uartclk = 56000000;
1422 p->uartclk = 48000000;
1427 p->uartclk = 40000000;
1432 p->uartclk = 73728000;
1435 /* Reset the clock */
1436 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1437 writel(reg, p->membase + BYT_PRV_CLK);
1438 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1439 writel(reg, p->membase + BYT_PRV_CLK);
1441 serial8250_do_set_termios(p, termios, old);
1444 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1446 struct dw_dma_slave *dws = param;
1448 if (dws->dma_dev != chan->device->dev)
1451 chan->private = dws;
1456 byt_serial_setup(struct serial_private *priv,
1457 const struct pciserial_board *board,
1458 struct uart_8250_port *port, int idx)
1460 struct pci_dev *pdev = priv->dev;
1461 struct device *dev = port->port.dev;
1462 struct uart_8250_dma *dma;
1463 struct dw_dma_slave *tx_param, *rx_param;
1464 struct pci_dev *dma_dev;
1467 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1471 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1475 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1479 switch (pdev->device) {
1480 case PCI_DEVICE_ID_INTEL_BYT_UART1:
1481 case PCI_DEVICE_ID_INTEL_BSW_UART1:
1482 rx_param->src_id = 3;
1483 tx_param->dst_id = 2;
1485 case PCI_DEVICE_ID_INTEL_BYT_UART2:
1486 case PCI_DEVICE_ID_INTEL_BSW_UART2:
1487 rx_param->src_id = 5;
1488 tx_param->dst_id = 4;
1494 rx_param->src_master = 1;
1495 rx_param->dst_master = 0;
1497 dma->rxconf.src_maxburst = 16;
1499 tx_param->src_master = 1;
1500 tx_param->dst_master = 0;
1502 dma->txconf.dst_maxburst = 16;
1504 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1505 rx_param->dma_dev = &dma_dev->dev;
1506 tx_param->dma_dev = &dma_dev->dev;
1508 dma->fn = byt_dma_filter;
1509 dma->rx_param = rx_param;
1510 dma->tx_param = tx_param;
1512 ret = pci_default_setup(priv, board, port, idx);
1513 port->port.iotype = UPIO_MEM;
1514 port->port.type = PORT_16550A;
1515 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1516 port->port.set_termios = byt_set_termios;
1517 port->port.fifosize = 64;
1518 port->tx_loadsz = 64;
1520 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1522 /* Disable Tx counter interrupts */
1523 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1529 pci_omegapci_setup(struct serial_private *priv,
1530 const struct pciserial_board *board,
1531 struct uart_8250_port *port, int idx)
1533 return setup_port(priv, port, 2, idx * 8, 0);
1537 pci_brcm_trumanage_setup(struct serial_private *priv,
1538 const struct pciserial_board *board,
1539 struct uart_8250_port *port, int idx)
1541 int ret = pci_default_setup(priv, board, port, idx);
1543 port->port.type = PORT_BRCM_TRUMANAGE;
1544 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1548 static int pci_fintek_setup(struct serial_private *priv,
1549 const struct pciserial_board *board,
1550 struct uart_8250_port *port, int idx)
1552 struct pci_dev *pdev = priv->dev;
1554 unsigned long iobase;
1555 unsigned long ciobase = 0;
1560 * Find each UARTs offset in PCI configuraion space
1600 /* Unknown number of ports, get out of here */
1605 base = pci_resource_start(priv->dev, 3);
1606 ciobase = (int)(base + (0x8 * idx));
1609 /* Get the io address dispatch from the BIOS */
1610 pci_read_config_dword(pdev, 0x24, &bar_data[0]);
1611 pci_read_config_dword(pdev, 0x20, &bar_data[1]);
1612 pci_read_config_dword(pdev, 0x1c, &bar_data[2]);
1614 /* Calculate Real IO Port */
1615 iobase = (bar_data[idx/4] & 0xffffffe0) + (idx % 4) * 8;
1617 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx ciobase=0x%lx config_base=0x%2x\n",
1618 __func__, idx, iobase, ciobase, config_base);
1620 /* Enable UART I/O port */
1621 pci_write_config_byte(pdev, config_base + 0x00, 0x01);
1623 /* Select 128-byte FIFO and 8x FIFO threshold */
1624 pci_write_config_byte(pdev, config_base + 0x01, 0x33);
1627 pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff));
1630 pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8));
1632 /* irq number, this usually fails, but the spec says to do it anyway. */
1633 pci_write_config_byte(pdev, config_base + 0x06, pdev->irq);
1635 port->port.iotype = UPIO_PORT;
1636 port->port.iobase = iobase;
1637 port->port.mapbase = 0;
1638 port->port.membase = NULL;
1639 port->port.regshift = 0;
1644 static int skip_tx_en_setup(struct serial_private *priv,
1645 const struct pciserial_board *board,
1646 struct uart_8250_port *port, int idx)
1648 port->port.flags |= UPF_NO_TXEN_TEST;
1649 dev_dbg(&priv->dev->dev,
1650 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1651 priv->dev->vendor, priv->dev->device,
1652 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1654 return pci_default_setup(priv, board, port, idx);
1657 static void kt_handle_break(struct uart_port *p)
1659 struct uart_8250_port *up = up_to_u8250p(p);
1661 * On receipt of a BI, serial device in Intel ME (Intel
1662 * management engine) needs to have its fifos cleared for sane
1663 * SOL (Serial Over Lan) output.
1665 serial8250_clear_and_reinit_fifos(up);
1668 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1670 struct uart_8250_port *up = up_to_u8250p(p);
1674 * When the Intel ME (management engine) gets reset its serial
1675 * port registers could return 0 momentarily. Functions like
1676 * serial8250_console_write, read and save the IER, perform
1677 * some operation and then restore it. In order to avoid
1678 * setting IER register inadvertently to 0, if the value read
1679 * is 0, double check with ier value in uart_8250_port and use
1680 * that instead. up->ier should be the same value as what is
1681 * currently configured.
1683 val = inb(p->iobase + offset);
1684 if (offset == UART_IER) {
1691 static int kt_serial_setup(struct serial_private *priv,
1692 const struct pciserial_board *board,
1693 struct uart_8250_port *port, int idx)
1695 port->port.flags |= UPF_BUG_THRE;
1696 port->port.serial_in = kt_serial_in;
1697 port->port.handle_break = kt_handle_break;
1698 return skip_tx_en_setup(priv, board, port, idx);
1701 static int pci_eg20t_init(struct pci_dev *dev)
1703 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1711 pci_xr17c154_setup(struct serial_private *priv,
1712 const struct pciserial_board *board,
1713 struct uart_8250_port *port, int idx)
1715 port->port.flags |= UPF_EXAR_EFR;
1716 return pci_default_setup(priv, board, port, idx);
1720 pci_xr17v35x_setup(struct serial_private *priv,
1721 const struct pciserial_board *board,
1722 struct uart_8250_port *port, int idx)
1726 p = pci_ioremap_bar(priv->dev, 0);
1730 port->port.flags |= UPF_EXAR_EFR;
1733 * Setup Multipurpose Input/Output pins.
1736 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1737 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1738 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1739 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1740 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1741 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1742 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1743 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1744 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1745 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1746 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1747 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1749 writeb(0x00, p + UART_EXAR_8XMODE);
1750 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1751 writeb(128, p + UART_EXAR_TXTRG);
1752 writeb(128, p + UART_EXAR_RXTRG);
1755 return pci_default_setup(priv, board, port, idx);
1758 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1759 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1760 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1761 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1764 pci_fastcom335_setup(struct serial_private *priv,
1765 const struct pciserial_board *board,
1766 struct uart_8250_port *port, int idx)
1770 p = pci_ioremap_bar(priv->dev, 0);
1774 port->port.flags |= UPF_EXAR_EFR;
1777 * Setup Multipurpose Input/Output pins.
1780 switch (priv->dev->device) {
1781 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1782 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1783 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1784 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1785 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1787 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1788 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1789 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1790 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1791 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1794 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1795 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1796 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1798 writeb(0x00, p + UART_EXAR_8XMODE);
1799 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1800 writeb(32, p + UART_EXAR_TXTRG);
1801 writeb(32, p + UART_EXAR_RXTRG);
1804 return pci_default_setup(priv, board, port, idx);
1808 pci_wch_ch353_setup(struct serial_private *priv,
1809 const struct pciserial_board *board,
1810 struct uart_8250_port *port, int idx)
1812 port->port.flags |= UPF_FIXED_TYPE;
1813 port->port.type = PORT_16550A;
1814 return pci_default_setup(priv, board, port, idx);
1818 pci_wch_ch382_setup(struct serial_private *priv,
1819 const struct pciserial_board *board,
1820 struct uart_8250_port *port, int idx)
1822 port->port.flags |= UPF_FIXED_TYPE;
1823 port->port.type = PORT_16850;
1824 return pci_default_setup(priv, board, port, idx);
1827 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1828 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1829 #define PCI_DEVICE_ID_OCTPRO 0x0001
1830 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1831 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1832 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1833 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1834 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1835 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1836 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1837 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1838 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1839 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1840 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1841 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1842 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1843 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1844 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1845 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1846 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1847 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1848 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1849 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1850 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1851 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1852 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1853 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1854 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1855 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1856 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1857 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1858 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1859 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1860 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1861 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1862 #define PCI_VENDOR_ID_WCH 0x4348
1863 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1864 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1865 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1866 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1867 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1868 #define PCI_VENDOR_ID_AGESTAR 0x5372
1869 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1870 #define PCI_VENDOR_ID_ASIX 0x9710
1871 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1872 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1873 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1874 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1875 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1876 #define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936
1878 #define PCI_VENDOR_ID_SUNIX 0x1fd4
1879 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
1881 #define PCIE_VENDOR_ID_WCH 0x1c00
1882 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1884 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1885 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1886 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1889 * Master list of serial port init/setup/exit quirks.
1890 * This does not describe the general nature of the port.
1891 * (ie, baud base, number and location of ports, etc)
1893 * This list is ordered alphabetically by vendor then device.
1894 * Specific entries must come before more generic entries.
1896 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1898 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1901 .vendor = PCI_VENDOR_ID_AMCC,
1902 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1903 .subvendor = PCI_ANY_ID,
1904 .subdevice = PCI_ANY_ID,
1905 .setup = addidata_apci7800_setup,
1908 * AFAVLAB cards - these may be called via parport_serial
1909 * It is not clear whether this applies to all products.
1912 .vendor = PCI_VENDOR_ID_AFAVLAB,
1913 .device = PCI_ANY_ID,
1914 .subvendor = PCI_ANY_ID,
1915 .subdevice = PCI_ANY_ID,
1916 .setup = afavlab_setup,
1922 .vendor = PCI_VENDOR_ID_HP,
1923 .device = PCI_DEVICE_ID_HP_DIVA,
1924 .subvendor = PCI_ANY_ID,
1925 .subdevice = PCI_ANY_ID,
1926 .init = pci_hp_diva_init,
1927 .setup = pci_hp_diva_setup,
1933 .vendor = PCI_VENDOR_ID_INTEL,
1934 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1935 .subvendor = 0xe4bf,
1936 .subdevice = PCI_ANY_ID,
1937 .init = pci_inteli960ni_init,
1938 .setup = pci_default_setup,
1941 .vendor = PCI_VENDOR_ID_INTEL,
1942 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1943 .subvendor = PCI_ANY_ID,
1944 .subdevice = PCI_ANY_ID,
1945 .setup = skip_tx_en_setup,
1948 .vendor = PCI_VENDOR_ID_INTEL,
1949 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1950 .subvendor = PCI_ANY_ID,
1951 .subdevice = PCI_ANY_ID,
1952 .setup = skip_tx_en_setup,
1955 .vendor = PCI_VENDOR_ID_INTEL,
1956 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1957 .subvendor = PCI_ANY_ID,
1958 .subdevice = PCI_ANY_ID,
1959 .setup = skip_tx_en_setup,
1962 .vendor = PCI_VENDOR_ID_INTEL,
1963 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1964 .subvendor = PCI_ANY_ID,
1965 .subdevice = PCI_ANY_ID,
1966 .setup = ce4100_serial_setup,
1969 .vendor = PCI_VENDOR_ID_INTEL,
1970 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1971 .subvendor = PCI_ANY_ID,
1972 .subdevice = PCI_ANY_ID,
1973 .setup = kt_serial_setup,
1976 .vendor = PCI_VENDOR_ID_INTEL,
1977 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
1978 .subvendor = PCI_ANY_ID,
1979 .subdevice = PCI_ANY_ID,
1980 .setup = byt_serial_setup,
1983 .vendor = PCI_VENDOR_ID_INTEL,
1984 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
1985 .subvendor = PCI_ANY_ID,
1986 .subdevice = PCI_ANY_ID,
1987 .setup = byt_serial_setup,
1990 .vendor = PCI_VENDOR_ID_INTEL,
1991 .device = PCI_DEVICE_ID_INTEL_QRK_UART,
1992 .subvendor = PCI_ANY_ID,
1993 .subdevice = PCI_ANY_ID,
1994 .setup = pci_default_setup,
1997 .vendor = PCI_VENDOR_ID_INTEL,
1998 .device = PCI_DEVICE_ID_INTEL_BSW_UART1,
1999 .subvendor = PCI_ANY_ID,
2000 .subdevice = PCI_ANY_ID,
2001 .setup = byt_serial_setup,
2004 .vendor = PCI_VENDOR_ID_INTEL,
2005 .device = PCI_DEVICE_ID_INTEL_BSW_UART2,
2006 .subvendor = PCI_ANY_ID,
2007 .subdevice = PCI_ANY_ID,
2008 .setup = byt_serial_setup,
2014 .vendor = PCI_VENDOR_ID_ITE,
2015 .device = PCI_DEVICE_ID_ITE_8872,
2016 .subvendor = PCI_ANY_ID,
2017 .subdevice = PCI_ANY_ID,
2018 .init = pci_ite887x_init,
2019 .setup = pci_default_setup,
2020 .exit = pci_ite887x_exit,
2023 * National Instruments
2026 .vendor = PCI_VENDOR_ID_NI,
2027 .device = PCI_DEVICE_ID_NI_PCI23216,
2028 .subvendor = PCI_ANY_ID,
2029 .subdevice = PCI_ANY_ID,
2030 .init = pci_ni8420_init,
2031 .setup = pci_default_setup,
2032 .exit = pci_ni8420_exit,
2035 .vendor = PCI_VENDOR_ID_NI,
2036 .device = PCI_DEVICE_ID_NI_PCI2328,
2037 .subvendor = PCI_ANY_ID,
2038 .subdevice = PCI_ANY_ID,
2039 .init = pci_ni8420_init,
2040 .setup = pci_default_setup,
2041 .exit = pci_ni8420_exit,
2044 .vendor = PCI_VENDOR_ID_NI,
2045 .device = PCI_DEVICE_ID_NI_PCI2324,
2046 .subvendor = PCI_ANY_ID,
2047 .subdevice = PCI_ANY_ID,
2048 .init = pci_ni8420_init,
2049 .setup = pci_default_setup,
2050 .exit = pci_ni8420_exit,
2053 .vendor = PCI_VENDOR_ID_NI,
2054 .device = PCI_DEVICE_ID_NI_PCI2322,
2055 .subvendor = PCI_ANY_ID,
2056 .subdevice = PCI_ANY_ID,
2057 .init = pci_ni8420_init,
2058 .setup = pci_default_setup,
2059 .exit = pci_ni8420_exit,
2062 .vendor = PCI_VENDOR_ID_NI,
2063 .device = PCI_DEVICE_ID_NI_PCI2324I,
2064 .subvendor = PCI_ANY_ID,
2065 .subdevice = PCI_ANY_ID,
2066 .init = pci_ni8420_init,
2067 .setup = pci_default_setup,
2068 .exit = pci_ni8420_exit,
2071 .vendor = PCI_VENDOR_ID_NI,
2072 .device = PCI_DEVICE_ID_NI_PCI2322I,
2073 .subvendor = PCI_ANY_ID,
2074 .subdevice = PCI_ANY_ID,
2075 .init = pci_ni8420_init,
2076 .setup = pci_default_setup,
2077 .exit = pci_ni8420_exit,
2080 .vendor = PCI_VENDOR_ID_NI,
2081 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2082 .subvendor = PCI_ANY_ID,
2083 .subdevice = PCI_ANY_ID,
2084 .init = pci_ni8420_init,
2085 .setup = pci_default_setup,
2086 .exit = pci_ni8420_exit,
2089 .vendor = PCI_VENDOR_ID_NI,
2090 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2091 .subvendor = PCI_ANY_ID,
2092 .subdevice = PCI_ANY_ID,
2093 .init = pci_ni8420_init,
2094 .setup = pci_default_setup,
2095 .exit = pci_ni8420_exit,
2098 .vendor = PCI_VENDOR_ID_NI,
2099 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2100 .subvendor = PCI_ANY_ID,
2101 .subdevice = PCI_ANY_ID,
2102 .init = pci_ni8420_init,
2103 .setup = pci_default_setup,
2104 .exit = pci_ni8420_exit,
2107 .vendor = PCI_VENDOR_ID_NI,
2108 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2109 .subvendor = PCI_ANY_ID,
2110 .subdevice = PCI_ANY_ID,
2111 .init = pci_ni8420_init,
2112 .setup = pci_default_setup,
2113 .exit = pci_ni8420_exit,
2116 .vendor = PCI_VENDOR_ID_NI,
2117 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2118 .subvendor = PCI_ANY_ID,
2119 .subdevice = PCI_ANY_ID,
2120 .init = pci_ni8420_init,
2121 .setup = pci_default_setup,
2122 .exit = pci_ni8420_exit,
2125 .vendor = PCI_VENDOR_ID_NI,
2126 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2127 .subvendor = PCI_ANY_ID,
2128 .subdevice = PCI_ANY_ID,
2129 .init = pci_ni8420_init,
2130 .setup = pci_default_setup,
2131 .exit = pci_ni8420_exit,
2134 .vendor = PCI_VENDOR_ID_NI,
2135 .device = PCI_ANY_ID,
2136 .subvendor = PCI_ANY_ID,
2137 .subdevice = PCI_ANY_ID,
2138 .init = pci_ni8430_init,
2139 .setup = pci_ni8430_setup,
2140 .exit = pci_ni8430_exit,
2144 .vendor = PCI_VENDOR_ID_QUATECH,
2145 .device = PCI_ANY_ID,
2146 .subvendor = PCI_ANY_ID,
2147 .subdevice = PCI_ANY_ID,
2148 .init = pci_quatech_init,
2149 .setup = pci_quatech_setup,
2150 .exit = pci_quatech_exit,
2156 .vendor = PCI_VENDOR_ID_PANACOM,
2157 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2158 .subvendor = PCI_ANY_ID,
2159 .subdevice = PCI_ANY_ID,
2160 .init = pci_plx9050_init,
2161 .setup = pci_default_setup,
2162 .exit = pci_plx9050_exit,
2165 .vendor = PCI_VENDOR_ID_PANACOM,
2166 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2167 .subvendor = PCI_ANY_ID,
2168 .subdevice = PCI_ANY_ID,
2169 .init = pci_plx9050_init,
2170 .setup = pci_default_setup,
2171 .exit = pci_plx9050_exit,
2179 .subvendor = PCI_ANY_ID,
2180 .subdevice = PCI_ANY_ID,
2181 .setup = pci_pericom_setup,
2186 .subvendor = PCI_ANY_ID,
2187 .subdevice = PCI_ANY_ID,
2188 .setup = pci_pericom_setup,
2193 .subvendor = PCI_ANY_ID,
2194 .subdevice = PCI_ANY_ID,
2195 .setup = pci_pericom_setup,
2202 .vendor = PCI_VENDOR_ID_PLX,
2203 .device = PCI_DEVICE_ID_PLX_9030,
2204 .subvendor = PCI_SUBVENDOR_ID_PERLE,
2205 .subdevice = PCI_ANY_ID,
2206 .setup = pci_default_setup,
2209 .vendor = PCI_VENDOR_ID_PLX,
2210 .device = PCI_DEVICE_ID_PLX_9050,
2211 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2212 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2213 .init = pci_plx9050_init,
2214 .setup = pci_default_setup,
2215 .exit = pci_plx9050_exit,
2218 .vendor = PCI_VENDOR_ID_PLX,
2219 .device = PCI_DEVICE_ID_PLX_9050,
2220 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2221 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2222 .init = pci_plx9050_init,
2223 .setup = pci_default_setup,
2224 .exit = pci_plx9050_exit,
2227 .vendor = PCI_VENDOR_ID_PLX,
2228 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2229 .subvendor = PCI_VENDOR_ID_PLX,
2230 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2231 .init = pci_plx9050_init,
2232 .setup = pci_default_setup,
2233 .exit = pci_plx9050_exit,
2236 * SBS Technologies, Inc., PMC-OCTALPRO 232
2239 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2240 .device = PCI_DEVICE_ID_OCTPRO,
2241 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2242 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2248 * SBS Technologies, Inc., PMC-OCTALPRO 422
2251 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2252 .device = PCI_DEVICE_ID_OCTPRO,
2253 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2254 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2260 * SBS Technologies, Inc., P-Octal 232
2263 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2264 .device = PCI_DEVICE_ID_OCTPRO,
2265 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2266 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2272 * SBS Technologies, Inc., P-Octal 422
2275 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2276 .device = PCI_DEVICE_ID_OCTPRO,
2277 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2278 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2284 * SIIG cards - these may be called via parport_serial
2287 .vendor = PCI_VENDOR_ID_SIIG,
2288 .device = PCI_ANY_ID,
2289 .subvendor = PCI_ANY_ID,
2290 .subdevice = PCI_ANY_ID,
2291 .init = pci_siig_init,
2292 .setup = pci_siig_setup,
2298 .vendor = PCI_VENDOR_ID_TITAN,
2299 .device = PCI_DEVICE_ID_TITAN_400L,
2300 .subvendor = PCI_ANY_ID,
2301 .subdevice = PCI_ANY_ID,
2302 .setup = titan_400l_800l_setup,
2305 .vendor = PCI_VENDOR_ID_TITAN,
2306 .device = PCI_DEVICE_ID_TITAN_800L,
2307 .subvendor = PCI_ANY_ID,
2308 .subdevice = PCI_ANY_ID,
2309 .setup = titan_400l_800l_setup,
2315 .vendor = PCI_VENDOR_ID_TIMEDIA,
2316 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2317 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2318 .subdevice = PCI_ANY_ID,
2319 .probe = pci_timedia_probe,
2320 .init = pci_timedia_init,
2321 .setup = pci_timedia_setup,
2324 .vendor = PCI_VENDOR_ID_TIMEDIA,
2325 .device = PCI_ANY_ID,
2326 .subvendor = PCI_ANY_ID,
2327 .subdevice = PCI_ANY_ID,
2328 .setup = pci_timedia_setup,
2331 * SUNIX (Timedia) cards
2332 * Do not "probe" for these cards as there is at least one combination
2333 * card that should be handled by parport_pc that doesn't match the
2334 * rule in pci_timedia_probe.
2335 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2336 * There are some boards with part number SER5037AL that report
2337 * subdevice ID 0x0002.
2340 .vendor = PCI_VENDOR_ID_SUNIX,
2341 .device = PCI_DEVICE_ID_SUNIX_1999,
2342 .subvendor = PCI_VENDOR_ID_SUNIX,
2343 .subdevice = PCI_ANY_ID,
2344 .init = pci_timedia_init,
2345 .setup = pci_timedia_setup,
2351 .vendor = PCI_VENDOR_ID_EXAR,
2352 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2353 .subvendor = PCI_ANY_ID,
2354 .subdevice = PCI_ANY_ID,
2355 .setup = pci_xr17c154_setup,
2358 .vendor = PCI_VENDOR_ID_EXAR,
2359 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2360 .subvendor = PCI_ANY_ID,
2361 .subdevice = PCI_ANY_ID,
2362 .setup = pci_xr17c154_setup,
2365 .vendor = PCI_VENDOR_ID_EXAR,
2366 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2367 .subvendor = PCI_ANY_ID,
2368 .subdevice = PCI_ANY_ID,
2369 .setup = pci_xr17c154_setup,
2372 .vendor = PCI_VENDOR_ID_EXAR,
2373 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2374 .subvendor = PCI_ANY_ID,
2375 .subdevice = PCI_ANY_ID,
2376 .setup = pci_xr17v35x_setup,
2379 .vendor = PCI_VENDOR_ID_EXAR,
2380 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2381 .subvendor = PCI_ANY_ID,
2382 .subdevice = PCI_ANY_ID,
2383 .setup = pci_xr17v35x_setup,
2386 .vendor = PCI_VENDOR_ID_EXAR,
2387 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2388 .subvendor = PCI_ANY_ID,
2389 .subdevice = PCI_ANY_ID,
2390 .setup = pci_xr17v35x_setup,
2396 .vendor = PCI_VENDOR_ID_XIRCOM,
2397 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2398 .subvendor = PCI_ANY_ID,
2399 .subdevice = PCI_ANY_ID,
2400 .init = pci_xircom_init,
2401 .setup = pci_default_setup,
2404 * Netmos cards - these may be called via parport_serial
2407 .vendor = PCI_VENDOR_ID_NETMOS,
2408 .device = PCI_ANY_ID,
2409 .subvendor = PCI_ANY_ID,
2410 .subdevice = PCI_ANY_ID,
2411 .init = pci_netmos_init,
2412 .setup = pci_netmos_9900_setup,
2415 * EndRun Technologies
2418 .vendor = PCI_VENDOR_ID_ENDRUN,
2419 .device = PCI_ANY_ID,
2420 .subvendor = PCI_ANY_ID,
2421 .subdevice = PCI_ANY_ID,
2422 .init = pci_endrun_init,
2423 .setup = pci_default_setup,
2426 * For Oxford Semiconductor Tornado based devices
2429 .vendor = PCI_VENDOR_ID_OXSEMI,
2430 .device = PCI_ANY_ID,
2431 .subvendor = PCI_ANY_ID,
2432 .subdevice = PCI_ANY_ID,
2433 .init = pci_oxsemi_tornado_init,
2434 .setup = pci_default_setup,
2437 .vendor = PCI_VENDOR_ID_MAINPINE,
2438 .device = PCI_ANY_ID,
2439 .subvendor = PCI_ANY_ID,
2440 .subdevice = PCI_ANY_ID,
2441 .init = pci_oxsemi_tornado_init,
2442 .setup = pci_default_setup,
2445 .vendor = PCI_VENDOR_ID_DIGI,
2446 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2447 .subvendor = PCI_SUBVENDOR_ID_IBM,
2448 .subdevice = PCI_ANY_ID,
2449 .init = pci_oxsemi_tornado_init,
2450 .setup = pci_default_setup,
2453 .vendor = PCI_VENDOR_ID_INTEL,
2455 .subvendor = PCI_ANY_ID,
2456 .subdevice = PCI_ANY_ID,
2457 .init = pci_eg20t_init,
2458 .setup = pci_default_setup,
2461 .vendor = PCI_VENDOR_ID_INTEL,
2463 .subvendor = PCI_ANY_ID,
2464 .subdevice = PCI_ANY_ID,
2465 .init = pci_eg20t_init,
2466 .setup = pci_default_setup,
2469 .vendor = PCI_VENDOR_ID_INTEL,
2471 .subvendor = PCI_ANY_ID,
2472 .subdevice = PCI_ANY_ID,
2473 .init = pci_eg20t_init,
2474 .setup = pci_default_setup,
2477 .vendor = PCI_VENDOR_ID_INTEL,
2479 .subvendor = PCI_ANY_ID,
2480 .subdevice = PCI_ANY_ID,
2481 .init = pci_eg20t_init,
2482 .setup = pci_default_setup,
2487 .subvendor = PCI_ANY_ID,
2488 .subdevice = PCI_ANY_ID,
2489 .init = pci_eg20t_init,
2490 .setup = pci_default_setup,
2495 .subvendor = PCI_ANY_ID,
2496 .subdevice = PCI_ANY_ID,
2497 .init = pci_eg20t_init,
2498 .setup = pci_default_setup,
2503 .subvendor = PCI_ANY_ID,
2504 .subdevice = PCI_ANY_ID,
2505 .init = pci_eg20t_init,
2506 .setup = pci_default_setup,
2511 .subvendor = PCI_ANY_ID,
2512 .subdevice = PCI_ANY_ID,
2513 .init = pci_eg20t_init,
2514 .setup = pci_default_setup,
2519 .subvendor = PCI_ANY_ID,
2520 .subdevice = PCI_ANY_ID,
2521 .init = pci_eg20t_init,
2522 .setup = pci_default_setup,
2525 * Cronyx Omega PCI (PLX-chip based)
2528 .vendor = PCI_VENDOR_ID_PLX,
2529 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2530 .subvendor = PCI_ANY_ID,
2531 .subdevice = PCI_ANY_ID,
2532 .setup = pci_omegapci_setup,
2534 /* WCH CH353 1S1P card (16550 clone) */
2536 .vendor = PCI_VENDOR_ID_WCH,
2537 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2538 .subvendor = PCI_ANY_ID,
2539 .subdevice = PCI_ANY_ID,
2540 .setup = pci_wch_ch353_setup,
2542 /* WCH CH353 2S1P card (16550 clone) */
2544 .vendor = PCI_VENDOR_ID_WCH,
2545 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2546 .subvendor = PCI_ANY_ID,
2547 .subdevice = PCI_ANY_ID,
2548 .setup = pci_wch_ch353_setup,
2550 /* WCH CH353 4S card (16550 clone) */
2552 .vendor = PCI_VENDOR_ID_WCH,
2553 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2554 .subvendor = PCI_ANY_ID,
2555 .subdevice = PCI_ANY_ID,
2556 .setup = pci_wch_ch353_setup,
2558 /* WCH CH353 2S1PF card (16550 clone) */
2560 .vendor = PCI_VENDOR_ID_WCH,
2561 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2562 .subvendor = PCI_ANY_ID,
2563 .subdevice = PCI_ANY_ID,
2564 .setup = pci_wch_ch353_setup,
2566 /* WCH CH352 2S card (16550 clone) */
2568 .vendor = PCI_VENDOR_ID_WCH,
2569 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2570 .subvendor = PCI_ANY_ID,
2571 .subdevice = PCI_ANY_ID,
2572 .setup = pci_wch_ch353_setup,
2574 /* WCH CH382 2S1P card (16750 clone) */
2576 .vendor = PCIE_VENDOR_ID_WCH,
2577 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2578 .subvendor = PCI_ANY_ID,
2579 .subdevice = PCI_ANY_ID,
2580 .setup = pci_wch_ch382_setup,
2583 * ASIX devices with FIFO bug
2586 .vendor = PCI_VENDOR_ID_ASIX,
2587 .device = PCI_ANY_ID,
2588 .subvendor = PCI_ANY_ID,
2589 .subdevice = PCI_ANY_ID,
2590 .setup = pci_asix_setup,
2593 * Commtech, Inc. Fastcom adapters
2597 .vendor = PCI_VENDOR_ID_COMMTECH,
2598 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2599 .subvendor = PCI_ANY_ID,
2600 .subdevice = PCI_ANY_ID,
2601 .setup = pci_fastcom335_setup,
2604 .vendor = PCI_VENDOR_ID_COMMTECH,
2605 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2606 .subvendor = PCI_ANY_ID,
2607 .subdevice = PCI_ANY_ID,
2608 .setup = pci_fastcom335_setup,
2611 .vendor = PCI_VENDOR_ID_COMMTECH,
2612 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2613 .subvendor = PCI_ANY_ID,
2614 .subdevice = PCI_ANY_ID,
2615 .setup = pci_fastcom335_setup,
2618 .vendor = PCI_VENDOR_ID_COMMTECH,
2619 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2620 .subvendor = PCI_ANY_ID,
2621 .subdevice = PCI_ANY_ID,
2622 .setup = pci_fastcom335_setup,
2625 .vendor = PCI_VENDOR_ID_COMMTECH,
2626 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2627 .subvendor = PCI_ANY_ID,
2628 .subdevice = PCI_ANY_ID,
2629 .setup = pci_xr17v35x_setup,
2632 .vendor = PCI_VENDOR_ID_COMMTECH,
2633 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2634 .subvendor = PCI_ANY_ID,
2635 .subdevice = PCI_ANY_ID,
2636 .setup = pci_xr17v35x_setup,
2639 .vendor = PCI_VENDOR_ID_COMMTECH,
2640 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2641 .subvendor = PCI_ANY_ID,
2642 .subdevice = PCI_ANY_ID,
2643 .setup = pci_xr17v35x_setup,
2646 * Broadcom TruManage (NetXtreme)
2649 .vendor = PCI_VENDOR_ID_BROADCOM,
2650 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2651 .subvendor = PCI_ANY_ID,
2652 .subdevice = PCI_ANY_ID,
2653 .setup = pci_brcm_trumanage_setup,
2658 .subvendor = PCI_ANY_ID,
2659 .subdevice = PCI_ANY_ID,
2660 .setup = pci_fintek_setup,
2665 .subvendor = PCI_ANY_ID,
2666 .subdevice = PCI_ANY_ID,
2667 .setup = pci_fintek_setup,
2672 .subvendor = PCI_ANY_ID,
2673 .subdevice = PCI_ANY_ID,
2674 .setup = pci_fintek_setup,
2678 * Default "match everything" terminator entry
2681 .vendor = PCI_ANY_ID,
2682 .device = PCI_ANY_ID,
2683 .subvendor = PCI_ANY_ID,
2684 .subdevice = PCI_ANY_ID,
2685 .setup = pci_default_setup,
2689 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2691 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2694 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2696 struct pci_serial_quirk *quirk;
2698 for (quirk = pci_serial_quirks; ; quirk++)
2699 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2700 quirk_id_matches(quirk->device, dev->device) &&
2701 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2702 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2707 static inline int get_pci_irq(struct pci_dev *dev,
2708 const struct pciserial_board *board)
2710 if (board->flags & FL_NOIRQ)
2717 * This is the configuration table for all of the PCI serial boards
2718 * which we support. It is directly indexed by the pci_board_num_t enum
2719 * value, which is encoded in the pci_device_id PCI probe table's
2720 * driver_data member.
2722 * The makeup of these names are:
2723 * pbn_bn{_bt}_n_baud{_offsetinhex}
2725 * bn = PCI BAR number
2726 * bt = Index using PCI BARs
2727 * n = number of serial ports
2729 * offsetinhex = offset for each sequential port (in hex)
2731 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2733 * Please note: in theory if n = 1, _bt infix should make no difference.
2734 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2736 enum pci_board_num_t {
2753 pbn_b0_2_1152000_200,
2754 pbn_b0_4_1152000_200,
2755 pbn_b0_8_1152000_200,
2760 pbn_b0_2_1843200_200,
2761 pbn_b0_4_1843200_200,
2762 pbn_b0_8_1843200_200,
2836 * Board-specific versions.
2842 pbn_endrun_2_4000000,
2844 pbn_oxsemi_1_4000000,
2845 pbn_oxsemi_2_4000000,
2846 pbn_oxsemi_4_4000000,
2847 pbn_oxsemi_8_4000000,
2860 pbn_exar_ibm_saturn,
2866 pbn_ADDIDATA_PCIe_1_3906250,
2867 pbn_ADDIDATA_PCIe_2_3906250,
2868 pbn_ADDIDATA_PCIe_4_3906250,
2869 pbn_ADDIDATA_PCIe_8_3906250,
2870 pbn_ce4100_1_115200,
2874 pbn_NETMOS9900_2s_115200,
2882 * uart_offset - the space between channels
2883 * reg_shift - describes how the UART registers are mapped
2884 * to PCI memory by the card.
2885 * For example IER register on SBS, Inc. PMC-OctPro is located at
2886 * offset 0x10 from the UART base, while UART_IER is defined as 1
2887 * in include/linux/serial_reg.h,
2888 * see first lines of serial_in() and serial_out() in 8250.c
2891 static struct pciserial_board pci_boards[] = {
2895 .base_baud = 115200,
2898 [pbn_b0_1_115200] = {
2901 .base_baud = 115200,
2904 [pbn_b0_2_115200] = {
2907 .base_baud = 115200,
2910 [pbn_b0_4_115200] = {
2913 .base_baud = 115200,
2916 [pbn_b0_5_115200] = {
2919 .base_baud = 115200,
2922 [pbn_b0_8_115200] = {
2925 .base_baud = 115200,
2928 [pbn_b0_1_921600] = {
2931 .base_baud = 921600,
2934 [pbn_b0_2_921600] = {
2937 .base_baud = 921600,
2940 [pbn_b0_4_921600] = {
2943 .base_baud = 921600,
2947 [pbn_b0_2_1130000] = {
2950 .base_baud = 1130000,
2954 [pbn_b0_4_1152000] = {
2957 .base_baud = 1152000,
2961 [pbn_b0_2_1152000_200] = {
2964 .base_baud = 1152000,
2965 .uart_offset = 0x200,
2968 [pbn_b0_4_1152000_200] = {
2971 .base_baud = 1152000,
2972 .uart_offset = 0x200,
2975 [pbn_b0_8_1152000_200] = {
2978 .base_baud = 1152000,
2979 .uart_offset = 0x200,
2982 [pbn_b0_2_1843200] = {
2985 .base_baud = 1843200,
2988 [pbn_b0_4_1843200] = {
2991 .base_baud = 1843200,
2995 [pbn_b0_2_1843200_200] = {
2998 .base_baud = 1843200,
2999 .uart_offset = 0x200,
3001 [pbn_b0_4_1843200_200] = {
3004 .base_baud = 1843200,
3005 .uart_offset = 0x200,
3007 [pbn_b0_8_1843200_200] = {
3010 .base_baud = 1843200,
3011 .uart_offset = 0x200,
3013 [pbn_b0_1_4000000] = {
3016 .base_baud = 4000000,
3020 [pbn_b0_bt_1_115200] = {
3021 .flags = FL_BASE0|FL_BASE_BARS,
3023 .base_baud = 115200,
3026 [pbn_b0_bt_2_115200] = {
3027 .flags = FL_BASE0|FL_BASE_BARS,
3029 .base_baud = 115200,
3032 [pbn_b0_bt_4_115200] = {
3033 .flags = FL_BASE0|FL_BASE_BARS,
3035 .base_baud = 115200,
3038 [pbn_b0_bt_8_115200] = {
3039 .flags = FL_BASE0|FL_BASE_BARS,
3041 .base_baud = 115200,
3045 [pbn_b0_bt_1_460800] = {
3046 .flags = FL_BASE0|FL_BASE_BARS,
3048 .base_baud = 460800,
3051 [pbn_b0_bt_2_460800] = {
3052 .flags = FL_BASE0|FL_BASE_BARS,
3054 .base_baud = 460800,
3057 [pbn_b0_bt_4_460800] = {
3058 .flags = FL_BASE0|FL_BASE_BARS,
3060 .base_baud = 460800,
3064 [pbn_b0_bt_1_921600] = {
3065 .flags = FL_BASE0|FL_BASE_BARS,
3067 .base_baud = 921600,
3070 [pbn_b0_bt_2_921600] = {
3071 .flags = FL_BASE0|FL_BASE_BARS,
3073 .base_baud = 921600,
3076 [pbn_b0_bt_4_921600] = {
3077 .flags = FL_BASE0|FL_BASE_BARS,
3079 .base_baud = 921600,
3082 [pbn_b0_bt_8_921600] = {
3083 .flags = FL_BASE0|FL_BASE_BARS,
3085 .base_baud = 921600,
3089 [pbn_b1_1_115200] = {
3092 .base_baud = 115200,
3095 [pbn_b1_2_115200] = {
3098 .base_baud = 115200,
3101 [pbn_b1_4_115200] = {
3104 .base_baud = 115200,
3107 [pbn_b1_8_115200] = {
3110 .base_baud = 115200,
3113 [pbn_b1_16_115200] = {
3116 .base_baud = 115200,
3120 [pbn_b1_1_921600] = {
3123 .base_baud = 921600,
3126 [pbn_b1_2_921600] = {
3129 .base_baud = 921600,
3132 [pbn_b1_4_921600] = {
3135 .base_baud = 921600,
3138 [pbn_b1_8_921600] = {
3141 .base_baud = 921600,
3144 [pbn_b1_2_1250000] = {
3147 .base_baud = 1250000,
3151 [pbn_b1_bt_1_115200] = {
3152 .flags = FL_BASE1|FL_BASE_BARS,
3154 .base_baud = 115200,
3157 [pbn_b1_bt_2_115200] = {
3158 .flags = FL_BASE1|FL_BASE_BARS,
3160 .base_baud = 115200,
3163 [pbn_b1_bt_4_115200] = {
3164 .flags = FL_BASE1|FL_BASE_BARS,
3166 .base_baud = 115200,
3170 [pbn_b1_bt_2_921600] = {
3171 .flags = FL_BASE1|FL_BASE_BARS,
3173 .base_baud = 921600,
3177 [pbn_b1_1_1382400] = {
3180 .base_baud = 1382400,
3183 [pbn_b1_2_1382400] = {
3186 .base_baud = 1382400,
3189 [pbn_b1_4_1382400] = {
3192 .base_baud = 1382400,
3195 [pbn_b1_8_1382400] = {
3198 .base_baud = 1382400,
3202 [pbn_b2_1_115200] = {
3205 .base_baud = 115200,
3208 [pbn_b2_2_115200] = {
3211 .base_baud = 115200,
3214 [pbn_b2_4_115200] = {
3217 .base_baud = 115200,
3220 [pbn_b2_8_115200] = {
3223 .base_baud = 115200,
3227 [pbn_b2_1_460800] = {
3230 .base_baud = 460800,
3233 [pbn_b2_4_460800] = {
3236 .base_baud = 460800,
3239 [pbn_b2_8_460800] = {
3242 .base_baud = 460800,
3245 [pbn_b2_16_460800] = {
3248 .base_baud = 460800,
3252 [pbn_b2_1_921600] = {
3255 .base_baud = 921600,
3258 [pbn_b2_4_921600] = {
3261 .base_baud = 921600,
3264 [pbn_b2_8_921600] = {
3267 .base_baud = 921600,
3271 [pbn_b2_8_1152000] = {
3274 .base_baud = 1152000,
3278 [pbn_b2_bt_1_115200] = {
3279 .flags = FL_BASE2|FL_BASE_BARS,
3281 .base_baud = 115200,
3284 [pbn_b2_bt_2_115200] = {
3285 .flags = FL_BASE2|FL_BASE_BARS,
3287 .base_baud = 115200,
3290 [pbn_b2_bt_4_115200] = {
3291 .flags = FL_BASE2|FL_BASE_BARS,
3293 .base_baud = 115200,
3297 [pbn_b2_bt_2_921600] = {
3298 .flags = FL_BASE2|FL_BASE_BARS,
3300 .base_baud = 921600,
3303 [pbn_b2_bt_4_921600] = {
3304 .flags = FL_BASE2|FL_BASE_BARS,
3306 .base_baud = 921600,
3310 [pbn_b3_2_115200] = {
3313 .base_baud = 115200,
3316 [pbn_b3_4_115200] = {
3319 .base_baud = 115200,
3322 [pbn_b3_8_115200] = {
3325 .base_baud = 115200,
3329 [pbn_b4_bt_2_921600] = {
3332 .base_baud = 921600,
3335 [pbn_b4_bt_4_921600] = {
3338 .base_baud = 921600,
3341 [pbn_b4_bt_8_921600] = {
3344 .base_baud = 921600,
3349 * Entries following this are board-specific.
3358 .base_baud = 921600,
3359 .uart_offset = 0x400,
3363 .flags = FL_BASE2|FL_BASE_BARS,
3365 .base_baud = 921600,
3366 .uart_offset = 0x400,
3370 .flags = FL_BASE2|FL_BASE_BARS,
3372 .base_baud = 921600,
3373 .uart_offset = 0x400,
3377 /* I think this entry is broken - the first_offset looks wrong --rmk */
3378 [pbn_plx_romulus] = {
3381 .base_baud = 921600,
3382 .uart_offset = 8 << 2,
3384 .first_offset = 0x03,
3388 * EndRun Technologies
3389 * Uses the size of PCI Base region 0 to
3390 * signal now many ports are available
3391 * 2 port 952 Uart support
3393 [pbn_endrun_2_4000000] = {
3396 .base_baud = 4000000,
3397 .uart_offset = 0x200,
3398 .first_offset = 0x1000,
3402 * This board uses the size of PCI Base region 0 to
3403 * signal now many ports are available
3406 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3408 .base_baud = 115200,
3411 [pbn_oxsemi_1_4000000] = {
3414 .base_baud = 4000000,
3415 .uart_offset = 0x200,
3416 .first_offset = 0x1000,
3418 [pbn_oxsemi_2_4000000] = {
3421 .base_baud = 4000000,
3422 .uart_offset = 0x200,
3423 .first_offset = 0x1000,
3425 [pbn_oxsemi_4_4000000] = {
3428 .base_baud = 4000000,
3429 .uart_offset = 0x200,
3430 .first_offset = 0x1000,
3432 [pbn_oxsemi_8_4000000] = {
3435 .base_baud = 4000000,
3436 .uart_offset = 0x200,
3437 .first_offset = 0x1000,
3442 * EKF addition for i960 Boards form EKF with serial port.
3445 [pbn_intel_i960] = {
3448 .base_baud = 921600,
3449 .uart_offset = 8 << 2,
3451 .first_offset = 0x10000,
3454 .flags = FL_BASE0|FL_NOIRQ,
3456 .base_baud = 458333,
3459 .first_offset = 0x20178,
3463 * Computone - uses IOMEM.
3465 [pbn_computone_4] = {
3468 .base_baud = 921600,
3469 .uart_offset = 0x40,
3471 .first_offset = 0x200,
3473 [pbn_computone_6] = {
3476 .base_baud = 921600,
3477 .uart_offset = 0x40,
3479 .first_offset = 0x200,
3481 [pbn_computone_8] = {
3484 .base_baud = 921600,
3485 .uart_offset = 0x40,
3487 .first_offset = 0x200,
3492 .base_baud = 460800,
3497 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3498 * Only basic 16550A support.
3499 * XR17C15[24] are not tested, but they should work.
3501 [pbn_exar_XR17C152] = {
3504 .base_baud = 921600,
3505 .uart_offset = 0x200,
3507 [pbn_exar_XR17C154] = {
3510 .base_baud = 921600,
3511 .uart_offset = 0x200,
3513 [pbn_exar_XR17C158] = {
3516 .base_baud = 921600,
3517 .uart_offset = 0x200,
3519 [pbn_exar_XR17V352] = {
3522 .base_baud = 7812500,
3523 .uart_offset = 0x400,
3527 [pbn_exar_XR17V354] = {
3530 .base_baud = 7812500,
3531 .uart_offset = 0x400,
3535 [pbn_exar_XR17V358] = {
3538 .base_baud = 7812500,
3539 .uart_offset = 0x400,
3543 [pbn_exar_ibm_saturn] = {
3546 .base_baud = 921600,
3547 .uart_offset = 0x200,
3551 * PA Semi PWRficient PA6T-1682M on-chip UART
3553 [pbn_pasemi_1682M] = {
3556 .base_baud = 8333333,
3559 * National Instruments 843x
3564 .base_baud = 3686400,
3565 .uart_offset = 0x10,
3566 .first_offset = 0x800,
3571 .base_baud = 3686400,
3572 .uart_offset = 0x10,
3573 .first_offset = 0x800,
3578 .base_baud = 3686400,
3579 .uart_offset = 0x10,
3580 .first_offset = 0x800,
3585 .base_baud = 3686400,
3586 .uart_offset = 0x10,
3587 .first_offset = 0x800,
3590 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3592 [pbn_ADDIDATA_PCIe_1_3906250] = {
3595 .base_baud = 3906250,
3596 .uart_offset = 0x200,
3597 .first_offset = 0x1000,
3599 [pbn_ADDIDATA_PCIe_2_3906250] = {
3602 .base_baud = 3906250,
3603 .uart_offset = 0x200,
3604 .first_offset = 0x1000,
3606 [pbn_ADDIDATA_PCIe_4_3906250] = {
3609 .base_baud = 3906250,
3610 .uart_offset = 0x200,
3611 .first_offset = 0x1000,
3613 [pbn_ADDIDATA_PCIe_8_3906250] = {
3616 .base_baud = 3906250,
3617 .uart_offset = 0x200,
3618 .first_offset = 0x1000,
3620 [pbn_ce4100_1_115200] = {
3621 .flags = FL_BASE_BARS,
3623 .base_baud = 921600,
3627 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3628 * but is overridden by byt_set_termios.
3633 .base_baud = 2764800,
3634 .uart_offset = 0x80,
3640 .base_baud = 2764800,
3646 .base_baud = 115200,
3647 .uart_offset = 0x200,
3649 [pbn_NETMOS9900_2s_115200] = {
3652 .base_baud = 115200,
3654 [pbn_brcm_trumanage] = {
3658 .base_baud = 115200,
3663 .base_baud = 115200,
3664 .first_offset = 0x40,
3669 .base_baud = 115200,
3670 .first_offset = 0x40,
3675 .base_baud = 115200,
3676 .first_offset = 0x40,
3680 static const struct pci_device_id blacklist[] = {
3682 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3683 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3684 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3686 /* multi-io cards handled by parport_serial */
3687 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3688 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3689 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3693 * Given a complete unknown PCI device, try to use some heuristics to
3694 * guess what the configuration might be, based on the pitiful PCI
3695 * serial specs. Returns 0 on success, 1 on failure.
3698 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3700 const struct pci_device_id *bldev;
3701 int num_iomem, num_port, first_port = -1, i;
3704 * If it is not a communications device or the programming
3705 * interface is greater than 6, give up.
3707 * (Should we try to make guesses for multiport serial devices
3710 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3711 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3712 (dev->class & 0xff) > 6)
3716 * Do not access blacklisted devices that are known not to
3717 * feature serial ports or are handled by other modules.
3719 for (bldev = blacklist;
3720 bldev < blacklist + ARRAY_SIZE(blacklist);
3722 if (dev->vendor == bldev->vendor &&
3723 dev->device == bldev->device)
3727 num_iomem = num_port = 0;
3728 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3729 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3731 if (first_port == -1)
3734 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3739 * If there is 1 or 0 iomem regions, and exactly one port,
3740 * use it. We guess the number of ports based on the IO
3743 if (num_iomem <= 1 && num_port == 1) {
3744 board->flags = first_port;
3745 board->num_ports = pci_resource_len(dev, first_port) / 8;
3750 * Now guess if we've got a board which indexes by BARs.
3751 * Each IO BAR should be 8 bytes, and they should follow
3756 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3757 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3758 pci_resource_len(dev, i) == 8 &&
3759 (first_port == -1 || (first_port + num_port) == i)) {
3761 if (first_port == -1)
3767 board->flags = first_port | FL_BASE_BARS;
3768 board->num_ports = num_port;
3776 serial_pci_matches(const struct pciserial_board *board,
3777 const struct pciserial_board *guessed)
3780 board->num_ports == guessed->num_ports &&
3781 board->base_baud == guessed->base_baud &&
3782 board->uart_offset == guessed->uart_offset &&
3783 board->reg_shift == guessed->reg_shift &&
3784 board->first_offset == guessed->first_offset;
3787 struct serial_private *
3788 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3790 struct uart_8250_port uart;
3791 struct serial_private *priv;
3792 struct pci_serial_quirk *quirk;
3793 int rc, nr_ports, i;
3795 nr_ports = board->num_ports;
3798 * Find an init and setup quirks.
3800 quirk = find_quirk(dev);
3803 * Run the new-style initialization function.
3804 * The initialization function returns:
3806 * 0 - use board->num_ports
3807 * >0 - number of ports
3810 rc = quirk->init(dev);
3819 priv = kzalloc(sizeof(struct serial_private) +
3820 sizeof(unsigned int) * nr_ports,
3823 priv = ERR_PTR(-ENOMEM);
3828 priv->quirk = quirk;
3830 memset(&uart, 0, sizeof(uart));
3831 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3832 uart.port.uartclk = board->base_baud * 16;
3833 uart.port.irq = get_pci_irq(dev, board);
3834 uart.port.dev = &dev->dev;
3836 for (i = 0; i < nr_ports; i++) {
3837 if (quirk->setup(priv, board, &uart, i))
3840 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3841 uart.port.iobase, uart.port.irq, uart.port.iotype);
3843 priv->line[i] = serial8250_register_8250_port(&uart);
3844 if (priv->line[i] < 0) {
3846 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3847 uart.port.iobase, uart.port.irq,
3848 uart.port.iotype, priv->line[i]);
3861 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3863 void pciserial_remove_ports(struct serial_private *priv)
3865 struct pci_serial_quirk *quirk;
3868 for (i = 0; i < priv->nr; i++)
3869 serial8250_unregister_port(priv->line[i]);
3871 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3872 if (priv->remapped_bar[i])
3873 iounmap(priv->remapped_bar[i]);
3874 priv->remapped_bar[i] = NULL;
3878 * Find the exit quirks.
3880 quirk = find_quirk(priv->dev);
3882 quirk->exit(priv->dev);
3886 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3888 void pciserial_suspend_ports(struct serial_private *priv)
3892 for (i = 0; i < priv->nr; i++)
3893 if (priv->line[i] >= 0)
3894 serial8250_suspend_port(priv->line[i]);
3897 * Ensure that every init quirk is properly torn down
3899 if (priv->quirk->exit)
3900 priv->quirk->exit(priv->dev);
3902 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3904 void pciserial_resume_ports(struct serial_private *priv)
3909 * Ensure that the board is correctly configured.
3911 if (priv->quirk->init)
3912 priv->quirk->init(priv->dev);
3914 for (i = 0; i < priv->nr; i++)
3915 if (priv->line[i] >= 0)
3916 serial8250_resume_port(priv->line[i]);
3918 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3921 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3922 * to the arrangement of serial ports on a PCI card.
3925 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3927 struct pci_serial_quirk *quirk;
3928 struct serial_private *priv;
3929 const struct pciserial_board *board;
3930 struct pciserial_board tmp;
3933 quirk = find_quirk(dev);
3935 rc = quirk->probe(dev);
3940 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3941 dev_err(&dev->dev, "invalid driver_data: %ld\n",
3946 board = &pci_boards[ent->driver_data];
3948 rc = pci_enable_device(dev);
3949 pci_save_state(dev);
3953 if (ent->driver_data == pbn_default) {
3955 * Use a copy of the pci_board entry for this;
3956 * avoid changing entries in the table.
3958 memcpy(&tmp, board, sizeof(struct pciserial_board));
3962 * We matched one of our class entries. Try to
3963 * determine the parameters of this board.
3965 rc = serial_pci_guess_board(dev, &tmp);
3970 * We matched an explicit entry. If we are able to
3971 * detect this boards settings with our heuristic,
3972 * then we no longer need this entry.
3974 memcpy(&tmp, &pci_boards[pbn_default],
3975 sizeof(struct pciserial_board));
3976 rc = serial_pci_guess_board(dev, &tmp);
3977 if (rc == 0 && serial_pci_matches(board, &tmp))
3978 moan_device("Redundant entry in serial pci_table.",
3982 priv = pciserial_init_ports(dev, board);
3983 if (!IS_ERR(priv)) {
3984 pci_set_drvdata(dev, priv);
3991 pci_disable_device(dev);
3995 static void pciserial_remove_one(struct pci_dev *dev)
3997 struct serial_private *priv = pci_get_drvdata(dev);
3999 pciserial_remove_ports(priv);
4001 pci_disable_device(dev);
4005 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
4007 struct serial_private *priv = pci_get_drvdata(dev);
4010 pciserial_suspend_ports(priv);
4012 pci_save_state(dev);
4013 pci_set_power_state(dev, pci_choose_state(dev, state));
4017 static int pciserial_resume_one(struct pci_dev *dev)
4020 struct serial_private *priv = pci_get_drvdata(dev);
4022 pci_set_power_state(dev, PCI_D0);
4023 pci_restore_state(dev);
4027 * The device may have been disabled. Re-enable it.
4029 err = pci_enable_device(dev);
4030 /* FIXME: We cannot simply error out here */
4032 dev_err(&dev->dev, "Unable to re-enable ports, trying to continue.\n");
4033 pciserial_resume_ports(priv);
4039 static struct pci_device_id serial_pci_tbl[] = {
4040 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4041 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4042 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4044 /* Advantech also use 0x3618 and 0xf618 */
4045 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4046 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4048 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4049 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4051 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4052 PCI_SUBVENDOR_ID_CONNECT_TECH,
4053 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4055 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4056 PCI_SUBVENDOR_ID_CONNECT_TECH,
4057 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4059 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4060 PCI_SUBVENDOR_ID_CONNECT_TECH,
4061 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4063 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4064 PCI_SUBVENDOR_ID_CONNECT_TECH,
4065 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4067 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4068 PCI_SUBVENDOR_ID_CONNECT_TECH,
4069 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4071 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4072 PCI_SUBVENDOR_ID_CONNECT_TECH,
4073 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4075 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4076 PCI_SUBVENDOR_ID_CONNECT_TECH,
4077 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4079 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4080 PCI_SUBVENDOR_ID_CONNECT_TECH,
4081 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4083 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4084 PCI_SUBVENDOR_ID_CONNECT_TECH,
4085 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4087 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4088 PCI_SUBVENDOR_ID_CONNECT_TECH,
4089 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4091 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4092 PCI_SUBVENDOR_ID_CONNECT_TECH,
4093 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4095 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4096 PCI_SUBVENDOR_ID_CONNECT_TECH,
4097 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4099 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4100 PCI_SUBVENDOR_ID_CONNECT_TECH,
4101 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4103 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4104 PCI_SUBVENDOR_ID_CONNECT_TECH,
4105 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4107 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4108 PCI_SUBVENDOR_ID_CONNECT_TECH,
4109 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4111 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4112 PCI_SUBVENDOR_ID_CONNECT_TECH,
4113 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4115 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4116 PCI_SUBVENDOR_ID_CONNECT_TECH,
4117 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4119 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4120 PCI_VENDOR_ID_AFAVLAB,
4121 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4123 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4124 PCI_SUBVENDOR_ID_CONNECT_TECH,
4125 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4126 pbn_b0_2_1843200_200 },
4127 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4128 PCI_SUBVENDOR_ID_CONNECT_TECH,
4129 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4130 pbn_b0_4_1843200_200 },
4131 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4132 PCI_SUBVENDOR_ID_CONNECT_TECH,
4133 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4134 pbn_b0_8_1843200_200 },
4135 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4136 PCI_SUBVENDOR_ID_CONNECT_TECH,
4137 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4138 pbn_b0_2_1843200_200 },
4139 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4140 PCI_SUBVENDOR_ID_CONNECT_TECH,
4141 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4142 pbn_b0_4_1843200_200 },
4143 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4144 PCI_SUBVENDOR_ID_CONNECT_TECH,
4145 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4146 pbn_b0_8_1843200_200 },
4147 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4148 PCI_SUBVENDOR_ID_CONNECT_TECH,
4149 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4150 pbn_b0_2_1843200_200 },
4151 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4152 PCI_SUBVENDOR_ID_CONNECT_TECH,
4153 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4154 pbn_b0_4_1843200_200 },
4155 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4156 PCI_SUBVENDOR_ID_CONNECT_TECH,
4157 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4158 pbn_b0_8_1843200_200 },
4159 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4160 PCI_SUBVENDOR_ID_CONNECT_TECH,
4161 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4162 pbn_b0_2_1843200_200 },
4163 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4164 PCI_SUBVENDOR_ID_CONNECT_TECH,
4165 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4166 pbn_b0_4_1843200_200 },
4167 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4168 PCI_SUBVENDOR_ID_CONNECT_TECH,
4169 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4170 pbn_b0_8_1843200_200 },
4171 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4172 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4173 0, 0, pbn_exar_ibm_saturn },
4175 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4176 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4177 pbn_b2_bt_1_115200 },
4178 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4179 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4180 pbn_b2_bt_2_115200 },
4181 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4182 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4183 pbn_b2_bt_4_115200 },
4184 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4185 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4186 pbn_b2_bt_2_115200 },
4187 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4188 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4189 pbn_b2_bt_4_115200 },
4190 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4191 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4193 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4194 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4196 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4197 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4200 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4201 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4202 pbn_b2_bt_2_115200 },
4203 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4204 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4205 pbn_b2_bt_2_921600 },
4207 * VScom SPCOM800, from sl@s.pl
4209 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4212 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4213 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4215 /* Unknown card - subdevice 0x1584 */
4216 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4218 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4220 /* Unknown card - subdevice 0x1588 */
4221 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4223 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4225 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4226 PCI_SUBVENDOR_ID_KEYSPAN,
4227 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4229 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4230 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4232 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4233 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4235 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4236 PCI_VENDOR_ID_ESDGMBH,
4237 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4239 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4240 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4241 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4243 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4244 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4245 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4247 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4248 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4249 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4251 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4252 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4253 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4255 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4256 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4257 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4259 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4260 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4261 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4263 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4264 PCI_SUBVENDOR_ID_EXSYS,
4265 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4268 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4271 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4272 0x10b5, 0x106a, 0, 0,
4275 * EndRun Technologies. PCI express device range.
4276 * EndRun PTP/1588 has 2 Native UARTs.
4278 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4279 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4280 pbn_endrun_2_4000000 },
4282 * Quatech cards. These actually have configurable clocks but for
4283 * now we just use the default.
4285 * 100 series are RS232, 200 series RS422,
4287 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4288 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4290 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4291 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4293 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4294 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4296 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4297 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4299 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4300 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4302 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4303 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4305 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4306 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4308 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4309 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4311 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4312 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4314 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4315 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4317 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4318 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4320 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4321 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4323 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4324 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4326 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4327 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4329 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4330 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4332 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4333 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4335 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4336 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4338 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4339 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4341 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4342 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4345 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4346 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4349 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4350 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4353 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4354 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4355 pbn_b0_bt_2_921600 },
4358 * The below card is a little controversial since it is the
4359 * subject of a PCI vendor/device ID clash. (See
4360 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4361 * For now just used the hex ID 0x950a.
4363 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4364 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4365 0, 0, pbn_b0_2_115200 },
4366 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4367 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4368 0, 0, pbn_b0_2_115200 },
4369 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4370 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4372 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4373 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4375 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4376 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4378 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4379 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4380 pbn_b0_bt_2_921600 },
4381 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4382 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4386 * Oxford Semiconductor Inc. Tornado PCI express device range.
4388 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4389 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4391 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4392 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4394 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4395 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4396 pbn_oxsemi_1_4000000 },
4397 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4398 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4399 pbn_oxsemi_1_4000000 },
4400 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4401 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4403 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4404 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4406 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4407 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4408 pbn_oxsemi_1_4000000 },
4409 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4410 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4411 pbn_oxsemi_1_4000000 },
4412 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4413 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4415 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4416 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4418 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4419 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4421 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4422 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4424 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4425 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4426 pbn_oxsemi_2_4000000 },
4427 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4428 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4429 pbn_oxsemi_2_4000000 },
4430 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4431 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4432 pbn_oxsemi_4_4000000 },
4433 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4434 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4435 pbn_oxsemi_4_4000000 },
4436 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4437 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4438 pbn_oxsemi_8_4000000 },
4439 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4440 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4441 pbn_oxsemi_8_4000000 },
4442 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4444 pbn_oxsemi_1_4000000 },
4445 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4447 pbn_oxsemi_1_4000000 },
4448 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4449 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4450 pbn_oxsemi_1_4000000 },
4451 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4452 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4453 pbn_oxsemi_1_4000000 },
4454 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4455 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4456 pbn_oxsemi_1_4000000 },
4457 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4458 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4459 pbn_oxsemi_1_4000000 },
4460 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4461 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4462 pbn_oxsemi_1_4000000 },
4463 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4464 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4465 pbn_oxsemi_1_4000000 },
4466 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4467 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4468 pbn_oxsemi_1_4000000 },
4469 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4471 pbn_oxsemi_1_4000000 },
4472 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4474 pbn_oxsemi_1_4000000 },
4475 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4476 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4477 pbn_oxsemi_1_4000000 },
4478 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4479 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4480 pbn_oxsemi_1_4000000 },
4481 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4482 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4483 pbn_oxsemi_1_4000000 },
4484 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4485 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4486 pbn_oxsemi_1_4000000 },
4487 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4488 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4489 pbn_oxsemi_1_4000000 },
4490 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4491 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4492 pbn_oxsemi_1_4000000 },
4493 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4494 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4495 pbn_oxsemi_1_4000000 },
4496 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4497 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4498 pbn_oxsemi_1_4000000 },
4499 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4500 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4501 pbn_oxsemi_1_4000000 },
4502 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4503 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4504 pbn_oxsemi_1_4000000 },
4505 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4506 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4507 pbn_oxsemi_1_4000000 },
4508 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4510 pbn_oxsemi_1_4000000 },
4511 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4512 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4513 pbn_oxsemi_1_4000000 },
4514 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4515 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4516 pbn_oxsemi_1_4000000 },
4517 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4518 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4519 pbn_oxsemi_1_4000000 },
4521 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4523 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4524 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4525 pbn_oxsemi_1_4000000 },
4526 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4527 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4528 pbn_oxsemi_2_4000000 },
4529 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4530 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4531 pbn_oxsemi_4_4000000 },
4532 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4533 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4534 pbn_oxsemi_8_4000000 },
4537 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4539 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4540 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4541 pbn_oxsemi_2_4000000 },
4544 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4545 * from skokodyn@yahoo.com
4547 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4548 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4550 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4551 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4553 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4554 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4556 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4557 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4561 * Digitan DS560-558, from jimd@esoft.com
4563 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4564 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4568 * Titan Electronic cards
4569 * The 400L and 800L have a custom setup quirk.
4571 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4572 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4574 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4575 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4577 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4578 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4580 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4581 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4583 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4584 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4587 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4588 pbn_b1_bt_2_921600 },
4589 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4590 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4591 pbn_b0_bt_4_921600 },
4592 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4593 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4594 pbn_b0_bt_8_921600 },
4595 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4596 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4597 pbn_b4_bt_2_921600 },
4598 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4599 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4600 pbn_b4_bt_4_921600 },
4601 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4602 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4603 pbn_b4_bt_8_921600 },
4604 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4605 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4608 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4611 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4614 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4615 pbn_oxsemi_1_4000000 },
4616 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4617 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4618 pbn_oxsemi_2_4000000 },
4619 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4620 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4621 pbn_oxsemi_4_4000000 },
4622 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4623 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4624 pbn_oxsemi_8_4000000 },
4625 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4626 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4627 pbn_oxsemi_2_4000000 },
4628 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4629 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4630 pbn_oxsemi_2_4000000 },
4631 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4632 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4633 pbn_b0_bt_2_921600 },
4634 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4635 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4637 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4640 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4643 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4644 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4647 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4650 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4651 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4653 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4654 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4656 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4657 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4658 pbn_b2_bt_2_921600 },
4659 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4660 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4661 pbn_b2_bt_2_921600 },
4662 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4663 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4664 pbn_b2_bt_2_921600 },
4665 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4666 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4667 pbn_b2_bt_4_921600 },
4668 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4669 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4670 pbn_b2_bt_4_921600 },
4671 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4672 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4673 pbn_b2_bt_4_921600 },
4674 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4675 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4677 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4678 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4680 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4681 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4683 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4684 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4685 pbn_b0_bt_2_921600 },
4686 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4687 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4688 pbn_b0_bt_2_921600 },
4689 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4690 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4691 pbn_b0_bt_2_921600 },
4692 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4693 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4694 pbn_b0_bt_4_921600 },
4695 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4696 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4697 pbn_b0_bt_4_921600 },
4698 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4699 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4700 pbn_b0_bt_4_921600 },
4701 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4702 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4703 pbn_b0_bt_8_921600 },
4704 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4705 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4706 pbn_b0_bt_8_921600 },
4707 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4708 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4709 pbn_b0_bt_8_921600 },
4712 * Computone devices submitted by Doug McNash dmcnash@computone.com
4714 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4715 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4716 0, 0, pbn_computone_4 },
4717 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4718 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4719 0, 0, pbn_computone_8 },
4720 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4721 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4722 0, 0, pbn_computone_6 },
4724 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4725 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4727 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4728 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4729 pbn_b0_bt_1_921600 },
4734 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4735 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4736 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4737 pbn_b0_bt_1_921600 },
4739 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4740 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4741 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4742 pbn_b0_bt_1_921600 },
4745 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4747 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4748 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4749 pbn_b0_bt_8_115200 },
4750 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4751 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4752 pbn_b0_bt_8_115200 },
4754 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4755 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4756 pbn_b0_bt_2_115200 },
4757 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4758 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4759 pbn_b0_bt_2_115200 },
4760 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4761 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4762 pbn_b0_bt_2_115200 },
4763 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4764 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4765 pbn_b0_bt_2_115200 },
4766 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4767 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4768 pbn_b0_bt_2_115200 },
4769 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4770 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4771 pbn_b0_bt_4_460800 },
4772 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4773 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4774 pbn_b0_bt_4_460800 },
4775 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4776 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4777 pbn_b0_bt_2_460800 },
4778 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4779 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4780 pbn_b0_bt_2_460800 },
4781 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4782 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4783 pbn_b0_bt_2_460800 },
4784 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4785 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4786 pbn_b0_bt_1_115200 },
4787 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4788 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4789 pbn_b0_bt_1_460800 },
4792 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4793 * Cards are identified by their subsystem vendor IDs, which
4794 * (in hex) match the model number.
4796 * Note that JC140x are RS422/485 cards which require ox950
4797 * ACR = 0x10, and as such are not currently fully supported.
4799 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4800 0x1204, 0x0004, 0, 0,
4802 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4803 0x1208, 0x0004, 0, 0,
4805 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4806 0x1402, 0x0002, 0, 0,
4807 pbn_b0_2_921600 }, */
4808 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4809 0x1404, 0x0004, 0, 0,
4810 pbn_b0_4_921600 }, */
4811 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4812 0x1208, 0x0004, 0, 0,
4815 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4816 0x1204, 0x0004, 0, 0,
4818 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4819 0x1208, 0x0004, 0, 0,
4821 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4822 0x1208, 0x0004, 0, 0,
4825 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4827 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4828 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4832 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4834 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4835 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4839 * RAStel 2 port modem, gerg@moreton.com.au
4841 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4842 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4843 pbn_b2_bt_2_115200 },
4846 * EKF addition for i960 Boards form EKF with serial port
4848 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4849 0xE4BF, PCI_ANY_ID, 0, 0,
4853 * Xircom Cardbus/Ethernet combos
4855 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4856 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4859 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4861 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4862 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4866 * Untested PCI modems, sent in from various folks...
4870 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4872 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4873 0x1048, 0x1500, 0, 0,
4876 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4883 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4884 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4886 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4887 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4889 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4893 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4894 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4896 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4899 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4900 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4904 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4906 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4907 PCI_ANY_ID, PCI_ANY_ID,
4909 0, pbn_exar_XR17C152 },
4910 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4911 PCI_ANY_ID, PCI_ANY_ID,
4913 0, pbn_exar_XR17C154 },
4914 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4915 PCI_ANY_ID, PCI_ANY_ID,
4917 0, pbn_exar_XR17C158 },
4919 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4921 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4922 PCI_ANY_ID, PCI_ANY_ID,
4924 0, pbn_exar_XR17V352 },
4925 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4926 PCI_ANY_ID, PCI_ANY_ID,
4928 0, pbn_exar_XR17V354 },
4929 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4930 PCI_ANY_ID, PCI_ANY_ID,
4932 0, pbn_exar_XR17V358 },
4935 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4937 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4938 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4943 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4944 PCI_ANY_ID, PCI_ANY_ID,
4946 pbn_b1_bt_1_115200 },
4951 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4952 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4957 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4958 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4961 * Perle PCI-RAS cards
4963 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4964 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4965 0, 0, pbn_b2_4_921600 },
4966 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4967 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4968 0, 0, pbn_b2_8_921600 },
4971 * Mainpine series cards: Fairly standard layout but fools
4972 * parts of the autodetect in some cases and uses otherwise
4973 * unmatched communications subclasses in the PCI Express case
4976 { /* RockForceDUO */
4977 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4978 PCI_VENDOR_ID_MAINPINE, 0x0200,
4979 0, 0, pbn_b0_2_115200 },
4980 { /* RockForceQUATRO */
4981 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4982 PCI_VENDOR_ID_MAINPINE, 0x0300,
4983 0, 0, pbn_b0_4_115200 },
4984 { /* RockForceDUO+ */
4985 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4986 PCI_VENDOR_ID_MAINPINE, 0x0400,
4987 0, 0, pbn_b0_2_115200 },
4988 { /* RockForceQUATRO+ */
4989 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4990 PCI_VENDOR_ID_MAINPINE, 0x0500,
4991 0, 0, pbn_b0_4_115200 },
4993 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4994 PCI_VENDOR_ID_MAINPINE, 0x0600,
4995 0, 0, pbn_b0_2_115200 },
4997 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4998 PCI_VENDOR_ID_MAINPINE, 0x0700,
4999 0, 0, pbn_b0_4_115200 },
5000 { /* RockForceOCTO+ */
5001 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5002 PCI_VENDOR_ID_MAINPINE, 0x0800,
5003 0, 0, pbn_b0_8_115200 },
5004 { /* RockForceDUO+ */
5005 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5006 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5007 0, 0, pbn_b0_2_115200 },
5008 { /* RockForceQUARTRO+ */
5009 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5010 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5011 0, 0, pbn_b0_4_115200 },
5012 { /* RockForceOCTO+ */
5013 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5014 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5015 0, 0, pbn_b0_8_115200 },
5017 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5018 PCI_VENDOR_ID_MAINPINE, 0x2000,
5019 0, 0, pbn_b0_1_115200 },
5021 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5022 PCI_VENDOR_ID_MAINPINE, 0x2100,
5023 0, 0, pbn_b0_1_115200 },
5025 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5026 PCI_VENDOR_ID_MAINPINE, 0x2200,
5027 0, 0, pbn_b0_2_115200 },
5029 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5030 PCI_VENDOR_ID_MAINPINE, 0x2300,
5031 0, 0, pbn_b0_2_115200 },
5033 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5034 PCI_VENDOR_ID_MAINPINE, 0x2400,
5035 0, 0, pbn_b0_4_115200 },
5037 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5038 PCI_VENDOR_ID_MAINPINE, 0x2500,
5039 0, 0, pbn_b0_4_115200 },
5041 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5042 PCI_VENDOR_ID_MAINPINE, 0x2600,
5043 0, 0, pbn_b0_8_115200 },
5045 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5046 PCI_VENDOR_ID_MAINPINE, 0x2700,
5047 0, 0, pbn_b0_8_115200 },
5048 { /* IQ Express D1 */
5049 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5050 PCI_VENDOR_ID_MAINPINE, 0x3000,
5051 0, 0, pbn_b0_1_115200 },
5052 { /* IQ Express F1 */
5053 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5054 PCI_VENDOR_ID_MAINPINE, 0x3100,
5055 0, 0, pbn_b0_1_115200 },
5056 { /* IQ Express D2 */
5057 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5058 PCI_VENDOR_ID_MAINPINE, 0x3200,
5059 0, 0, pbn_b0_2_115200 },
5060 { /* IQ Express F2 */
5061 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5062 PCI_VENDOR_ID_MAINPINE, 0x3300,
5063 0, 0, pbn_b0_2_115200 },
5064 { /* IQ Express D4 */
5065 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5066 PCI_VENDOR_ID_MAINPINE, 0x3400,
5067 0, 0, pbn_b0_4_115200 },
5068 { /* IQ Express F4 */
5069 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5070 PCI_VENDOR_ID_MAINPINE, 0x3500,
5071 0, 0, pbn_b0_4_115200 },
5072 { /* IQ Express D8 */
5073 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5074 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5075 0, 0, pbn_b0_8_115200 },
5076 { /* IQ Express F8 */
5077 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5078 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5079 0, 0, pbn_b0_8_115200 },
5083 * PA Semi PA6T-1682M on-chip UART
5085 { PCI_VENDOR_ID_PASEMI, 0xa004,
5086 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5090 * National Instruments
5092 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5095 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5096 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5098 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5100 pbn_b1_bt_4_115200 },
5101 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5102 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5103 pbn_b1_bt_2_115200 },
5104 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5106 pbn_b1_bt_4_115200 },
5107 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5108 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5109 pbn_b1_bt_2_115200 },
5110 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5113 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5114 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5116 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5117 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5118 pbn_b1_bt_4_115200 },
5119 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5120 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5121 pbn_b1_bt_2_115200 },
5122 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5123 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5124 pbn_b1_bt_4_115200 },
5125 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5126 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5127 pbn_b1_bt_2_115200 },
5128 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5129 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5131 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5134 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5137 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5140 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5143 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5146 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5149 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5150 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5152 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5155 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5156 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5158 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5159 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5161 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5166 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5168 { PCI_VENDOR_ID_ADDIDATA,
5169 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5176 { PCI_VENDOR_ID_ADDIDATA,
5177 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5184 { PCI_VENDOR_ID_ADDIDATA,
5185 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5192 { PCI_VENDOR_ID_AMCC,
5193 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5200 { PCI_VENDOR_ID_ADDIDATA,
5201 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5208 { PCI_VENDOR_ID_ADDIDATA,
5209 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5216 { PCI_VENDOR_ID_ADDIDATA,
5217 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5224 { PCI_VENDOR_ID_ADDIDATA,
5225 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5232 { PCI_VENDOR_ID_ADDIDATA,
5233 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5240 { PCI_VENDOR_ID_ADDIDATA,
5241 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5248 { PCI_VENDOR_ID_ADDIDATA,
5249 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5256 { PCI_VENDOR_ID_ADDIDATA,
5257 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5262 pbn_ADDIDATA_PCIe_4_3906250 },
5264 { PCI_VENDOR_ID_ADDIDATA,
5265 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5270 pbn_ADDIDATA_PCIe_2_3906250 },
5272 { PCI_VENDOR_ID_ADDIDATA,
5273 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5278 pbn_ADDIDATA_PCIe_1_3906250 },
5280 { PCI_VENDOR_ID_ADDIDATA,
5281 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5286 pbn_ADDIDATA_PCIe_8_3906250 },
5288 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5289 PCI_VENDOR_ID_IBM, 0x0299,
5290 0, 0, pbn_b0_bt_2_115200 },
5293 * other NetMos 9835 devices are most likely handled by the
5294 * parport_serial driver, check drivers/parport/parport_serial.c
5295 * before adding them here.
5298 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5300 0, 0, pbn_b0_1_115200 },
5302 /* the 9901 is a rebranded 9912 */
5303 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5305 0, 0, pbn_b0_1_115200 },
5307 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5309 0, 0, pbn_b0_1_115200 },
5311 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5313 0, 0, pbn_b0_1_115200 },
5315 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5317 0, 0, pbn_b0_1_115200 },
5319 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5321 0, 0, pbn_NETMOS9900_2s_115200 },
5324 * Best Connectivity and Rosewill PCI Multi I/O cards
5327 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5329 0, 0, pbn_b0_1_115200 },
5331 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5333 0, 0, pbn_b0_bt_2_115200 },
5335 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5337 0, 0, pbn_b0_bt_4_115200 },
5339 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5340 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5341 pbn_ce4100_1_115200 },
5342 /* Intel BayTrail */
5343 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5344 PCI_ANY_ID, PCI_ANY_ID,
5345 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5347 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5348 PCI_ANY_ID, PCI_ANY_ID,
5349 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5351 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5352 PCI_ANY_ID, PCI_ANY_ID,
5353 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5355 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5356 PCI_ANY_ID, PCI_ANY_ID,
5357 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5363 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5364 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5369 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5370 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5374 * Broadcom TruManage
5376 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5377 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5378 pbn_brcm_trumanage },
5381 * AgeStar as-prs2-009
5383 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5384 PCI_ANY_ID, PCI_ANY_ID,
5385 0, 0, pbn_b0_bt_2_115200 },
5388 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5389 * so not listed here.
5391 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5392 PCI_ANY_ID, PCI_ANY_ID,
5393 0, 0, pbn_b0_bt_4_115200 },
5395 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5396 PCI_ANY_ID, PCI_ANY_ID,
5397 0, 0, pbn_b0_bt_2_115200 },
5399 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S,
5400 PCI_ANY_ID, PCI_ANY_ID,
5401 0, 0, pbn_b0_bt_2_115200 },
5404 * Commtech, Inc. Fastcom adapters
5406 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5407 PCI_ANY_ID, PCI_ANY_ID,
5409 0, pbn_b0_2_1152000_200 },
5410 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5411 PCI_ANY_ID, PCI_ANY_ID,
5413 0, pbn_b0_4_1152000_200 },
5414 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5415 PCI_ANY_ID, PCI_ANY_ID,
5417 0, pbn_b0_4_1152000_200 },
5418 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5419 PCI_ANY_ID, PCI_ANY_ID,
5421 0, pbn_b0_8_1152000_200 },
5422 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5423 PCI_ANY_ID, PCI_ANY_ID,
5425 0, pbn_exar_XR17V352 },
5426 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5427 PCI_ANY_ID, PCI_ANY_ID,
5429 0, pbn_exar_XR17V354 },
5430 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5431 PCI_ANY_ID, PCI_ANY_ID,
5433 0, pbn_exar_XR17V358 },
5435 /* Fintek PCI serial cards */
5436 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5437 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5438 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5441 * These entries match devices with class COMMUNICATION_SERIAL,
5442 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5444 { PCI_ANY_ID, PCI_ANY_ID,
5445 PCI_ANY_ID, PCI_ANY_ID,
5446 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5447 0xffff00, pbn_default },
5448 { PCI_ANY_ID, PCI_ANY_ID,
5449 PCI_ANY_ID, PCI_ANY_ID,
5450 PCI_CLASS_COMMUNICATION_MODEM << 8,
5451 0xffff00, pbn_default },
5452 { PCI_ANY_ID, PCI_ANY_ID,
5453 PCI_ANY_ID, PCI_ANY_ID,
5454 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5455 0xffff00, pbn_default },
5459 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5460 pci_channel_state_t state)
5462 struct serial_private *priv = pci_get_drvdata(dev);
5464 if (state == pci_channel_io_perm_failure)
5465 return PCI_ERS_RESULT_DISCONNECT;
5468 pciserial_suspend_ports(priv);
5470 pci_disable_device(dev);
5472 return PCI_ERS_RESULT_NEED_RESET;
5475 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5479 rc = pci_enable_device(dev);
5482 return PCI_ERS_RESULT_DISCONNECT;
5484 pci_restore_state(dev);
5485 pci_save_state(dev);
5487 return PCI_ERS_RESULT_RECOVERED;
5490 static void serial8250_io_resume(struct pci_dev *dev)
5492 struct serial_private *priv = pci_get_drvdata(dev);
5495 pciserial_resume_ports(priv);
5498 static const struct pci_error_handlers serial8250_err_handler = {
5499 .error_detected = serial8250_io_error_detected,
5500 .slot_reset = serial8250_io_slot_reset,
5501 .resume = serial8250_io_resume,
5504 static struct pci_driver serial_pci_driver = {
5506 .probe = pciserial_init_one,
5507 .remove = pciserial_remove_one,
5509 .suspend = pciserial_suspend_one,
5510 .resume = pciserial_resume_one,
5512 .id_table = serial_pci_tbl,
5513 .err_handler = &serial8250_err_handler,
5516 module_pci_driver(serial_pci_driver);
5518 MODULE_LICENSE("GPL");
5519 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5520 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);