1 // SPDX-License-Identifier: GPL-2.0
3 * 8250-core based driver for the OMAP internal UART
5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
7 * Copyright (C) 2014 Sebastian Andrzej Siewior
11 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
15 #include <linux/clk.h>
16 #include <linux/device.h>
18 #include <linux/module.h>
19 #include <linux/serial_8250.h>
20 #include <linux/serial_reg.h>
21 #include <linux/tty_flip.h>
22 #include <linux/platform_device.h>
23 #include <linux/slab.h>
25 #include <linux/of_device.h>
26 #include <linux/of_gpio.h>
27 #include <linux/of_irq.h>
28 #include <linux/delay.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/console.h>
31 #include <linux/pm_qos.h>
32 #include <linux/pm_wakeirq.h>
33 #include <linux/dma-mapping.h>
37 #define DEFAULT_CLK_SPEED 48000000
39 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0)
40 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
41 #define OMAP_DMA_TX_KICK (1 << 2)
43 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
44 * The same errata is applicable to AM335x and DRA7x processors too.
46 #define UART_ERRATA_CLOCK_DISABLE (1 << 3)
48 #define OMAP_UART_FCR_RX_TRIG 6
49 #define OMAP_UART_FCR_TX_TRIG 4
51 /* SCR register bitmasks */
52 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
53 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
54 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
55 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
56 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1)
57 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0)
59 /* MVR register bitmasks */
60 #define OMAP_UART_MVR_SCHEME_SHIFT 30
61 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
62 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
63 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
64 #define OMAP_UART_MVR_MAJ_MASK 0x700
65 #define OMAP_UART_MVR_MAJ_SHIFT 8
66 #define OMAP_UART_MVR_MIN_MASK 0x3f
68 /* SYSC register bitmasks */
69 #define OMAP_UART_SYSC_SOFTRESET (1 << 1)
71 /* SYSS register bitmasks */
72 #define OMAP_UART_SYSS_RESETDONE (1 << 0)
74 #define UART_TI752_TLR_TX 0
75 #define UART_TI752_TLR_RX 4
77 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2)
78 #define TRIGGER_FCR_MASK(x) (x & 3)
80 /* Enable XON/XOFF flow control on output */
81 #define OMAP_UART_SW_TX 0x08
82 /* Enable XON/XOFF flow control on input */
83 #define OMAP_UART_SW_RX 0x02
85 #define OMAP_UART_WER_MOD_WKUP 0x7f
86 #define OMAP_UART_TX_WAKEUP_EN (1 << 7)
91 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4)
92 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0)
94 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
96 #define OMAP_UART_REV_46 0x0406
97 #define OMAP_UART_REV_52 0x0502
98 #define OMAP_UART_REV_63 0x0603
100 struct omap8250_priv {
117 struct pm_qos_request pm_qos_request;
118 struct work_struct qos_work;
119 struct uart_8250_dma omap8250_dma;
120 spinlock_t rx_dma_lock;
125 #ifdef CONFIG_SERIAL_8250_DMA
126 static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
128 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
131 static u32 uart_read(struct uart_8250_port *up, u32 reg)
133 return readl(up->port.membase + (reg << up->port.regshift));
136 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
138 struct uart_8250_port *up = up_to_u8250p(port);
139 struct omap8250_priv *priv = up->port.private_data;
142 serial8250_do_set_mctrl(port, mctrl);
144 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) {
146 * Turn off autoRTS if RTS is lowered and restore autoRTS
147 * setting if RTS is raised
149 lcr = serial_in(up, UART_LCR);
150 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
151 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
152 priv->efr |= UART_EFR_RTS;
154 priv->efr &= ~UART_EFR_RTS;
155 serial_out(up, UART_EFR, priv->efr);
156 serial_out(up, UART_LCR, lcr);
161 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
162 * The access to uart register after MDR1 Access
163 * causes UART to corrupt data.
166 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
167 * give 10 times as much
169 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
170 struct omap8250_priv *priv)
175 old_mdr1 = serial_in(up, UART_OMAP_MDR1);
176 if (old_mdr1 == priv->mdr1)
179 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
181 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
182 UART_FCR_CLEAR_RCVR);
184 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
185 * TX_FIFO_E bit is 1.
187 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
188 (UART_LSR_THRE | UART_LSR_DR))) {
191 /* Should *never* happen. we warn and carry on */
192 dev_crit(up->port.dev, "Errata i202: timedout %x\n",
193 serial_in(up, UART_LSR));
200 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
201 struct omap8250_priv *priv)
203 unsigned int uartclk = port->uartclk;
204 unsigned int div_13, div_16;
205 unsigned int abs_d13, abs_d16;
208 * Old custom speed handling.
210 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
211 priv->quot = port->custom_divisor & UART_DIV_MAX;
213 * I assume that nobody is using this. But hey, if somebody
214 * would like to specify the divisor _and_ the mode then the
215 * driver is ready and waiting for it.
217 if (port->custom_divisor & (1 << 16))
218 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
220 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
223 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
224 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
231 abs_d13 = abs(baud - uartclk / 13 / div_13);
232 abs_d16 = abs(baud - uartclk / 16 / div_16);
234 if (abs_d13 >= abs_d16) {
235 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
238 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
243 static void omap8250_update_scr(struct uart_8250_port *up,
244 struct omap8250_priv *priv)
248 old_scr = serial_in(up, UART_OMAP_SCR);
249 if (old_scr == priv->scr)
253 * The manual recommends not to enable the DMA mode selector in the SCR
254 * (instead of the FCR) register _and_ selecting the DMA mode as one
255 * register write because this may lead to malfunction.
257 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
258 serial_out(up, UART_OMAP_SCR,
259 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
260 serial_out(up, UART_OMAP_SCR, priv->scr);
263 static void omap8250_update_mdr1(struct uart_8250_port *up,
264 struct omap8250_priv *priv)
266 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
267 omap_8250_mdr1_errataset(up, priv);
269 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
272 static void omap8250_restore_regs(struct uart_8250_port *up)
274 struct omap8250_priv *priv = up->port.private_data;
275 struct uart_8250_dma *dma = up->dma;
277 if (dma && dma->tx_running) {
279 * TCSANOW requests the change to occur immediately however if
280 * we have a TX-DMA operation in progress then it has been
281 * observed that it might stall and never complete. Therefore we
282 * delay DMA completes to prevent this hang from happen.
284 priv->delayed_restore = 1;
288 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
289 serial_out(up, UART_EFR, UART_EFR_ECB);
291 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
292 serial8250_out_MCR(up, UART_MCR_TCRTLR);
293 serial_out(up, UART_FCR, up->fcr);
295 omap8250_update_scr(up, priv);
297 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
299 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
300 OMAP_UART_TCR_HALT(52));
301 serial_out(up, UART_TI752_TLR,
302 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX |
303 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX);
305 serial_out(up, UART_LCR, 0);
307 /* drop TCR + TLR access, we setup XON/XOFF later */
308 serial8250_out_MCR(up, up->mcr);
309 serial_out(up, UART_IER, up->ier);
311 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
312 serial_dl_write(up, priv->quot);
314 serial_out(up, UART_EFR, priv->efr);
316 /* Configure flow control */
317 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
318 serial_out(up, UART_XON1, priv->xon);
319 serial_out(up, UART_XOFF1, priv->xoff);
321 serial_out(up, UART_LCR, up->lcr);
323 omap8250_update_mdr1(up, priv);
325 up->port.ops->set_mctrl(&up->port, up->port.mctrl);
329 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
330 * some differences in how we want to handle flow control.
332 static void omap_8250_set_termios(struct uart_port *port,
333 struct ktermios *termios,
334 struct ktermios *old)
336 struct uart_8250_port *up = up_to_u8250p(port);
337 struct omap8250_priv *priv = up->port.private_data;
338 unsigned char cval = 0;
341 switch (termios->c_cflag & CSIZE) {
343 cval = UART_LCR_WLEN5;
346 cval = UART_LCR_WLEN6;
349 cval = UART_LCR_WLEN7;
353 cval = UART_LCR_WLEN8;
357 if (termios->c_cflag & CSTOPB)
358 cval |= UART_LCR_STOP;
359 if (termios->c_cflag & PARENB)
360 cval |= UART_LCR_PARITY;
361 if (!(termios->c_cflag & PARODD))
362 cval |= UART_LCR_EPAR;
363 if (termios->c_cflag & CMSPAR)
364 cval |= UART_LCR_SPAR;
367 * Ask the core to calculate the divisor for us.
369 baud = uart_get_baud_rate(port, termios, old,
370 port->uartclk / 16 / UART_DIV_MAX,
372 omap_8250_get_divisor(port, baud, priv);
375 * Ok, we're now changing the port state. Do it with
376 * interrupts disabled.
378 pm_runtime_get_sync(port->dev);
379 spin_lock_irq(&port->lock);
382 * Update the per-port timeout.
384 uart_update_timeout(port, termios->c_cflag, baud);
386 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
387 if (termios->c_iflag & INPCK)
388 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
389 if (termios->c_iflag & (IGNBRK | PARMRK))
390 up->port.read_status_mask |= UART_LSR_BI;
393 * Characters to ignore
395 up->port.ignore_status_mask = 0;
396 if (termios->c_iflag & IGNPAR)
397 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
398 if (termios->c_iflag & IGNBRK) {
399 up->port.ignore_status_mask |= UART_LSR_BI;
401 * If we're ignoring parity and break indicators,
402 * ignore overruns too (for real raw support).
404 if (termios->c_iflag & IGNPAR)
405 up->port.ignore_status_mask |= UART_LSR_OE;
409 * ignore all characters if CREAD is not set
411 if ((termios->c_cflag & CREAD) == 0)
412 up->port.ignore_status_mask |= UART_LSR_DR;
415 * Modem status interrupts
417 up->ier &= ~UART_IER_MSI;
418 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
419 up->ier |= UART_IER_MSI;
422 /* Up to here it was mostly serial8250_do_set_termios() */
425 * We enable TRIG_GRANU for RX and TX and additionally we set
426 * SCR_TX_EMPTY bit. The result is the following:
427 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
428 * - less than RX_TRIGGER number of bytes will also cause an interrupt
429 * once the UART decides that there no new bytes arriving.
430 * - Once THRE is enabled, the interrupt will be fired once the FIFO is
431 * empty - the trigger level is ignored here.
433 * Once DMA is enabled:
434 * - UART will assert the TX DMA line once there is room for TX_TRIGGER
435 * bytes in the TX FIFO. On each assert the DMA engine will move
436 * TX_TRIGGER bytes into the FIFO.
437 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
438 * the FIFO and move RX_TRIGGER bytes.
439 * This is because threshold and trigger values are the same.
441 up->fcr = UART_FCR_ENABLE_FIFO;
442 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG;
443 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG;
445 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
446 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
449 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
450 OMAP_UART_SCR_DMAMODE_CTL;
452 priv->xon = termios->c_cc[VSTART];
453 priv->xoff = termios->c_cc[VSTOP];
456 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
458 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW &&
459 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) &&
460 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) {
461 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
462 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
463 priv->efr |= UART_EFR_CTS;
464 } else if (up->port.flags & UPF_SOFT_FLOW) {
466 * OMAP rx s/w flow control is borked; the transmitter remains
467 * stuck off even if rx flow control is subsequently disabled
472 * Enable XON/XOFF flow control on output.
473 * Transmit XON1, XOFF1
475 if (termios->c_iflag & IXOFF) {
476 up->port.status |= UPSTAT_AUTOXOFF;
477 priv->efr |= OMAP_UART_SW_TX;
480 omap8250_restore_regs(up);
482 spin_unlock_irq(&up->port.lock);
483 pm_runtime_mark_last_busy(port->dev);
484 pm_runtime_put_autosuspend(port->dev);
486 /* calculate wakeup latency constraint */
487 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
488 priv->latency = priv->calc_latency;
490 schedule_work(&priv->qos_work);
492 /* Don't rewrite B0 */
493 if (tty_termios_baud_rate(termios))
494 tty_termios_encode_baud_rate(termios, baud, baud);
497 /* same as 8250 except that we may have extra flow bits set in EFR */
498 static void omap_8250_pm(struct uart_port *port, unsigned int state,
499 unsigned int oldstate)
501 struct uart_8250_port *up = up_to_u8250p(port);
504 pm_runtime_get_sync(port->dev);
505 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
506 efr = serial_in(up, UART_EFR);
507 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
508 serial_out(up, UART_LCR, 0);
510 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
511 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
512 serial_out(up, UART_EFR, efr);
513 serial_out(up, UART_LCR, 0);
515 pm_runtime_mark_last_busy(port->dev);
516 pm_runtime_put_autosuspend(port->dev);
519 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
520 struct omap8250_priv *priv)
523 u16 revision, major, minor;
525 mvr = uart_read(up, UART_OMAP_MVER);
527 /* Check revision register scheme */
528 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
531 case 0: /* Legacy Scheme: OMAP2/3 */
532 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
533 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
534 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
535 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
538 /* New Scheme: OMAP4+ */
539 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
540 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
541 OMAP_UART_MVR_MAJ_SHIFT;
542 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
545 dev_warn(up->port.dev,
546 "Unknown revision, defaulting to highest\n");
547 /* highest possible revision */
551 /* normalize revision for the driver */
552 revision = UART_BUILD_REVISION(major, minor);
555 case OMAP_UART_REV_46:
556 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
558 case OMAP_UART_REV_52:
559 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
560 OMAP_UART_WER_HAS_TX_WAKEUP;
562 case OMAP_UART_REV_63:
563 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
564 OMAP_UART_WER_HAS_TX_WAKEUP;
571 static void omap8250_uart_qos_work(struct work_struct *work)
573 struct omap8250_priv *priv;
575 priv = container_of(work, struct omap8250_priv, qos_work);
576 pm_qos_update_request(&priv->pm_qos_request, priv->latency);
579 #ifdef CONFIG_SERIAL_8250_DMA
580 static int omap_8250_dma_handle_irq(struct uart_port *port);
583 static irqreturn_t omap8250_irq(int irq, void *dev_id)
585 struct uart_port *port = dev_id;
586 struct uart_8250_port *up = up_to_u8250p(port);
590 #ifdef CONFIG_SERIAL_8250_DMA
592 ret = omap_8250_dma_handle_irq(port);
593 return IRQ_RETVAL(ret);
597 serial8250_rpm_get(up);
598 iir = serial_port_in(port, UART_IIR);
599 ret = serial8250_handle_irq(port, iir);
600 serial8250_rpm_put(up);
602 return IRQ_RETVAL(ret);
605 static int omap_8250_startup(struct uart_port *port)
607 struct uart_8250_port *up = up_to_u8250p(port);
608 struct omap8250_priv *priv = port->private_data;
612 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
617 pm_runtime_get_sync(port->dev);
620 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
622 serial_out(up, UART_LCR, UART_LCR_WLEN8);
624 up->lsr_saved_flags = 0;
625 up->msr_saved_flags = 0;
627 /* Disable DMA for console UART */
628 if (uart_console(port))
632 ret = serial8250_request_dma(up);
634 dev_warn_ratelimited(port->dev,
635 "failed to request DMA\n");
640 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
641 dev_name(port->dev), port);
645 up->ier = UART_IER_RLSI | UART_IER_RDI;
646 serial_out(up, UART_IER, up->ier);
649 up->capabilities |= UART_CAP_RPM;
652 /* Enable module level wake up */
653 priv->wer = OMAP_UART_WER_MOD_WKUP;
654 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
655 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
656 serial_out(up, UART_OMAP_WER, priv->wer);
661 pm_runtime_mark_last_busy(port->dev);
662 pm_runtime_put_autosuspend(port->dev);
665 pm_runtime_mark_last_busy(port->dev);
666 pm_runtime_put_autosuspend(port->dev);
667 dev_pm_clear_wake_irq(port->dev);
671 static void omap_8250_shutdown(struct uart_port *port)
673 struct uart_8250_port *up = up_to_u8250p(port);
674 struct omap8250_priv *priv = port->private_data;
676 flush_work(&priv->qos_work);
678 omap_8250_rx_dma_flush(up);
680 pm_runtime_get_sync(port->dev);
682 serial_out(up, UART_OMAP_WER, 0);
685 serial_out(up, UART_IER, 0);
688 serial8250_release_dma(up);
691 * Disable break condition and FIFOs
693 if (up->lcr & UART_LCR_SBC)
694 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
695 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
697 pm_runtime_mark_last_busy(port->dev);
698 pm_runtime_put_autosuspend(port->dev);
699 free_irq(port->irq, port);
700 dev_pm_clear_wake_irq(port->dev);
703 static void omap_8250_throttle(struct uart_port *port)
705 struct omap8250_priv *priv = port->private_data;
706 struct uart_8250_port *up = up_to_u8250p(port);
709 pm_runtime_get_sync(port->dev);
711 spin_lock_irqsave(&port->lock, flags);
712 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
713 serial_out(up, UART_IER, up->ier);
714 priv->throttled = true;
715 spin_unlock_irqrestore(&port->lock, flags);
717 pm_runtime_mark_last_busy(port->dev);
718 pm_runtime_put_autosuspend(port->dev);
721 static int omap_8250_rs485_config(struct uart_port *port,
722 struct serial_rs485 *rs485)
724 struct uart_8250_port *up = up_to_u8250p(port);
726 /* Clamp the delays to [0, 100ms] */
727 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
728 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
730 port->rs485 = *rs485;
733 * Both serial8250_em485_init and serial8250_em485_destroy
736 if (rs485->flags & SER_RS485_ENABLED) {
737 int ret = serial8250_em485_init(up);
740 rs485->flags &= ~SER_RS485_ENABLED;
741 port->rs485.flags &= ~SER_RS485_ENABLED;
746 serial8250_em485_destroy(up);
751 static void omap_8250_unthrottle(struct uart_port *port)
753 struct omap8250_priv *priv = port->private_data;
754 struct uart_8250_port *up = up_to_u8250p(port);
757 pm_runtime_get_sync(port->dev);
759 spin_lock_irqsave(&port->lock, flags);
760 priv->throttled = false;
763 up->ier |= UART_IER_RLSI | UART_IER_RDI;
764 serial_out(up, UART_IER, up->ier);
765 spin_unlock_irqrestore(&port->lock, flags);
767 pm_runtime_mark_last_busy(port->dev);
768 pm_runtime_put_autosuspend(port->dev);
771 #ifdef CONFIG_SERIAL_8250_DMA
772 static int omap_8250_rx_dma(struct uart_8250_port *p);
774 static void __dma_rx_do_complete(struct uart_8250_port *p)
776 struct omap8250_priv *priv = p->port.private_data;
777 struct uart_8250_dma *dma = p->dma;
778 struct tty_port *tty_port = &p->port.state->port;
779 struct dma_tx_state state;
784 spin_lock_irqsave(&priv->rx_dma_lock, flags);
786 if (!dma->rx_running)
790 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
792 count = dma->rx_size - state.residue;
794 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
796 p->port.icount.rx += ret;
797 p->port.icount.buf_overrun += count - ret;
799 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
801 tty_flip_buffer_push(tty_port);
804 static void __dma_rx_complete(void *param)
806 struct uart_8250_port *p = param;
807 struct omap8250_priv *priv = p->port.private_data;
808 struct uart_8250_dma *dma = p->dma;
809 struct dma_tx_state state;
812 spin_lock_irqsave(&p->port.lock, flags);
815 * If the tx status is not DMA_COMPLETE, then this is a delayed
816 * completion callback. A previous RX timeout flush would have
817 * already pushed the data, so exit.
819 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
821 spin_unlock_irqrestore(&p->port.lock, flags);
824 __dma_rx_do_complete(p);
825 if (!priv->throttled)
828 spin_unlock_irqrestore(&p->port.lock, flags);
831 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
833 struct omap8250_priv *priv = p->port.private_data;
834 struct uart_8250_dma *dma = p->dma;
835 struct dma_tx_state state;
839 spin_lock_irqsave(&priv->rx_dma_lock, flags);
841 if (!dma->rx_running) {
842 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
846 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
847 if (ret == DMA_IN_PROGRESS) {
848 ret = dmaengine_pause(dma->rxchan);
849 if (WARN_ON_ONCE(ret))
850 priv->rx_dma_broken = true;
852 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
854 __dma_rx_do_complete(p);
855 dmaengine_terminate_all(dma->rxchan);
858 static int omap_8250_rx_dma(struct uart_8250_port *p)
860 struct omap8250_priv *priv = p->port.private_data;
861 struct uart_8250_dma *dma = p->dma;
863 struct dma_async_tx_descriptor *desc;
866 if (priv->rx_dma_broken)
869 spin_lock_irqsave(&priv->rx_dma_lock, flags);
874 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
875 dma->rx_size, DMA_DEV_TO_MEM,
876 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
883 desc->callback = __dma_rx_complete;
884 desc->callback_param = p;
886 dma->rx_cookie = dmaengine_submit(desc);
888 dma_async_issue_pending(dma->rxchan);
890 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
894 static int omap_8250_tx_dma(struct uart_8250_port *p);
896 static void omap_8250_dma_tx_complete(void *param)
898 struct uart_8250_port *p = param;
899 struct uart_8250_dma *dma = p->dma;
900 struct circ_buf *xmit = &p->port.state->xmit;
902 bool en_thri = false;
903 struct omap8250_priv *priv = p->port.private_data;
905 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
906 UART_XMIT_SIZE, DMA_TO_DEVICE);
908 spin_lock_irqsave(&p->port.lock, flags);
912 xmit->tail += dma->tx_size;
913 xmit->tail &= UART_XMIT_SIZE - 1;
914 p->port.icount.tx += dma->tx_size;
916 if (priv->delayed_restore) {
917 priv->delayed_restore = 0;
918 omap8250_restore_regs(p);
921 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
922 uart_write_wakeup(&p->port);
924 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
927 ret = omap_8250_tx_dma(p);
930 } else if (p->capabilities & UART_CAP_RPM) {
936 serial8250_set_THRI(p);
939 spin_unlock_irqrestore(&p->port.lock, flags);
942 static int omap_8250_tx_dma(struct uart_8250_port *p)
944 struct uart_8250_dma *dma = p->dma;
945 struct omap8250_priv *priv = p->port.private_data;
946 struct circ_buf *xmit = &p->port.state->xmit;
947 struct dma_async_tx_descriptor *desc;
948 unsigned int skip_byte = 0;
953 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
956 * Even if no data, we need to return an error for the two cases
957 * below so serial8250_tx_chars() is invoked and properly clears
958 * THRI and/or runtime suspend.
960 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
964 serial8250_clear_THRI(p);
968 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
969 if (priv->habit & OMAP_DMA_TX_KICK) {
973 * We need to put the first byte into the FIFO in order to start
974 * the DMA transfer. For transfers smaller than four bytes we
975 * don't bother doing DMA at all. It seem not matter if there
976 * are still bytes in the FIFO from the last transfer (in case
977 * we got here directly from omap_8250_dma_tx_complete()). Bytes
978 * leaving the FIFO seem not to trigger the DMA transfer. It is
979 * really the byte that we put into the FIFO.
980 * If the FIFO is already full then we most likely got here from
981 * omap_8250_dma_tx_complete(). And this means the DMA engine
982 * just completed its work. We don't have to wait the complete
983 * 86us at 115200,8n1 but around 60us (not to mention lower
984 * baudrates). So in that case we take the interrupt and try
985 * again with an empty FIFO.
987 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
988 if (tx_lvl == p->tx_loadsz) {
992 if (dma->tx_size < 4) {
999 desc = dmaengine_prep_slave_single(dma->txchan,
1000 dma->tx_addr + xmit->tail + skip_byte,
1001 dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
1002 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1008 dma->tx_running = 1;
1010 desc->callback = omap_8250_dma_tx_complete;
1011 desc->callback_param = p;
1013 dma->tx_cookie = dmaengine_submit(desc);
1015 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
1016 UART_XMIT_SIZE, DMA_TO_DEVICE);
1018 dma_async_issue_pending(dma->txchan);
1022 serial8250_clear_THRI(p);
1024 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1031 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1033 switch (iir & 0x3f) {
1035 case UART_IIR_RX_TIMEOUT:
1037 omap_8250_rx_dma_flush(up);
1040 return omap_8250_rx_dma(up);
1044 * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1045 * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1046 * use the default routine in the non-DMA case and this one for with DMA.
1048 static int omap_8250_dma_handle_irq(struct uart_port *port)
1050 struct uart_8250_port *up = up_to_u8250p(port);
1051 unsigned char status;
1052 unsigned long flags;
1055 serial8250_rpm_get(up);
1057 iir = serial_port_in(port, UART_IIR);
1058 if (iir & UART_IIR_NO_INT) {
1059 serial8250_rpm_put(up);
1063 spin_lock_irqsave(&port->lock, flags);
1065 status = serial_port_in(port, UART_LSR);
1067 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1068 if (handle_rx_dma(up, iir)) {
1069 status = serial8250_rx_chars(up, status);
1070 omap_8250_rx_dma(up);
1073 serial8250_modem_status(up);
1074 if (status & UART_LSR_THRE && up->dma->tx_err) {
1075 if (uart_tx_stopped(&up->port) ||
1076 uart_circ_empty(&up->port.state->xmit)) {
1077 up->dma->tx_err = 0;
1078 serial8250_tx_chars(up);
1081 * try again due to an earlier failer which
1082 * might have been resolved by now.
1084 if (omap_8250_tx_dma(up))
1085 serial8250_tx_chars(up);
1089 uart_unlock_and_check_sysrq(port, flags);
1090 serial8250_rpm_put(up);
1094 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1101 static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1107 static int omap8250_no_handle_irq(struct uart_port *port)
1109 /* IRQ has not been requested but handling irq? */
1110 WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1114 static const u8 omap4_habit = UART_ERRATA_CLOCK_DISABLE;
1115 static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE;
1116 static const u8 dra742_habit = UART_ERRATA_CLOCK_DISABLE;
1118 static const struct of_device_id omap8250_dt_ids[] = {
1119 { .compatible = "ti,am654-uart" },
1120 { .compatible = "ti,omap2-uart" },
1121 { .compatible = "ti,omap3-uart" },
1122 { .compatible = "ti,omap4-uart", .data = &omap4_habit, },
1123 { .compatible = "ti,am3352-uart", .data = &am3352_habit, },
1124 { .compatible = "ti,am4372-uart", .data = &am3352_habit, },
1125 { .compatible = "ti,dra742-uart", .data = &dra742_habit, },
1128 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1130 static int omap8250_probe(struct platform_device *pdev)
1132 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1133 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1134 struct device_node *np = pdev->dev.of_node;
1135 struct omap8250_priv *priv;
1136 struct uart_8250_port up;
1138 void __iomem *membase;
1139 const struct of_device_id *id;
1141 if (!regs || !irq) {
1142 dev_err(&pdev->dev, "missing registers or irq\n");
1146 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1150 membase = devm_ioremap_nocache(&pdev->dev, regs->start,
1151 resource_size(regs));
1155 memset(&up, 0, sizeof(up));
1156 up.port.dev = &pdev->dev;
1157 up.port.mapbase = regs->start;
1158 up.port.membase = membase;
1159 up.port.irq = irq->start;
1161 * It claims to be 16C750 compatible however it is a little different.
1162 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1163 * have) is enabled via EFR instead of MCR. The type is set here 8250
1164 * just to get things going. UNKNOWN does not work for a few reasons and
1165 * we don't need our own type since we don't use 8250's set_termios()
1168 up.port.type = PORT_8250;
1169 up.port.iotype = UPIO_MEM;
1170 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1172 up.port.private_data = priv;
1174 up.port.regshift = 2;
1175 up.port.fifosize = 64;
1177 up.capabilities = UART_CAP_FIFO;
1180 * Runtime PM is mostly transparent. However to do it right we need to a
1181 * TX empty interrupt before we can put the device to auto idle. So if
1182 * PM is not enabled we don't add that flag and can spare that one extra
1183 * interrupt in the TX path.
1185 up.capabilities |= UART_CAP_RPM;
1187 up.port.set_termios = omap_8250_set_termios;
1188 up.port.set_mctrl = omap8250_set_mctrl;
1189 up.port.pm = omap_8250_pm;
1190 up.port.startup = omap_8250_startup;
1191 up.port.shutdown = omap_8250_shutdown;
1192 up.port.throttle = omap_8250_throttle;
1193 up.port.unthrottle = omap_8250_unthrottle;
1194 up.port.rs485_config = omap_8250_rs485_config;
1196 ret = of_alias_get_id(np, "serial");
1198 dev_err(&pdev->dev, "failed to get alias\n");
1203 if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) {
1206 clk = devm_clk_get(&pdev->dev, NULL);
1208 if (PTR_ERR(clk) == -EPROBE_DEFER)
1209 return -EPROBE_DEFER;
1211 up.port.uartclk = clk_get_rate(clk);
1215 priv->wakeirq = irq_of_parse_and_map(np, 1);
1217 id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev);
1219 priv->habit |= *(u8 *)id->data;
1221 if (!up.port.uartclk) {
1222 up.port.uartclk = DEFAULT_CLK_SPEED;
1223 dev_warn(&pdev->dev,
1224 "No clock speed specified: using default: %d\n",
1228 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1229 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1230 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY,
1232 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1234 spin_lock_init(&priv->rx_dma_lock);
1236 device_init_wakeup(&pdev->dev, true);
1237 pm_runtime_use_autosuspend(&pdev->dev);
1240 * Disable runtime PM until autosuspend delay unless specifically
1241 * enabled by the user via sysfs. This is the historic way to
1242 * prevent an unsafe default policy with lossy characters on wake-up.
1243 * For serdev devices this is not needed, the policy can be managed by
1244 * the serdev driver.
1246 if (!of_get_available_child_count(pdev->dev.of_node))
1247 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1249 pm_runtime_irq_safe(&pdev->dev);
1250 pm_runtime_enable(&pdev->dev);
1252 pm_runtime_get_sync(&pdev->dev);
1254 omap_serial_fill_features_erratas(&up, priv);
1255 up.port.handle_irq = omap8250_no_handle_irq;
1256 #ifdef CONFIG_SERIAL_8250_DMA
1258 * Oh DMA support. If there are no DMA properties in the DT then
1259 * we will fall back to a generic DMA channel which does not
1260 * really work here. To ensure that we do not get a generic DMA
1261 * channel assigned, we have the the_no_dma_filter_fn() here.
1262 * To avoid "failed to request DMA" messages we check for DMA
1265 ret = of_property_count_strings(np, "dma-names");
1267 up.dma = &priv->omap8250_dma;
1268 priv->omap8250_dma.fn = the_no_dma_filter_fn;
1269 priv->omap8250_dma.tx_dma = omap_8250_tx_dma;
1270 priv->omap8250_dma.rx_dma = omap_8250_rx_dma;
1271 priv->omap8250_dma.rx_size = RX_TRIGGER;
1272 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER;
1273 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER;
1276 ret = serial8250_register_8250_port(&up);
1278 dev_err(&pdev->dev, "unable to register 8250 port\n");
1282 platform_set_drvdata(pdev, priv);
1283 pm_runtime_mark_last_busy(&pdev->dev);
1284 pm_runtime_put_autosuspend(&pdev->dev);
1287 pm_runtime_dont_use_autosuspend(&pdev->dev);
1288 pm_runtime_put_sync(&pdev->dev);
1289 pm_runtime_disable(&pdev->dev);
1293 static int omap8250_remove(struct platform_device *pdev)
1295 struct omap8250_priv *priv = platform_get_drvdata(pdev);
1297 pm_runtime_dont_use_autosuspend(&pdev->dev);
1298 pm_runtime_put_sync(&pdev->dev);
1299 pm_runtime_disable(&pdev->dev);
1300 serial8250_unregister_port(priv->line);
1301 pm_qos_remove_request(&priv->pm_qos_request);
1302 device_init_wakeup(&pdev->dev, false);
1306 #ifdef CONFIG_PM_SLEEP
1307 static int omap8250_prepare(struct device *dev)
1309 struct omap8250_priv *priv = dev_get_drvdata(dev);
1313 priv->is_suspending = true;
1317 static void omap8250_complete(struct device *dev)
1319 struct omap8250_priv *priv = dev_get_drvdata(dev);
1323 priv->is_suspending = false;
1326 static int omap8250_suspend(struct device *dev)
1328 struct omap8250_priv *priv = dev_get_drvdata(dev);
1329 struct uart_8250_port *up = serial8250_get_port(priv->line);
1331 serial8250_suspend_port(priv->line);
1333 pm_runtime_get_sync(dev);
1334 if (!device_may_wakeup(dev))
1336 serial_out(up, UART_OMAP_WER, priv->wer);
1337 pm_runtime_mark_last_busy(dev);
1338 pm_runtime_put_autosuspend(dev);
1340 flush_work(&priv->qos_work);
1344 static int omap8250_resume(struct device *dev)
1346 struct omap8250_priv *priv = dev_get_drvdata(dev);
1348 serial8250_resume_port(priv->line);
1352 #define omap8250_prepare NULL
1353 #define omap8250_complete NULL
1357 static int omap8250_lost_context(struct uart_8250_port *up)
1361 val = serial_in(up, UART_OMAP_SCR);
1363 * If we lose context, then SCR is set to its reset value of zero.
1364 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1365 * among other bits, to never set the register back to zero again.
1372 /* TODO: in future, this should happen via API in drivers/reset/ */
1373 static int omap8250_soft_reset(struct device *dev)
1375 struct omap8250_priv *priv = dev_get_drvdata(dev);
1376 struct uart_8250_port *up = serial8250_get_port(priv->line);
1382 * At least on omap4, unused uarts may not idle after reset without
1383 * a basic scr dma configuration even with no dma in use. The
1384 * module clkctrl status bits will be 1 instead of 3 blocking idle
1385 * for the whole clockdomain. The softreset below will clear scr,
1386 * and we restore it on resume so this is safe to do on all SoCs
1387 * needing omap8250_soft_reset() quirk. Do it in two writes as
1388 * recommended in the comment for omap8250_update_scr().
1390 serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1);
1391 serial_out(up, UART_OMAP_SCR,
1392 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL);
1394 sysc = serial_in(up, UART_OMAP_SYSC);
1396 /* softreset the UART */
1397 sysc |= OMAP_UART_SYSC_SOFTRESET;
1398 serial_out(up, UART_OMAP_SYSC, sysc);
1400 /* By experiments, 1us enough for reset complete on AM335x */
1403 syss = serial_in(up, UART_OMAP_SYSS);
1404 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1407 dev_err(dev, "timed out waiting for reset done\n");
1414 static int omap8250_runtime_suspend(struct device *dev)
1416 struct omap8250_priv *priv = dev_get_drvdata(dev);
1417 struct uart_8250_port *up;
1419 /* In case runtime-pm tries this before we are setup */
1423 up = serial8250_get_port(priv->line);
1425 * When using 'no_console_suspend', the console UART must not be
1426 * suspended. Since driver suspend is managed by runtime suspend,
1427 * preventing runtime suspend (by returning error) will keep device
1428 * active during suspend.
1430 if (priv->is_suspending && !console_suspend_enabled) {
1431 if (uart_console(&up->port))
1435 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1438 ret = omap8250_soft_reset(dev);
1442 /* Restore to UART mode after reset (for wakeup) */
1443 omap8250_update_mdr1(up, priv);
1444 /* Restore wakeup enable register */
1445 serial_out(up, UART_OMAP_WER, priv->wer);
1448 if (up->dma && up->dma->rxchan)
1449 omap_8250_rx_dma_flush(up);
1451 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1452 schedule_work(&priv->qos_work);
1457 static int omap8250_runtime_resume(struct device *dev)
1459 struct omap8250_priv *priv = dev_get_drvdata(dev);
1460 struct uart_8250_port *up;
1462 /* In case runtime-pm tries this before we are setup */
1466 up = serial8250_get_port(priv->line);
1468 if (omap8250_lost_context(up))
1469 omap8250_restore_regs(up);
1471 if (up->dma && up->dma->rxchan)
1472 omap_8250_rx_dma(up);
1474 priv->latency = priv->calc_latency;
1475 schedule_work(&priv->qos_work);
1480 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1481 static int __init omap8250_console_fixup(void)
1487 if (strstr(boot_command_line, "console=ttyS"))
1488 /* user set a ttyS based name for the console */
1491 omap_str = strstr(boot_command_line, "console=ttyO");
1493 /* user did not set ttyO based console, so we don't care */
1497 if ('0' <= *omap_str && *omap_str <= '9')
1498 idx = *omap_str - '0';
1503 if (omap_str[0] == ',') {
1510 add_preferred_console("ttyS", idx, options);
1511 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1513 pr_err("This ensures that you still see kernel messages. Please\n");
1514 pr_err("update your kernel commandline.\n");
1517 console_initcall(omap8250_console_fixup);
1520 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1521 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1522 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1523 omap8250_runtime_resume, NULL)
1524 .prepare = omap8250_prepare,
1525 .complete = omap8250_complete,
1528 static struct platform_driver omap8250_platform_driver = {
1531 .pm = &omap8250_dev_pm_ops,
1532 .of_match_table = omap8250_dt_ids,
1534 .probe = omap8250_probe,
1535 .remove = omap8250_remove,
1537 module_platform_driver(omap8250_platform_driver);
1539 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1540 MODULE_DESCRIPTION("OMAP 8250 Driver");
1541 MODULE_LICENSE("GPL v2");