drivers/tty/serial/8250/8250_omap.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * 8250-core based driver for the OMAP internal UART
   4  *
   5  * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Copyright (C) 2014 Sebastian Andrzej Siewior
   8  *
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/device.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/serial_8250.h>
  16 #include <linux/serial_reg.h>
  17 #include <linux/tty_flip.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/slab.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_gpio.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/delay.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/console.h>
  27 #include <linux/pm_qos.h>
  28 #include <linux/pm_wakeirq.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/sys_soc.h>
  31
  32 #include "8250.h"
  33
  34 #define DEFAULT_CLK_SPEED       48000000
  35
  36 #define UART_ERRATA_i202_MDR1_ACCESS    (1 << 0)
  37 #define OMAP_UART_WER_HAS_TX_WAKEUP     (1 << 1)
  38 #define OMAP_DMA_TX_KICK                (1 << 2)
  39 /*
  40  * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
  41  * The same errata is applicable to AM335x and DRA7x processors too.
  42  */
  43 #define UART_ERRATA_CLOCK_DISABLE       (1 << 3)
  44 #define UART_HAS_EFR2                   BIT(4)
  45 #define UART_HAS_RHR_IT_DIS             BIT(5)
  46 #define UART_RX_TIMEOUT_QUIRK           BIT(6)
  47
  48 #define OMAP_UART_FCR_RX_TRIG           6
  49 #define OMAP_UART_FCR_TX_TRIG           4
  50
  51 /* SCR register bitmasks */
  52 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK       (1 << 7)
  53 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK       (1 << 6)
  54 #define OMAP_UART_SCR_TX_EMPTY                  (1 << 3)
  55 #define OMAP_UART_SCR_DMAMODE_MASK              (3 << 1)
  56 #define OMAP_UART_SCR_DMAMODE_1                 (1 << 1)
  57 #define OMAP_UART_SCR_DMAMODE_CTL               (1 << 0)
  58
  59 /* MVR register bitmasks */
  60 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  61 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  62 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  63 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  64 #define OMAP_UART_MVR_MAJ_MASK          0x700
  65 #define OMAP_UART_MVR_MAJ_SHIFT         8
  66 #define OMAP_UART_MVR_MIN_MASK          0x3f
  67
  68 /* SYSC register bitmasks */
  69 #define OMAP_UART_SYSC_SOFTRESET        (1 << 1)
  70
  71 /* SYSS register bitmasks */
  72 #define OMAP_UART_SYSS_RESETDONE        (1 << 0)
  73
  74 #define UART_TI752_TLR_TX       0
  75 #define UART_TI752_TLR_RX       4
  76
  77 #define TRIGGER_TLR_MASK(x)     ((x & 0x3c) >> 2)
  78 #define TRIGGER_FCR_MASK(x)     (x & 3)
  79
  80 /* Enable XON/XOFF flow control on output */
  81 #define OMAP_UART_SW_TX         0x08
  82 /* Enable XON/XOFF flow control on input */
  83 #define OMAP_UART_SW_RX         0x02
  84
  85 #define OMAP_UART_WER_MOD_WKUP  0x7f
  86 #define OMAP_UART_TX_WAKEUP_EN  (1 << 7)
  87
  88 #define TX_TRIGGER      1
  89 #define RX_TRIGGER      48
  90
  91 #define OMAP_UART_TCR_RESTORE(x)        ((x / 4) << 4)
  92 #define OMAP_UART_TCR_HALT(x)           ((x / 4) << 0)
  93
  94 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  95
  96 #define OMAP_UART_REV_46 0x0406
  97 #define OMAP_UART_REV_52 0x0502
  98 #define OMAP_UART_REV_63 0x0603
  99
 100 /* Interrupt Enable Register 2 */
 101 #define UART_OMAP_IER2                  0x1B
 102 #define UART_OMAP_IER2_RHR_IT_DIS       BIT(2)
 103
 104 /* Enhanced features register 2 */
 105 #define UART_OMAP_EFR2                  0x23
 106 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE   BIT(6)
 107
 108 /* RX FIFO occupancy indicator */
 109 #define UART_OMAP_RX_LVL                0x64
 110
 111 struct omap8250_priv {
 112         int line;
 113         u8 habit;
 114         u8 mdr1;
 115         u8 efr;
 116         u8 scr;
 117         u8 wer;
 118         u8 xon;
 119         u8 xoff;
 120         u8 delayed_restore;
 121         u16 quot;
 122
 123         u8 tx_trigger;
 124         u8 rx_trigger;
 125         bool is_suspending;
 126         int wakeirq;
 127         int wakeups_enabled;
 128         u32 latency;
 129         u32 calc_latency;
 130         struct pm_qos_request pm_qos_request;
 131         struct work_struct qos_work;
 132         struct uart_8250_dma omap8250_dma;
 133         spinlock_t rx_dma_lock;
 134         bool rx_dma_broken;
 135         bool throttled;
 136 };
 137
 138 struct omap8250_dma_params {
 139         u32 rx_size;
 140         u8 rx_trigger;
 141         u8 tx_trigger;
 142 };
 143
 144 struct omap8250_platdata {
 145         struct omap8250_dma_params *dma_params;
 146         u8 habit;
 147 };
 148
 149 #ifdef CONFIG_SERIAL_8250_DMA
 150 static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
 151 #else
 152 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
 153 #endif
 154
 155 static u32 uart_read(struct uart_8250_port *up, u32 reg)
 156 {
 157         return readl(up->port.membase + (reg << up->port.regshift));
 158 }
 159
 160 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
 161 {
 162         struct uart_8250_port *up = up_to_u8250p(port);
 163         struct omap8250_priv *priv = up->port.private_data;
 164         u8 lcr;
 165
 166         serial8250_do_set_mctrl(port, mctrl);
 167
 168         if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) {
 169                 /*
 170                  * Turn off autoRTS if RTS is lowered and restore autoRTS
 171                  * setting if RTS is raised
 172                  */
 173                 lcr = serial_in(up, UART_LCR);
 174                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 175                 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 176                         priv->efr |= UART_EFR_RTS;
 177                 else
 178                         priv->efr &= ~UART_EFR_RTS;
 179                 serial_out(up, UART_EFR, priv->efr);
 180                 serial_out(up, UART_LCR, lcr);
 181         }
 182 }
 183
 184 /*
 185  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
 186  * The access to uart register after MDR1 Access
 187  * causes UART to corrupt data.
 188  *
 189  * Need a delay =
 190  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
 191  * give 10 times as much
 192  */
 193 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
 194                                      struct omap8250_priv *priv)
 195 {
 196         u8 timeout = 255;
 197
 198         serial_out(up, UART_OMAP_MDR1, priv->mdr1);
 199         udelay(2);
 200         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
 201                         UART_FCR_CLEAR_RCVR);
 202         /*
 203          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
 204          * TX_FIFO_E bit is 1.
 205          */
 206         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
 207                                 (UART_LSR_THRE | UART_LSR_DR))) {
 208                 timeout--;
 209                 if (!timeout) {
 210                         /* Should *never* happen. we warn and carry on */
 211                         dev_crit(up->port.dev, "Errata i202: timedout %x\n",
 212                                  serial_in(up, UART_LSR));
 213                         break;
 214                 }
 215                 udelay(1);
 216         }
 217 }
 218
 219 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
 220                                   struct omap8250_priv *priv)
 221 {
 222         unsigned int uartclk = port->uartclk;
 223         unsigned int div_13, div_16;
 224         unsigned int abs_d13, abs_d16;
 225
 226         /*
 227          * Old custom speed handling.
 228          */
 229         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
 230                 priv->quot = port->custom_divisor & UART_DIV_MAX;
 231                 /*
 232                  * I assume that nobody is using this. But hey, if somebody
 233                  * would like to specify the divisor _and_ the mode then the
 234                  * driver is ready and waiting for it.
 235                  */
 236                 if (port->custom_divisor & (1 << 16))
 237                         priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
 238                 else
 239                         priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
 240                 return;
 241         }
 242         div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
 243         div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
 244
 245         if (!div_13)
 246                 div_13 = 1;
 247         if (!div_16)
 248                 div_16 = 1;
 249
 250         abs_d13 = abs(baud - uartclk / 13 / div_13);
 251         abs_d16 = abs(baud - uartclk / 16 / div_16);
 252
 253         if (abs_d13 >= abs_d16) {
 254                 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
 255                 priv->quot = div_16;
 256         } else {
 257                 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
 258                 priv->quot = div_13;
 259         }
 260 }
 261
 262 static void omap8250_update_scr(struct uart_8250_port *up,
 263                                 struct omap8250_priv *priv)
 264 {
 265         u8 old_scr;
 266
 267         old_scr = serial_in(up, UART_OMAP_SCR);
 268         if (old_scr == priv->scr)
 269                 return;
 270
 271         /*
 272          * The manual recommends not to enable the DMA mode selector in the SCR
 273          * (instead of the FCR) register _and_ selecting the DMA mode as one
 274          * register write because this may lead to malfunction.
 275          */
 276         if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
 277                 serial_out(up, UART_OMAP_SCR,
 278                            priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
 279         serial_out(up, UART_OMAP_SCR, priv->scr);
 280 }
 281
 282 static void omap8250_update_mdr1(struct uart_8250_port *up,
 283                                  struct omap8250_priv *priv)
 284 {
 285         if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
 286                 omap_8250_mdr1_errataset(up, priv);
 287         else
 288                 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
 289 }
 290
 291 static void omap8250_restore_regs(struct uart_8250_port *up)
 292 {
 293         struct omap8250_priv *priv = up->port.private_data;
 294         struct uart_8250_dma    *dma = up->dma;
 295
 296         if (dma && dma->tx_running) {
 297                 /*
 298                  * TCSANOW requests the change to occur immediately however if
 299                  * we have a TX-DMA operation in progress then it has been
 300                  * observed that it might stall and never complete. Therefore we
 301                  * delay DMA completes to prevent this hang from happen.
 302                  */
 303                 priv->delayed_restore = 1;
 304                 return;
 305         }
 306
 307         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 308         serial_out(up, UART_EFR, UART_EFR_ECB);
 309
 310         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 311         serial8250_out_MCR(up, UART_MCR_TCRTLR);
 312         serial_out(up, UART_FCR, up->fcr);
 313
 314         omap8250_update_scr(up, priv);
 315
 316         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 317
 318         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
 319                         OMAP_UART_TCR_HALT(52));
 320         serial_out(up, UART_TI752_TLR,
 321                    TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX |
 322                    TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX);
 323
 324         serial_out(up, UART_LCR, 0);
 325
 326         /* drop TCR + TLR access, we setup XON/XOFF later */
 327         serial8250_out_MCR(up, up->mcr);
 328         serial_out(up, UART_IER, up->ier);
 329
 330         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 331         serial_dl_write(up, priv->quot);
 332
 333         serial_out(up, UART_EFR, priv->efr);
 334
 335         /* Configure flow control */
 336         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 337         serial_out(up, UART_XON1, priv->xon);
 338         serial_out(up, UART_XOFF1, priv->xoff);
 339
 340         serial_out(up, UART_LCR, up->lcr);
 341
 342         omap8250_update_mdr1(up, priv);
 343
 344         up->port.ops->set_mctrl(&up->port, up->port.mctrl);
 345 }
 346
 347 /*
 348  * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
 349  * some differences in how we want to handle flow control.
 350  */
 351 static void omap_8250_set_termios(struct uart_port *port,
 352                                   struct ktermios *termios,
 353                                   struct ktermios *old)
 354 {
 355         struct uart_8250_port *up = up_to_u8250p(port);
 356         struct omap8250_priv *priv = up->port.private_data;
 357         unsigned char cval = 0;
 358         unsigned int baud;
 359
 360         switch (termios->c_cflag & CSIZE) {
 361         case CS5:
 362                 cval = UART_LCR_WLEN5;
 363                 break;
 364         case CS6:
 365                 cval = UART_LCR_WLEN6;
 366                 break;
 367         case CS7:
 368                 cval = UART_LCR_WLEN7;
 369                 break;
 370         default:
 371         case CS8:
 372                 cval = UART_LCR_WLEN8;
 373                 break;
 374         }
 375
 376         if (termios->c_cflag & CSTOPB)
 377                 cval |= UART_LCR_STOP;
 378         if (termios->c_cflag & PARENB)
 379                 cval |= UART_LCR_PARITY;
 380         if (!(termios->c_cflag & PARODD))
 381                 cval |= UART_LCR_EPAR;
 382         if (termios->c_cflag & CMSPAR)
 383                 cval |= UART_LCR_SPAR;
 384
 385         /*
 386          * Ask the core to calculate the divisor for us.
 387          */
 388         baud = uart_get_baud_rate(port, termios, old,
 389                                   port->uartclk / 16 / UART_DIV_MAX,
 390                                   port->uartclk / 13);
 391         omap_8250_get_divisor(port, baud, priv);
 392
 393         /*
 394          * Ok, we're now changing the port state. Do it with
 395          * interrupts disabled.
 396          */
 397         pm_runtime_get_sync(port->dev);
 398         spin_lock_irq(&port->lock);
 399
 400         /*
 401          * Update the per-port timeout.
 402          */
 403         uart_update_timeout(port, termios->c_cflag, baud);
 404
 405         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 406         if (termios->c_iflag & INPCK)
 407                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 408         if (termios->c_iflag & (IGNBRK | PARMRK))
 409                 up->port.read_status_mask |= UART_LSR_BI;
 410
 411         /*
 412          * Characters to ignore
 413          */
 414         up->port.ignore_status_mask = 0;
 415         if (termios->c_iflag & IGNPAR)
 416                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 417         if (termios->c_iflag & IGNBRK) {
 418                 up->port.ignore_status_mask |= UART_LSR_BI;
 419                 /*
 420                  * If we're ignoring parity and break indicators,
 421                  * ignore overruns too (for real raw support).
 422                  */
 423                 if (termios->c_iflag & IGNPAR)
 424                         up->port.ignore_status_mask |= UART_LSR_OE;
 425         }
 426
 427         /*
 428          * ignore all characters if CREAD is not set
 429          */
 430         if ((termios->c_cflag & CREAD) == 0)
 431                 up->port.ignore_status_mask |= UART_LSR_DR;
 432
 433         /*
 434          * Modem status interrupts
 435          */
 436         up->ier &= ~UART_IER_MSI;
 437         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 438                 up->ier |= UART_IER_MSI;
 439
 440         up->lcr = cval;
 441         /* Up to here it was mostly serial8250_do_set_termios() */
 442
 443         /*
 444          * We enable TRIG_GRANU for RX and TX and additionally we set
 445          * SCR_TX_EMPTY bit. The result is the following:
 446          * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
 447          * - less than RX_TRIGGER number of bytes will also cause an interrupt
 448          *   once the UART decides that there no new bytes arriving.
 449          * - Once THRE is enabled, the interrupt will be fired once the FIFO is
 450          *   empty - the trigger level is ignored here.
 451          *
 452          * Once DMA is enabled:
 453          * - UART will assert the TX DMA line once there is room for TX_TRIGGER
 454          *   bytes in the TX FIFO. On each assert the DMA engine will move
 455          *   TX_TRIGGER bytes into the FIFO.
 456          * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
 457          *   the FIFO and move RX_TRIGGER bytes.
 458          * This is because threshold and trigger values are the same.
 459          */
 460         up->fcr = UART_FCR_ENABLE_FIFO;
 461         up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG;
 462         up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG;
 463
 464         priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
 465                 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
 466
 467         if (up->dma)
 468                 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
 469                         OMAP_UART_SCR_DMAMODE_CTL;
 470
 471         priv->xon = termios->c_cc[VSTART];
 472         priv->xoff = termios->c_cc[VSTOP];
 473
 474         priv->efr = 0;
 475         up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
 476
 477         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW &&
 478             !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) &&
 479             !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) {
 480                 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
 481                 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
 482                 priv->efr |= UART_EFR_CTS;
 483         } else  if (up->port.flags & UPF_SOFT_FLOW) {
 484                 /*
 485                  * OMAP rx s/w flow control is borked; the transmitter remains
 486                  * stuck off even if rx flow control is subsequently disabled
 487                  */
 488
 489                 /*
 490                  * IXOFF Flag:
 491                  * Enable XON/XOFF flow control on output.
 492                  * Transmit XON1, XOFF1
 493                  */
 494                 if (termios->c_iflag & IXOFF) {
 495                         up->port.status |= UPSTAT_AUTOXOFF;
 496                         priv->efr |= OMAP_UART_SW_TX;
 497                 }
 498         }
 499         omap8250_restore_regs(up);
 500
 501         spin_unlock_irq(&up->port.lock);
 502         pm_runtime_mark_last_busy(port->dev);
 503         pm_runtime_put_autosuspend(port->dev);
 504
 505         /* calculate wakeup latency constraint */
 506         priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
 507         priv->latency = priv->calc_latency;
 508
 509         schedule_work(&priv->qos_work);
 510
 511         /* Don't rewrite B0 */
 512         if (tty_termios_baud_rate(termios))
 513                 tty_termios_encode_baud_rate(termios, baud, baud);
 514 }
 515
 516 /* same as 8250 except that we may have extra flow bits set in EFR */
 517 static void omap_8250_pm(struct uart_port *port, unsigned int state,
 518                          unsigned int oldstate)
 519 {
 520         struct uart_8250_port *up = up_to_u8250p(port);
 521         u8 efr;
 522
 523         pm_runtime_get_sync(port->dev);
 524         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 525         efr = serial_in(up, UART_EFR);
 526         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
 527         serial_out(up, UART_LCR, 0);
 528
 529         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
 530         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 531         serial_out(up, UART_EFR, efr);
 532         serial_out(up, UART_LCR, 0);
 533
 534         pm_runtime_mark_last_busy(port->dev);
 535         pm_runtime_put_autosuspend(port->dev);
 536 }
 537
 538 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
 539                                               struct omap8250_priv *priv)
 540 {
 541         const struct soc_device_attribute k3_soc_devices[] = {
 542                 { .family = "AM65X",  },
 543                 { .family = "J721E", .revision = "SR1.0" },
 544                 { /* sentinel */ }
 545         };
 546         u32 mvr, scheme;
 547         u16 revision, major, minor;
 548
 549         mvr = uart_read(up, UART_OMAP_MVER);
 550
 551         /* Check revision register scheme */
 552         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
 553
 554         switch (scheme) {
 555         case 0: /* Legacy Scheme: OMAP2/3 */
 556                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
 557                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
 558                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
 559                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
 560                 break;
 561         case 1:
 562                 /* New Scheme: OMAP4+ */
 563                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
 564                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
 565                         OMAP_UART_MVR_MAJ_SHIFT;
 566                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
 567                 break;
 568         default:
 569                 dev_warn(up->port.dev,
 570                          "Unknown revision, defaulting to highest\n");
 571                 /* highest possible revision */
 572                 major = 0xff;
 573                 minor = 0xff;
 574         }
 575         /* normalize revision for the driver */
 576         revision = UART_BUILD_REVISION(major, minor);
 577
 578         switch (revision) {
 579         case OMAP_UART_REV_46:
 580                 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
 581                 break;
 582         case OMAP_UART_REV_52:
 583                 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
 584                                 OMAP_UART_WER_HAS_TX_WAKEUP;
 585                 break;
 586         case OMAP_UART_REV_63:
 587                 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
 588                         OMAP_UART_WER_HAS_TX_WAKEUP;
 589                 break;
 590         default:
 591                 break;
 592         }
 593
 594         /*
 595          * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't
 596          * don't have RHR_IT_DIS bit in IER2 register. So drop to flag
 597          * to enable errata workaround.
 598          */
 599         if (soc_device_match(k3_soc_devices))
 600                 priv->habit &= ~UART_HAS_RHR_IT_DIS;
 601 }
 602
 603 static void omap8250_uart_qos_work(struct work_struct *work)
 604 {
 605         struct omap8250_priv *priv;
 606
 607         priv = container_of(work, struct omap8250_priv, qos_work);
 608         cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency);
 609 }
 610
 611 #ifdef CONFIG_SERIAL_8250_DMA
 612 static int omap_8250_dma_handle_irq(struct uart_port *port);
 613 #endif
 614
 615 static irqreturn_t omap8250_irq(int irq, void *dev_id)
 616 {
 617         struct uart_port *port = dev_id;
 618         struct omap8250_priv *priv = port->private_data;
 619         struct uart_8250_port *up = up_to_u8250p(port);
 620         unsigned int iir;
 621         int ret;
 622
 623 #ifdef CONFIG_SERIAL_8250_DMA
 624         if (up->dma) {
 625                 ret = omap_8250_dma_handle_irq(port);
 626                 return IRQ_RETVAL(ret);
 627         }
 628 #endif
 629
 630         serial8250_rpm_get(up);
 631         iir = serial_port_in(port, UART_IIR);
 632         ret = serial8250_handle_irq(port, iir);
 633
 634         /*
 635          * On K3 SoCs, it is observed that RX TIMEOUT is signalled after
 636          * FIFO has been drained, in which case a dummy read of RX FIFO
 637          * is required to clear RX TIMEOUT condition.
 638          */
 639         if (priv->habit & UART_RX_TIMEOUT_QUIRK &&
 640             (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT &&
 641             serial_port_in(port, UART_OMAP_RX_LVL) == 0) {
 642                 serial_port_in(port, UART_RX);
 643         }
 644
 645         serial8250_rpm_put(up);
 646
 647         return IRQ_RETVAL(ret);
 648 }
 649
 650 static int omap_8250_startup(struct uart_port *port)
 651 {
 652         struct uart_8250_port *up = up_to_u8250p(port);
 653         struct omap8250_priv *priv = port->private_data;
 654         int ret;
 655
 656         if (priv->wakeirq) {
 657                 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
 658                 if (ret)
 659                         return ret;
 660         }
 661
 662         pm_runtime_get_sync(port->dev);
 663
 664         up->mcr = 0;
 665         serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 666
 667         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 668
 669         up->lsr_saved_flags = 0;
 670         up->msr_saved_flags = 0;
 671
 672         /* Disable DMA for console UART */
 673         if (uart_console(port))
 674                 up->dma = NULL;
 675
 676         if (up->dma) {
 677                 ret = serial8250_request_dma(up);
 678                 if (ret) {
 679                         dev_warn_ratelimited(port->dev,
 680                                              "failed to request DMA\n");
 681                         up->dma = NULL;
 682                 }
 683         }
 684
 685         ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
 686                           dev_name(port->dev), port);
 687         if (ret < 0)
 688                 goto err;
 689
 690         up->ier = UART_IER_RLSI | UART_IER_RDI;
 691         serial_out(up, UART_IER, up->ier);
 692
 693 #ifdef CONFIG_PM
 694         up->capabilities |= UART_CAP_RPM;
 695 #endif
 696
 697         /* Enable module level wake up */
 698         priv->wer = OMAP_UART_WER_MOD_WKUP;
 699         if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
 700                 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
 701         serial_out(up, UART_OMAP_WER, priv->wer);
 702
 703         if (up->dma && !(priv->habit & UART_HAS_EFR2))
 704                 up->dma->rx_dma(up);
 705
 706         pm_runtime_mark_last_busy(port->dev);
 707         pm_runtime_put_autosuspend(port->dev);
 708         return 0;
 709 err:
 710         pm_runtime_mark_last_busy(port->dev);
 711         pm_runtime_put_autosuspend(port->dev);
 712         dev_pm_clear_wake_irq(port->dev);
 713         return ret;
 714 }
 715
 716 static void omap_8250_shutdown(struct uart_port *port)
 717 {
 718         struct uart_8250_port *up = up_to_u8250p(port);
 719         struct omap8250_priv *priv = port->private_data;
 720
 721         flush_work(&priv->qos_work);
 722         if (up->dma)
 723                 omap_8250_rx_dma_flush(up);
 724
 725         pm_runtime_get_sync(port->dev);
 726
 727         serial_out(up, UART_OMAP_WER, 0);
 728         if (priv->habit & UART_HAS_EFR2)
 729                 serial_out(up, UART_OMAP_EFR2, 0x0);
 730
 731         up->ier = 0;
 732         serial_out(up, UART_IER, 0);
 733
 734         if (up->dma)
 735                 serial8250_release_dma(up);
 736
 737         /*
 738          * Disable break condition and FIFOs
 739          */
 740         if (up->lcr & UART_LCR_SBC)
 741                 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
 742         serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 743
 744         pm_runtime_mark_last_busy(port->dev);
 745         pm_runtime_put_autosuspend(port->dev);
 746         free_irq(port->irq, port);
 747         dev_pm_clear_wake_irq(port->dev);
 748 }
 749
 750 static void omap_8250_throttle(struct uart_port *port)
 751 {
 752         struct omap8250_priv *priv = port->private_data;
 753         unsigned long flags;
 754
 755         pm_runtime_get_sync(port->dev);
 756
 757         spin_lock_irqsave(&port->lock, flags);
 758         port->ops->stop_rx(port);
 759         priv->throttled = true;
 760         spin_unlock_irqrestore(&port->lock, flags);
 761
 762         pm_runtime_mark_last_busy(port->dev);
 763         pm_runtime_put_autosuspend(port->dev);
 764 }
 765
 766 static void omap_8250_unthrottle(struct uart_port *port)
 767 {
 768         struct omap8250_priv *priv = port->private_data;
 769         struct uart_8250_port *up = up_to_u8250p(port);
 770         unsigned long flags;
 771
 772         pm_runtime_get_sync(port->dev);
 773
 774         spin_lock_irqsave(&port->lock, flags);
 775         priv->throttled = false;
 776         if (up->dma)
 777                 up->dma->rx_dma(up);
 778         up->ier |= UART_IER_RLSI | UART_IER_RDI;
 779         port->read_status_mask |= UART_LSR_DR;
 780         serial_out(up, UART_IER, up->ier);
 781         spin_unlock_irqrestore(&port->lock, flags);
 782
 783         pm_runtime_mark_last_busy(port->dev);
 784         pm_runtime_put_autosuspend(port->dev);
 785 }
 786
 787 #ifdef CONFIG_SERIAL_8250_DMA
 788 static int omap_8250_rx_dma(struct uart_8250_port *p);
 789
 790 /* Must be called while priv->rx_dma_lock is held */
 791 static void __dma_rx_do_complete(struct uart_8250_port *p)
 792 {
 793         struct uart_8250_dma    *dma = p->dma;
 794         struct tty_port         *tty_port = &p->port.state->port;
 795         struct omap8250_priv    *priv = p->port.private_data;
 796         struct dma_chan         *rxchan = dma->rxchan;
 797         dma_cookie_t            cookie;
 798         struct dma_tx_state     state;
 799         int                     count;
 800         int                     ret;
 801         u32                     reg;
 802
 803         if (!dma->rx_running)
 804                 goto out;
 805
 806         cookie = dma->rx_cookie;
 807         dma->rx_running = 0;
 808
 809         /* Re-enable RX FIFO interrupt now that transfer is complete */
 810         if (priv->habit & UART_HAS_RHR_IT_DIS) {
 811                 reg = serial_in(p, UART_OMAP_IER2);
 812                 reg &= ~UART_OMAP_IER2_RHR_IT_DIS;
 813                 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS);
 814         }
 815
 816         dmaengine_tx_status(rxchan, cookie, &state);
 817
 818         count = dma->rx_size - state.residue + state.in_flight_bytes;
 819         if (count < dma->rx_size) {
 820                 dmaengine_terminate_async(rxchan);
 821
 822                 /*
 823                  * Poll for teardown to complete which guarantees in
 824                  * flight data is drained.
 825                  */
 826                 if (state.in_flight_bytes) {
 827                         int poll_count = 25;
 828
 829                         while (dmaengine_tx_status(rxchan, cookie, NULL) &&
 830                                poll_count--)
 831                                 cpu_relax();
 832
 833                         if (poll_count == -1)
 834                                 dev_err(p->port.dev, "teardown incomplete\n");
 835                 }
 836         }
 837         if (!count)
 838                 goto out;
 839         ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
 840
 841         p->port.icount.rx += ret;
 842         p->port.icount.buf_overrun += count - ret;
 843 out:
 844
 845         tty_flip_buffer_push(tty_port);
 846 }
 847
 848 static void __dma_rx_complete(void *param)
 849 {
 850         struct uart_8250_port *p = param;
 851         struct omap8250_priv *priv = p->port.private_data;
 852         struct uart_8250_dma *dma = p->dma;
 853         struct dma_tx_state     state;
 854         unsigned long flags;
 855
 856         spin_lock_irqsave(&p->port.lock, flags);
 857
 858         /*
 859          * If the tx status is not DMA_COMPLETE, then this is a delayed
 860          * completion callback. A previous RX timeout flush would have
 861          * already pushed the data, so exit.
 862          */
 863         if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
 864                         DMA_COMPLETE) {
 865                 spin_unlock_irqrestore(&p->port.lock, flags);
 866                 return;
 867         }
 868         __dma_rx_do_complete(p);
 869         if (!priv->throttled) {
 870                 p->ier |= UART_IER_RLSI | UART_IER_RDI;
 871                 serial_out(p, UART_IER, p->ier);
 872                 if (!(priv->habit & UART_HAS_EFR2))
 873                         omap_8250_rx_dma(p);
 874         }
 875
 876         spin_unlock_irqrestore(&p->port.lock, flags);
 877 }
 878
 879 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
 880 {
 881         struct omap8250_priv    *priv = p->port.private_data;
 882         struct uart_8250_dma    *dma = p->dma;
 883         struct dma_tx_state     state;
 884         unsigned long           flags;
 885         int ret;
 886
 887         spin_lock_irqsave(&priv->rx_dma_lock, flags);
 888
 889         if (!dma->rx_running) {
 890                 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
 891                 return;
 892         }
 893
 894         ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
 895         if (ret == DMA_IN_PROGRESS) {
 896                 ret = dmaengine_pause(dma->rxchan);
 897                 if (WARN_ON_ONCE(ret))
 898                         priv->rx_dma_broken = true;
 899         }
 900         __dma_rx_do_complete(p);
 901         spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
 902 }
 903
 904 static int omap_8250_rx_dma(struct uart_8250_port *p)
 905 {
 906         struct omap8250_priv            *priv = p->port.private_data;
 907         struct uart_8250_dma            *dma = p->dma;
 908         int                             err = 0;
 909         struct dma_async_tx_descriptor  *desc;
 910         unsigned long                   flags;
 911         u32                             reg;
 912
 913         if (priv->rx_dma_broken)
 914                 return -EINVAL;
 915
 916         spin_lock_irqsave(&priv->rx_dma_lock, flags);
 917
 918         if (dma->rx_running) {
 919                 enum dma_status state;
 920
 921                 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL);
 922                 if (state == DMA_COMPLETE) {
 923                         /*
 924                          * Disable RX interrupts to allow RX DMA completion
 925                          * callback to run.
 926                          */
 927                         p->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 928                         serial_out(p, UART_IER, p->ier);
 929                 }
 930                 goto out;
 931         }
 932
 933         desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
 934                                            dma->rx_size, DMA_DEV_TO_MEM,
 935                                            DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 936         if (!desc) {
 937                 err = -EBUSY;
 938                 goto out;
 939         }
 940
 941         dma->rx_running = 1;
 942         desc->callback = __dma_rx_complete;
 943         desc->callback_param = p;
 944
 945         dma->rx_cookie = dmaengine_submit(desc);
 946
 947         /*
 948          * Disable RX FIFO interrupt while RX DMA is enabled, else
 949          * spurious interrupt may be raised when data is in the RX FIFO
 950          * but is yet to be drained by DMA.
 951          */
 952         if (priv->habit & UART_HAS_RHR_IT_DIS) {
 953                 reg = serial_in(p, UART_OMAP_IER2);
 954                 reg |= UART_OMAP_IER2_RHR_IT_DIS;
 955                 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS);
 956         }
 957
 958         dma_async_issue_pending(dma->rxchan);
 959 out:
 960         spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
 961         return err;
 962 }
 963
 964 static int omap_8250_tx_dma(struct uart_8250_port *p);
 965
 966 static void omap_8250_dma_tx_complete(void *param)
 967 {
 968         struct uart_8250_port   *p = param;
 969         struct uart_8250_dma    *dma = p->dma;
 970         struct circ_buf         *xmit = &p->port.state->xmit;
 971         unsigned long           flags;
 972         bool                    en_thri = false;
 973         struct omap8250_priv    *priv = p->port.private_data;
 974
 975         dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
 976                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 977
 978         spin_lock_irqsave(&p->port.lock, flags);
 979
 980         dma->tx_running = 0;
 981
 982         xmit->tail += dma->tx_size;
 983         xmit->tail &= UART_XMIT_SIZE - 1;
 984         p->port.icount.tx += dma->tx_size;
 985
 986         if (priv->delayed_restore) {
 987                 priv->delayed_restore = 0;
 988                 omap8250_restore_regs(p);
 989         }
 990
 991         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 992                 uart_write_wakeup(&p->port);
 993
 994         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
 995                 int ret;
 996
 997                 ret = omap_8250_tx_dma(p);
 998                 if (ret)
 999                         en_thri = true;
1000         } else if (p->capabilities & UART_CAP_RPM) {
1001                 en_thri = true;
1002         }
1003
1004         if (en_thri) {
1005                 dma->tx_err = 1;
1006                 serial8250_set_THRI(p);
1007         }
1008
1009         spin_unlock_irqrestore(&p->port.lock, flags);
1010 }
1011
1012 static int omap_8250_tx_dma(struct uart_8250_port *p)
1013 {
1014         struct uart_8250_dma            *dma = p->dma;
1015         struct omap8250_priv            *priv = p->port.private_data;
1016         struct circ_buf                 *xmit = &p->port.state->xmit;
1017         struct dma_async_tx_descriptor  *desc;
1018         unsigned int    skip_byte = 0;
1019         int ret;
1020
1021         if (dma->tx_running)
1022                 return 0;
1023         if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
1024
1025                 /*
1026                  * Even if no data, we need to return an error for the two cases
1027                  * below so serial8250_tx_chars() is invoked and properly clears
1028                  * THRI and/or runtime suspend.
1029                  */
1030                 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
1031                         ret = -EBUSY;
1032                         goto err;
1033                 }
1034                 serial8250_clear_THRI(p);
1035                 return 0;
1036         }
1037
1038         dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1039         if (priv->habit & OMAP_DMA_TX_KICK) {
1040                 u8 tx_lvl;
1041
1042                 /*
1043                  * We need to put the first byte into the FIFO in order to start
1044                  * the DMA transfer. For transfers smaller than four bytes we
1045                  * don't bother doing DMA at all. It seem not matter if there
1046                  * are still bytes in the FIFO from the last transfer (in case
1047                  * we got here directly from omap_8250_dma_tx_complete()). Bytes
1048                  * leaving the FIFO seem not to trigger the DMA transfer. It is
1049                  * really the byte that we put into the FIFO.
1050                  * If the FIFO is already full then we most likely got here from
1051                  * omap_8250_dma_tx_complete(). And this means the DMA engine
1052                  * just completed its work. We don't have to wait the complete
1053                  * 86us at 115200,8n1 but around 60us (not to mention lower
1054                  * baudrates). So in that case we take the interrupt and try
1055                  * again with an empty FIFO.
1056                  */
1057                 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
1058                 if (tx_lvl == p->tx_loadsz) {
1059                         ret = -EBUSY;
1060                         goto err;
1061                 }
1062                 if (dma->tx_size < 4) {
1063                         ret = -EINVAL;
1064                         goto err;
1065                 }
1066                 skip_byte = 1;
1067         }
1068
1069         desc = dmaengine_prep_slave_single(dma->txchan,
1070                         dma->tx_addr + xmit->tail + skip_byte,
1071                         dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
1072                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1073         if (!desc) {
1074                 ret = -EBUSY;
1075                 goto err;
1076         }
1077
1078         dma->tx_running = 1;
1079
1080         desc->callback = omap_8250_dma_tx_complete;
1081         desc->callback_param = p;
1082
1083         dma->tx_cookie = dmaengine_submit(desc);
1084
1085         dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
1086                                    UART_XMIT_SIZE, DMA_TO_DEVICE);
1087
1088         dma_async_issue_pending(dma->txchan);
1089         if (dma->tx_err)
1090                 dma->tx_err = 0;
1091
1092         serial8250_clear_THRI(p);
1093         if (skip_byte)
1094                 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1095         return 0;
1096 err:
1097         dma->tx_err = 1;
1098         return ret;
1099 }
1100
1101 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1102 {
1103         switch (iir & 0x3f) {
1104         case UART_IIR_RLSI:
1105         case UART_IIR_RX_TIMEOUT:
1106         case UART_IIR_RDI:
1107                 omap_8250_rx_dma_flush(up);
1108                 return true;
1109         }
1110         return omap_8250_rx_dma(up);
1111 }
1112
1113 static unsigned char omap_8250_handle_rx_dma(struct uart_8250_port *up,
1114                                              u8 iir, unsigned char status)
1115 {
1116         if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1117             (iir & UART_IIR_RDI)) {
1118                 if (handle_rx_dma(up, iir)) {
1119                         status = serial8250_rx_chars(up, status);
1120                         omap_8250_rx_dma(up);
1121                 }
1122         }
1123
1124         return status;
1125 }
1126
1127 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir,
1128                                      unsigned char status)
1129 {
1130         /*
1131          * Queue a new transfer if FIFO has data.
1132          */
1133         if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1134             (up->ier & UART_IER_RDI)) {
1135                 omap_8250_rx_dma(up);
1136                 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE);
1137         } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) {
1138                 /*
1139                  * Disable RX timeout, read IIR to clear
1140                  * current timeout condition, clear EFR2 to
1141                  * periodic timeouts, re-enable interrupts.
1142                  */
1143                 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1144                 serial_out(up, UART_IER, up->ier);
1145                 omap_8250_rx_dma_flush(up);
1146                 serial_in(up, UART_IIR);
1147                 serial_out(up, UART_OMAP_EFR2, 0x0);
1148                 up->ier |= UART_IER_RLSI | UART_IER_RDI;
1149                 serial_out(up, UART_IER, up->ier);
1150         }
1151 }
1152
1153 /*
1154  * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1155  * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1156  * use the default routine in the non-DMA case and this one for with DMA.
1157  */
1158 static int omap_8250_dma_handle_irq(struct uart_port *port)
1159 {
1160         struct uart_8250_port *up = up_to_u8250p(port);
1161         struct omap8250_priv *priv = up->port.private_data;
1162         unsigned char status;
1163         u8 iir;
1164
1165         serial8250_rpm_get(up);
1166
1167         iir = serial_port_in(port, UART_IIR);
1168         if (iir & UART_IIR_NO_INT) {
1169                 serial8250_rpm_put(up);
1170                 return IRQ_HANDLED;
1171         }
1172
1173         spin_lock(&port->lock);
1174
1175         status = serial_port_in(port, UART_LSR);
1176
1177         if (priv->habit & UART_HAS_EFR2)
1178                 am654_8250_handle_rx_dma(up, iir, status);
1179         else
1180                 status = omap_8250_handle_rx_dma(up, iir, status);
1181
1182         serial8250_modem_status(up);
1183         if (status & UART_LSR_THRE && up->dma->tx_err) {
1184                 if (uart_tx_stopped(&up->port) ||
1185                     uart_circ_empty(&up->port.state->xmit)) {
1186                         up->dma->tx_err = 0;
1187                         serial8250_tx_chars(up);
1188                 } else  {
1189                         /*
1190                          * try again due to an earlier failer which
1191                          * might have been resolved by now.
1192                          */
1193                         if (omap_8250_tx_dma(up))
1194                                 serial8250_tx_chars(up);
1195                 }
1196         }
1197
1198         uart_unlock_and_check_sysrq(port);
1199
1200         serial8250_rpm_put(up);
1201         return 1;
1202 }
1203
1204 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1205 {
1206         return false;
1207 }
1208
1209 #else
1210
1211 static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1212 {
1213         return -EINVAL;
1214 }
1215 #endif
1216
1217 static int omap8250_no_handle_irq(struct uart_port *port)
1218 {
1219         /* IRQ has not been requested but handling irq? */
1220         WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1221         return 0;
1222 }
1223
1224 static struct omap8250_dma_params am654_dma = {
1225         .rx_size = SZ_2K,
1226         .rx_trigger = 1,
1227         .tx_trigger = TX_TRIGGER,
1228 };
1229
1230 static struct omap8250_dma_params am33xx_dma = {
1231         .rx_size = RX_TRIGGER,
1232         .rx_trigger = RX_TRIGGER,
1233         .tx_trigger = TX_TRIGGER,
1234 };
1235
1236 static struct omap8250_platdata am654_platdata = {
1237         .dma_params     = &am654_dma,
1238         .habit          = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS |
1239                           UART_RX_TIMEOUT_QUIRK,
1240 };
1241
1242 static struct omap8250_platdata am33xx_platdata = {
1243         .dma_params     = &am33xx_dma,
1244         .habit          = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE,
1245 };
1246
1247 static struct omap8250_platdata omap4_platdata = {
1248         .dma_params     = &am33xx_dma,
1249         .habit          = UART_ERRATA_CLOCK_DISABLE,
1250 };
1251
1252 static const struct of_device_id omap8250_dt_ids[] = {
1253         { .compatible = "ti,am654-uart", .data = &am654_platdata, },
1254         { .compatible = "ti,omap2-uart" },
1255         { .compatible = "ti,omap3-uart" },
1256         { .compatible = "ti,omap4-uart", .data = &omap4_platdata, },
1257         { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, },
1258         { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, },
1259         { .compatible = "ti,dra742-uart", .data = &omap4_platdata, },
1260         {},
1261 };
1262 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1263
1264 static int omap8250_probe(struct platform_device *pdev)
1265 {
1266         struct device_node *np = pdev->dev.of_node;
1267         struct omap8250_priv *priv;
1268         const struct omap8250_platdata *pdata;
1269         struct uart_8250_port up;
1270         struct resource *regs;
1271         void __iomem *membase;
1272         int irq, ret;
1273
1274         irq = platform_get_irq(pdev, 0);
1275         if (irq < 0)
1276                 return irq;
1277
1278         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1279         if (!regs) {
1280                 dev_err(&pdev->dev, "missing registers\n");
1281                 return -EINVAL;
1282         }
1283
1284         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1285         if (!priv)
1286                 return -ENOMEM;
1287
1288         membase = devm_ioremap(&pdev->dev, regs->start,
1289                                        resource_size(regs));
1290         if (!membase)
1291                 return -ENODEV;
1292
1293         memset(&up, 0, sizeof(up));
1294         up.port.dev = &pdev->dev;
1295         up.port.mapbase = regs->start;
1296         up.port.membase = membase;
1297         up.port.irq = irq;
1298         /*
1299          * It claims to be 16C750 compatible however it is a little different.
1300          * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1301          * have) is enabled via EFR instead of MCR. The type is set here 8250
1302          * just to get things going. UNKNOWN does not work for a few reasons and
1303          * we don't need our own type since we don't use 8250's set_termios()
1304          * or pm callback.
1305          */
1306         up.port.type = PORT_8250;
1307         up.port.iotype = UPIO_MEM;
1308         up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1309                 UPF_HARD_FLOW;
1310         up.port.private_data = priv;
1311
1312         up.port.regshift = 2;
1313         up.port.fifosize = 64;
1314         up.tx_loadsz = 64;
1315         up.capabilities = UART_CAP_FIFO;
1316 #ifdef CONFIG_PM
1317         /*
1318          * Runtime PM is mostly transparent. However to do it right we need to a
1319          * TX empty interrupt before we can put the device to auto idle. So if
1320          * PM is not enabled we don't add that flag and can spare that one extra
1321          * interrupt in the TX path.
1322          */
1323         up.capabilities |= UART_CAP_RPM;
1324 #endif
1325         up.port.set_termios = omap_8250_set_termios;
1326         up.port.set_mctrl = omap8250_set_mctrl;
1327         up.port.pm = omap_8250_pm;
1328         up.port.startup = omap_8250_startup;
1329         up.port.shutdown = omap_8250_shutdown;
1330         up.port.throttle = omap_8250_throttle;
1331         up.port.unthrottle = omap_8250_unthrottle;
1332         up.port.rs485_config = serial8250_em485_config;
1333         up.rs485_start_tx = serial8250_em485_start_tx;
1334         up.rs485_stop_tx = serial8250_em485_stop_tx;
1335         up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
1336
1337         ret = of_alias_get_id(np, "serial");
1338         if (ret < 0) {
1339                 dev_err(&pdev->dev, "failed to get alias\n");
1340                 return ret;
1341         }
1342         up.port.line = ret;
1343
1344         if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) {
1345                 struct clk *clk;
1346
1347                 clk = devm_clk_get(&pdev->dev, NULL);
1348                 if (IS_ERR(clk)) {
1349                         if (PTR_ERR(clk) == -EPROBE_DEFER)
1350                                 return -EPROBE_DEFER;
1351                 } else {
1352                         up.port.uartclk = clk_get_rate(clk);
1353                 }
1354         }
1355
1356         priv->wakeirq = irq_of_parse_and_map(np, 1);
1357
1358         pdata = of_device_get_match_data(&pdev->dev);
1359         if (pdata)
1360                 priv->habit |= pdata->habit;
1361
1362         if (!up.port.uartclk) {
1363                 up.port.uartclk = DEFAULT_CLK_SPEED;
1364                 dev_warn(&pdev->dev,
1365                          "No clock speed specified: using default: %d\n",
1366                          DEFAULT_CLK_SPEED);
1367         }
1368
1369         priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1370         priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1371         cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency);
1372         INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1373
1374         spin_lock_init(&priv->rx_dma_lock);
1375
1376         device_init_wakeup(&pdev->dev, true);
1377         pm_runtime_enable(&pdev->dev);
1378         pm_runtime_use_autosuspend(&pdev->dev);
1379
1380         /*
1381          * Disable runtime PM until autosuspend delay unless specifically
1382          * enabled by the user via sysfs. This is the historic way to
1383          * prevent an unsafe default policy with lossy characters on wake-up.
1384          * For serdev devices this is not needed, the policy can be managed by
1385          * the serdev driver.
1386          */
1387         if (!of_get_available_child_count(pdev->dev.of_node))
1388                 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1389
1390         pm_runtime_irq_safe(&pdev->dev);
1391
1392         pm_runtime_get_sync(&pdev->dev);
1393
1394         omap_serial_fill_features_erratas(&up, priv);
1395         up.port.handle_irq = omap8250_no_handle_irq;
1396         priv->rx_trigger = RX_TRIGGER;
1397         priv->tx_trigger = TX_TRIGGER;
1398 #ifdef CONFIG_SERIAL_8250_DMA
1399         /*
1400          * Oh DMA support. If there are no DMA properties in the DT then
1401          * we will fall back to a generic DMA channel which does not
1402          * really work here. To ensure that we do not get a generic DMA
1403          * channel assigned, we have the the_no_dma_filter_fn() here.
1404          * To avoid "failed to request DMA" messages we check for DMA
1405          * properties in DT.
1406          */
1407         ret = of_property_count_strings(np, "dma-names");
1408         if (ret == 2) {
1409                 struct omap8250_dma_params *dma_params = NULL;
1410
1411                 up.dma = &priv->omap8250_dma;
1412                 up.dma->fn = the_no_dma_filter_fn;
1413                 up.dma->tx_dma = omap_8250_tx_dma;
1414                 up.dma->rx_dma = omap_8250_rx_dma;
1415                 if (pdata)
1416                         dma_params = pdata->dma_params;
1417
1418                 if (dma_params) {
1419                         up.dma->rx_size = dma_params->rx_size;
1420                         up.dma->rxconf.src_maxburst = dma_params->rx_trigger;
1421                         up.dma->txconf.dst_maxburst = dma_params->tx_trigger;
1422                         priv->rx_trigger = dma_params->rx_trigger;
1423                         priv->tx_trigger = dma_params->tx_trigger;
1424                 } else {
1425                         up.dma->rx_size = RX_TRIGGER;
1426                         up.dma->rxconf.src_maxburst = RX_TRIGGER;
1427                         up.dma->txconf.dst_maxburst = TX_TRIGGER;
1428                 }
1429         }
1430 #endif
1431         ret = serial8250_register_8250_port(&up);
1432         if (ret < 0) {
1433                 dev_err(&pdev->dev, "unable to register 8250 port\n");
1434                 goto err;
1435         }
1436         priv->line = ret;
1437         platform_set_drvdata(pdev, priv);
1438         pm_runtime_mark_last_busy(&pdev->dev);
1439         pm_runtime_put_autosuspend(&pdev->dev);
1440         return 0;
1441 err:
1442         pm_runtime_dont_use_autosuspend(&pdev->dev);
1443         pm_runtime_put_sync(&pdev->dev);
1444         pm_runtime_disable(&pdev->dev);
1445         return ret;
1446 }
1447
1448 static int omap8250_remove(struct platform_device *pdev)
1449 {
1450         struct omap8250_priv *priv = platform_get_drvdata(pdev);
1451
1452         pm_runtime_dont_use_autosuspend(&pdev->dev);
1453         pm_runtime_put_sync(&pdev->dev);
1454         pm_runtime_disable(&pdev->dev);
1455         serial8250_unregister_port(priv->line);
1456         cpu_latency_qos_remove_request(&priv->pm_qos_request);
1457         device_init_wakeup(&pdev->dev, false);
1458         return 0;
1459 }
1460
1461 #ifdef CONFIG_PM_SLEEP
1462 static int omap8250_prepare(struct device *dev)
1463 {
1464         struct omap8250_priv *priv = dev_get_drvdata(dev);
1465
1466         if (!priv)
1467                 return 0;
1468         priv->is_suspending = true;
1469         return 0;
1470 }
1471
1472 static void omap8250_complete(struct device *dev)
1473 {
1474         struct omap8250_priv *priv = dev_get_drvdata(dev);
1475
1476         if (!priv)
1477                 return;
1478         priv->is_suspending = false;
1479 }
1480
1481 static int omap8250_suspend(struct device *dev)
1482 {
1483         struct omap8250_priv *priv = dev_get_drvdata(dev);
1484         struct uart_8250_port *up = serial8250_get_port(priv->line);
1485
1486         serial8250_suspend_port(priv->line);
1487
1488         pm_runtime_get_sync(dev);
1489         if (!device_may_wakeup(dev))
1490                 priv->wer = 0;
1491         serial_out(up, UART_OMAP_WER, priv->wer);
1492         pm_runtime_mark_last_busy(dev);
1493         pm_runtime_put_autosuspend(dev);
1494
1495         flush_work(&priv->qos_work);
1496         return 0;
1497 }
1498
1499 static int omap8250_resume(struct device *dev)
1500 {
1501         struct omap8250_priv *priv = dev_get_drvdata(dev);
1502
1503         serial8250_resume_port(priv->line);
1504         return 0;
1505 }
1506 #else
1507 #define omap8250_prepare NULL
1508 #define omap8250_complete NULL
1509 #endif
1510
1511 #ifdef CONFIG_PM
1512 static int omap8250_lost_context(struct uart_8250_port *up)
1513 {
1514         u32 val;
1515
1516         val = serial_in(up, UART_OMAP_SCR);
1517         /*
1518          * If we lose context, then SCR is set to its reset value of zero.
1519          * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1520          * among other bits, to never set the register back to zero again.
1521          */
1522         if (!val)
1523                 return 1;
1524         return 0;
1525 }
1526
1527 /* TODO: in future, this should happen via API in drivers/reset/ */
1528 static int omap8250_soft_reset(struct device *dev)
1529 {
1530         struct omap8250_priv *priv = dev_get_drvdata(dev);
1531         struct uart_8250_port *up = serial8250_get_port(priv->line);
1532         int timeout = 100;
1533         int sysc;
1534         int syss;
1535
1536         /*
1537          * At least on omap4, unused uarts may not idle after reset without
1538          * a basic scr dma configuration even with no dma in use. The
1539          * module clkctrl status bits will be 1 instead of 3 blocking idle
1540          * for the whole clockdomain. The softreset below will clear scr,
1541          * and we restore it on resume so this is safe to do on all SoCs
1542          * needing omap8250_soft_reset() quirk. Do it in two writes as
1543          * recommended in the comment for omap8250_update_scr().
1544          */
1545         serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1);
1546         serial_out(up, UART_OMAP_SCR,
1547                    OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL);
1548
1549         sysc = serial_in(up, UART_OMAP_SYSC);
1550
1551         /* softreset the UART */
1552         sysc |= OMAP_UART_SYSC_SOFTRESET;
1553         serial_out(up, UART_OMAP_SYSC, sysc);
1554
1555         /* By experiments, 1us enough for reset complete on AM335x */
1556         do {
1557                 udelay(1);
1558                 syss = serial_in(up, UART_OMAP_SYSS);
1559         } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1560
1561         if (!timeout) {
1562                 dev_err(dev, "timed out waiting for reset done\n");
1563                 return -ETIMEDOUT;
1564         }
1565
1566         return 0;
1567 }
1568
1569 static int omap8250_runtime_suspend(struct device *dev)
1570 {
1571         struct omap8250_priv *priv = dev_get_drvdata(dev);
1572         struct uart_8250_port *up;
1573
1574         /* In case runtime-pm tries this before we are setup */
1575         if (!priv)
1576                 return 0;
1577
1578         up = serial8250_get_port(priv->line);
1579         /*
1580          * When using 'no_console_suspend', the console UART must not be
1581          * suspended. Since driver suspend is managed by runtime suspend,
1582          * preventing runtime suspend (by returning error) will keep device
1583          * active during suspend.
1584          */
1585         if (priv->is_suspending && !console_suspend_enabled) {
1586                 if (uart_console(&up->port))
1587                         return -EBUSY;
1588         }
1589
1590         if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1591                 int ret;
1592
1593                 ret = omap8250_soft_reset(dev);
1594                 if (ret)
1595                         return ret;
1596
1597                 /* Restore to UART mode after reset (for wakeup) */
1598                 omap8250_update_mdr1(up, priv);
1599                 /* Restore wakeup enable register */
1600                 serial_out(up, UART_OMAP_WER, priv->wer);
1601         }
1602
1603         if (up->dma && up->dma->rxchan)
1604                 omap_8250_rx_dma_flush(up);
1605
1606         priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1607         schedule_work(&priv->qos_work);
1608
1609         return 0;
1610 }
1611
1612 static int omap8250_runtime_resume(struct device *dev)
1613 {
1614         struct omap8250_priv *priv = dev_get_drvdata(dev);
1615         struct uart_8250_port *up;
1616
1617         /* In case runtime-pm tries this before we are setup */
1618         if (!priv)
1619                 return 0;
1620
1621         up = serial8250_get_port(priv->line);
1622
1623         if (omap8250_lost_context(up))
1624                 omap8250_restore_regs(up);
1625
1626         if (up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2))
1627                 omap_8250_rx_dma(up);
1628
1629         priv->latency = priv->calc_latency;
1630         schedule_work(&priv->qos_work);
1631         return 0;
1632 }
1633 #endif
1634
1635 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1636 static int __init omap8250_console_fixup(void)
1637 {
1638         char *omap_str;
1639         char *options;
1640         u8 idx;
1641
1642         if (strstr(boot_command_line, "console=ttyS"))
1643                 /* user set a ttyS based name for the console */
1644                 return 0;
1645
1646         omap_str = strstr(boot_command_line, "console=ttyO");
1647         if (!omap_str)
1648                 /* user did not set ttyO based console, so we don't care */
1649                 return 0;
1650
1651         omap_str += 12;
1652         if ('0' <= *omap_str && *omap_str <= '9')
1653                 idx = *omap_str - '0';
1654         else
1655                 return 0;
1656
1657         omap_str++;
1658         if (omap_str[0] == ',') {
1659                 omap_str++;
1660                 options = omap_str;
1661         } else {
1662                 options = NULL;
1663         }
1664
1665         add_preferred_console("ttyS", idx, options);
1666         pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1667                idx, idx);
1668         pr_err("This ensures that you still see kernel messages. Please\n");
1669         pr_err("update your kernel commandline.\n");
1670         return 0;
1671 }
1672 console_initcall(omap8250_console_fixup);
1673 #endif
1674
1675 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1676         SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1677         SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1678                            omap8250_runtime_resume, NULL)
1679         .prepare        = omap8250_prepare,
1680         .complete       = omap8250_complete,
1681 };
1682
1683 static struct platform_driver omap8250_platform_driver = {
1684         .driver = {
1685                 .name           = "omap8250",
1686                 .pm             = &omap8250_dev_pm_ops,
1687                 .of_match_table = omap8250_dt_ids,
1688         },
1689         .probe                  = omap8250_probe,
1690         .remove                 = omap8250_remove,
1691 };
1692 module_platform_driver(omap8250_platform_driver);
1693
1694 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1695 MODULE_DESCRIPTION("OMAP 8250 Driver");
1696 MODULE_LICENSE("GPL v2");