1 // SPDX-License-Identifier: GPL-2.0
3 * Probe for F81216A LPC to 4 UART
5 * Copyright (C) 2014-2016 Ricardo Ribalda, Qtechnology A/S
7 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/serial_core.h>
12 #include <linux/irq.h>
20 #define CHIP_ID_F81865 0x0407
21 #define CHIP_ID_F81866 0x1010
22 #define CHIP_ID_F81966 0x0215
23 #define CHIP_ID_F81216AD 0x1602
24 #define CHIP_ID_F81216H 0x0501
25 #define CHIP_ID_F81216 0x0802
26 #define VENDOR_ID1 0x23
27 #define VENDOR_ID1_VAL 0x19
28 #define VENDOR_ID2 0x24
29 #define VENDOR_ID2_VAL 0x34
34 #define FINTEK_IRQ_MODE 0x70
35 #define IRQ_SHARE BIT(4)
36 #define IRQ_MODE_MASK (BIT(6) | BIT(5))
37 #define IRQ_LEVEL_LOW 0
38 #define IRQ_EDGE_HIGH BIT(5)
41 * F81216H clock source register, the value and mask is the same with F81866,
44 * Clock speeds for UART (register F0h)
51 #define RTS_INVERT BIT(5)
52 #define RS485_URA BIT(4)
53 #define RXW4C_IRA BIT(3)
54 #define TXW4C_IRA BIT(2)
56 #define FIFO_CTRL 0xF6
57 #define FIFO_MODE_MASK (BIT(1) | BIT(0))
58 #define FIFO_MODE_128 (BIT(1) | BIT(0))
59 #define RXFTHR_MODE_MASK (BIT(5) | BIT(4))
60 #define RXFTHR_MODE_4X BIT(5)
62 #define F81216_LDN_LOW 0x0
63 #define F81216_LDN_HIGH 0x4
66 * F81866/966 registers
68 * The IRQ setting mode of F81866/966 is not the same with F81216 series.
69 * Level/Low: IRQ_MODE0:0, IRQ_MODE1:0
70 * Edge/High: IRQ_MODE0:1, IRQ_MODE1:0
72 * Clock speeds for UART (register F2h)
78 #define F81866_IRQ_MODE 0xf0
79 #define F81866_IRQ_SHARE BIT(0)
80 #define F81866_IRQ_MODE0 BIT(1)
82 #define F81866_FIFO_CTRL FIFO_CTRL
83 #define F81866_IRQ_MODE1 BIT(3)
85 #define F81866_LDN_LOW 0x10
86 #define F81866_LDN_HIGH 0x16
88 #define F81866_UART_CLK 0xF2
89 #define F81866_UART_CLK_MASK (BIT(1) | BIT(0))
90 #define F81866_UART_CLK_1_8432MHZ 0
91 #define F81866_UART_CLK_14_769MHZ (BIT(1) | BIT(0))
92 #define F81866_UART_CLK_18_432MHZ BIT(0)
93 #define F81866_UART_CLK_24MHZ BIT(1)
102 static u8 sio_read_reg(struct fintek_8250 *pdata, u8 reg)
104 outb(reg, pdata->base_port + ADDR_PORT);
105 return inb(pdata->base_port + DATA_PORT);
108 static void sio_write_reg(struct fintek_8250 *pdata, u8 reg, u8 data)
110 outb(reg, pdata->base_port + ADDR_PORT);
111 outb(data, pdata->base_port + DATA_PORT);
114 static void sio_write_mask_reg(struct fintek_8250 *pdata, u8 reg, u8 mask,
119 tmp = (sio_read_reg(pdata, reg) & ~mask) | (mask & data);
120 sio_write_reg(pdata, reg, tmp);
123 static int fintek_8250_enter_key(u16 base_port, u8 key)
125 if (!request_muxed_region(base_port, 2, "8250_fintek"))
128 /* Force to deactive all SuperIO in this base_port */
129 outb(EXIT_KEY, base_port + ADDR_PORT);
131 outb(key, base_port + ADDR_PORT);
132 outb(key, base_port + ADDR_PORT);
136 static void fintek_8250_exit_key(u16 base_port)
139 outb(EXIT_KEY, base_port + ADDR_PORT);
140 release_region(base_port + ADDR_PORT, 2);
143 static int fintek_8250_check_id(struct fintek_8250 *pdata)
147 if (sio_read_reg(pdata, VENDOR_ID1) != VENDOR_ID1_VAL)
150 if (sio_read_reg(pdata, VENDOR_ID2) != VENDOR_ID2_VAL)
153 chip = sio_read_reg(pdata, CHIP_ID1);
154 chip |= sio_read_reg(pdata, CHIP_ID2) << 8;
160 case CHIP_ID_F81216AD:
161 case CHIP_ID_F81216H:
172 static int fintek_8250_get_ldn_range(struct fintek_8250 *pdata, int *min,
175 switch (pdata->pid) {
179 *min = F81866_LDN_LOW;
180 *max = F81866_LDN_HIGH;
183 case CHIP_ID_F81216AD:
184 case CHIP_ID_F81216H:
186 *min = F81216_LDN_LOW;
187 *max = F81216_LDN_HIGH;
194 static int fintek_8250_rs485_config(struct uart_port *port,
195 struct serial_rs485 *rs485)
198 struct fintek_8250 *pdata = port->private_data;
203 /* Hardware do not support same RTS level on send and receive */
204 if (!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
205 !(rs485->flags & SER_RS485_RTS_AFTER_SEND))
208 if (rs485->flags & SER_RS485_ENABLED) {
209 memset(rs485->padding, 0, sizeof(rs485->padding));
212 memset(rs485, 0, sizeof(*rs485));
215 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND |
216 SER_RS485_RTS_AFTER_SEND;
218 /* Only the first port supports delays */
220 rs485->delay_rts_before_send = 0;
221 rs485->delay_rts_after_send = 0;
224 if (rs485->delay_rts_before_send) {
225 rs485->delay_rts_before_send = 1;
229 if (rs485->delay_rts_after_send) {
230 rs485->delay_rts_after_send = 1;
234 if (rs485->flags & SER_RS485_RTS_ON_SEND)
235 config |= RTS_INVERT;
237 if (fintek_8250_enter_key(pdata->base_port, pdata->key))
240 sio_write_reg(pdata, LDN, pdata->index);
241 sio_write_reg(pdata, RS485, config);
242 fintek_8250_exit_key(pdata->base_port);
244 port->rs485 = *rs485;
249 static void fintek_8250_set_irq_mode(struct fintek_8250 *pdata, bool is_level)
251 sio_write_reg(pdata, LDN, pdata->index);
253 switch (pdata->pid) {
256 sio_write_mask_reg(pdata, F81866_FIFO_CTRL, F81866_IRQ_MODE1,
260 sio_write_mask_reg(pdata, F81866_IRQ_MODE, F81866_IRQ_SHARE,
262 sio_write_mask_reg(pdata, F81866_IRQ_MODE, F81866_IRQ_MODE0,
263 is_level ? 0 : F81866_IRQ_MODE0);
266 case CHIP_ID_F81216AD:
267 case CHIP_ID_F81216H:
269 sio_write_mask_reg(pdata, FINTEK_IRQ_MODE, IRQ_SHARE,
271 sio_write_mask_reg(pdata, FINTEK_IRQ_MODE, IRQ_MODE_MASK,
272 is_level ? IRQ_LEVEL_LOW : IRQ_EDGE_HIGH);
277 static void fintek_8250_set_max_fifo(struct fintek_8250 *pdata)
279 switch (pdata->pid) {
280 case CHIP_ID_F81216H: /* 128Bytes FIFO */
283 sio_write_mask_reg(pdata, FIFO_CTRL,
284 FIFO_MODE_MASK | RXFTHR_MODE_MASK,
285 FIFO_MODE_128 | RXFTHR_MODE_4X);
288 default: /* Default 16Bytes FIFO */
293 static void fintek_8250_goto_highspeed(struct uart_8250_port *uart,
294 struct fintek_8250 *pdata)
296 sio_write_reg(pdata, LDN, pdata->index);
298 switch (pdata->pid) {
300 case CHIP_ID_F81866: /* set uart clock for high speed serial mode */
301 sio_write_mask_reg(pdata, F81866_UART_CLK,
302 F81866_UART_CLK_MASK,
303 F81866_UART_CLK_14_769MHZ);
305 uart->port.uartclk = 921600 * 16;
307 default: /* leave clock speed untouched */
312 static void fintek_8250_set_termios(struct uart_port *port,
313 struct ktermios *termios,
314 struct ktermios *old)
316 struct fintek_8250 *pdata = port->private_data;
317 unsigned int baud = tty_termios_baud_rate(termios);
320 static u32 baudrate_table[] = {115200, 921600, 1152000, 1500000};
321 static u8 clock_table[] = { F81866_UART_CLK_1_8432MHZ,
322 F81866_UART_CLK_14_769MHZ, F81866_UART_CLK_18_432MHZ,
323 F81866_UART_CLK_24MHZ };
326 * We'll use serial8250_do_set_termios() for baud = 0, otherwise It'll
327 * crash on baudrate_table[i] % baud with "division by zero".
332 switch (pdata->pid) {
333 case CHIP_ID_F81216H:
338 reg = F81866_UART_CLK;
341 /* Don't change clocksource with unknown PID */
343 "%s: pid: %x Not support. use default set_termios.\n",
344 __func__, pdata->pid);
348 for (i = 0; i < ARRAY_SIZE(baudrate_table); ++i) {
349 if (baud > baudrate_table[i] || baudrate_table[i] % baud != 0)
352 if (port->uartclk == baudrate_table[i] * 16)
355 if (fintek_8250_enter_key(pdata->base_port, pdata->key))
358 port->uartclk = baudrate_table[i] * 16;
360 sio_write_reg(pdata, LDN, pdata->index);
361 sio_write_mask_reg(pdata, reg, F81866_UART_CLK_MASK,
364 fintek_8250_exit_key(pdata->base_port);
368 if (i == ARRAY_SIZE(baudrate_table)) {
369 baud = tty_termios_baud_rate(old);
370 tty_termios_encode_baud_rate(termios, baud, baud);
374 serial8250_do_set_termios(port, termios, old);
377 static void fintek_8250_set_termios_handler(struct uart_8250_port *uart)
379 struct fintek_8250 *pdata = uart->port.private_data;
381 switch (pdata->pid) {
382 case CHIP_ID_F81216H:
385 uart->port.set_termios = fintek_8250_set_termios;
393 static int probe_setup_port(struct fintek_8250 *pdata,
394 struct uart_8250_port *uart)
396 static const u16 addr[] = {0x4e, 0x2e};
397 static const u8 keys[] = {0x77, 0xa0, 0x87, 0x67};
398 struct irq_data *irq_data;
399 bool level_mode = false;
400 int i, j, k, min, max;
402 for (i = 0; i < ARRAY_SIZE(addr); i++) {
403 for (j = 0; j < ARRAY_SIZE(keys); j++) {
404 pdata->base_port = addr[i];
405 pdata->key = keys[j];
407 if (fintek_8250_enter_key(addr[i], keys[j]))
409 if (fintek_8250_check_id(pdata) ||
410 fintek_8250_get_ldn_range(pdata, &min, &max)) {
411 fintek_8250_exit_key(addr[i]);
415 for (k = min; k < max; k++) {
418 sio_write_reg(pdata, LDN, k);
419 aux = sio_read_reg(pdata, IO_ADDR1);
420 aux |= sio_read_reg(pdata, IO_ADDR2) << 8;
421 if (aux != uart->port.iobase)
426 irq_data = irq_get_irq_data(uart->port.irq);
429 irqd_is_level_type(irq_data);
431 fintek_8250_set_irq_mode(pdata, level_mode);
432 fintek_8250_set_max_fifo(pdata);
433 fintek_8250_goto_highspeed(uart, pdata);
435 fintek_8250_exit_key(addr[i]);
440 fintek_8250_exit_key(addr[i]);
447 static void fintek_8250_set_rs485_handler(struct uart_8250_port *uart)
449 struct fintek_8250 *pdata = uart->port.private_data;
451 switch (pdata->pid) {
452 case CHIP_ID_F81216AD:
453 case CHIP_ID_F81216H:
457 uart->port.rs485_config = fintek_8250_rs485_config;
460 default: /* No RS485 Auto direction functional */
465 int fintek_8250_probe(struct uart_8250_port *uart)
467 struct fintek_8250 *pdata;
468 struct fintek_8250 probe_data;
470 if (probe_setup_port(&probe_data, uart))
473 pdata = devm_kzalloc(uart->port.dev, sizeof(*pdata), GFP_KERNEL);
477 memcpy(pdata, &probe_data, sizeof(probe_data));
478 uart->port.private_data = pdata;
479 fintek_8250_set_rs485_handler(uart);
480 fintek_8250_set_termios_handler(uart);