1 // SPDX-License-Identifier: GPL-2.0
3 * Probe module for 8250/16550-type Exar chips PCI serial ports.
5 * Based on drivers/tty/serial/8250/8250_pci.c,
7 * Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved.
9 #include <linux/acpi.h>
10 #include <linux/dmi.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/property.h>
16 #include <linux/serial_core.h>
17 #include <linux/serial_reg.h>
18 #include <linux/slab.h>
19 #include <linux/string.h>
20 #include <linux/tty.h>
21 #include <linux/8250_pci.h>
22 #include <linux/delay.h>
24 #include <asm/byteorder.h>
28 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
29 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
30 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
31 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
32 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
33 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
34 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
35 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
36 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
38 #define UART_EXAR_INT0 0x80
39 #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */
40 #define UART_EXAR_SLEEP 0x8b /* Sleep mode */
41 #define UART_EXAR_DVID 0x8d /* Device identification */
43 #define UART_EXAR_FCTR 0x08 /* Feature Control Register */
44 #define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */
45 #define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */
46 #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */
47 #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */
48 #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */
49 #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
51 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
52 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
54 #define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */
55 #define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */
56 #define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */
57 #define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */
58 #define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */
59 #define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */
60 #define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */
61 #define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */
62 #define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */
63 #define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */
64 #define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */
65 #define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */
67 #define UART_EXAR_RS485_DLY(x) ((x) << 4)
70 * IOT2040 MPIO wiring semantics:
88 /* IOT2040 MPIOs 0..7 */
89 #define IOT2040_UART_MODE_RS232 0x01
90 #define IOT2040_UART_MODE_RS485 0x02
91 #define IOT2040_UART_MODE_RS422 0x03
92 #define IOT2040_UART_TERMINATE_BUS 0x04
94 #define IOT2040_UART1_MASK 0x0f
95 #define IOT2040_UART2_SHIFT 4
97 #define IOT2040_UARTS_DEFAULT_MODE 0x11 /* both RS232 */
98 #define IOT2040_UARTS_GPIO_LO_MODE 0x88 /* reserved pins as input */
100 /* IOT2040 MPIOs 8..15 */
101 #define IOT2040_UARTS_ENABLE 0x03
102 #define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */
106 struct exar8250_platform {
107 int (*rs485_config)(struct uart_port *, struct serial_rs485 *);
108 int (*register_gpio)(struct pci_dev *, struct uart_8250_port *);
112 * struct exar8250_board - board information
113 * @num_ports: number of serial ports
114 * @reg_shift: describes UART register mapping in PCI memory
115 * @setup: quirk run at ->probe() stage
116 * @exit: quirk run at ->remove() stage
118 struct exar8250_board {
119 unsigned int num_ports;
120 unsigned int reg_shift;
121 int (*setup)(struct exar8250 *, struct pci_dev *,
122 struct uart_8250_port *, int);
123 void (*exit)(struct pci_dev *pcidev);
128 struct exar8250_board *board;
133 static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old)
136 * Exar UARTs have a SLEEP register that enables or disables each UART
137 * to enter sleep mode separately. On the XR17V35x the register
138 * is accessible to each UART at the UART_EXAR_SLEEP offset, but
139 * the UART channel may only write to the corresponding bit.
141 serial_port_out(port, UART_EXAR_SLEEP, state ? 0xff : 0);
145 * XR17V35x UARTs have an extra fractional divisor register (DLD)
146 * Calculate divisor with extra 4-bit fractional portion
148 static unsigned int xr17v35x_get_divisor(struct uart_port *p, unsigned int baud,
151 unsigned int quot_16;
153 quot_16 = DIV_ROUND_CLOSEST(p->uartclk, baud);
154 *frac = quot_16 & 0x0f;
159 static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud,
160 unsigned int quot, unsigned int quot_frac)
162 serial8250_do_set_divisor(p, baud, quot, quot_frac);
164 /* Preserve bits not related to baudrate; DLD[7:4]. */
165 quot_frac |= serial_port_in(p, 0x2) & 0xf0;
166 serial_port_out(p, 0x2, quot_frac);
169 static void exar_shutdown(struct uart_port *port)
172 bool tx_complete = 0;
173 struct uart_8250_port *up = up_to_u8250p(port);
174 struct circ_buf *xmit = &port->state->xmit;
178 lsr = serial_in(up, UART_LSR);
179 if (lsr & (UART_LSR_TEMT | UART_LSR_THRE))
184 } while (!uart_circ_empty(xmit) && !tx_complete && i++ < 1000);
186 serial8250_do_shutdown(port);
189 static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
190 int idx, unsigned int offset,
191 struct uart_8250_port *port)
193 const struct exar8250_board *board = priv->board;
194 unsigned int bar = 0;
195 unsigned char status;
197 port->port.iotype = UPIO_MEM;
198 port->port.mapbase = pci_resource_start(pcidev, bar) + offset;
199 port->port.membase = priv->virt + offset;
200 port->port.regshift = board->reg_shift;
203 * XR17V35x UARTs have an extra divisor register, DLD that gets enabled
204 * with when DLAB is set which will cause the device to incorrectly match
205 * and assign port type to PORT_16650. The EFR for this UART is found
206 * at offset 0x09. Instead check the Deice ID (DVID) register
207 * for a 2, 4 or 8 port UART.
209 status = readb(port->port.membase + UART_EXAR_DVID);
210 if (status == 0x82 || status == 0x84 || status == 0x88) {
211 port->port.type = PORT_XR17V35X;
213 port->port.get_divisor = xr17v35x_get_divisor;
214 port->port.set_divisor = xr17v35x_set_divisor;
216 port->port.type = PORT_XR17D15X;
219 port->port.pm = exar_pm;
220 port->port.shutdown = exar_shutdown;
226 pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev,
227 struct uart_8250_port *port, int idx)
229 unsigned int offset = idx * 0x200;
230 unsigned int baud = 1843200;
234 port->port.uartclk = baud * 16;
236 err = default_setup(priv, pcidev, idx, offset, port);
240 p = port->port.membase;
242 writeb(0x00, p + UART_EXAR_8XMODE);
243 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
244 writeb(32, p + UART_EXAR_TXTRG);
245 writeb(32, p + UART_EXAR_RXTRG);
248 * Setup Multipurpose Input/Output pins.
251 switch (pcidev->device) {
252 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
253 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
254 writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
255 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
256 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
258 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
259 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
260 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
261 writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
262 writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
265 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
266 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
267 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
274 pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev,
275 struct uart_8250_port *port, int idx)
277 unsigned int offset = idx * 0x200;
278 unsigned int baud = 1843200;
280 port->port.uartclk = baud * 16;
281 return default_setup(priv, pcidev, idx, offset, port);
285 pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev,
286 struct uart_8250_port *port, int idx)
288 unsigned int offset = idx * 0x200;
289 unsigned int baud = 921600;
291 port->port.uartclk = baud * 16;
292 return default_setup(priv, pcidev, idx, offset, port);
295 static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p)
298 * The Commtech adapters required the MPIOs to be driven low. The Exar
299 * devices will export them as GPIOs, so we pre-configure them safely
302 u8 dir = pcidev->vendor == PCI_VENDOR_ID_EXAR ? 0xff : 0x00;
304 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
305 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
306 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
307 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
308 writeb(dir, p + UART_EXAR_MPIOSEL_7_0);
309 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
310 writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
311 writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
312 writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
313 writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
314 writeb(dir, p + UART_EXAR_MPIOSEL_15_8);
315 writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
319 __xr17v35x_register_gpio(struct pci_dev *pcidev,
320 const struct property_entry *properties)
322 struct platform_device *pdev;
324 pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO);
328 pdev->dev.parent = &pcidev->dev;
329 ACPI_COMPANION_SET(&pdev->dev, ACPI_COMPANION(&pcidev->dev));
331 if (platform_device_add_properties(pdev, properties) < 0 ||
332 platform_device_add(pdev) < 0) {
333 platform_device_put(pdev);
340 static const struct property_entry exar_gpio_properties[] = {
341 PROPERTY_ENTRY_U32("exar,first-pin", 0),
342 PROPERTY_ENTRY_U32("ngpios", 16),
346 static int xr17v35x_register_gpio(struct pci_dev *pcidev,
347 struct uart_8250_port *port)
349 if (pcidev->vendor == PCI_VENDOR_ID_EXAR)
350 port->port.private_data =
351 __xr17v35x_register_gpio(pcidev, exar_gpio_properties);
356 static int generic_rs485_config(struct uart_port *port,
357 struct serial_rs485 *rs485)
359 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
360 u8 __iomem *p = port->membase;
363 value = readb(p + UART_EXAR_FCTR);
365 value |= UART_FCTR_EXAR_485;
367 value &= ~UART_FCTR_EXAR_485;
369 writeb(value, p + UART_EXAR_FCTR);
372 writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR);
374 port->rs485 = *rs485;
379 static const struct exar8250_platform exar8250_default_platform = {
380 .register_gpio = xr17v35x_register_gpio,
381 .rs485_config = generic_rs485_config,
384 static int iot2040_rs485_config(struct uart_port *port,
385 struct serial_rs485 *rs485)
387 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
388 u8 __iomem *p = port->membase;
389 u8 mask = IOT2040_UART1_MASK;
393 if (rs485->flags & SER_RS485_RX_DURING_TX)
394 mode = IOT2040_UART_MODE_RS422;
396 mode = IOT2040_UART_MODE_RS485;
398 if (rs485->flags & SER_RS485_TERMINATE_BUS)
399 mode |= IOT2040_UART_TERMINATE_BUS;
401 mode = IOT2040_UART_MODE_RS232;
404 if (port->line == 3) {
405 mask <<= IOT2040_UART2_SHIFT;
406 mode <<= IOT2040_UART2_SHIFT;
409 value = readb(p + UART_EXAR_MPIOLVL_7_0);
412 writeb(value, p + UART_EXAR_MPIOLVL_7_0);
414 return generic_rs485_config(port, rs485);
417 static const struct property_entry iot2040_gpio_properties[] = {
418 PROPERTY_ENTRY_U32("exar,first-pin", 10),
419 PROPERTY_ENTRY_U32("ngpios", 1),
423 static int iot2040_register_gpio(struct pci_dev *pcidev,
424 struct uart_8250_port *port)
426 u8 __iomem *p = port->port.membase;
428 writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0);
429 writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0);
430 writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8);
431 writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8);
433 port->port.private_data =
434 __xr17v35x_register_gpio(pcidev, iot2040_gpio_properties);
439 static const struct exar8250_platform iot2040_platform = {
440 .rs485_config = iot2040_rs485_config,
441 .register_gpio = iot2040_register_gpio,
445 * For SIMATIC IOT2000, only IOT2040 and its variants have the Exar device,
446 * IOT2020 doesn't have. Therefore it is sufficient to match on the common
447 * board name after the device was found.
449 static const struct dmi_system_id exar_platforms[] = {
452 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
454 .driver_data = (void *)&iot2040_platform,
460 pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
461 struct uart_8250_port *port, int idx)
463 const struct exar8250_platform *platform;
464 const struct dmi_system_id *dmi_match;
465 unsigned int offset = idx * 0x400;
466 unsigned int baud = 7812500;
470 dmi_match = dmi_first_match(exar_platforms);
472 platform = dmi_match->driver_data;
474 platform = &exar8250_default_platform;
476 port->port.uartclk = baud * 16;
477 port->port.rs485_config = platform->rs485_config;
480 * Setup the UART clock for the devices on expansion slot to
481 * half the clock speed of the main chip (which is 125MHz)
484 port->port.uartclk /= 2;
486 ret = default_setup(priv, pcidev, idx, offset, port);
490 p = port->port.membase;
492 writeb(0x00, p + UART_EXAR_8XMODE);
493 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
494 writeb(128, p + UART_EXAR_TXTRG);
495 writeb(128, p + UART_EXAR_RXTRG);
498 /* Setup Multipurpose Input/Output pins. */
499 setup_gpio(pcidev, p);
501 ret = platform->register_gpio(pcidev, port);
507 static void pci_xr17v35x_exit(struct pci_dev *pcidev)
509 struct exar8250 *priv = pci_get_drvdata(pcidev);
510 struct uart_8250_port *port = serial8250_get_port(priv->line[0]);
511 struct platform_device *pdev = port->port.private_data;
513 platform_device_unregister(pdev);
514 port->port.private_data = NULL;
517 static inline void exar_misc_clear(struct exar8250 *priv)
519 /* Clear all PCI interrupts by reading INT0. No effect on IIR */
520 readb(priv->virt + UART_EXAR_INT0);
522 /* Clear INT0 for Expansion Interface slave ports, too */
523 if (priv->board->num_ports > 8)
524 readb(priv->virt + 0x2000 + UART_EXAR_INT0);
528 * These Exar UARTs have an extra interrupt indicator that could fire for a
529 * few interrupts that are not presented/cleared through IIR. One of which is
530 * a wakeup interrupt when coming out of sleep. These interrupts are only
531 * cleared by reading global INT0 or INT1 registers as interrupts are
532 * associated with channel 0. The INT[3:0] registers _are_ accessible from each
533 * channel's address space, but for the sake of bus efficiency we register a
534 * dedicated handler at the PCI device level to handle them.
536 static irqreturn_t exar_misc_handler(int irq, void *data)
538 exar_misc_clear(data);
544 exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
546 unsigned int nr_ports, i, bar = 0, maxnr;
547 struct exar8250_board *board;
548 struct uart_8250_port uart;
549 struct exar8250 *priv;
552 board = (struct exar8250_board *)ent->driver_data;
556 rc = pcim_enable_device(pcidev);
560 maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3);
562 nr_ports = board->num_ports ? board->num_ports : pcidev->device & 0x0f;
564 priv = devm_kzalloc(&pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL);
569 priv->virt = pcim_iomap(pcidev, bar, 0);
573 pci_set_master(pcidev);
575 rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES);
579 memset(&uart, 0, sizeof(uart));
580 uart.port.flags = UPF_SHARE_IRQ | UPF_EXAR_EFR | UPF_FIXED_TYPE | UPF_FIXED_PORT;
581 uart.port.irq = pci_irq_vector(pcidev, 0);
582 uart.port.dev = &pcidev->dev;
584 rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler,
585 IRQF_SHARED, "exar_uart", priv);
589 /* Clear interrupts */
590 exar_misc_clear(priv);
592 for (i = 0; i < nr_ports && i < maxnr; i++) {
593 rc = board->setup(priv, pcidev, &uart, i);
595 dev_err(&pcidev->dev, "Failed to setup port %u\n", i);
599 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
600 uart.port.iobase, uart.port.irq, uart.port.iotype);
602 priv->line[i] = serial8250_register_8250_port(&uart);
603 if (priv->line[i] < 0) {
604 dev_err(&pcidev->dev,
605 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
606 uart.port.iobase, uart.port.irq,
607 uart.port.iotype, priv->line[i]);
612 pci_set_drvdata(pcidev, priv);
616 static void exar_pci_remove(struct pci_dev *pcidev)
618 struct exar8250 *priv = pci_get_drvdata(pcidev);
621 for (i = 0; i < priv->nr; i++)
622 serial8250_unregister_port(priv->line[i]);
624 if (priv->board->exit)
625 priv->board->exit(pcidev);
628 static int __maybe_unused exar_suspend(struct device *dev)
630 struct pci_dev *pcidev = to_pci_dev(dev);
631 struct exar8250 *priv = pci_get_drvdata(pcidev);
634 for (i = 0; i < priv->nr; i++)
635 if (priv->line[i] >= 0)
636 serial8250_suspend_port(priv->line[i]);
638 /* Ensure that every init quirk is properly torn down */
639 if (priv->board->exit)
640 priv->board->exit(pcidev);
645 static int __maybe_unused exar_resume(struct device *dev)
647 struct exar8250 *priv = dev_get_drvdata(dev);
650 exar_misc_clear(priv);
652 for (i = 0; i < priv->nr; i++)
653 if (priv->line[i] >= 0)
654 serial8250_resume_port(priv->line[i]);
659 static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
661 static const struct exar8250_board pbn_fastcom335_2 = {
663 .setup = pci_fastcom335_setup,
666 static const struct exar8250_board pbn_fastcom335_4 = {
668 .setup = pci_fastcom335_setup,
671 static const struct exar8250_board pbn_fastcom335_8 = {
673 .setup = pci_fastcom335_setup,
676 static const struct exar8250_board pbn_connect = {
677 .setup = pci_connect_tech_setup,
680 static const struct exar8250_board pbn_exar_ibm_saturn = {
682 .setup = pci_xr17c154_setup,
685 static const struct exar8250_board pbn_exar_XR17C15x = {
686 .setup = pci_xr17c154_setup,
689 static const struct exar8250_board pbn_exar_XR17V35x = {
690 .setup = pci_xr17v35x_setup,
691 .exit = pci_xr17v35x_exit,
694 static const struct exar8250_board pbn_exar_XR17V4358 = {
696 .setup = pci_xr17v35x_setup,
697 .exit = pci_xr17v35x_exit,
700 static const struct exar8250_board pbn_exar_XR17V8358 = {
702 .setup = pci_xr17v35x_setup,
703 .exit = pci_xr17v35x_exit,
706 #define CONNECT_DEVICE(devid, sdevid, bd) { \
708 PCI_VENDOR_ID_EXAR, \
709 PCI_DEVICE_ID_EXAR_##devid, \
710 PCI_SUBVENDOR_ID_CONNECT_TECH, \
711 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \
712 (kernel_ulong_t)&bd \
715 #define EXAR_DEVICE(vend, devid, bd) { \
716 PCI_VDEVICE(vend, PCI_DEVICE_ID_##devid), (kernel_ulong_t)&bd \
719 #define IBM_DEVICE(devid, sdevid, bd) { \
721 PCI_VENDOR_ID_EXAR, \
722 PCI_DEVICE_ID_EXAR_##devid, \
724 PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \
725 (kernel_ulong_t)&bd \
728 static const struct pci_device_id exar_pci_tbl[] = {
729 CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),
730 CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),
731 CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect),
732 CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect),
733 CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect),
734 CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect),
735 CONNECT_DEVICE(XR17C152, UART_2, pbn_connect),
736 CONNECT_DEVICE(XR17C154, UART_4, pbn_connect),
737 CONNECT_DEVICE(XR17C158, UART_8, pbn_connect),
738 CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect),
739 CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect),
740 CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect),
742 IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn),
744 /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */
745 EXAR_DEVICE(EXAR, EXAR_XR17C152, pbn_exar_XR17C15x),
746 EXAR_DEVICE(EXAR, EXAR_XR17C154, pbn_exar_XR17C15x),
747 EXAR_DEVICE(EXAR, EXAR_XR17C158, pbn_exar_XR17C15x),
749 /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
750 EXAR_DEVICE(EXAR, EXAR_XR17V352, pbn_exar_XR17V35x),
751 EXAR_DEVICE(EXAR, EXAR_XR17V354, pbn_exar_XR17V35x),
752 EXAR_DEVICE(EXAR, EXAR_XR17V358, pbn_exar_XR17V35x),
753 EXAR_DEVICE(EXAR, EXAR_XR17V4358, pbn_exar_XR17V4358),
754 EXAR_DEVICE(EXAR, EXAR_XR17V8358, pbn_exar_XR17V8358),
755 EXAR_DEVICE(COMMTECH, COMMTECH_4222PCIE, pbn_exar_XR17V35x),
756 EXAR_DEVICE(COMMTECH, COMMTECH_4224PCIE, pbn_exar_XR17V35x),
757 EXAR_DEVICE(COMMTECH, COMMTECH_4228PCIE, pbn_exar_XR17V35x),
759 EXAR_DEVICE(COMMTECH, COMMTECH_4222PCI335, pbn_fastcom335_2),
760 EXAR_DEVICE(COMMTECH, COMMTECH_4224PCI335, pbn_fastcom335_4),
761 EXAR_DEVICE(COMMTECH, COMMTECH_2324PCI335, pbn_fastcom335_4),
762 EXAR_DEVICE(COMMTECH, COMMTECH_2328PCI335, pbn_fastcom335_8),
765 MODULE_DEVICE_TABLE(pci, exar_pci_tbl);
767 static struct pci_driver exar_pci_driver = {
768 .name = "exar_serial",
769 .probe = exar_pci_probe,
770 .remove = exar_pci_remove,
774 .id_table = exar_pci_tbl,
776 module_pci_driver(exar_pci_driver);
778 MODULE_LICENSE("GPL");
779 MODULE_DESCRIPTION("Exar Serial Driver");
780 MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>");