1 // SPDX-License-Identifier: GPL-2.0
3 * Probe module for 8250/16550-type Exar chips PCI serial ports.
5 * Based on drivers/tty/serial/8250/8250_pci.c,
7 * Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved.
9 #include <linux/acpi.h>
10 #include <linux/dmi.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/property.h>
16 #include <linux/serial_core.h>
17 #include <linux/serial_reg.h>
18 #include <linux/slab.h>
19 #include <linux/string.h>
20 #include <linux/tty.h>
21 #include <linux/8250_pci.h>
22 #include <linux/delay.h>
24 #include <asm/byteorder.h>
28 #define PCI_DEVICE_ID_ACCESSIO_COM_2S 0x1052
29 #define PCI_DEVICE_ID_ACCESSIO_COM_4S 0x105d
30 #define PCI_DEVICE_ID_ACCESSIO_COM_8S 0x106c
31 #define PCI_DEVICE_ID_ACCESSIO_COM232_8 0x10a8
32 #define PCI_DEVICE_ID_ACCESSIO_COM_2SM 0x10d2
33 #define PCI_DEVICE_ID_ACCESSIO_COM_4SM 0x10db
34 #define PCI_DEVICE_ID_ACCESSIO_COM_8SM 0x10ea
36 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
37 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
38 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
39 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
40 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
41 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
42 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
43 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
44 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
46 #define UART_EXAR_INT0 0x80
47 #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */
48 #define UART_EXAR_SLEEP 0x8b /* Sleep mode */
49 #define UART_EXAR_DVID 0x8d /* Device identification */
51 #define UART_EXAR_FCTR 0x08 /* Feature Control Register */
52 #define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */
53 #define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */
54 #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */
55 #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */
56 #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */
57 #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
59 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
60 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
62 #define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */
63 #define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */
64 #define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */
65 #define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */
66 #define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */
67 #define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */
68 #define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */
69 #define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */
70 #define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */
71 #define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */
72 #define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */
73 #define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */
75 #define UART_EXAR_RS485_DLY(x) ((x) << 4)
78 * IOT2040 MPIO wiring semantics:
96 /* IOT2040 MPIOs 0..7 */
97 #define IOT2040_UART_MODE_RS232 0x01
98 #define IOT2040_UART_MODE_RS485 0x02
99 #define IOT2040_UART_MODE_RS422 0x03
100 #define IOT2040_UART_TERMINATE_BUS 0x04
102 #define IOT2040_UART1_MASK 0x0f
103 #define IOT2040_UART2_SHIFT 4
105 #define IOT2040_UARTS_DEFAULT_MODE 0x11 /* both RS232 */
106 #define IOT2040_UARTS_GPIO_LO_MODE 0x88 /* reserved pins as input */
108 /* IOT2040 MPIOs 8..15 */
109 #define IOT2040_UARTS_ENABLE 0x03
110 #define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */
114 struct exar8250_platform {
115 int (*rs485_config)(struct uart_port *, struct serial_rs485 *);
116 int (*register_gpio)(struct pci_dev *, struct uart_8250_port *);
120 * struct exar8250_board - board information
121 * @num_ports: number of serial ports
122 * @reg_shift: describes UART register mapping in PCI memory
123 * @setup: quirk run at ->probe() stage
124 * @exit: quirk run at ->remove() stage
126 struct exar8250_board {
127 unsigned int num_ports;
128 unsigned int reg_shift;
129 int (*setup)(struct exar8250 *, struct pci_dev *,
130 struct uart_8250_port *, int);
131 void (*exit)(struct pci_dev *pcidev);
136 struct exar8250_board *board;
141 static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old)
144 * Exar UARTs have a SLEEP register that enables or disables each UART
145 * to enter sleep mode separately. On the XR17V35x the register
146 * is accessible to each UART at the UART_EXAR_SLEEP offset, but
147 * the UART channel may only write to the corresponding bit.
149 serial_port_out(port, UART_EXAR_SLEEP, state ? 0xff : 0);
153 * XR17V35x UARTs have an extra fractional divisor register (DLD)
154 * Calculate divisor with extra 4-bit fractional portion
156 static unsigned int xr17v35x_get_divisor(struct uart_port *p, unsigned int baud,
159 unsigned int quot_16;
161 quot_16 = DIV_ROUND_CLOSEST(p->uartclk, baud);
162 *frac = quot_16 & 0x0f;
167 static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud,
168 unsigned int quot, unsigned int quot_frac)
170 serial8250_do_set_divisor(p, baud, quot, quot_frac);
172 /* Preserve bits not related to baudrate; DLD[7:4]. */
173 quot_frac |= serial_port_in(p, 0x2) & 0xf0;
174 serial_port_out(p, 0x2, quot_frac);
177 static int xr17v35x_startup(struct uart_port *port)
180 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
181 * MCR [7:5] and MSR [7:0]
183 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
186 * Make sure all interrups are masked until initialization is
187 * complete and the FIFOs are cleared
189 serial_port_out(port, UART_IER, 0);
191 return serial8250_do_startup(port);
194 static void exar_shutdown(struct uart_port *port)
197 bool tx_complete = false;
198 struct uart_8250_port *up = up_to_u8250p(port);
199 struct circ_buf *xmit = &port->state->xmit;
203 lsr = serial_in(up, UART_LSR);
204 if (lsr & (UART_LSR_TEMT | UART_LSR_THRE))
208 usleep_range(1000, 1100);
209 } while (!uart_circ_empty(xmit) && !tx_complete && i++ < 1000);
211 serial8250_do_shutdown(port);
214 static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
215 int idx, unsigned int offset,
216 struct uart_8250_port *port)
218 const struct exar8250_board *board = priv->board;
219 unsigned int bar = 0;
220 unsigned char status;
222 port->port.iotype = UPIO_MEM;
223 port->port.mapbase = pci_resource_start(pcidev, bar) + offset;
224 port->port.membase = priv->virt + offset;
225 port->port.regshift = board->reg_shift;
228 * XR17V35x UARTs have an extra divisor register, DLD that gets enabled
229 * with when DLAB is set which will cause the device to incorrectly match
230 * and assign port type to PORT_16650. The EFR for this UART is found
231 * at offset 0x09. Instead check the Deice ID (DVID) register
232 * for a 2, 4 or 8 port UART.
234 status = readb(port->port.membase + UART_EXAR_DVID);
235 if (status == 0x82 || status == 0x84 || status == 0x88) {
236 port->port.type = PORT_XR17V35X;
238 port->port.get_divisor = xr17v35x_get_divisor;
239 port->port.set_divisor = xr17v35x_set_divisor;
241 port->port.startup = xr17v35x_startup;
243 port->port.type = PORT_XR17D15X;
246 port->port.pm = exar_pm;
247 port->port.shutdown = exar_shutdown;
253 pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev,
254 struct uart_8250_port *port, int idx)
256 unsigned int offset = idx * 0x200;
257 unsigned int baud = 1843200;
261 port->port.uartclk = baud * 16;
263 err = default_setup(priv, pcidev, idx, offset, port);
267 p = port->port.membase;
269 writeb(0x00, p + UART_EXAR_8XMODE);
270 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
271 writeb(32, p + UART_EXAR_TXTRG);
272 writeb(32, p + UART_EXAR_RXTRG);
275 * Setup Multipurpose Input/Output pins.
278 switch (pcidev->device) {
279 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
280 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
281 writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
282 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
283 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
285 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
286 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
287 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
288 writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
289 writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
292 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
293 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
294 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
301 pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev,
302 struct uart_8250_port *port, int idx)
304 unsigned int offset = idx * 0x200;
305 unsigned int baud = 1843200;
307 port->port.uartclk = baud * 16;
308 return default_setup(priv, pcidev, idx, offset, port);
312 pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev,
313 struct uart_8250_port *port, int idx)
315 unsigned int offset = idx * 0x200;
316 unsigned int baud = 921600;
318 port->port.uartclk = baud * 16;
319 return default_setup(priv, pcidev, idx, offset, port);
322 static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p)
325 * The Commtech adapters required the MPIOs to be driven low. The Exar
326 * devices will export them as GPIOs, so we pre-configure them safely
332 if ((pcidev->vendor == PCI_VENDOR_ID_EXAR) &&
333 (pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) {
334 // Configure GPIO as inputs for Commtech adapters
337 // Configure GPIO as outputs for SeaLevel adapters
341 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
342 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
343 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
344 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
345 writeb(dir, p + UART_EXAR_MPIOSEL_7_0);
346 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
347 writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
348 writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
349 writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
350 writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
351 writeb(dir, p + UART_EXAR_MPIOSEL_15_8);
352 writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
356 __xr17v35x_register_gpio(struct pci_dev *pcidev,
357 const struct software_node *node)
359 struct platform_device *pdev;
361 pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO);
365 pdev->dev.parent = &pcidev->dev;
366 ACPI_COMPANION_SET(&pdev->dev, ACPI_COMPANION(&pcidev->dev));
368 if (device_add_software_node(&pdev->dev, node) < 0 ||
369 platform_device_add(pdev) < 0) {
370 platform_device_put(pdev);
377 static const struct property_entry exar_gpio_properties[] = {
378 PROPERTY_ENTRY_U32("exar,first-pin", 0),
379 PROPERTY_ENTRY_U32("ngpios", 16),
383 static const struct software_node exar_gpio_node = {
384 .properties = exar_gpio_properties,
387 static int xr17v35x_register_gpio(struct pci_dev *pcidev,
388 struct uart_8250_port *port)
390 if (pcidev->vendor == PCI_VENDOR_ID_EXAR)
391 port->port.private_data =
392 __xr17v35x_register_gpio(pcidev, &exar_gpio_node);
397 static int generic_rs485_config(struct uart_port *port,
398 struct serial_rs485 *rs485)
400 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
401 u8 __iomem *p = port->membase;
404 value = readb(p + UART_EXAR_FCTR);
406 value |= UART_FCTR_EXAR_485;
408 value &= ~UART_FCTR_EXAR_485;
410 writeb(value, p + UART_EXAR_FCTR);
413 writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR);
415 port->rs485 = *rs485;
420 static const struct exar8250_platform exar8250_default_platform = {
421 .register_gpio = xr17v35x_register_gpio,
422 .rs485_config = generic_rs485_config,
425 static int iot2040_rs485_config(struct uart_port *port,
426 struct serial_rs485 *rs485)
428 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
429 u8 __iomem *p = port->membase;
430 u8 mask = IOT2040_UART1_MASK;
434 if (rs485->flags & SER_RS485_RX_DURING_TX)
435 mode = IOT2040_UART_MODE_RS422;
437 mode = IOT2040_UART_MODE_RS485;
439 if (rs485->flags & SER_RS485_TERMINATE_BUS)
440 mode |= IOT2040_UART_TERMINATE_BUS;
442 mode = IOT2040_UART_MODE_RS232;
445 if (port->line == 3) {
446 mask <<= IOT2040_UART2_SHIFT;
447 mode <<= IOT2040_UART2_SHIFT;
450 value = readb(p + UART_EXAR_MPIOLVL_7_0);
453 writeb(value, p + UART_EXAR_MPIOLVL_7_0);
455 return generic_rs485_config(port, rs485);
458 static const struct property_entry iot2040_gpio_properties[] = {
459 PROPERTY_ENTRY_U32("exar,first-pin", 10),
460 PROPERTY_ENTRY_U32("ngpios", 1),
464 static const struct software_node iot2040_gpio_node = {
465 .properties = iot2040_gpio_properties,
468 static int iot2040_register_gpio(struct pci_dev *pcidev,
469 struct uart_8250_port *port)
471 u8 __iomem *p = port->port.membase;
473 writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0);
474 writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0);
475 writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8);
476 writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8);
478 port->port.private_data =
479 __xr17v35x_register_gpio(pcidev, &iot2040_gpio_node);
484 static const struct exar8250_platform iot2040_platform = {
485 .rs485_config = iot2040_rs485_config,
486 .register_gpio = iot2040_register_gpio,
490 * For SIMATIC IOT2000, only IOT2040 and its variants have the Exar device,
491 * IOT2020 doesn't have. Therefore it is sufficient to match on the common
492 * board name after the device was found.
494 static const struct dmi_system_id exar_platforms[] = {
497 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
499 .driver_data = (void *)&iot2040_platform,
504 static const struct exar8250_platform *exar_get_platform(void)
506 const struct dmi_system_id *dmi_match;
508 dmi_match = dmi_first_match(exar_platforms);
510 return dmi_match->driver_data;
512 return &exar8250_default_platform;
516 pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
517 struct uart_8250_port *port, int idx)
519 const struct exar8250_platform *platform = exar_get_platform();
520 unsigned int offset = idx * 0x400;
521 unsigned int baud = 7812500;
525 port->port.uartclk = baud * 16;
526 port->port.rs485_config = platform->rs485_config;
529 * Setup the UART clock for the devices on expansion slot to
530 * half the clock speed of the main chip (which is 125MHz)
533 port->port.uartclk /= 2;
535 ret = default_setup(priv, pcidev, idx, offset, port);
539 p = port->port.membase;
541 writeb(0x00, p + UART_EXAR_8XMODE);
542 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
543 writeb(128, p + UART_EXAR_TXTRG);
544 writeb(128, p + UART_EXAR_RXTRG);
547 /* Setup Multipurpose Input/Output pins. */
548 setup_gpio(pcidev, p);
550 ret = platform->register_gpio(pcidev, port);
556 static void pci_xr17v35x_exit(struct pci_dev *pcidev)
558 struct exar8250 *priv = pci_get_drvdata(pcidev);
559 struct uart_8250_port *port = serial8250_get_port(priv->line[0]);
560 struct platform_device *pdev;
562 pdev = port->port.private_data;
566 device_remove_software_node(&pdev->dev);
567 platform_device_unregister(pdev);
568 port->port.private_data = NULL;
571 static inline void exar_misc_clear(struct exar8250 *priv)
573 /* Clear all PCI interrupts by reading INT0. No effect on IIR */
574 readb(priv->virt + UART_EXAR_INT0);
576 /* Clear INT0 for Expansion Interface slave ports, too */
577 if (priv->board->num_ports > 8)
578 readb(priv->virt + 0x2000 + UART_EXAR_INT0);
582 * These Exar UARTs have an extra interrupt indicator that could fire for a
583 * few interrupts that are not presented/cleared through IIR. One of which is
584 * a wakeup interrupt when coming out of sleep. These interrupts are only
585 * cleared by reading global INT0 or INT1 registers as interrupts are
586 * associated with channel 0. The INT[3:0] registers _are_ accessible from each
587 * channel's address space, but for the sake of bus efficiency we register a
588 * dedicated handler at the PCI device level to handle them.
590 static irqreturn_t exar_misc_handler(int irq, void *data)
592 exar_misc_clear(data);
598 exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
600 unsigned int nr_ports, i, bar = 0, maxnr;
601 struct exar8250_board *board;
602 struct uart_8250_port uart;
603 struct exar8250 *priv;
606 board = (struct exar8250_board *)ent->driver_data;
610 rc = pcim_enable_device(pcidev);
614 maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3);
616 nr_ports = board->num_ports ? board->num_ports : pcidev->device & 0x0f;
618 priv = devm_kzalloc(&pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL);
623 priv->virt = pcim_iomap(pcidev, bar, 0);
627 pci_set_master(pcidev);
629 rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES);
633 memset(&uart, 0, sizeof(uart));
634 uart.port.flags = UPF_SHARE_IRQ | UPF_EXAR_EFR | UPF_FIXED_TYPE | UPF_FIXED_PORT;
635 uart.port.irq = pci_irq_vector(pcidev, 0);
636 uart.port.dev = &pcidev->dev;
638 rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler,
639 IRQF_SHARED, "exar_uart", priv);
643 /* Clear interrupts */
644 exar_misc_clear(priv);
646 for (i = 0; i < nr_ports && i < maxnr; i++) {
647 rc = board->setup(priv, pcidev, &uart, i);
649 dev_err(&pcidev->dev, "Failed to setup port %u\n", i);
653 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
654 uart.port.iobase, uart.port.irq, uart.port.iotype);
656 priv->line[i] = serial8250_register_8250_port(&uart);
657 if (priv->line[i] < 0) {
658 dev_err(&pcidev->dev,
659 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
660 uart.port.iobase, uart.port.irq,
661 uart.port.iotype, priv->line[i]);
666 pci_set_drvdata(pcidev, priv);
670 static void exar_pci_remove(struct pci_dev *pcidev)
672 struct exar8250 *priv = pci_get_drvdata(pcidev);
675 for (i = 0; i < priv->nr; i++)
676 serial8250_unregister_port(priv->line[i]);
678 if (priv->board->exit)
679 priv->board->exit(pcidev);
682 static int __maybe_unused exar_suspend(struct device *dev)
684 struct pci_dev *pcidev = to_pci_dev(dev);
685 struct exar8250 *priv = pci_get_drvdata(pcidev);
688 for (i = 0; i < priv->nr; i++)
689 if (priv->line[i] >= 0)
690 serial8250_suspend_port(priv->line[i]);
692 /* Ensure that every init quirk is properly torn down */
693 if (priv->board->exit)
694 priv->board->exit(pcidev);
699 static int __maybe_unused exar_resume(struct device *dev)
701 struct exar8250 *priv = dev_get_drvdata(dev);
704 exar_misc_clear(priv);
706 for (i = 0; i < priv->nr; i++)
707 if (priv->line[i] >= 0)
708 serial8250_resume_port(priv->line[i]);
713 static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
715 static const struct exar8250_board acces_com_2x = {
717 .setup = pci_xr17c154_setup,
720 static const struct exar8250_board acces_com_4x = {
722 .setup = pci_xr17c154_setup,
725 static const struct exar8250_board acces_com_8x = {
727 .setup = pci_xr17c154_setup,
731 static const struct exar8250_board pbn_fastcom335_2 = {
733 .setup = pci_fastcom335_setup,
736 static const struct exar8250_board pbn_fastcom335_4 = {
738 .setup = pci_fastcom335_setup,
741 static const struct exar8250_board pbn_fastcom335_8 = {
743 .setup = pci_fastcom335_setup,
746 static const struct exar8250_board pbn_connect = {
747 .setup = pci_connect_tech_setup,
750 static const struct exar8250_board pbn_exar_ibm_saturn = {
752 .setup = pci_xr17c154_setup,
755 static const struct exar8250_board pbn_exar_XR17C15x = {
756 .setup = pci_xr17c154_setup,
759 static const struct exar8250_board pbn_exar_XR17V35x = {
760 .setup = pci_xr17v35x_setup,
761 .exit = pci_xr17v35x_exit,
764 static const struct exar8250_board pbn_fastcom35x_2 = {
766 .setup = pci_xr17v35x_setup,
767 .exit = pci_xr17v35x_exit,
770 static const struct exar8250_board pbn_fastcom35x_4 = {
772 .setup = pci_xr17v35x_setup,
773 .exit = pci_xr17v35x_exit,
776 static const struct exar8250_board pbn_fastcom35x_8 = {
778 .setup = pci_xr17v35x_setup,
779 .exit = pci_xr17v35x_exit,
782 static const struct exar8250_board pbn_exar_XR17V4358 = {
784 .setup = pci_xr17v35x_setup,
785 .exit = pci_xr17v35x_exit,
788 static const struct exar8250_board pbn_exar_XR17V8358 = {
790 .setup = pci_xr17v35x_setup,
791 .exit = pci_xr17v35x_exit,
794 #define CONNECT_DEVICE(devid, sdevid, bd) { \
796 PCI_VENDOR_ID_EXAR, \
797 PCI_DEVICE_ID_EXAR_##devid, \
798 PCI_SUBVENDOR_ID_CONNECT_TECH, \
799 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \
800 (kernel_ulong_t)&bd \
803 #define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) }
805 #define IBM_DEVICE(devid, sdevid, bd) { \
807 PCI_VENDOR_ID_EXAR, \
808 PCI_DEVICE_ID_EXAR_##devid, \
810 PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \
811 (kernel_ulong_t)&bd \
814 static const struct pci_device_id exar_pci_tbl[] = {
815 EXAR_DEVICE(ACCESSIO, COM_2S, acces_com_2x),
816 EXAR_DEVICE(ACCESSIO, COM_4S, acces_com_4x),
817 EXAR_DEVICE(ACCESSIO, COM_8S, acces_com_8x),
818 EXAR_DEVICE(ACCESSIO, COM232_8, acces_com_8x),
819 EXAR_DEVICE(ACCESSIO, COM_2SM, acces_com_2x),
820 EXAR_DEVICE(ACCESSIO, COM_4SM, acces_com_4x),
821 EXAR_DEVICE(ACCESSIO, COM_8SM, acces_com_8x),
823 CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),
824 CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),
825 CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect),
826 CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect),
827 CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect),
828 CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect),
829 CONNECT_DEVICE(XR17C152, UART_2, pbn_connect),
830 CONNECT_DEVICE(XR17C154, UART_4, pbn_connect),
831 CONNECT_DEVICE(XR17C158, UART_8, pbn_connect),
832 CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect),
833 CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect),
834 CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect),
836 IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn),
838 /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */
839 EXAR_DEVICE(EXAR, XR17C152, pbn_exar_XR17C15x),
840 EXAR_DEVICE(EXAR, XR17C154, pbn_exar_XR17C15x),
841 EXAR_DEVICE(EXAR, XR17C158, pbn_exar_XR17C15x),
843 /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
844 EXAR_DEVICE(EXAR, XR17V352, pbn_exar_XR17V35x),
845 EXAR_DEVICE(EXAR, XR17V354, pbn_exar_XR17V35x),
846 EXAR_DEVICE(EXAR, XR17V358, pbn_exar_XR17V35x),
847 EXAR_DEVICE(EXAR, XR17V4358, pbn_exar_XR17V4358),
848 EXAR_DEVICE(EXAR, XR17V8358, pbn_exar_XR17V8358),
849 EXAR_DEVICE(COMMTECH, 4222PCIE, pbn_fastcom35x_2),
850 EXAR_DEVICE(COMMTECH, 4224PCIE, pbn_fastcom35x_4),
851 EXAR_DEVICE(COMMTECH, 4228PCIE, pbn_fastcom35x_8),
853 EXAR_DEVICE(COMMTECH, 4222PCI335, pbn_fastcom335_2),
854 EXAR_DEVICE(COMMTECH, 4224PCI335, pbn_fastcom335_4),
855 EXAR_DEVICE(COMMTECH, 2324PCI335, pbn_fastcom335_4),
856 EXAR_DEVICE(COMMTECH, 2328PCI335, pbn_fastcom335_8),
859 MODULE_DEVICE_TABLE(pci, exar_pci_tbl);
861 static struct pci_driver exar_pci_driver = {
862 .name = "exar_serial",
863 .probe = exar_pci_probe,
864 .remove = exar_pci_remove,
868 .id_table = exar_pci_tbl,
870 module_pci_driver(exar_pci_driver);
872 MODULE_LICENSE("GPL");
873 MODULE_DESCRIPTION("Exar Serial Driver");
874 MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>");