2 * Synopsys DesignWare 8250 driver.
4 * Copyright 2011 Picochip, Jamie Iles.
5 * Copyright 2013 Intel Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
13 * LCR is written whilst busy. If it is, then a busy detect interrupt is
14 * raised, the LCR needs to be rewritten and the uart status register read.
16 #include <linux/device.h>
17 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/serial_8250.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial_reg.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_platform.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <linux/acpi.h>
29 #include <linux/clk.h>
30 #include <linux/pm_runtime.h>
32 #include <asm/byteorder.h>
36 /* Offsets for the DesignWare specific registers */
37 #define DW_UART_USR 0x1f /* UART Status Register */
38 #define DW_UART_CPR 0xf4 /* Component Parameter Register */
39 #define DW_UART_UCV 0xf8 /* UART Component Version */
41 /* Component Parameter Register bits */
42 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
43 #define DW_UART_CPR_AFCE_MODE (1 << 4)
44 #define DW_UART_CPR_THRE_MODE (1 << 5)
45 #define DW_UART_CPR_SIR_MODE (1 << 6)
46 #define DW_UART_CPR_SIR_LP_MODE (1 << 7)
47 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
48 #define DW_UART_CPR_FIFO_ACCESS (1 << 9)
49 #define DW_UART_CPR_FIFO_STAT (1 << 10)
50 #define DW_UART_CPR_SHADOW (1 << 11)
51 #define DW_UART_CPR_ENCODED_PARMS (1 << 12)
52 #define DW_UART_CPR_DMA_EXTRA (1 << 13)
53 #define DW_UART_CPR_FIFO_MODE (0xff << 16)
54 /* Helper for fifo size calculation */
55 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
63 struct uart_8250_dma dma;
66 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
68 struct dw8250_data *d = p->private_data;
70 /* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
71 if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
72 value |= UART_MSR_CTS;
73 value &= ~UART_MSR_DCTS;
79 static void dw8250_force_idle(struct uart_port *p)
81 serial8250_clear_and_reinit_fifos(container_of
82 (p, struct uart_8250_port, port));
83 (void)p->serial_in(p, UART_RX);
86 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
88 struct dw8250_data *d = p->private_data;
90 if (offset == UART_MCR)
93 writeb(value, p->membase + (offset << p->regshift));
95 /* Make sure LCR write wasn't ignored */
96 if (offset == UART_LCR) {
99 unsigned int lcr = p->serial_in(p, UART_LCR);
100 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
102 dw8250_force_idle(p);
103 writeb(value, p->membase + (UART_LCR << p->regshift));
105 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
109 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
111 unsigned int value = readb(p->membase + (offset << p->regshift));
113 return dw8250_modify_msr(p, offset, value);
116 /* Read Back (rb) version to ensure register access ording. */
117 static void dw8250_serial_out_rb(struct uart_port *p, int offset, int value)
119 dw8250_serial_out(p, offset, value);
120 dw8250_serial_in(p, UART_LCR);
123 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
125 struct dw8250_data *d = p->private_data;
127 if (offset == UART_MCR)
130 writel(value, p->membase + (offset << p->regshift));
132 /* Make sure LCR write wasn't ignored */
133 if (offset == UART_LCR) {
136 unsigned int lcr = p->serial_in(p, UART_LCR);
137 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
139 dw8250_force_idle(p);
140 writel(value, p->membase + (UART_LCR << p->regshift));
142 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
146 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
148 unsigned int value = readl(p->membase + (offset << p->regshift));
150 return dw8250_modify_msr(p, offset, value);
153 static int dw8250_handle_irq(struct uart_port *p)
155 struct dw8250_data *d = p->private_data;
156 unsigned int iir = p->serial_in(p, UART_IIR);
158 if (serial8250_handle_irq(p, iir)) {
160 } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
162 (void)p->serial_in(p, d->usr_reg);
171 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
174 pm_runtime_get_sync(port->dev);
176 serial8250_do_pm(port, state, old);
179 pm_runtime_put_sync_suspend(port->dev);
182 static bool dw8250_dma_filter(struct dma_chan *chan, void *param)
184 struct dw8250_data *data = param;
186 return chan->chan_id == data->dma.tx_chan_id ||
187 chan->chan_id == data->dma.rx_chan_id;
190 static void dw8250_setup_port(struct uart_8250_port *up)
192 struct uart_port *p = &up->port;
193 u32 reg = readl(p->membase + DW_UART_UCV);
196 * If the Component Version Register returns zero, we know that
197 * ADDITIONAL_FEATURES are not enabled. No need to go any further.
202 dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
203 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
205 reg = readl(p->membase + DW_UART_CPR);
209 /* Select the type based on fifo */
210 if (reg & DW_UART_CPR_FIFO_MODE) {
211 p->type = PORT_16550A;
212 p->flags |= UPF_FIXED_TYPE;
213 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
214 up->tx_loadsz = p->fifosize;
215 up->capabilities = UART_CAP_FIFO;
218 if (reg & DW_UART_CPR_AFCE_MODE)
219 up->capabilities |= UART_CAP_AFE;
222 static int dw8250_probe_of(struct uart_port *p,
223 struct dw8250_data *data)
225 struct device_node *np = p->dev->of_node;
229 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
232 * Low order bits of these 64-bit registers, when
233 * accessed as a byte, are 7 bytes further down in the
234 * address space in big endian mode.
238 p->serial_out = dw8250_serial_out_rb;
239 p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
240 p->type = PORT_OCTEON;
241 data->usr_reg = 0x27;
243 } else if (!of_property_read_u32(np, "reg-io-width", &val)) {
248 p->iotype = UPIO_MEM32;
249 p->serial_in = dw8250_serial_in32;
250 p->serial_out = dw8250_serial_out32;
253 dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
258 dw8250_setup_port(container_of(p, struct uart_8250_port, port));
260 if (!of_property_read_u32(np, "reg-shift", &val))
263 /* clock got configured through clk api, all done */
267 /* try to find out clock frequency from DT as fallback */
268 if (of_property_read_u32(np, "clock-frequency", &val)) {
269 dev_err(p->dev, "clk or clock-frequency not defined\n");
278 static int dw8250_probe_acpi(struct uart_8250_port *up,
279 struct dw8250_data *data)
281 const struct acpi_device_id *id;
282 struct uart_port *p = &up->port;
284 dw8250_setup_port(up);
286 id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev);
290 p->iotype = UPIO_MEM32;
291 p->serial_in = dw8250_serial_in32;
292 p->serial_out = dw8250_serial_out32;
296 p->uartclk = (unsigned int)id->driver_data;
298 up->dma = &data->dma;
300 up->dma->rxconf.src_maxburst = p->fifosize / 4;
301 up->dma->txconf.dst_maxburst = p->fifosize / 4;
306 static inline int dw8250_probe_acpi(struct uart_8250_port *up,
307 struct dw8250_data *data)
311 #endif /* CONFIG_ACPI */
313 static int dw8250_probe(struct platform_device *pdev)
315 struct uart_8250_port uart = {};
316 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
317 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
318 struct dw8250_data *data;
322 dev_err(&pdev->dev, "no registers/irq defined\n");
326 spin_lock_init(&uart.port.lock);
327 uart.port.mapbase = regs->start;
328 uart.port.irq = irq->start;
329 uart.port.handle_irq = dw8250_handle_irq;
330 uart.port.pm = dw8250_do_pm;
331 uart.port.type = PORT_8250;
332 uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
333 uart.port.dev = &pdev->dev;
335 uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
336 resource_size(regs));
337 if (!uart.port.membase)
340 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
344 data->usr_reg = DW_UART_USR;
345 data->clk = devm_clk_get(&pdev->dev, NULL);
346 if (!IS_ERR(data->clk)) {
347 clk_prepare_enable(data->clk);
348 uart.port.uartclk = clk_get_rate(data->clk);
351 data->dma.rx_chan_id = -1;
352 data->dma.tx_chan_id = -1;
353 data->dma.rx_param = data;
354 data->dma.tx_param = data;
355 data->dma.fn = dw8250_dma_filter;
357 uart.port.iotype = UPIO_MEM;
358 uart.port.serial_in = dw8250_serial_in;
359 uart.port.serial_out = dw8250_serial_out;
360 uart.port.private_data = data;
362 if (pdev->dev.of_node) {
363 err = dw8250_probe_of(&uart.port, data);
366 } else if (ACPI_HANDLE(&pdev->dev)) {
367 err = dw8250_probe_acpi(&uart, data);
374 data->line = serial8250_register_8250_port(&uart);
378 platform_set_drvdata(pdev, data);
380 pm_runtime_set_active(&pdev->dev);
381 pm_runtime_enable(&pdev->dev);
386 static int dw8250_remove(struct platform_device *pdev)
388 struct dw8250_data *data = platform_get_drvdata(pdev);
390 pm_runtime_get_sync(&pdev->dev);
392 serial8250_unregister_port(data->line);
394 if (!IS_ERR(data->clk))
395 clk_disable_unprepare(data->clk);
397 pm_runtime_disable(&pdev->dev);
398 pm_runtime_put_noidle(&pdev->dev);
404 static int dw8250_suspend(struct device *dev)
406 struct dw8250_data *data = dev_get_drvdata(dev);
408 serial8250_suspend_port(data->line);
413 static int dw8250_resume(struct device *dev)
415 struct dw8250_data *data = dev_get_drvdata(dev);
417 serial8250_resume_port(data->line);
421 #endif /* CONFIG_PM */
423 #ifdef CONFIG_PM_RUNTIME
424 static int dw8250_runtime_suspend(struct device *dev)
426 struct dw8250_data *data = dev_get_drvdata(dev);
428 if (!IS_ERR(data->clk))
429 clk_disable_unprepare(data->clk);
434 static int dw8250_runtime_resume(struct device *dev)
436 struct dw8250_data *data = dev_get_drvdata(dev);
438 if (!IS_ERR(data->clk))
439 clk_prepare_enable(data->clk);
445 static const struct dev_pm_ops dw8250_pm_ops = {
446 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
447 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
450 static const struct of_device_id dw8250_of_match[] = {
451 { .compatible = "snps,dw-apb-uart" },
452 { .compatible = "cavium,octeon-3860-uart" },
455 MODULE_DEVICE_TABLE(of, dw8250_of_match);
457 static const struct acpi_device_id dw8250_acpi_match[] = {
465 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
467 static struct platform_driver dw8250_platform_driver = {
469 .name = "dw-apb-uart",
470 .owner = THIS_MODULE,
471 .pm = &dw8250_pm_ops,
472 .of_match_table = dw8250_of_match,
473 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
475 .probe = dw8250_probe,
476 .remove = dw8250_remove,
479 module_platform_driver(dw8250_platform_driver);
481 MODULE_AUTHOR("Jamie Iles");
482 MODULE_LICENSE("GPL");
483 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");