drivers/tty/serial/8250/8250_bcm7271.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2020, Broadcom */
   3 /*
   4  * 8250-core based driver for Broadcom ns16550a UARTs
   5  *
   6  * This driver uses the standard 8250 driver core but adds additional
   7  * optional features including the ability to use a baud rate clock
   8  * mux for more accurate high speed baud rate selection and also
   9  * an optional DMA engine.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/types.h>
  15 #include <linux/tty.h>
  16 #include <linux/errno.h>
  17 #include <linux/device.h>
  18 #include <linux/io.h>
  19 #include <linux/of.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/tty_flip.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24 #include <linux/debugfs.h>
  25
  26 #include "8250.h"
  27
  28 /* Register definitions for UART DMA block. Version 1.1 or later. */
  29 #define UDMA_ARB_RX             0x00
  30 #define UDMA_ARB_TX             0x04
  31 #define         UDMA_ARB_REQ                            0x00000001
  32 #define         UDMA_ARB_GRANT                          0x00000002
  33
  34 #define UDMA_RX_REVISION        0x00
  35 #define UDMA_RX_REVISION_REQUIRED                       0x00000101
  36 #define UDMA_RX_CTRL            0x04
  37 #define         UDMA_RX_CTRL_BUF_CLOSE_MODE             0x00010000
  38 #define         UDMA_RX_CTRL_MASK_WR_DONE               0x00008000
  39 #define         UDMA_RX_CTRL_ENDIAN_OVERRIDE            0x00004000
  40 #define         UDMA_RX_CTRL_ENDIAN                     0x00002000
  41 #define         UDMA_RX_CTRL_OE_IS_ERR                  0x00001000
  42 #define         UDMA_RX_CTRL_PE_IS_ERR                  0x00000800
  43 #define         UDMA_RX_CTRL_FE_IS_ERR                  0x00000400
  44 #define         UDMA_RX_CTRL_NUM_BUF_USED_MASK          0x000003c0
  45 #define         UDMA_RX_CTRL_NUM_BUF_USED_SHIFT 6
  46 #define         UDMA_RX_CTRL_BUF_CLOSE_CLK_SEL_SYS      0x00000020
  47 #define         UDMA_RX_CTRL_BUF_CLOSE_ENA              0x00000010
  48 #define         UDMA_RX_CTRL_TIMEOUT_CLK_SEL_SYS        0x00000008
  49 #define         UDMA_RX_CTRL_TIMEOUT_ENA                0x00000004
  50 #define         UDMA_RX_CTRL_ABORT                      0x00000002
  51 #define         UDMA_RX_CTRL_ENA                        0x00000001
  52 #define UDMA_RX_STATUS          0x08
  53 #define         UDMA_RX_STATUS_ACTIVE_BUF_MASK          0x0000000f
  54 #define UDMA_RX_TRANSFER_LEN    0x0c
  55 #define UDMA_RX_TRANSFER_TOTAL  0x10
  56 #define UDMA_RX_BUFFER_SIZE     0x14
  57 #define UDMA_RX_SRC_ADDR        0x18
  58 #define UDMA_RX_TIMEOUT         0x1c
  59 #define UDMA_RX_BUFFER_CLOSE    0x20
  60 #define UDMA_RX_BLOCKOUT_COUNTER 0x24
  61 #define UDMA_RX_BUF0_PTR_LO     0x28
  62 #define UDMA_RX_BUF0_PTR_HI     0x2c
  63 #define UDMA_RX_BUF0_STATUS     0x30
  64 #define         UDMA_RX_BUFX_STATUS_OVERRUN_ERR         0x00000010
  65 #define         UDMA_RX_BUFX_STATUS_FRAME_ERR           0x00000008
  66 #define         UDMA_RX_BUFX_STATUS_PARITY_ERR          0x00000004
  67 #define         UDMA_RX_BUFX_STATUS_CLOSE_EXPIRED       0x00000002
  68 #define         UDMA_RX_BUFX_STATUS_DATA_RDY            0x00000001
  69 #define UDMA_RX_BUF0_DATA_LEN   0x34
  70 #define UDMA_RX_BUF1_PTR_LO     0x38
  71 #define UDMA_RX_BUF1_PTR_HI     0x3c
  72 #define UDMA_RX_BUF1_STATUS     0x40
  73 #define UDMA_RX_BUF1_DATA_LEN   0x44
  74
  75 #define UDMA_TX_REVISION        0x00
  76 #define UDMA_TX_REVISION_REQUIRED                       0x00000101
  77 #define UDMA_TX_CTRL            0x04
  78 #define         UDMA_TX_CTRL_ENDIAN_OVERRIDE            0x00000080
  79 #define         UDMA_TX_CTRL_ENDIAN                     0x00000040
  80 #define         UDMA_TX_CTRL_NUM_BUF_USED_MASK          0x00000030
  81 #define         UDMA_TX_CTRL_NUM_BUF_USED_1             0x00000010
  82 #define         UDMA_TX_CTRL_ABORT                      0x00000002
  83 #define         UDMA_TX_CTRL_ENA                        0x00000001
  84 #define UDMA_TX_DST_ADDR        0x08
  85 #define UDMA_TX_BLOCKOUT_COUNTER 0x10
  86 #define UDMA_TX_TRANSFER_LEN    0x14
  87 #define UDMA_TX_TRANSFER_TOTAL  0x18
  88 #define UDMA_TX_STATUS          0x20
  89 #define UDMA_TX_BUF0_PTR_LO     0x24
  90 #define UDMA_TX_BUF0_PTR_HI     0x28
  91 #define UDMA_TX_BUF0_STATUS     0x2c
  92 #define         UDMA_TX_BUFX_LAST                       0x00000002
  93 #define         UDMA_TX_BUFX_EMPTY                      0x00000001
  94 #define UDMA_TX_BUF0_DATA_LEN   0x30
  95 #define UDMA_TX_BUF0_DATA_SENT  0x34
  96 #define UDMA_TX_BUF1_PTR_LO     0x38
  97
  98 #define UDMA_INTR_STATUS        0x00
  99 #define         UDMA_INTR_ARB_TX_GRANT                  0x00040000
 100 #define         UDMA_INTR_ARB_RX_GRANT                  0x00020000
 101 #define         UDMA_INTR_TX_ALL_EMPTY                  0x00010000
 102 #define         UDMA_INTR_TX_EMPTY_BUF1                 0x00008000
 103 #define         UDMA_INTR_TX_EMPTY_BUF0                 0x00004000
 104 #define         UDMA_INTR_TX_ABORT                      0x00002000
 105 #define         UDMA_INTR_TX_DONE                       0x00001000
 106 #define         UDMA_INTR_RX_ERROR                      0x00000800
 107 #define         UDMA_INTR_RX_TIMEOUT                    0x00000400
 108 #define         UDMA_INTR_RX_READY_BUF7                 0x00000200
 109 #define         UDMA_INTR_RX_READY_BUF6                 0x00000100
 110 #define         UDMA_INTR_RX_READY_BUF5                 0x00000080
 111 #define         UDMA_INTR_RX_READY_BUF4                 0x00000040
 112 #define         UDMA_INTR_RX_READY_BUF3                 0x00000020
 113 #define         UDMA_INTR_RX_READY_BUF2                 0x00000010
 114 #define         UDMA_INTR_RX_READY_BUF1                 0x00000008
 115 #define         UDMA_INTR_RX_READY_BUF0                 0x00000004
 116 #define         UDMA_INTR_RX_READY_MASK                 0x000003fc
 117 #define         UDMA_INTR_RX_READY_SHIFT                2
 118 #define         UDMA_INTR_RX_ABORT                      0x00000002
 119 #define         UDMA_INTR_RX_DONE                       0x00000001
 120 #define UDMA_INTR_SET           0x04
 121 #define UDMA_INTR_CLEAR         0x08
 122 #define UDMA_INTR_MASK_STATUS   0x0c
 123 #define UDMA_INTR_MASK_SET      0x10
 124 #define UDMA_INTR_MASK_CLEAR    0x14
 125
 126
 127 #define UDMA_RX_INTERRUPTS ( \
 128         UDMA_INTR_RX_ERROR | \
 129         UDMA_INTR_RX_TIMEOUT | \
 130         UDMA_INTR_RX_READY_BUF0 | \
 131         UDMA_INTR_RX_READY_BUF1 | \
 132         UDMA_INTR_RX_READY_BUF2 | \
 133         UDMA_INTR_RX_READY_BUF3 | \
 134         UDMA_INTR_RX_READY_BUF4 | \
 135         UDMA_INTR_RX_READY_BUF5 | \
 136         UDMA_INTR_RX_READY_BUF6 | \
 137         UDMA_INTR_RX_READY_BUF7 | \
 138         UDMA_INTR_RX_ABORT | \
 139         UDMA_INTR_RX_DONE)
 140
 141 #define UDMA_RX_ERR_INTERRUPTS ( \
 142         UDMA_INTR_RX_ERROR | \
 143         UDMA_INTR_RX_TIMEOUT | \
 144         UDMA_INTR_RX_ABORT | \
 145         UDMA_INTR_RX_DONE)
 146
 147 #define UDMA_TX_INTERRUPTS ( \
 148         UDMA_INTR_TX_ABORT | \
 149         UDMA_INTR_TX_DONE)
 150
 151 #define UDMA_IS_RX_INTERRUPT(status) ((status) & UDMA_RX_INTERRUPTS)
 152 #define UDMA_IS_TX_INTERRUPT(status) ((status) & UDMA_TX_INTERRUPTS)
 153
 154
 155 /* Current devices have 8 sets of RX buffer registers */
 156 #define UDMA_RX_BUFS_COUNT      8
 157 #define UDMA_RX_BUFS_REG_OFFSET (UDMA_RX_BUF1_PTR_LO - UDMA_RX_BUF0_PTR_LO)
 158 #define UDMA_RX_BUFx_PTR_LO(x)  (UDMA_RX_BUF0_PTR_LO + \
 159                                  ((x) * UDMA_RX_BUFS_REG_OFFSET))
 160 #define UDMA_RX_BUFx_PTR_HI(x)  (UDMA_RX_BUF0_PTR_HI + \
 161                                  ((x) * UDMA_RX_BUFS_REG_OFFSET))
 162 #define UDMA_RX_BUFx_STATUS(x)  (UDMA_RX_BUF0_STATUS + \
 163                                  ((x) * UDMA_RX_BUFS_REG_OFFSET))
 164 #define UDMA_RX_BUFx_DATA_LEN(x) (UDMA_RX_BUF0_DATA_LEN + \
 165                                   ((x) * UDMA_RX_BUFS_REG_OFFSET))
 166
 167 /* Current devices have 2 sets of TX buffer registers */
 168 #define UDMA_TX_BUFS_COUNT      2
 169 #define UDMA_TX_BUFS_REG_OFFSET (UDMA_TX_BUF1_PTR_LO - UDMA_TX_BUF0_PTR_LO)
 170 #define UDMA_TX_BUFx_PTR_LO(x)  (UDMA_TX_BUF0_PTR_LO + \
 171                                  ((x) * UDMA_TX_BUFS_REG_OFFSET))
 172 #define UDMA_TX_BUFx_PTR_HI(x)  (UDMA_TX_BUF0_PTR_HI + \
 173                                  ((x) * UDMA_TX_BUFS_REG_OFFSET))
 174 #define UDMA_TX_BUFx_STATUS(x)  (UDMA_TX_BUF0_STATUS + \
 175                                  ((x) * UDMA_TX_BUFS_REG_OFFSET))
 176 #define UDMA_TX_BUFx_DATA_LEN(x) (UDMA_TX_BUF0_DATA_LEN + \
 177                                   ((x) * UDMA_TX_BUFS_REG_OFFSET))
 178 #define UDMA_TX_BUFx_DATA_SENT(x) (UDMA_TX_BUF0_DATA_SENT + \
 179                                    ((x) * UDMA_TX_BUFS_REG_OFFSET))
 180 #define REGS_8250 0
 181 #define REGS_DMA_RX 1
 182 #define REGS_DMA_TX 2
 183 #define REGS_DMA_ISR 3
 184 #define REGS_DMA_ARB 4
 185 #define REGS_MAX 5
 186
 187 #define TX_BUF_SIZE 4096
 188 #define RX_BUF_SIZE 4096
 189 #define RX_BUFS_COUNT 2
 190 #define KHZ    1000
 191 #define MHZ(x) ((x) * KHZ * KHZ)
 192
 193 static const u32 brcmstb_rate_table[] = {
 194         MHZ(81),
 195         MHZ(108),
 196         MHZ(64),                /* Actually 64285715 for some chips */
 197         MHZ(48),
 198 };
 199
 200 static const u32 brcmstb_rate_table_7278[] = {
 201         MHZ(81),
 202         MHZ(108),
 203         0,
 204         MHZ(48),
 205 };
 206
 207 struct brcmuart_priv {
 208         int             line;
 209         struct clk      *baud_mux_clk;
 210         unsigned long   default_mux_rate;
 211         u32             real_rates[ARRAY_SIZE(brcmstb_rate_table)];
 212         const u32       *rate_table;
 213         ktime_t         char_wait;
 214         struct uart_port *up;
 215         struct hrtimer  hrt;
 216         bool            shutdown;
 217         bool            dma_enabled;
 218         struct uart_8250_dma dma;
 219         void __iomem    *regs[REGS_MAX];
 220         dma_addr_t      rx_addr;
 221         void            *rx_bufs;
 222         size_t          rx_size;
 223         int             rx_next_buf;
 224         dma_addr_t      tx_addr;
 225         void            *tx_buf;
 226         size_t          tx_size;
 227         bool            tx_running;
 228         bool            rx_running;
 229         struct dentry   *debugfs_dir;
 230
 231         /* stats exposed through debugfs */
 232         u64             dma_rx_partial_buf;
 233         u64             dma_rx_full_buf;
 234         u32             rx_bad_timeout_late_char;
 235         u32             rx_bad_timeout_no_char;
 236         u32             rx_missing_close_timeout;
 237         u32             rx_err;
 238         u32             rx_timeout;
 239         u32             rx_abort;
 240 };
 241
 242 struct dentry *brcmuart_debugfs_root;
 243
 244 /*
 245  * Register access routines
 246  */
 247 static u32 udma_readl(struct brcmuart_priv *priv,
 248                 int reg_type, int offset)
 249 {
 250         return readl(priv->regs[reg_type] + offset);
 251 }
 252
 253 static void udma_writel(struct brcmuart_priv *priv,
 254                         int reg_type, int offset, u32 value)
 255 {
 256         writel(value, priv->regs[reg_type] + offset);
 257 }
 258
 259 static void udma_set(struct brcmuart_priv *priv,
 260                 int reg_type, int offset, u32 bits)
 261 {
 262         void __iomem *reg = priv->regs[reg_type] + offset;
 263         u32 value;
 264
 265         value = readl(reg);
 266         value |= bits;
 267         writel(value, reg);
 268 }
 269
 270 static void udma_unset(struct brcmuart_priv *priv,
 271                 int reg_type, int offset, u32 bits)
 272 {
 273         void __iomem *reg = priv->regs[reg_type] + offset;
 274         u32 value;
 275
 276         value = readl(reg);
 277         value &= ~bits;
 278         writel(value, reg);
 279 }
 280
 281 /*
 282  * The UART DMA engine hardware can be used by multiple UARTS, but
 283  * only one at a time. Sharing is not currently supported so
 284  * the first UART to request the DMA engine will get it and any
 285  * subsequent requests by other UARTS will fail.
 286  */
 287 static int brcmuart_arbitration(struct brcmuart_priv *priv, bool acquire)
 288 {
 289         u32 rx_grant;
 290         u32 tx_grant;
 291         int waits;
 292         int ret = 0;
 293
 294         if (acquire) {
 295                 udma_set(priv, REGS_DMA_ARB, UDMA_ARB_RX, UDMA_ARB_REQ);
 296                 udma_set(priv, REGS_DMA_ARB, UDMA_ARB_TX, UDMA_ARB_REQ);
 297
 298                 waits = 1;
 299                 while (1) {
 300                         rx_grant = udma_readl(priv, REGS_DMA_ARB, UDMA_ARB_RX);
 301                         tx_grant = udma_readl(priv, REGS_DMA_ARB, UDMA_ARB_TX);
 302                         if (rx_grant & tx_grant & UDMA_ARB_GRANT)
 303                                 return 0;
 304                         if (waits-- == 0)
 305                                 break;
 306                         msleep(1);
 307                 }
 308                 ret = 1;
 309         }
 310
 311         udma_unset(priv, REGS_DMA_ARB, UDMA_ARB_RX, UDMA_ARB_REQ);
 312         udma_unset(priv, REGS_DMA_ARB, UDMA_ARB_TX, UDMA_ARB_REQ);
 313         return ret;
 314 }
 315
 316 static void brcmuart_init_dma_hardware(struct brcmuart_priv *priv)
 317 {
 318         u32 daddr;
 319         u32 value;
 320         int x;
 321
 322         /* Start with all interrupts disabled */
 323         udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_MASK_SET, 0xffffffff);
 324
 325         udma_writel(priv, REGS_DMA_RX, UDMA_RX_BUFFER_SIZE, RX_BUF_SIZE);
 326
 327         /*
 328          * Setup buffer close to happen when 32 character times have
 329          * elapsed since the last character was received.
 330          */
 331         udma_writel(priv, REGS_DMA_RX, UDMA_RX_BUFFER_CLOSE, 16*10*32);
 332         value = (RX_BUFS_COUNT << UDMA_RX_CTRL_NUM_BUF_USED_SHIFT)
 333                 | UDMA_RX_CTRL_BUF_CLOSE_MODE
 334                 | UDMA_RX_CTRL_BUF_CLOSE_ENA;
 335         udma_writel(priv, REGS_DMA_RX, UDMA_RX_CTRL, value);
 336
 337         udma_writel(priv, REGS_DMA_RX, UDMA_RX_BLOCKOUT_COUNTER, 0);
 338         daddr = priv->rx_addr;
 339         for (x = 0; x < RX_BUFS_COUNT; x++) {
 340
 341                 /* Set RX transfer length to 0 for unknown */
 342                 udma_writel(priv, REGS_DMA_RX, UDMA_RX_TRANSFER_LEN, 0);
 343
 344                 udma_writel(priv, REGS_DMA_RX, UDMA_RX_BUFx_PTR_LO(x),
 345                             lower_32_bits(daddr));
 346                 udma_writel(priv, REGS_DMA_RX, UDMA_RX_BUFx_PTR_HI(x),
 347                             upper_32_bits(daddr));
 348                 daddr += RX_BUF_SIZE;
 349         }
 350
 351         daddr = priv->tx_addr;
 352         udma_writel(priv, REGS_DMA_TX, UDMA_TX_BUFx_PTR_LO(0),
 353                     lower_32_bits(daddr));
 354         udma_writel(priv, REGS_DMA_TX, UDMA_TX_BUFx_PTR_HI(0),
 355                     upper_32_bits(daddr));
 356         udma_writel(priv, REGS_DMA_TX, UDMA_TX_CTRL,
 357                     UDMA_TX_CTRL_NUM_BUF_USED_1);
 358
 359         /* clear all interrupts then enable them */
 360         udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_CLEAR, 0xffffffff);
 361         udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_MASK_CLEAR,
 362                 UDMA_RX_INTERRUPTS | UDMA_TX_INTERRUPTS);
 363
 364 }
 365
 366 static void start_rx_dma(struct uart_8250_port *p)
 367 {
 368         struct brcmuart_priv *priv = p->port.private_data;
 369         int x;
 370
 371         udma_unset(priv, REGS_DMA_RX, UDMA_RX_CTRL, UDMA_RX_CTRL_ENA);
 372
 373         /* Clear the RX ready bit for all buffers */
 374         for (x = 0; x < RX_BUFS_COUNT; x++)
 375                 udma_unset(priv, REGS_DMA_RX, UDMA_RX_BUFx_STATUS(x),
 376                         UDMA_RX_BUFX_STATUS_DATA_RDY);
 377
 378         /* always start with buffer 0 */
 379         udma_unset(priv, REGS_DMA_RX, UDMA_RX_STATUS,
 380                    UDMA_RX_STATUS_ACTIVE_BUF_MASK);
 381         priv->rx_next_buf = 0;
 382
 383         udma_set(priv, REGS_DMA_RX, UDMA_RX_CTRL, UDMA_RX_CTRL_ENA);
 384         priv->rx_running = true;
 385 }
 386
 387 static void stop_rx_dma(struct uart_8250_port *p)
 388 {
 389         struct brcmuart_priv *priv = p->port.private_data;
 390
 391         /* If RX is running, set the RX ABORT */
 392         if (priv->rx_running)
 393                 udma_set(priv, REGS_DMA_RX, UDMA_RX_CTRL, UDMA_RX_CTRL_ABORT);
 394 }
 395
 396 static int stop_tx_dma(struct uart_8250_port *p)
 397 {
 398         struct brcmuart_priv *priv = p->port.private_data;
 399         u32 value;
 400
 401         /* If TX is running, set the TX ABORT */
 402         value = udma_readl(priv, REGS_DMA_TX, UDMA_TX_CTRL);
 403         if (value & UDMA_TX_CTRL_ENA)
 404                 udma_set(priv, REGS_DMA_TX, UDMA_TX_CTRL, UDMA_TX_CTRL_ABORT);
 405         priv->tx_running = false;
 406         return 0;
 407 }
 408
 409 /*
 410  * NOTE: printk's in this routine will hang the system if this is
 411  * the console tty
 412  */
 413 static int brcmuart_tx_dma(struct uart_8250_port *p)
 414 {
 415         struct brcmuart_priv *priv = p->port.private_data;
 416         struct circ_buf *xmit = &p->port.state->xmit;
 417         u32 tx_size;
 418
 419         if (uart_tx_stopped(&p->port) || priv->tx_running ||
 420                 uart_circ_empty(xmit)) {
 421                 return 0;
 422         }
 423         tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 424
 425         priv->dma.tx_err = 0;
 426         memcpy(priv->tx_buf, &xmit->buf[xmit->tail], tx_size);
 427         xmit->tail += tx_size;
 428         xmit->tail &= UART_XMIT_SIZE - 1;
 429         p->port.icount.tx += tx_size;
 430
 431         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 432                 uart_write_wakeup(&p->port);
 433
 434         udma_writel(priv, REGS_DMA_TX, UDMA_TX_TRANSFER_LEN, tx_size);
 435         udma_writel(priv, REGS_DMA_TX, UDMA_TX_BUF0_DATA_LEN, tx_size);
 436         udma_unset(priv, REGS_DMA_TX, UDMA_TX_BUF0_STATUS, UDMA_TX_BUFX_EMPTY);
 437         udma_set(priv, REGS_DMA_TX, UDMA_TX_CTRL, UDMA_TX_CTRL_ENA);
 438         priv->tx_running = true;
 439
 440         return 0;
 441 }
 442
 443 static void brcmuart_rx_buf_done_isr(struct uart_port *up, int index)
 444 {
 445         struct brcmuart_priv *priv = up->private_data;
 446         struct tty_port *tty_port = &up->state->port;
 447         u32 status;
 448         u32 length;
 449         u32 copied;
 450
 451         /* Make sure we're still in sync with the hardware */
 452         status = udma_readl(priv, REGS_DMA_RX, UDMA_RX_BUFx_STATUS(index));
 453         length = udma_readl(priv, REGS_DMA_RX, UDMA_RX_BUFx_DATA_LEN(index));
 454
 455         if ((status & UDMA_RX_BUFX_STATUS_DATA_RDY) == 0) {
 456                 dev_err(up->dev, "RX done interrupt but DATA_RDY not found\n");
 457                 return;
 458         }
 459         if (status & (UDMA_RX_BUFX_STATUS_OVERRUN_ERR |
 460                       UDMA_RX_BUFX_STATUS_FRAME_ERR |
 461                       UDMA_RX_BUFX_STATUS_PARITY_ERR)) {
 462                 if (status & UDMA_RX_BUFX_STATUS_OVERRUN_ERR) {
 463                         up->icount.overrun++;
 464                         dev_warn(up->dev, "RX OVERRUN Error\n");
 465                 }
 466                 if (status & UDMA_RX_BUFX_STATUS_FRAME_ERR) {
 467                         up->icount.frame++;
 468                         dev_warn(up->dev, "RX FRAMING Error\n");
 469                 }
 470                 if (status & UDMA_RX_BUFX_STATUS_PARITY_ERR) {
 471                         up->icount.parity++;
 472                         dev_warn(up->dev, "RX PARITY Error\n");
 473                 }
 474         }
 475         copied = (u32)tty_insert_flip_string(
 476                 tty_port,
 477                 priv->rx_bufs + (index * RX_BUF_SIZE),
 478                 length);
 479         if (copied != length) {
 480                 dev_warn(up->dev, "Flip buffer overrun of %d bytes\n",
 481                          length - copied);
 482                 up->icount.overrun += length - copied;
 483         }
 484         up->icount.rx += length;
 485         if (status & UDMA_RX_BUFX_STATUS_CLOSE_EXPIRED)
 486                 priv->dma_rx_partial_buf++;
 487         else if (length != RX_BUF_SIZE)
 488                 /*
 489                  * This is a bug in the controller that doesn't cause
 490                  * any problems but will be fixed in the future.
 491                  */
 492                 priv->rx_missing_close_timeout++;
 493         else
 494                 priv->dma_rx_full_buf++;
 495
 496         tty_flip_buffer_push(tty_port);
 497 }
 498
 499 static void brcmuart_rx_isr(struct uart_port *up, u32 rx_isr)
 500 {
 501         struct brcmuart_priv *priv = up->private_data;
 502         struct device *dev = up->dev;
 503         u32 rx_done_isr;
 504         u32 check_isr;
 505
 506         rx_done_isr = (rx_isr & UDMA_INTR_RX_READY_MASK);
 507         while (rx_done_isr) {
 508                 check_isr = UDMA_INTR_RX_READY_BUF0 << priv->rx_next_buf;
 509                 if (check_isr & rx_done_isr) {
 510                         brcmuart_rx_buf_done_isr(up, priv->rx_next_buf);
 511                 } else {
 512                         dev_err(dev,
 513                                 "RX buffer ready out of sequence, restarting RX DMA\n");
 514                         start_rx_dma(up_to_u8250p(up));
 515                         break;
 516                 }
 517                 if (rx_isr & UDMA_RX_ERR_INTERRUPTS) {
 518                         if (rx_isr & UDMA_INTR_RX_ERROR)
 519                                 priv->rx_err++;
 520                         if (rx_isr & UDMA_INTR_RX_TIMEOUT) {
 521                                 priv->rx_timeout++;
 522                                 dev_err(dev, "RX TIMEOUT Error\n");
 523                         }
 524                         if (rx_isr & UDMA_INTR_RX_ABORT)
 525                                 priv->rx_abort++;
 526                         priv->rx_running = false;
 527                 }
 528                 /* If not ABORT, re-enable RX buffer */
 529                 if (!(rx_isr & UDMA_INTR_RX_ABORT))
 530                         udma_unset(priv, REGS_DMA_RX,
 531                                    UDMA_RX_BUFx_STATUS(priv->rx_next_buf),
 532                                    UDMA_RX_BUFX_STATUS_DATA_RDY);
 533                 rx_done_isr &= ~check_isr;
 534                 priv->rx_next_buf++;
 535                 if (priv->rx_next_buf == RX_BUFS_COUNT)
 536                         priv->rx_next_buf = 0;
 537         }
 538 }
 539
 540 static void brcmuart_tx_isr(struct uart_port *up, u32 isr)
 541 {
 542         struct brcmuart_priv *priv = up->private_data;
 543         struct device *dev = up->dev;
 544         struct uart_8250_port *port_8250 = up_to_u8250p(up);
 545         struct circ_buf *xmit = &port_8250->port.state->xmit;
 546
 547         if (isr & UDMA_INTR_TX_ABORT) {
 548                 if (priv->tx_running)
 549                         dev_err(dev, "Unexpected TX_ABORT interrupt\n");
 550                 return;
 551         }
 552         priv->tx_running = false;
 553         if (!uart_circ_empty(xmit) && !uart_tx_stopped(up))
 554                 brcmuart_tx_dma(port_8250);
 555 }
 556
 557 static irqreturn_t brcmuart_isr(int irq, void *dev_id)
 558 {
 559         struct uart_port *up = dev_id;
 560         struct device *dev = up->dev;
 561         struct brcmuart_priv *priv = up->private_data;
 562         unsigned long flags;
 563         u32 interrupts;
 564         u32 rval;
 565         u32 tval;
 566
 567         interrupts = udma_readl(priv, REGS_DMA_ISR, UDMA_INTR_STATUS);
 568         if (interrupts == 0)
 569                 return IRQ_NONE;
 570
 571         spin_lock_irqsave(&up->lock, flags);
 572
 573         /* Clear all interrupts */
 574         udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_CLEAR, interrupts);
 575
 576         rval = UDMA_IS_RX_INTERRUPT(interrupts);
 577         if (rval)
 578                 brcmuart_rx_isr(up, rval);
 579         tval = UDMA_IS_TX_INTERRUPT(interrupts);
 580         if (tval)
 581                 brcmuart_tx_isr(up, tval);
 582         if ((rval | tval) == 0)
 583                 dev_warn(dev, "Spurious interrupt: 0x%x\n", interrupts);
 584
 585         spin_unlock_irqrestore(&up->lock, flags);
 586         return IRQ_HANDLED;
 587 }
 588
 589 static int brcmuart_startup(struct uart_port *port)
 590 {
 591         int res;
 592         struct uart_8250_port *up = up_to_u8250p(port);
 593         struct brcmuart_priv *priv = up->port.private_data;
 594
 595         priv->shutdown = false;
 596
 597         /*
 598          * prevent serial8250_do_startup() from allocating non-existent
 599          * DMA resources
 600          */
 601         up->dma = NULL;
 602
 603         res = serial8250_do_startup(port);
 604         if (!priv->dma_enabled)
 605                 return res;
 606         /*
 607          * Disable the Receive Data Interrupt because the DMA engine
 608          * will handle this.
 609          */
 610         up->ier &= ~UART_IER_RDI;
 611         serial_port_out(port, UART_IER, up->ier);
 612
 613         priv->tx_running = false;
 614         priv->dma.rx_dma = NULL;
 615         priv->dma.tx_dma = brcmuart_tx_dma;
 616         up->dma = &priv->dma;
 617
 618         brcmuart_init_dma_hardware(priv);
 619         start_rx_dma(up);
 620         return res;
 621 }
 622
 623 static void brcmuart_shutdown(struct uart_port *port)
 624 {
 625         struct uart_8250_port *up = up_to_u8250p(port);
 626         struct brcmuart_priv *priv = up->port.private_data;
 627         unsigned long flags;
 628
 629         spin_lock_irqsave(&port->lock, flags);
 630         priv->shutdown = true;
 631         if (priv->dma_enabled) {
 632                 stop_rx_dma(up);
 633                 stop_tx_dma(up);
 634                 /* disable all interrupts */
 635                 udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_MASK_SET,
 636                         UDMA_RX_INTERRUPTS | UDMA_TX_INTERRUPTS);
 637         }
 638
 639         /*
 640          * prevent serial8250_do_shutdown() from trying to free
 641          * DMA resources that we never alloc'd for this driver.
 642          */
 643         up->dma = NULL;
 644
 645         spin_unlock_irqrestore(&port->lock, flags);
 646         serial8250_do_shutdown(port);
 647 }
 648
 649 /*
 650  * Not all clocks run at the exact specified rate, so set each requested
 651  * rate and then get the actual rate.
 652  */
 653 static void init_real_clk_rates(struct device *dev, struct brcmuart_priv *priv)
 654 {
 655         int x;
 656         int rc;
 657
 658         priv->default_mux_rate = clk_get_rate(priv->baud_mux_clk);
 659         for (x = 0; x < ARRAY_SIZE(priv->real_rates); x++) {
 660                 if (priv->rate_table[x] == 0) {
 661                         priv->real_rates[x] = 0;
 662                         continue;
 663                 }
 664                 rc = clk_set_rate(priv->baud_mux_clk, priv->rate_table[x]);
 665                 if (rc) {
 666                         dev_err(dev, "Error selecting BAUD MUX clock for %u\n",
 667                                 priv->rate_table[x]);
 668                         priv->real_rates[x] = priv->rate_table[x];
 669                 } else {
 670                         priv->real_rates[x] = clk_get_rate(priv->baud_mux_clk);
 671                 }
 672         }
 673         clk_set_rate(priv->baud_mux_clk, priv->default_mux_rate);
 674 }
 675
 676 static void set_clock_mux(struct uart_port *up, struct brcmuart_priv *priv,
 677                         u32 baud)
 678 {
 679         u32 percent;
 680         u32 best_percent = UINT_MAX;
 681         u32 quot;
 682         u32 best_quot = 1;
 683         u32 rate;
 684         int best_index = -1;
 685         u64 hires_rate;
 686         u64 hires_baud;
 687         u64 hires_err;
 688         int rc;
 689         int i;
 690         int real_baud;
 691
 692         /* If the Baud Mux Clock was not specified, just return */
 693         if (priv->baud_mux_clk == NULL)
 694                 return;
 695
 696         /* Find the closest match for specified baud */
 697         for (i = 0; i < ARRAY_SIZE(priv->real_rates); i++) {
 698                 if (priv->real_rates[i] == 0)
 699                         continue;
 700                 rate = priv->real_rates[i] / 16;
 701                 quot = DIV_ROUND_CLOSEST(rate, baud);
 702                 if (!quot)
 703                         continue;
 704
 705                 /* increase resolution to get xx.xx percent */
 706                 hires_rate = (u64)rate * 10000;
 707                 hires_baud = (u64)baud * 10000;
 708
 709                 hires_err = div_u64(hires_rate, (u64)quot);
 710
 711                 /* get the delta */
 712                 if (hires_err > hires_baud)
 713                         hires_err = (hires_err - hires_baud);
 714                 else
 715                         hires_err = (hires_baud - hires_err);
 716
 717                 percent = (unsigned long)DIV_ROUND_CLOSEST_ULL(hires_err, baud);
 718                 dev_dbg(up->dev,
 719                         "Baud rate: %u, MUX Clk: %u, Error: %u.%u%%\n",
 720                         baud, priv->real_rates[i], percent / 100,
 721                         percent % 100);
 722                 if (percent < best_percent) {
 723                         best_percent = percent;
 724                         best_index = i;
 725                         best_quot = quot;
 726                 }
 727         }
 728         if (best_index == -1) {
 729                 dev_err(up->dev, "Error, %d BAUD rate is too fast.\n", baud);
 730                 return;
 731         }
 732         rate = priv->real_rates[best_index];
 733         rc = clk_set_rate(priv->baud_mux_clk, rate);
 734         if (rc)
 735                 dev_err(up->dev, "Error selecting BAUD MUX clock\n");
 736
 737         /* Error over 3 percent will cause data errors */
 738         if (best_percent > 300)
 739                 dev_err(up->dev, "Error, baud: %d has %u.%u%% error\n",
 740                         baud, percent / 100, percent % 100);
 741
 742         real_baud = rate / 16 / best_quot;
 743         dev_dbg(up->dev, "Selecting BAUD MUX rate: %u\n", rate);
 744         dev_dbg(up->dev, "Requested baud: %u, Actual baud: %u\n",
 745                 baud, real_baud);
 746
 747         /* calc nanoseconds for 1.5 characters time at the given baud rate */
 748         i = NSEC_PER_SEC / real_baud / 10;
 749         i += (i / 2);
 750         priv->char_wait = ns_to_ktime(i);
 751
 752         up->uartclk = rate;
 753 }
 754
 755 static void brcmstb_set_termios(struct uart_port *up,
 756                                 struct ktermios *termios,
 757                                 struct ktermios *old)
 758 {
 759         struct uart_8250_port *p8250 = up_to_u8250p(up);
 760         struct brcmuart_priv *priv = up->private_data;
 761
 762         if (priv->dma_enabled)
 763                 stop_rx_dma(p8250);
 764         set_clock_mux(up, priv, tty_termios_baud_rate(termios));
 765         serial8250_do_set_termios(up, termios, old);
 766         if (p8250->mcr & UART_MCR_AFE)
 767                 p8250->port.status |= UPSTAT_AUTOCTS;
 768         if (priv->dma_enabled)
 769                 start_rx_dma(p8250);
 770 }
 771
 772 static int brcmuart_handle_irq(struct uart_port *p)
 773 {
 774         unsigned int iir = serial_port_in(p, UART_IIR);
 775         struct brcmuart_priv *priv = p->private_data;
 776         struct uart_8250_port *up = up_to_u8250p(p);
 777         unsigned int status;
 778         unsigned long flags;
 779         unsigned int ier;
 780         unsigned int mcr;
 781         int handled = 0;
 782
 783         /*
 784          * There's a bug in some 8250 cores where we get a timeout
 785          * interrupt but there is no data ready.
 786          */
 787         if (((iir & UART_IIR_ID) == UART_IIR_RX_TIMEOUT) && !(priv->shutdown)) {
 788                 spin_lock_irqsave(&p->lock, flags);
 789                 status = serial_port_in(p, UART_LSR);
 790                 if ((status & UART_LSR_DR) == 0) {
 791
 792                         ier = serial_port_in(p, UART_IER);
 793                         /*
 794                          * if Receive Data Interrupt is enabled and
 795                          * we're uing hardware flow control, deassert
 796                          * RTS and wait for any chars in the pipline to
 797                          * arrive and then check for DR again.
 798                          */
 799                         if ((ier & UART_IER_RDI) && (up->mcr & UART_MCR_AFE)) {
 800                                 ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 801                                 serial_port_out(p, UART_IER, ier);
 802                                 mcr = serial_port_in(p, UART_MCR);
 803                                 mcr &= ~UART_MCR_RTS;
 804                                 serial_port_out(p, UART_MCR, mcr);
 805                                 hrtimer_start(&priv->hrt, priv->char_wait,
 806                                               HRTIMER_MODE_REL);
 807                         } else {
 808                                 serial_port_in(p, UART_RX);
 809                         }
 810
 811                         handled = 1;
 812                 }
 813                 spin_unlock_irqrestore(&p->lock, flags);
 814                 if (handled)
 815                         return 1;
 816         }
 817         return serial8250_handle_irq(p, iir);
 818 }
 819
 820 static enum hrtimer_restart brcmuart_hrtimer_func(struct hrtimer *t)
 821 {
 822         struct brcmuart_priv *priv = container_of(t, struct brcmuart_priv, hrt);
 823         struct uart_port *p = priv->up;
 824         struct uart_8250_port *up = up_to_u8250p(p);
 825         unsigned int status;
 826         unsigned long flags;
 827
 828         if (priv->shutdown)
 829                 return HRTIMER_NORESTART;
 830
 831         spin_lock_irqsave(&p->lock, flags);
 832         status = serial_port_in(p, UART_LSR);
 833
 834         /*
 835          * If a character did not arrive after the timeout, clear the false
 836          * receive timeout.
 837          */
 838         if ((status & UART_LSR_DR) == 0) {
 839                 serial_port_in(p, UART_RX);
 840                 priv->rx_bad_timeout_no_char++;
 841         } else {
 842                 priv->rx_bad_timeout_late_char++;
 843         }
 844
 845         /* re-enable receive unless upper layer has disabled it */
 846         if ((up->ier & (UART_IER_RLSI | UART_IER_RDI)) ==
 847             (UART_IER_RLSI | UART_IER_RDI)) {
 848                 status = serial_port_in(p, UART_IER);
 849                 status |= (UART_IER_RLSI | UART_IER_RDI);
 850                 serial_port_out(p, UART_IER, status);
 851                 status = serial_port_in(p, UART_MCR);
 852                 status |= UART_MCR_RTS;
 853                 serial_port_out(p, UART_MCR, status);
 854         }
 855         spin_unlock_irqrestore(&p->lock, flags);
 856         return HRTIMER_NORESTART;
 857 }
 858
 859 static const struct of_device_id brcmuart_dt_ids[] = {
 860         {
 861                 .compatible = "brcm,bcm7278-uart",
 862                 .data = brcmstb_rate_table_7278,
 863         },
 864         {
 865                 .compatible = "brcm,bcm7271-uart",
 866                 .data = brcmstb_rate_table,
 867         },
 868         {},
 869 };
 870
 871 MODULE_DEVICE_TABLE(of, brcmuart_dt_ids);
 872
 873 static void brcmuart_free_bufs(struct device *dev, struct brcmuart_priv *priv)
 874 {
 875         if (priv->rx_bufs)
 876                 dma_free_coherent(dev, priv->rx_size, priv->rx_bufs,
 877                                   priv->rx_addr);
 878         if (priv->tx_buf)
 879                 dma_free_coherent(dev, priv->tx_size, priv->tx_buf,
 880                                   priv->tx_addr);
 881 }
 882
 883 static void brcmuart_throttle(struct uart_port *port)
 884 {
 885         struct brcmuart_priv *priv = port->private_data;
 886
 887         udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_MASK_SET, UDMA_RX_INTERRUPTS);
 888 }
 889
 890 static void brcmuart_unthrottle(struct uart_port *port)
 891 {
 892         struct brcmuart_priv *priv = port->private_data;
 893
 894         udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_MASK_CLEAR,
 895                     UDMA_RX_INTERRUPTS);
 896 }
 897
 898 static int debugfs_stats_show(struct seq_file *s, void *unused)
 899 {
 900         struct brcmuart_priv *priv = s->private;
 901
 902         seq_printf(s, "rx_err:\t\t\t\t%u\n",
 903                    priv->rx_err);
 904         seq_printf(s, "rx_timeout:\t\t\t%u\n",
 905                    priv->rx_timeout);
 906         seq_printf(s, "rx_abort:\t\t\t%u\n",
 907                    priv->rx_abort);
 908         seq_printf(s, "rx_bad_timeout_late_char:\t%u\n",
 909                    priv->rx_bad_timeout_late_char);
 910         seq_printf(s, "rx_bad_timeout_no_char:\t\t%u\n",
 911                    priv->rx_bad_timeout_no_char);
 912         seq_printf(s, "rx_missing_close_timeout:\t%u\n",
 913                    priv->rx_missing_close_timeout);
 914         if (priv->dma_enabled) {
 915                 seq_printf(s, "dma_rx_partial_buf:\t\t%llu\n",
 916                            priv->dma_rx_partial_buf);
 917                 seq_printf(s, "dma_rx_full_buf:\t\t%llu\n",
 918                            priv->dma_rx_full_buf);
 919         }
 920         return 0;
 921 }
 922 DEFINE_SHOW_ATTRIBUTE(debugfs_stats);
 923
 924 static void brcmuart_init_debugfs(struct brcmuart_priv *priv,
 925                                   const char *device)
 926 {
 927         priv->debugfs_dir = debugfs_create_dir(device, brcmuart_debugfs_root);
 928         debugfs_create_file("stats", 0444, priv->debugfs_dir, priv,
 929                             &debugfs_stats_fops);
 930 }
 931
 932
 933 static int brcmuart_probe(struct platform_device *pdev)
 934 {
 935         struct resource *regs;
 936         struct device_node *np = pdev->dev.of_node;
 937         const struct of_device_id *of_id = NULL;
 938         struct uart_8250_port *new_port;
 939         struct device *dev = &pdev->dev;
 940         struct brcmuart_priv *priv;
 941         struct clk *baud_mux_clk;
 942         struct uart_8250_port up;
 943         struct resource *irq;
 944         void __iomem *membase = 0;
 945         resource_size_t mapbase = 0;
 946         u32 clk_rate = 0;
 947         int ret;
 948         int x;
 949         int dma_irq;
 950         static const char * const reg_names[REGS_MAX] = {
 951                 "uart", "dma_rx", "dma_tx", "dma_intr2", "dma_arb"
 952         };
 953
 954         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 955         if (!irq) {
 956                 dev_err(dev, "missing irq\n");
 957                 return -EINVAL;
 958         }
 959         priv = devm_kzalloc(dev, sizeof(struct brcmuart_priv),
 960                         GFP_KERNEL);
 961         if (!priv)
 962                 return -ENOMEM;
 963
 964         of_id = of_match_node(brcmuart_dt_ids, np);
 965         if (!of_id || !of_id->data)
 966                 priv->rate_table = brcmstb_rate_table;
 967         else
 968                 priv->rate_table = of_id->data;
 969
 970         for (x = 0; x < REGS_MAX; x++) {
 971                 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 972                                                 reg_names[x]);
 973                 if (!regs)
 974                         break;
 975                 priv->regs[x] = devm_ioremap(dev, regs->start,
 976                                              resource_size(regs));
 977                 if (IS_ERR(priv->regs[x]))
 978                         return PTR_ERR(priv->regs[x]);
 979                 if (x == REGS_8250) {
 980                         mapbase = regs->start;
 981                         membase = priv->regs[x];
 982                 }
 983         }
 984
 985         /* We should have just the uart base registers or all the registers */
 986         if (x != 1 && x != REGS_MAX) {
 987                 dev_warn(dev, "%s registers not specified\n", reg_names[x]);
 988                 return -EINVAL;
 989         }
 990
 991         /* if the DMA registers were specified, try to enable DMA */
 992         if (x > REGS_DMA_RX) {
 993                 if (brcmuart_arbitration(priv, 1) == 0) {
 994                         u32 txrev = 0;
 995                         u32 rxrev = 0;
 996
 997                         txrev = udma_readl(priv, REGS_DMA_RX, UDMA_RX_REVISION);
 998                         rxrev = udma_readl(priv, REGS_DMA_TX, UDMA_TX_REVISION);
 999                         if ((txrev >= UDMA_TX_REVISION_REQUIRED) &&
1000                                 (rxrev >= UDMA_RX_REVISION_REQUIRED)) {
1001
1002                                 /* Enable the use of the DMA hardware */
1003                                 priv->dma_enabled = true;
1004                         } else {
1005                                 brcmuart_arbitration(priv, 0);
1006                                 dev_err(dev,
1007                                         "Unsupported DMA Hardware Revision\n");
1008                         }
1009                 } else {
1010                         dev_err(dev,
1011                                 "Timeout arbitrating for UART DMA hardware\n");
1012                 }
1013         }
1014
1015         of_property_read_u32(np, "clock-frequency", &clk_rate);
1016
1017         /* See if a Baud clock has been specified */
1018         baud_mux_clk = of_clk_get_by_name(np, "sw_baud");
1019         if (IS_ERR(baud_mux_clk)) {
1020                 if (PTR_ERR(baud_mux_clk) == -EPROBE_DEFER)
1021                         return -EPROBE_DEFER;
1022                 dev_dbg(dev, "BAUD MUX clock not specified\n");
1023         } else {
1024                 dev_dbg(dev, "BAUD MUX clock found\n");
1025                 ret = clk_prepare_enable(baud_mux_clk);
1026                 if (ret)
1027                         return ret;
1028                 priv->baud_mux_clk = baud_mux_clk;
1029                 init_real_clk_rates(dev, priv);
1030                 clk_rate = priv->default_mux_rate;
1031         }
1032
1033         if (clk_rate == 0) {
1034                 dev_err(dev, "clock-frequency or clk not defined\n");
1035                 return -EINVAL;
1036         }
1037
1038         dev_dbg(dev, "DMA is %senabled\n", priv->dma_enabled ? "" : "not ");
1039
1040         memset(&up, 0, sizeof(up));
1041         up.port.type = PORT_16550A;
1042         up.port.uartclk = clk_rate;
1043         up.port.dev = dev;
1044         up.port.mapbase = mapbase;
1045         up.port.membase = membase;
1046         up.port.irq = irq->start;
1047         up.port.handle_irq = brcmuart_handle_irq;
1048         up.port.regshift = 2;
1049         up.port.iotype = of_device_is_big_endian(np) ?
1050                 UPIO_MEM32BE : UPIO_MEM32;
1051         up.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF
1052                 | UPF_FIXED_PORT | UPF_FIXED_TYPE;
1053         up.port.dev = dev;
1054         up.port.private_data = priv;
1055         up.capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1056         up.port.fifosize = 32;
1057
1058         /* Check for a fixed line number */
1059         ret = of_alias_get_id(np, "serial");
1060         if (ret >= 0)
1061                 up.port.line = ret;
1062
1063         /* setup HR timer */
1064         hrtimer_init(&priv->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
1065         priv->hrt.function = brcmuart_hrtimer_func;
1066
1067         up.port.shutdown = brcmuart_shutdown;
1068         up.port.startup = brcmuart_startup;
1069         up.port.throttle = brcmuart_throttle;
1070         up.port.unthrottle = brcmuart_unthrottle;
1071         up.port.set_termios = brcmstb_set_termios;
1072
1073         if (priv->dma_enabled) {
1074                 priv->rx_size = RX_BUF_SIZE * RX_BUFS_COUNT;
1075                 priv->rx_bufs = dma_alloc_coherent(dev,
1076                                                    priv->rx_size,
1077                                                    &priv->rx_addr, GFP_KERNEL);
1078                 if (!priv->rx_bufs)
1079                         goto err;
1080                 priv->tx_size = UART_XMIT_SIZE;
1081                 priv->tx_buf = dma_alloc_coherent(dev,
1082                                                   priv->tx_size,
1083                                                   &priv->tx_addr, GFP_KERNEL);
1084                 if (!priv->tx_buf)
1085                         goto err;
1086         }
1087
1088         ret = serial8250_register_8250_port(&up);
1089         if (ret < 0) {
1090                 dev_err(dev, "unable to register 8250 port\n");
1091                 goto err;
1092         }
1093         priv->line = ret;
1094         new_port = serial8250_get_port(ret);
1095         priv->up = &new_port->port;
1096         if (priv->dma_enabled) {
1097                 dma_irq = platform_get_irq_byname(pdev,  "dma");
1098                 if (dma_irq < 0) {
1099                         dev_err(dev, "no IRQ resource info\n");
1100                         goto err1;
1101                 }
1102                 ret = devm_request_irq(dev, dma_irq, brcmuart_isr,
1103                                 IRQF_SHARED, "uart DMA irq", &new_port->port);
1104                 if (ret) {
1105                         dev_err(dev, "unable to register IRQ handler\n");
1106                         goto err1;
1107                 }
1108         }
1109         platform_set_drvdata(pdev, priv);
1110         brcmuart_init_debugfs(priv, dev_name(&pdev->dev));
1111         return 0;
1112
1113 err1:
1114         serial8250_unregister_port(priv->line);
1115 err:
1116         brcmuart_free_bufs(dev, priv);
1117         brcmuart_arbitration(priv, 0);
1118         return -ENODEV;
1119 }
1120
1121 static int brcmuart_remove(struct platform_device *pdev)
1122 {
1123         struct brcmuart_priv *priv = platform_get_drvdata(pdev);
1124
1125         debugfs_remove_recursive(priv->debugfs_dir);
1126         hrtimer_cancel(&priv->hrt);
1127         serial8250_unregister_port(priv->line);
1128         brcmuart_free_bufs(&pdev->dev, priv);
1129         brcmuart_arbitration(priv, 0);
1130         return 0;
1131 }
1132
1133 static int __maybe_unused brcmuart_suspend(struct device *dev)
1134 {
1135         struct brcmuart_priv *priv = dev_get_drvdata(dev);
1136
1137         serial8250_suspend_port(priv->line);
1138         clk_disable_unprepare(priv->baud_mux_clk);
1139
1140         return 0;
1141 }
1142
1143 static int __maybe_unused brcmuart_resume(struct device *dev)
1144 {
1145         struct brcmuart_priv *priv = dev_get_drvdata(dev);
1146         int ret;
1147
1148         ret = clk_prepare_enable(priv->baud_mux_clk);
1149         if (ret)
1150                 dev_err(dev, "Error enabling BAUD MUX clock\n");
1151
1152         /*
1153          * The hardware goes back to it's default after suspend
1154          * so get the "clk" back in sync.
1155          */
1156         ret = clk_set_rate(priv->baud_mux_clk, priv->default_mux_rate);
1157         if (ret)
1158                 dev_err(dev, "Error restoring default BAUD MUX clock\n");
1159         if (priv->dma_enabled) {
1160                 if (brcmuart_arbitration(priv, 1)) {
1161                         dev_err(dev, "Timeout arbitrating for DMA hardware on resume\n");
1162                         return(-EBUSY);
1163                 }
1164                 brcmuart_init_dma_hardware(priv);
1165                 start_rx_dma(serial8250_get_port(priv->line));
1166         }
1167         serial8250_resume_port(priv->line);
1168         return 0;
1169 }
1170
1171 static const struct dev_pm_ops brcmuart_dev_pm_ops = {
1172         SET_SYSTEM_SLEEP_PM_OPS(brcmuart_suspend, brcmuart_resume)
1173 };
1174
1175 static struct platform_driver brcmuart_platform_driver = {
1176         .driver = {
1177                 .name   = "bcm7271-uart",
1178                 .pm             = &brcmuart_dev_pm_ops,
1179                 .of_match_table = brcmuart_dt_ids,
1180         },
1181         .probe          = brcmuart_probe,
1182         .remove         = brcmuart_remove,
1183 };
1184
1185 static int __init brcmuart_init(void)
1186 {
1187         brcmuart_debugfs_root = debugfs_create_dir(
1188                 brcmuart_platform_driver.driver.name, NULL);
1189         return platform_driver_register(&brcmuart_platform_driver);
1190 }
1191 module_init(brcmuart_init);
1192
1193 static void __exit brcmuart_deinit(void)
1194 {
1195         platform_driver_unregister(&brcmuart_platform_driver);
1196         debugfs_remove_recursive(brcmuart_debugfs_root);
1197 }
1198 module_exit(brcmuart_deinit);
1199
1200 MODULE_AUTHOR("Al Cooper");
1201 MODULE_DESCRIPTION("Broadcom NS16550A compatible serial port driver");
1202 MODULE_LICENSE("GPL v2");