1 // SPDX-License-Identifier: GPL-2.0+
3 * mxser.c -- MOXA Smartio/Industio family multiport serial driver.
5 * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com).
6 * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com>
8 * This code is loosely based on the 1.8 moxa driver which is based on
9 * Linux serial driver, written by Linus Torvalds, Theodore T'so and
12 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
13 * <alan@lxorguk.ukuu.org.uk>. The original 1.8 code is available on
15 * - Fixed x86_64 cleanness
18 #include <linux/module.h>
19 #include <linux/errno.h>
20 #include <linux/signal.h>
21 #include <linux/sched.h>
22 #include <linux/timer.h>
23 #include <linux/interrupt.h>
24 #include <linux/tty.h>
25 #include <linux/tty_flip.h>
26 #include <linux/serial.h>
27 #include <linux/serial_reg.h>
28 #include <linux/major.h>
29 #include <linux/string.h>
30 #include <linux/fcntl.h>
31 #include <linux/ptrace.h>
32 #include <linux/ioport.h>
34 #include <linux/delay.h>
35 #include <linux/pci.h>
36 #include <linux/bitops.h>
37 #include <linux/slab.h>
38 #include <linux/ratelimit.h>
42 #include <linux/uaccess.h>
45 * Semi-public control interfaces
53 #define MOXA_SET_OP_MODE (MOXA + 66)
54 #define MOXA_GET_OP_MODE (MOXA + 67)
57 #define RS485_2WIRE_MODE 1
59 #define RS485_4WIRE_MODE 3
60 #define OP_MODE_MASK 3
62 /* --------------------------------------------------- */
65 * Follow just what Moxa Must chip defines.
67 * When LCR register (offset 0x03) is written the following value, the Must chip
68 * will enter enhanced mode. And a write to EFR (offset 0x02) bit 6,7 will
71 #define MOXA_MUST_ENTER_ENHANCED 0xBF
73 /* when enhanced mode is enabled, access to general bank register */
74 #define MOXA_MUST_GDL_REGISTER 0x07
75 #define MOXA_MUST_GDL_MASK 0x7F
76 #define MOXA_MUST_GDL_HAS_BAD_DATA 0x80
78 #define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */
79 /* enhanced register bank select and enhanced mode setting register */
80 /* This works only when LCR register equals to 0xBF */
81 #define MOXA_MUST_EFR_REGISTER 0x02
82 #define MOXA_MUST_EFR_EFRB_ENABLE 0x10 /* enhanced mode enable */
83 /* enhanced register bank set 0, 1, 2 */
84 #define MOXA_MUST_EFR_BANK0 0x00
85 #define MOXA_MUST_EFR_BANK1 0x40
86 #define MOXA_MUST_EFR_BANK2 0x80
87 #define MOXA_MUST_EFR_BANK3 0xC0
88 #define MOXA_MUST_EFR_BANK_MASK 0xC0
90 /* set XON1 value register, when LCR=0xBF and change to bank0 */
91 #define MOXA_MUST_XON1_REGISTER 0x04
93 /* set XON2 value register, when LCR=0xBF and change to bank0 */
94 #define MOXA_MUST_XON2_REGISTER 0x05
96 /* set XOFF1 value register, when LCR=0xBF and change to bank0 */
97 #define MOXA_MUST_XOFF1_REGISTER 0x06
99 /* set XOFF2 value register, when LCR=0xBF and change to bank0 */
100 #define MOXA_MUST_XOFF2_REGISTER 0x07
102 #define MOXA_MUST_RBRTL_REGISTER 0x04
103 #define MOXA_MUST_RBRTH_REGISTER 0x05
104 #define MOXA_MUST_RBRTI_REGISTER 0x06
105 #define MOXA_MUST_THRTL_REGISTER 0x07
106 #define MOXA_MUST_ENUM_REGISTER 0x04
107 #define MOXA_MUST_HWID_REGISTER 0x05
108 #define MOXA_MUST_ECR_REGISTER 0x06
109 #define MOXA_MUST_CSR_REGISTER 0x07
111 #define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 /* good data mode enable */
112 #define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 /* only good data put into RxFIFO */
114 #define MOXA_MUST_IER_ECTSI 0x80 /* enable CTS interrupt */
115 #define MOXA_MUST_IER_ERTSI 0x40 /* enable RTS interrupt */
116 #define MOXA_MUST_IER_XINT 0x20 /* enable Xon/Xoff interrupt */
117 #define MOXA_MUST_IER_EGDAI 0x10 /* enable GDA interrupt */
119 #define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI)
121 /* GDA interrupt pending */
122 #define MOXA_MUST_IIR_GDA 0x1C
123 #define MOXA_MUST_IIR_RDA 0x04
124 #define MOXA_MUST_IIR_RTO 0x0C
125 #define MOXA_MUST_IIR_LSR 0x06
127 /* received Xon/Xoff or specical interrupt pending */
128 #define MOXA_MUST_IIR_XSC 0x10
130 /* RTS/CTS change state interrupt pending */
131 #define MOXA_MUST_IIR_RTSCTS 0x20
132 #define MOXA_MUST_IIR_MASK 0x3E
134 #define MOXA_MUST_MCR_XON_FLAG 0x40
135 #define MOXA_MUST_MCR_XON_ANY 0x80
136 #define MOXA_MUST_MCR_TX_XON 0x08
138 #define MOXA_MUST_EFR_SF_MASK 0x0F /* software flow control on chip mask value */
139 #define MOXA_MUST_EFR_SF_TX1 0x08 /* send Xon1/Xoff1 */
140 #define MOXA_MUST_EFR_SF_TX2 0x04 /* send Xon2/Xoff2 */
141 #define MOXA_MUST_EFR_SF_TX12 0x0C /* send Xon1,Xon2/Xoff1,Xoff2 */
142 #define MOXA_MUST_EFR_SF_TX_NO 0x00 /* don't send Xon/Xoff */
143 #define MOXA_MUST_EFR_SF_TX_MASK 0x0C /* Tx software flow control mask */
144 #define MOXA_MUST_EFR_SF_RX_NO 0x00 /* don't receive Xon/Xoff */
145 #define MOXA_MUST_EFR_SF_RX1 0x02 /* receive Xon1/Xoff1 */
146 #define MOXA_MUST_EFR_SF_RX2 0x01 /* receive Xon2/Xoff2 */
147 #define MOXA_MUST_EFR_SF_RX12 0x03 /* receive Xon1,Xon2/Xoff1,Xoff2 */
148 #define MOXA_MUST_EFR_SF_RX_MASK 0x03 /* Rx software flow control mask */
150 #define MXSERMAJOR 174
152 #define MXSER_BOARDS 4 /* Max. boards */
153 #define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */
154 #define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
155 #define MXSER_ISR_PASS_LIMIT 100
157 #define WAKEUP_CHARS 256
159 #define MXSER_BAUD_BASE 921600
160 #define MXSER_CUSTOM_DIVISOR (MXSER_BAUD_BASE * 16)
162 #define PCI_DEVICE_ID_MOXA_RC7000 0x0001
163 #define PCI_DEVICE_ID_MOXA_CP102 0x1020
164 #define PCI_DEVICE_ID_MOXA_CP102UL 0x1021
165 #define PCI_DEVICE_ID_MOXA_CP102U 0x1022
166 #define PCI_DEVICE_ID_MOXA_CP102UF 0x1023
167 #define PCI_DEVICE_ID_MOXA_C104 0x1040
168 #define PCI_DEVICE_ID_MOXA_CP104U 0x1041
169 #define PCI_DEVICE_ID_MOXA_CP104JU 0x1042
170 #define PCI_DEVICE_ID_MOXA_CP104EL 0x1043
171 #define PCI_DEVICE_ID_MOXA_POS104UL 0x1044
172 #define PCI_DEVICE_ID_MOXA_CB108 0x1080
173 #define PCI_DEVICE_ID_MOXA_CP112UL 0x1120
174 #define PCI_DEVICE_ID_MOXA_CT114 0x1140
175 #define PCI_DEVICE_ID_MOXA_CP114 0x1141
176 #define PCI_DEVICE_ID_MOXA_CB114 0x1142
177 #define PCI_DEVICE_ID_MOXA_CP114UL 0x1143
178 #define PCI_DEVICE_ID_MOXA_CP118U 0x1180
179 #define PCI_DEVICE_ID_MOXA_CP118EL 0x1181
180 #define PCI_DEVICE_ID_MOXA_CP132 0x1320
181 #define PCI_DEVICE_ID_MOXA_CP132U 0x1321
182 #define PCI_DEVICE_ID_MOXA_CP134U 0x1340
183 #define PCI_DEVICE_ID_MOXA_CB134I 0x1341
184 #define PCI_DEVICE_ID_MOXA_CP138U 0x1380
185 #define PCI_DEVICE_ID_MOXA_C168 0x1680
186 #define PCI_DEVICE_ID_MOXA_CP168U 0x1681
187 #define PCI_DEVICE_ID_MOXA_CP168EL 0x1682
189 #define MXSER_NPORTS(ddata) ((ddata) & 0xffU)
190 #define MXSER_HIGHBAUD 0x0100
192 enum mxser_must_hwid {
193 MOXA_OTHER_UART = 0x00,
194 MOXA_MUST_MU150_HWID = 0x01,
195 MOXA_MUST_MU860_HWID = 0x02,
198 static const struct {
204 } Gpci_uart_info[] = {
205 { MOXA_OTHER_UART, 16, 14, 1, 921600 },
206 { MOXA_MUST_MU150_HWID, 64, 48, 16, 230400 },
207 { MOXA_MUST_MU860_HWID, 128, 96, 32, 921600 }
209 #define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info)
212 /* driver_data correspond to the lines in the structure above
213 see also ISA probe function before you change something */
214 static const struct pci_device_id mxser_pcibrds[] = {
215 { PCI_DEVICE_DATA(MOXA, C168, 8) },
216 { PCI_DEVICE_DATA(MOXA, C104, 4) },
217 { PCI_DEVICE_DATA(MOXA, CP132, 2) },
218 { PCI_DEVICE_DATA(MOXA, CP114, 4) },
219 { PCI_DEVICE_DATA(MOXA, CT114, 4) },
220 { PCI_DEVICE_DATA(MOXA, CP102, 2 | MXSER_HIGHBAUD) },
221 { PCI_DEVICE_DATA(MOXA, CP104U, 4) },
222 { PCI_DEVICE_DATA(MOXA, CP168U, 8) },
223 { PCI_DEVICE_DATA(MOXA, CP132U, 2) },
224 { PCI_DEVICE_DATA(MOXA, CP134U, 4) },
225 { PCI_DEVICE_DATA(MOXA, CP104JU, 4) },
226 { PCI_DEVICE_DATA(MOXA, RC7000, 8) }, /* RC7000 */
227 { PCI_DEVICE_DATA(MOXA, CP118U, 8) },
228 { PCI_DEVICE_DATA(MOXA, CP102UL, 2) },
229 { PCI_DEVICE_DATA(MOXA, CP102U, 2) },
230 { PCI_DEVICE_DATA(MOXA, CP118EL, 8) },
231 { PCI_DEVICE_DATA(MOXA, CP168EL, 8) },
232 { PCI_DEVICE_DATA(MOXA, CP104EL, 4) },
233 { PCI_DEVICE_DATA(MOXA, CB108, 8) },
234 { PCI_DEVICE_DATA(MOXA, CB114, 4) },
235 { PCI_DEVICE_DATA(MOXA, CB134I, 4) },
236 { PCI_DEVICE_DATA(MOXA, CP138U, 8) },
237 { PCI_DEVICE_DATA(MOXA, POS104UL, 4) },
238 { PCI_DEVICE_DATA(MOXA, CP114UL, 4) },
239 { PCI_DEVICE_DATA(MOXA, CP102UF, 2) },
240 { PCI_DEVICE_DATA(MOXA, CP112UL, 2) },
243 MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
245 static int ttymajor = MXSERMAJOR;
247 /* Variables for insmod */
249 MODULE_AUTHOR("Casper Yang");
250 MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
251 module_param(ttymajor, int, 0);
252 MODULE_LICENSE("GPL");
257 struct tty_port port;
258 struct mxser_board *board;
260 unsigned long ioaddr;
261 unsigned long opmode_ioaddr;
265 int type; /* UART type */
267 u8 x_char; /* xon/xoff character */
268 u8 IER; /* Interrupt Enable Register */
269 u8 MCR; /* Modem control register */
270 u8 FCR; /* FIFO control register */
272 struct async_icount icount; /* kernel counters for 4 input interrupts */
273 unsigned int timeout;
276 u8 ignore_status_mask;
284 unsigned short nports;
286 unsigned long vector;
288 enum mxser_must_hwid must_hwid;
291 struct mxser_port ports[] __counted_by(nports);
294 static DECLARE_BITMAP(mxser_boards, MXSER_BOARDS);
295 static struct tty_driver *mxvar_sdriver;
297 static u8 __mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set,
302 oldlcr = inb(baseio + UART_LCR);
303 outb(MOXA_MUST_ENTER_ENHANCED, baseio + UART_LCR);
305 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
309 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
312 outb(oldlcr, baseio + UART_LCR);
317 static u8 mxser_must_select_bank(unsigned long baseio, u8 bank)
319 return __mxser_must_set_EFR(baseio, MOXA_MUST_EFR_BANK_MASK, bank,
323 static void mxser_set_must_xon1_value(unsigned long baseio, u8 value)
325 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0);
326 outb(value, baseio + MOXA_MUST_XON1_REGISTER);
327 outb(oldlcr, baseio + UART_LCR);
330 static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value)
332 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0);
333 outb(value, baseio + MOXA_MUST_XOFF1_REGISTER);
334 outb(oldlcr, baseio + UART_LCR);
337 static void mxser_set_must_fifo_value(struct mxser_port *info)
339 u8 oldlcr = mxser_must_select_bank(info->ioaddr, MOXA_MUST_EFR_BANK1);
340 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER);
341 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTI_REGISTER);
342 outb(info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER);
343 outb(oldlcr, info->ioaddr + UART_LCR);
346 static void mxser_set_must_enum_value(unsigned long baseio, u8 value)
348 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2);
349 outb(value, baseio + MOXA_MUST_ENUM_REGISTER);
350 outb(oldlcr, baseio + UART_LCR);
353 static u8 mxser_get_must_hardware_id(unsigned long baseio)
355 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2);
356 u8 id = inb(baseio + MOXA_MUST_HWID_REGISTER);
357 outb(oldlcr, baseio + UART_LCR);
362 static void mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set)
364 __mxser_must_set_EFR(baseio, clear, set, true);
367 static void mxser_must_set_enhance_mode(unsigned long baseio, bool enable)
369 mxser_must_set_EFR(baseio,
370 enable ? 0 : MOXA_MUST_EFR_EFRB_ENABLE,
371 enable ? MOXA_MUST_EFR_EFRB_ENABLE : 0);
374 static void mxser_must_no_sw_flow_control(unsigned long baseio)
376 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_MASK, 0);
379 static void mxser_must_set_tx_sw_flow_control(unsigned long baseio, bool enable)
381 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_TX_MASK,
382 enable ? MOXA_MUST_EFR_SF_TX1 : 0);
385 static void mxser_must_set_rx_sw_flow_control(unsigned long baseio, bool enable)
387 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_RX_MASK,
388 enable ? MOXA_MUST_EFR_SF_RX1 : 0);
391 static enum mxser_must_hwid mxser_must_get_hwid(unsigned long io)
396 outb(0, io + UART_LCR);
397 mxser_must_set_enhance_mode(io, false);
398 oldmcr = inb(io + UART_MCR);
399 outb(0, io + UART_MCR);
400 mxser_set_must_xon1_value(io, 0x11);
401 if (inb(io + UART_MCR) != 0) {
402 outb(oldmcr, io + UART_MCR);
403 return MOXA_OTHER_UART;
406 hwid = mxser_get_must_hardware_id(io);
407 for (i = 1; i < UART_INFO_NUM; i++) /* 0 = OTHER_UART */
408 if (hwid == Gpci_uart_info[i].type)
411 return MOXA_OTHER_UART;
414 static bool mxser_16550A_or_MUST(struct mxser_port *info)
416 return info->type == PORT_16550A || info->board->must_hwid;
419 static void mxser_process_txrx_fifo(struct mxser_port *info)
423 if (info->type == PORT_16450 || info->type == PORT_8250) {
424 info->rx_high_water = 1;
425 info->rx_low_water = 1;
426 info->xmit_fifo_size = 1;
430 for (i = 0; i < UART_INFO_NUM; i++)
431 if (info->board->must_hwid == Gpci_uart_info[i].type) {
432 info->rx_low_water = Gpci_uart_info[i].rx_low_water;
433 info->rx_high_water = Gpci_uart_info[i].rx_high_water;
434 info->xmit_fifo_size = Gpci_uart_info[i].fifo_size;
439 static void __mxser_start_tx(struct mxser_port *info)
441 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
442 info->IER |= UART_IER_THRI;
443 outb(info->IER, info->ioaddr + UART_IER);
446 static void mxser_start_tx(struct mxser_port *info)
450 spin_lock_irqsave(&info->slock, flags);
451 __mxser_start_tx(info);
452 spin_unlock_irqrestore(&info->slock, flags);
455 static void __mxser_stop_tx(struct mxser_port *info)
457 info->IER &= ~UART_IER_THRI;
458 outb(info->IER, info->ioaddr + UART_IER);
461 static bool mxser_carrier_raised(struct tty_port *port)
463 struct mxser_port *mp = container_of(port, struct mxser_port, port);
465 return inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD;
468 static void mxser_dtr_rts(struct tty_port *port, bool active)
470 struct mxser_port *mp = container_of(port, struct mxser_port, port);
474 spin_lock_irqsave(&mp->slock, flags);
475 mcr = inb(mp->ioaddr + UART_MCR);
477 mcr |= UART_MCR_DTR | UART_MCR_RTS;
479 mcr &= ~(UART_MCR_DTR | UART_MCR_RTS);
480 outb(mcr, mp->ioaddr + UART_MCR);
481 spin_unlock_irqrestore(&mp->slock, flags);
484 static int mxser_set_baud(struct tty_struct *tty, speed_t newspd)
486 struct mxser_port *info = tty->driver_data;
487 unsigned int quot = 0, baud;
491 if (newspd > info->board->max_baud)
495 quot = 2 * MXSER_BAUD_BASE / 269;
496 tty_encode_baud_rate(tty, 134, 134);
498 quot = MXSER_BAUD_BASE / newspd;
501 baud = MXSER_BAUD_BASE / quot;
502 tty_encode_baud_rate(tty, baud, baud);
508 * worst case (128 * 1000 * 10 * 18432) needs 35 bits, so divide in the
511 timeout = (u64)info->xmit_fifo_size * HZ * 10 * quot;
512 do_div(timeout, MXSER_BAUD_BASE);
513 info->timeout = timeout + HZ / 50; /* Add .02 seconds of slop */
516 info->MCR |= UART_MCR_DTR;
517 outb(info->MCR, info->ioaddr + UART_MCR);
519 info->MCR &= ~UART_MCR_DTR;
520 outb(info->MCR, info->ioaddr + UART_MCR);
524 cval = inb(info->ioaddr + UART_LCR);
526 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */
528 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */
529 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */
530 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */
532 if (C_BAUD(tty) == BOTHER) {
533 quot = MXSER_BAUD_BASE % newspd;
535 if (quot % newspd > newspd / 2) {
541 mxser_set_must_enum_value(info->ioaddr, quot);
543 mxser_set_must_enum_value(info->ioaddr, 0);
549 static void mxser_handle_cts(struct tty_struct *tty, struct mxser_port *info,
552 bool cts = msr & UART_MSR_CTS;
554 if (tty->hw_stopped) {
556 tty->hw_stopped = false;
558 if (!mxser_16550A_or_MUST(info))
559 __mxser_start_tx(info);
566 tty->hw_stopped = true;
567 if (!mxser_16550A_or_MUST(info))
568 __mxser_stop_tx(info);
572 * This routine is called to set the UART divisor registers to match
573 * the specified baud rate for a serial port.
575 static void mxser_change_speed(struct tty_struct *tty,
576 const struct ktermios *old_termios)
578 struct mxser_port *info = tty->driver_data;
579 unsigned cflag, cval;
581 cflag = tty->termios.c_cflag;
583 if (mxser_set_baud(tty, tty_get_baud_rate(tty))) {
584 /* Use previous rate on a failure */
586 speed_t baud = tty_termios_baud_rate(old_termios);
587 tty_encode_baud_rate(tty, baud, baud);
591 /* byte size and parity */
592 cval = UART_LCR_WLEN(tty_get_char_size(tty->termios.c_cflag));
595 cval |= UART_LCR_STOP;
597 cval |= UART_LCR_PARITY;
598 if (!(cflag & PARODD))
599 cval |= UART_LCR_EPAR;
601 cval |= UART_LCR_SPAR;
604 if (info->board->must_hwid) {
605 info->FCR |= UART_FCR_ENABLE_FIFO |
606 MOXA_MUST_FCR_GDA_MODE_ENABLE;
607 mxser_set_must_fifo_value(info);
608 } else if (info->type != PORT_8250 && info->type != PORT_16450) {
609 info->FCR |= UART_FCR_ENABLE_FIFO;
610 switch (info->rx_high_water) {
612 info->FCR |= UART_FCR_TRIGGER_1;
615 info->FCR |= UART_FCR_TRIGGER_4;
618 info->FCR |= UART_FCR_TRIGGER_8;
621 info->FCR |= UART_FCR_TRIGGER_14;
626 /* CTS flow control flag and modem status interrupts */
627 info->IER &= ~UART_IER_MSI;
628 info->MCR &= ~UART_MCR_AFE;
629 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
630 if (cflag & CRTSCTS) {
631 info->IER |= UART_IER_MSI;
632 if (mxser_16550A_or_MUST(info)) {
633 info->MCR |= UART_MCR_AFE;
635 mxser_handle_cts(tty, info,
636 inb(info->ioaddr + UART_MSR));
639 outb(info->MCR, info->ioaddr + UART_MCR);
640 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
642 info->IER |= UART_IER_MSI;
643 outb(info->IER, info->ioaddr + UART_IER);
646 * Set up parity check flag
648 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
650 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
651 if (I_BRKINT(tty) || I_PARMRK(tty))
652 info->read_status_mask |= UART_LSR_BI;
654 info->ignore_status_mask = 0;
657 info->ignore_status_mask |= UART_LSR_BI;
658 info->read_status_mask |= UART_LSR_BI;
660 * If we're ignore parity and break indicators, ignore
661 * overruns too. (For real raw support).
664 info->ignore_status_mask |=
668 info->read_status_mask |=
674 if (info->board->must_hwid) {
675 mxser_set_must_xon1_value(info->ioaddr, START_CHAR(tty));
676 mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(tty));
677 mxser_must_set_rx_sw_flow_control(info->ioaddr, I_IXON(tty));
678 mxser_must_set_tx_sw_flow_control(info->ioaddr, I_IXOFF(tty));
682 outb(info->FCR, info->ioaddr + UART_FCR);
683 outb(cval, info->ioaddr + UART_LCR);
686 static u8 mxser_check_modem_status(struct tty_struct *tty,
687 struct mxser_port *port)
689 u8 msr = inb(port->ioaddr + UART_MSR);
691 if (!(msr & UART_MSR_ANY_DELTA))
694 /* update input line counters */
695 if (msr & UART_MSR_TERI)
697 if (msr & UART_MSR_DDSR)
699 if (msr & UART_MSR_DDCD)
701 if (msr & UART_MSR_DCTS)
703 wake_up_interruptible(&port->port.delta_msr_wait);
705 if (tty_port_check_carrier(&port->port) && (msr & UART_MSR_DDCD)) {
706 if (msr & UART_MSR_DCD)
707 wake_up_interruptible(&port->port.open_wait);
710 if (tty_port_cts_enabled(&port->port))
711 mxser_handle_cts(tty, port, msr);
716 static void mxser_disable_and_clear_FIFO(struct mxser_port *info)
718 u8 fcr = UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT;
720 if (info->board->must_hwid)
721 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
723 outb(fcr, info->ioaddr + UART_FCR);
726 static int mxser_activate(struct tty_port *port, struct tty_struct *tty)
728 struct mxser_port *info = container_of(port, struct mxser_port, port);
732 ret = tty_port_alloc_xmit_buf(port);
736 spin_lock_irqsave(&info->slock, flags);
739 set_bit(TTY_IO_ERROR, &tty->flags);
740 spin_unlock_irqrestore(&info->slock, flags);
746 * Clear the FIFO buffers and disable them
747 * (they will be reenabled in mxser_change_speed())
749 mxser_disable_and_clear_FIFO(info);
752 * At this point there's no way the LSR could still be 0xFF;
753 * if it is, then bail out, because there's likely no UART
756 if (inb(info->ioaddr + UART_LSR) == 0xff) {
757 spin_unlock_irqrestore(&info->slock, flags);
758 if (capable(CAP_SYS_ADMIN)) {
759 set_bit(TTY_IO_ERROR, &tty->flags);
768 * Clear the interrupt registers.
770 (void) inb(info->ioaddr + UART_LSR);
771 (void) inb(info->ioaddr + UART_RX);
772 (void) inb(info->ioaddr + UART_IIR);
773 (void) inb(info->ioaddr + UART_MSR);
776 * Now, initialize the UART
778 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */
779 info->MCR = UART_MCR_DTR | UART_MCR_RTS;
780 outb(info->MCR, info->ioaddr + UART_MCR);
783 * Finally, enable interrupts
785 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
787 if (info->board->must_hwid)
788 info->IER |= MOXA_MUST_IER_EGDAI;
789 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */
792 * And clear the interrupt registers again for luck.
794 (void) inb(info->ioaddr + UART_LSR);
795 (void) inb(info->ioaddr + UART_RX);
796 (void) inb(info->ioaddr + UART_IIR);
797 (void) inb(info->ioaddr + UART_MSR);
799 clear_bit(TTY_IO_ERROR, &tty->flags);
800 kfifo_reset(&port->xmit_fifo);
803 * and set the speed of the serial port
805 mxser_change_speed(tty, NULL);
806 spin_unlock_irqrestore(&info->slock, flags);
810 tty_port_free_xmit_buf(port);
815 * To stop accepting input, we disable the receive line status interrupts, and
816 * tell the interrupt driver to stop checking the data ready bit in the line
819 static void mxser_stop_rx(struct mxser_port *info)
821 info->IER &= ~UART_IER_RLSI;
822 if (info->board->must_hwid)
823 info->IER &= ~MOXA_MUST_RECV_ISR;
825 outb(info->IER, info->ioaddr + UART_IER);
829 * This routine will shutdown a serial port
831 static void mxser_shutdown_port(struct tty_port *port)
833 struct mxser_port *info = container_of(port, struct mxser_port, port);
836 spin_lock_irqsave(&info->slock, flags);
841 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
842 * here so the queue might never be waken up
844 wake_up_interruptible(&info->port.delta_msr_wait);
847 outb(0x00, info->ioaddr + UART_IER);
849 /* clear Rx/Tx FIFO's */
850 mxser_disable_and_clear_FIFO(info);
852 /* read data port to reset things */
853 (void) inb(info->ioaddr + UART_RX);
856 if (info->board->must_hwid)
857 mxser_must_no_sw_flow_control(info->ioaddr);
859 spin_unlock_irqrestore(&info->slock, flags);
861 /* make sure ISR is not running while we free the buffer */
862 synchronize_irq(info->board->irq);
864 tty_port_free_xmit_buf(port);
868 * This routine is called whenever a serial port is opened. It
869 * enables interrupts for a serial port, linking in its async structure into
870 * the IRQ chain. It also performs the serial-specific
871 * initialization for the tty structure.
873 static int mxser_open(struct tty_struct *tty, struct file *filp)
875 struct tty_port *tport = tty->port;
876 struct mxser_port *port = container_of(tport, struct mxser_port, port);
878 tty->driver_data = port;
880 return tty_port_open(tport, tty, filp);
883 static void mxser_flush_buffer(struct tty_struct *tty)
885 struct mxser_port *info = tty->driver_data;
888 spin_lock_irqsave(&info->slock, flags);
889 kfifo_reset(&info->port.xmit_fifo);
891 outb(info->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
892 info->ioaddr + UART_FCR);
894 spin_unlock_irqrestore(&info->slock, flags);
899 static void mxser_close(struct tty_struct *tty, struct file *filp)
901 tty_port_close(tty->port, tty, filp);
904 static ssize_t mxser_write(struct tty_struct *tty, const u8 *buf, size_t count)
906 struct mxser_port *info = tty->driver_data;
911 spin_lock_irqsave(&info->slock, flags);
912 written = kfifo_in(&info->port.xmit_fifo, buf, count);
913 is_empty = kfifo_is_empty(&info->port.xmit_fifo);
914 spin_unlock_irqrestore(&info->slock, flags);
916 if (!is_empty && !tty->flow.stopped)
917 if (!tty->hw_stopped || mxser_16550A_or_MUST(info))
918 mxser_start_tx(info);
923 static int mxser_put_char(struct tty_struct *tty, u8 ch)
925 struct mxser_port *info = tty->driver_data;
929 spin_lock_irqsave(&info->slock, flags);
930 ret = kfifo_put(&info->port.xmit_fifo, ch);
931 spin_unlock_irqrestore(&info->slock, flags);
937 static void mxser_flush_chars(struct tty_struct *tty)
939 struct mxser_port *info = tty->driver_data;
941 if (kfifo_is_empty(&info->port.xmit_fifo) || tty->flow.stopped ||
942 (tty->hw_stopped && !mxser_16550A_or_MUST(info)))
945 mxser_start_tx(info);
948 static unsigned int mxser_write_room(struct tty_struct *tty)
950 struct mxser_port *info = tty->driver_data;
952 return kfifo_avail(&info->port.xmit_fifo);
955 static unsigned int mxser_chars_in_buffer(struct tty_struct *tty)
957 struct mxser_port *info = tty->driver_data;
959 return kfifo_len(&info->port.xmit_fifo);
963 * ------------------------------------------------------------
964 * friends of mxser_ioctl()
965 * ------------------------------------------------------------
967 static int mxser_get_serial_info(struct tty_struct *tty,
968 struct serial_struct *ss)
970 struct mxser_port *info = tty->driver_data;
971 struct tty_port *port = &info->port;
972 unsigned int closing_wait, close_delay;
974 mutex_lock(&port->mutex);
976 close_delay = jiffies_to_msecs(info->port.close_delay) / 10;
977 closing_wait = info->port.closing_wait;
978 if (closing_wait != ASYNC_CLOSING_WAIT_NONE)
979 closing_wait = jiffies_to_msecs(closing_wait) / 10;
981 ss->type = info->type;
982 ss->line = tty->index;
983 ss->port = info->ioaddr;
984 ss->irq = info->board->irq;
985 ss->flags = info->port.flags;
986 ss->baud_base = MXSER_BAUD_BASE;
987 ss->close_delay = close_delay;
988 ss->closing_wait = closing_wait;
989 ss->custom_divisor = MXSER_CUSTOM_DIVISOR,
990 mutex_unlock(&port->mutex);
994 static int mxser_set_serial_info(struct tty_struct *tty,
995 struct serial_struct *ss)
997 struct mxser_port *info = tty->driver_data;
998 struct tty_port *port = &info->port;
1000 unsigned long sl_flags;
1001 unsigned int old_speed, close_delay, closing_wait;
1004 if (tty_io_error(tty))
1007 mutex_lock(&port->mutex);
1009 if (ss->irq != info->board->irq ||
1010 ss->port != info->ioaddr) {
1011 mutex_unlock(&port->mutex);
1015 old_speed = port->flags & ASYNC_SPD_MASK;
1017 close_delay = msecs_to_jiffies(ss->close_delay * 10);
1018 closing_wait = ss->closing_wait;
1019 if (closing_wait != ASYNC_CLOSING_WAIT_NONE)
1020 closing_wait = msecs_to_jiffies(closing_wait * 10);
1022 if (!capable(CAP_SYS_ADMIN)) {
1023 if ((ss->baud_base != MXSER_BAUD_BASE) ||
1024 (close_delay != port->close_delay) ||
1025 (closing_wait != port->closing_wait) ||
1026 ((ss->flags & ~ASYNC_USR_MASK) != (port->flags & ~ASYNC_USR_MASK))) {
1027 mutex_unlock(&port->mutex);
1030 port->flags = (port->flags & ~ASYNC_USR_MASK) |
1031 (ss->flags & ASYNC_USR_MASK);
1034 * OK, past this point, all the error checking has been done.
1035 * At this point, we start making changes.....
1037 port->flags = ((port->flags & ~ASYNC_FLAGS) |
1038 (ss->flags & ASYNC_FLAGS));
1039 port->close_delay = close_delay;
1040 port->closing_wait = closing_wait;
1041 if ((port->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST &&
1042 (ss->baud_base != MXSER_BAUD_BASE ||
1043 ss->custom_divisor !=
1044 MXSER_CUSTOM_DIVISOR)) {
1045 if (ss->custom_divisor == 0) {
1046 mutex_unlock(&port->mutex);
1049 baud = ss->baud_base / ss->custom_divisor;
1050 tty_encode_baud_rate(tty, baud, baud);
1053 info->type = ss->type;
1055 mxser_process_txrx_fifo(info);
1058 if (tty_port_initialized(port)) {
1059 if (old_speed != (port->flags & ASYNC_SPD_MASK)) {
1060 spin_lock_irqsave(&info->slock, sl_flags);
1061 mxser_change_speed(tty, NULL);
1062 spin_unlock_irqrestore(&info->slock, sl_flags);
1065 retval = mxser_activate(port, tty);
1067 tty_port_set_initialized(port, true);
1069 mutex_unlock(&port->mutex);
1074 * mxser_get_lsr_info - get line status register info
1076 * Purpose: Let user call ioctl() to get info when the UART physically
1077 * is emptied. On bus types like RS485, the transmitter must
1078 * release the bus after transmitting. This must be done when
1079 * the transmit shift register is empty, not be done when the
1080 * transmit holding register is empty. This functionality
1081 * allows an RS485 driver to be written in user space.
1083 static int mxser_get_lsr_info(struct mxser_port *info,
1084 unsigned int __user *value)
1086 unsigned char status;
1087 unsigned int result;
1088 unsigned long flags;
1090 spin_lock_irqsave(&info->slock, flags);
1091 status = inb(info->ioaddr + UART_LSR);
1092 spin_unlock_irqrestore(&info->slock, flags);
1093 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
1094 return put_user(result, value);
1097 static int mxser_tiocmget(struct tty_struct *tty)
1099 struct mxser_port *info = tty->driver_data;
1100 unsigned char control;
1101 unsigned long flags;
1104 if (tty_io_error(tty))
1107 spin_lock_irqsave(&info->slock, flags);
1108 control = info->MCR;
1109 msr = mxser_check_modem_status(tty, info);
1110 spin_unlock_irqrestore(&info->slock, flags);
1112 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
1113 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
1114 ((msr & UART_MSR_DCD) ? TIOCM_CAR : 0) |
1115 ((msr & UART_MSR_RI) ? TIOCM_RNG : 0) |
1116 ((msr & UART_MSR_DSR) ? TIOCM_DSR : 0) |
1117 ((msr & UART_MSR_CTS) ? TIOCM_CTS : 0);
1120 static int mxser_tiocmset(struct tty_struct *tty,
1121 unsigned int set, unsigned int clear)
1123 struct mxser_port *info = tty->driver_data;
1124 unsigned long flags;
1126 if (tty_io_error(tty))
1129 spin_lock_irqsave(&info->slock, flags);
1131 if (set & TIOCM_RTS)
1132 info->MCR |= UART_MCR_RTS;
1133 if (set & TIOCM_DTR)
1134 info->MCR |= UART_MCR_DTR;
1136 if (clear & TIOCM_RTS)
1137 info->MCR &= ~UART_MCR_RTS;
1138 if (clear & TIOCM_DTR)
1139 info->MCR &= ~UART_MCR_DTR;
1141 outb(info->MCR, info->ioaddr + UART_MCR);
1142 spin_unlock_irqrestore(&info->slock, flags);
1146 static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg,
1147 struct async_icount *cprev)
1149 struct async_icount cnow;
1150 unsigned long flags;
1153 spin_lock_irqsave(&info->slock, flags);
1154 cnow = info->icount; /* atomic copy */
1155 spin_unlock_irqrestore(&info->slock, flags);
1157 ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) ||
1158 ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) ||
1159 ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) ||
1160 ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts));
1167 /* We should likely switch to TIOCGRS485/TIOCSRS485. */
1168 static int mxser_ioctl_op_mode(struct mxser_port *port, int index, bool set,
1169 int __user *u_opmode)
1171 int opmode, p = index % 4;
1172 int shiftbit = p * 2;
1175 if (port->board->must_hwid != MOXA_MUST_MU860_HWID)
1179 if (get_user(opmode, u_opmode))
1182 if (opmode & ~OP_MODE_MASK)
1185 spin_lock_irq(&port->slock);
1186 val = inb(port->opmode_ioaddr);
1187 val &= ~(OP_MODE_MASK << shiftbit);
1188 val |= (opmode << shiftbit);
1189 outb(val, port->opmode_ioaddr);
1190 spin_unlock_irq(&port->slock);
1195 spin_lock_irq(&port->slock);
1196 opmode = inb(port->opmode_ioaddr) >> shiftbit;
1197 spin_unlock_irq(&port->slock);
1199 return put_user(opmode & OP_MODE_MASK, u_opmode);
1202 static int mxser_ioctl(struct tty_struct *tty,
1203 unsigned int cmd, unsigned long arg)
1205 struct mxser_port *info = tty->driver_data;
1206 struct async_icount cnow;
1207 unsigned long flags;
1208 void __user *argp = (void __user *)arg;
1210 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE)
1211 return mxser_ioctl_op_mode(info, tty->index,
1212 cmd == MOXA_SET_OP_MODE, argp);
1214 if (cmd != TIOCMIWAIT && tty_io_error(tty))
1218 case TIOCSERGETLSR: /* Get line status register */
1219 return mxser_get_lsr_info(info, argp);
1221 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
1222 * - mask passed in arg for lines of interest
1223 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
1224 * Caller should use TIOCGICOUNT to see which one it was
1227 spin_lock_irqsave(&info->slock, flags);
1228 cnow = info->icount; /* note the counters on entry */
1229 spin_unlock_irqrestore(&info->slock, flags);
1231 return wait_event_interruptible(info->port.delta_msr_wait,
1232 mxser_cflags_changed(info, arg, &cnow));
1234 return -ENOIOCTLCMD;
1240 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1241 * Return: write counters to the user passed counter struct
1242 * NB: both 1->0 and 0->1 transitions are counted except for
1243 * RI where only 0->1 is counted.
1246 static int mxser_get_icount(struct tty_struct *tty,
1247 struct serial_icounter_struct *icount)
1250 struct mxser_port *info = tty->driver_data;
1251 struct async_icount cnow;
1252 unsigned long flags;
1254 spin_lock_irqsave(&info->slock, flags);
1255 cnow = info->icount;
1256 spin_unlock_irqrestore(&info->slock, flags);
1258 icount->frame = cnow.frame;
1259 icount->brk = cnow.brk;
1260 icount->overrun = cnow.overrun;
1261 icount->buf_overrun = cnow.buf_overrun;
1262 icount->parity = cnow.parity;
1263 icount->rx = cnow.rx;
1264 icount->tx = cnow.tx;
1265 icount->cts = cnow.cts;
1266 icount->dsr = cnow.dsr;
1267 icount->rng = cnow.rng;
1268 icount->dcd = cnow.dcd;
1273 * This routine is called by the upper-layer tty layer to signal that
1274 * incoming characters should be throttled.
1276 static void mxser_throttle(struct tty_struct *tty)
1278 struct mxser_port *info = tty->driver_data;
1281 if (info->board->must_hwid) {
1282 info->IER &= ~MOXA_MUST_RECV_ISR;
1283 outb(info->IER, info->ioaddr + UART_IER);
1285 info->x_char = STOP_CHAR(tty);
1286 outb(0, info->ioaddr + UART_IER);
1287 info->IER |= UART_IER_THRI;
1288 outb(info->IER, info->ioaddr + UART_IER);
1292 if (C_CRTSCTS(tty)) {
1293 info->MCR &= ~UART_MCR_RTS;
1294 outb(info->MCR, info->ioaddr + UART_MCR);
1298 static void mxser_unthrottle(struct tty_struct *tty)
1300 struct mxser_port *info = tty->driver_data;
1307 if (info->board->must_hwid) {
1308 info->IER |= MOXA_MUST_RECV_ISR;
1309 outb(info->IER, info->ioaddr + UART_IER);
1311 info->x_char = START_CHAR(tty);
1312 outb(0, info->ioaddr + UART_IER);
1313 info->IER |= UART_IER_THRI;
1314 outb(info->IER, info->ioaddr + UART_IER);
1319 if (C_CRTSCTS(tty)) {
1320 info->MCR |= UART_MCR_RTS;
1321 outb(info->MCR, info->ioaddr + UART_MCR);
1326 * mxser_stop() and mxser_start()
1328 * This routines are called before setting or resetting tty->flow.stopped.
1329 * They enable or disable transmitter interrupts, as necessary.
1331 static void mxser_stop(struct tty_struct *tty)
1333 struct mxser_port *info = tty->driver_data;
1334 unsigned long flags;
1336 spin_lock_irqsave(&info->slock, flags);
1337 if (info->IER & UART_IER_THRI)
1338 __mxser_stop_tx(info);
1339 spin_unlock_irqrestore(&info->slock, flags);
1342 static void mxser_start(struct tty_struct *tty)
1344 struct mxser_port *info = tty->driver_data;
1345 unsigned long flags;
1347 spin_lock_irqsave(&info->slock, flags);
1348 if (!kfifo_is_empty(&info->port.xmit_fifo))
1349 __mxser_start_tx(info);
1350 spin_unlock_irqrestore(&info->slock, flags);
1353 static void mxser_set_termios(struct tty_struct *tty,
1354 const struct ktermios *old_termios)
1356 struct mxser_port *info = tty->driver_data;
1357 unsigned long flags;
1359 spin_lock_irqsave(&info->slock, flags);
1360 mxser_change_speed(tty, old_termios);
1361 spin_unlock_irqrestore(&info->slock, flags);
1363 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
1364 tty->hw_stopped = false;
1368 /* Handle sw stopped */
1369 if ((old_termios->c_iflag & IXON) && !I_IXON(tty)) {
1370 tty->flow.stopped = 0;
1372 if (info->board->must_hwid) {
1373 spin_lock_irqsave(&info->slock, flags);
1374 mxser_must_set_rx_sw_flow_control(info->ioaddr, false);
1375 spin_unlock_irqrestore(&info->slock, flags);
1382 static bool mxser_tx_empty(struct mxser_port *info)
1384 unsigned long flags;
1387 spin_lock_irqsave(&info->slock, flags);
1388 lsr = inb(info->ioaddr + UART_LSR);
1389 spin_unlock_irqrestore(&info->slock, flags);
1391 return !(lsr & UART_LSR_TEMT);
1395 * mxser_wait_until_sent() --- wait until the transmitter is empty
1397 static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
1399 struct mxser_port *info = tty->driver_data;
1400 unsigned long expire, char_time;
1402 if (info->type == PORT_UNKNOWN)
1405 if (info->xmit_fifo_size == 0)
1406 return; /* Just in case.... */
1409 * Set the check interval to be 1/5 of the estimated time to
1410 * send a single character, and make it at least 1. The check
1411 * interval should also be less than the timeout.
1413 * Note: we have to use pretty tight timings here to satisfy
1416 char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size;
1417 char_time = char_time / 5;
1420 if (timeout && timeout < char_time)
1421 char_time = timeout;
1423 char_time = jiffies_to_msecs(char_time);
1426 * If the transmitter hasn't cleared in twice the approximate
1427 * amount of time to send the entire FIFO, it probably won't
1428 * ever clear. This assumes the UART isn't doing flow
1429 * control, which is currently the case. Hence, if it ever
1430 * takes longer than info->timeout, this is probably due to a
1431 * UART bug of some kind. So, we clamp the timeout parameter at
1434 if (!timeout || timeout > 2 * info->timeout)
1435 timeout = 2 * info->timeout;
1437 expire = jiffies + timeout;
1439 while (mxser_tx_empty(info)) {
1440 msleep_interruptible(char_time);
1441 if (signal_pending(current))
1443 if (time_after(jiffies, expire))
1449 * This routine is called by tty_hangup() when a hangup is signaled.
1451 static void mxser_hangup(struct tty_struct *tty)
1453 struct mxser_port *info = tty->driver_data;
1455 mxser_flush_buffer(tty);
1456 tty_port_hangup(&info->port);
1460 * mxser_rs_break() --- routine which turns the break handling on or off
1462 static int mxser_rs_break(struct tty_struct *tty, int break_state)
1464 struct mxser_port *info = tty->driver_data;
1465 unsigned long flags;
1468 spin_lock_irqsave(&info->slock, flags);
1469 lcr = inb(info->ioaddr + UART_LCR);
1470 if (break_state == -1)
1471 lcr |= UART_LCR_SBC;
1473 lcr &= ~UART_LCR_SBC;
1474 outb(lcr, info->ioaddr + UART_LCR);
1475 spin_unlock_irqrestore(&info->slock, flags);
1480 static bool mxser_receive_chars_new(struct mxser_port *port, u8 status)
1482 enum mxser_must_hwid hwid = port->board->must_hwid;
1485 if (hwid == MOXA_OTHER_UART)
1487 if (status & (UART_LSR_BRK_ERROR_BITS | MOXA_MUST_LSR_RERR))
1490 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER);
1491 if (hwid == MOXA_MUST_MU150_HWID)
1492 gdl &= MOXA_MUST_GDL_MASK;
1495 u8 ch = inb(port->ioaddr + UART_RX);
1496 if (!tty_insert_flip_char(&port->port, ch, 0))
1497 port->icount.buf_overrun++;
1503 static u8 mxser_receive_chars_old(struct tty_struct *tty,
1504 struct mxser_port *port, u8 status)
1506 enum mxser_must_hwid hwid = port->board->must_hwid;
1515 ch = inb(port->ioaddr + UART_RX);
1516 if (hwid && (status & UART_LSR_OE))
1517 outb(port->FCR | UART_FCR_CLEAR_RCVR,
1518 port->ioaddr + UART_FCR);
1519 status &= port->read_status_mask;
1520 if (status & port->ignore_status_mask) {
1521 if (++ignored > 100)
1525 if (status & UART_LSR_BRK_ERROR_BITS) {
1526 if (status & UART_LSR_BI) {
1530 if (port->port.flags & ASYNC_SAK)
1532 } else if (status & UART_LSR_PE) {
1534 port->icount.parity++;
1535 } else if (status & UART_LSR_FE) {
1537 port->icount.frame++;
1538 } else if (status & UART_LSR_OE) {
1540 port->icount.overrun++;
1543 if (!tty_insert_flip_char(&port->port, ch, flag)) {
1544 port->icount.buf_overrun++;
1552 status = inb(port->ioaddr + UART_LSR);
1553 } while (status & UART_LSR_DR);
1558 static u8 mxser_receive_chars(struct tty_struct *tty,
1559 struct mxser_port *port, u8 status)
1561 if (!mxser_receive_chars_new(port, status))
1562 status = mxser_receive_chars_old(tty, port, status);
1564 tty_flip_buffer_push(&port->port);
1569 static void mxser_transmit_chars(struct tty_struct *tty, struct mxser_port *port)
1574 outb(port->x_char, port->ioaddr + UART_TX);
1580 if (kfifo_is_empty(&port->port.xmit_fifo) || tty->flow.stopped ||
1581 (tty->hw_stopped && !mxser_16550A_or_MUST(port))) {
1582 __mxser_stop_tx(port);
1586 count = port->xmit_fifo_size;
1590 if (!kfifo_get(&port->port.xmit_fifo, &c))
1593 outb(c, port->ioaddr + UART_TX);
1595 } while (--count > 0);
1597 if (kfifo_len(&port->port.xmit_fifo) < WAKEUP_CHARS)
1600 if (kfifo_is_empty(&port->port.xmit_fifo))
1601 __mxser_stop_tx(port);
1604 static bool mxser_port_isr(struct mxser_port *port)
1606 struct tty_struct *tty;
1610 iir = inb(port->ioaddr + UART_IIR);
1611 if (iir & UART_IIR_NO_INT)
1614 iir &= MOXA_MUST_IIR_MASK;
1615 tty = tty_port_tty_get(&port->port);
1617 status = inb(port->ioaddr + UART_LSR);
1618 outb(port->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
1619 port->ioaddr + UART_FCR);
1620 inb(port->ioaddr + UART_MSR);
1626 status = inb(port->ioaddr + UART_LSR);
1628 if (port->board->must_hwid) {
1629 if (iir == MOXA_MUST_IIR_GDA ||
1630 iir == MOXA_MUST_IIR_RDA ||
1631 iir == MOXA_MUST_IIR_RTO ||
1632 iir == MOXA_MUST_IIR_LSR)
1633 status = mxser_receive_chars(tty, port, status);
1635 status &= port->read_status_mask;
1636 if (status & UART_LSR_DR)
1637 status = mxser_receive_chars(tty, port, status);
1640 mxser_check_modem_status(tty, port);
1642 if (port->board->must_hwid) {
1643 if (iir == 0x02 && (status & UART_LSR_THRE))
1644 mxser_transmit_chars(tty, port);
1646 if (status & UART_LSR_THRE)
1647 mxser_transmit_chars(tty, port);
1657 * This is the serial driver's generic interrupt routine
1659 static irqreturn_t mxser_interrupt(int irq, void *dev_id)
1661 struct mxser_board *brd = dev_id;
1662 struct mxser_port *port;
1663 unsigned int int_cnt, pass_counter = 0;
1664 unsigned int i, max = brd->nports;
1665 int handled = IRQ_NONE;
1666 u8 irqbits, bits, mask = BIT(max) - 1;
1668 while (pass_counter++ < MXSER_ISR_PASS_LIMIT) {
1669 irqbits = inb(brd->vector) & mask;
1670 if (irqbits == mask)
1673 handled = IRQ_HANDLED;
1674 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
1675 if (irqbits == mask)
1679 port = &brd->ports[i];
1682 spin_lock(&port->slock);
1684 if (mxser_port_isr(port))
1686 } while (int_cnt++ < MXSER_ISR_PASS_LIMIT);
1687 spin_unlock(&port->slock);
1694 static const struct tty_operations mxser_ops = {
1696 .close = mxser_close,
1697 .write = mxser_write,
1698 .put_char = mxser_put_char,
1699 .flush_chars = mxser_flush_chars,
1700 .write_room = mxser_write_room,
1701 .chars_in_buffer = mxser_chars_in_buffer,
1702 .flush_buffer = mxser_flush_buffer,
1703 .ioctl = mxser_ioctl,
1704 .throttle = mxser_throttle,
1705 .unthrottle = mxser_unthrottle,
1706 .set_termios = mxser_set_termios,
1708 .start = mxser_start,
1709 .hangup = mxser_hangup,
1710 .break_ctl = mxser_rs_break,
1711 .wait_until_sent = mxser_wait_until_sent,
1712 .tiocmget = mxser_tiocmget,
1713 .tiocmset = mxser_tiocmset,
1714 .set_serial = mxser_set_serial_info,
1715 .get_serial = mxser_get_serial_info,
1716 .get_icount = mxser_get_icount,
1719 static const struct tty_port_operations mxser_port_ops = {
1720 .carrier_raised = mxser_carrier_raised,
1721 .dtr_rts = mxser_dtr_rts,
1722 .activate = mxser_activate,
1723 .shutdown = mxser_shutdown_port,
1727 * The MOXA Smartio/Industio serial driver boot-time initialization code!
1730 static void mxser_initbrd(struct mxser_board *brd, bool high_baud)
1732 struct mxser_port *info;
1736 brd->must_hwid = mxser_must_get_hwid(brd->ports[0].ioaddr);
1737 is_mu860 = brd->must_hwid == MOXA_MUST_MU860_HWID;
1739 for (i = 0; i < UART_INFO_NUM; i++) {
1740 if (Gpci_uart_info[i].type == brd->must_hwid) {
1741 brd->max_baud = Gpci_uart_info[i].max_baud;
1743 /* exception....CP-102 */
1745 brd->max_baud = 921600;
1751 /* set to RS232 mode by default */
1752 outb(0, brd->vector + 4);
1753 outb(0, brd->vector + 0x0c);
1756 for (i = 0; i < brd->nports; i++) {
1757 info = &brd->ports[i];
1760 info->opmode_ioaddr = brd->vector + 4;
1762 info->opmode_ioaddr = brd->vector + 0x0c;
1764 tty_port_init(&info->port);
1765 info->port.ops = &mxser_port_ops;
1768 /* Enhance mode enabled here */
1769 if (brd->must_hwid != MOXA_OTHER_UART)
1770 mxser_must_set_enhance_mode(info->ioaddr, true);
1772 info->type = PORT_16550A;
1774 mxser_process_txrx_fifo(info);
1776 info->port.close_delay = 5 * HZ / 10;
1777 info->port.closing_wait = 30 * HZ;
1778 spin_lock_init(&info->slock);
1780 /* before set INT ISR, disable all int */
1781 outb(inb(info->ioaddr + UART_IER) & 0xf0,
1782 info->ioaddr + UART_IER);
1786 static int mxser_probe(struct pci_dev *pdev,
1787 const struct pci_device_id *ent)
1789 struct mxser_board *brd;
1790 unsigned int i, base;
1791 unsigned long ioaddress;
1792 unsigned short nports = MXSER_NPORTS(ent->driver_data);
1793 struct device *tty_dev;
1794 int retval = -EINVAL;
1796 i = find_first_zero_bit(mxser_boards, MXSER_BOARDS);
1797 if (i >= MXSER_BOARDS) {
1798 dev_err(&pdev->dev, "too many boards found (maximum %d), board "
1799 "not configured\n", MXSER_BOARDS);
1803 brd = devm_kzalloc(&pdev->dev, struct_size(brd, ports, nports),
1809 __set_bit(brd->idx, mxser_boards);
1810 base = i * MXSER_PORTS_PER_BOARD;
1812 retval = pcim_enable_device(pdev);
1814 dev_err(&pdev->dev, "PCI enable failed\n");
1819 ioaddress = pci_resource_start(pdev, 2);
1820 retval = pci_request_region(pdev, 2, "mxser(IO)");
1824 brd->nports = nports;
1825 for (i = 0; i < nports; i++)
1826 brd->ports[i].ioaddr = ioaddress + 8 * i;
1829 ioaddress = pci_resource_start(pdev, 3);
1830 retval = pci_request_region(pdev, 3, "mxser(vector)");
1833 brd->vector = ioaddress;
1836 brd->irq = pdev->irq;
1838 mxser_initbrd(brd, ent->driver_data & MXSER_HIGHBAUD);
1840 retval = devm_request_irq(&pdev->dev, brd->irq, mxser_interrupt,
1841 IRQF_SHARED, "mxser", brd);
1843 dev_err(&pdev->dev, "request irq failed");
1847 for (i = 0; i < nports; i++) {
1848 tty_dev = tty_port_register_device(&brd->ports[i].port,
1849 mxvar_sdriver, base + i, &pdev->dev);
1850 if (IS_ERR(tty_dev)) {
1851 retval = PTR_ERR(tty_dev);
1853 tty_unregister_device(mxvar_sdriver,
1859 pci_set_drvdata(pdev, brd);
1863 for (i = 0; i < nports; i++)
1864 tty_port_destroy(&brd->ports[i].port);
1866 __clear_bit(brd->idx, mxser_boards);
1871 static void mxser_remove(struct pci_dev *pdev)
1873 struct mxser_board *brd = pci_get_drvdata(pdev);
1874 unsigned int i, base = brd->idx * MXSER_PORTS_PER_BOARD;
1876 for (i = 0; i < brd->nports; i++) {
1877 tty_unregister_device(mxvar_sdriver, base + i);
1878 tty_port_destroy(&brd->ports[i].port);
1881 __clear_bit(brd->idx, mxser_boards);
1884 static struct pci_driver mxser_driver = {
1886 .id_table = mxser_pcibrds,
1887 .probe = mxser_probe,
1888 .remove = mxser_remove
1891 static int __init mxser_module_init(void)
1895 mxvar_sdriver = tty_alloc_driver(MXSER_PORTS, TTY_DRIVER_REAL_RAW |
1896 TTY_DRIVER_DYNAMIC_DEV);
1897 if (IS_ERR(mxvar_sdriver))
1898 return PTR_ERR(mxvar_sdriver);
1900 /* Initialize the tty_driver structure */
1901 mxvar_sdriver->name = "ttyMI";
1902 mxvar_sdriver->major = ttymajor;
1903 mxvar_sdriver->minor_start = 0;
1904 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
1905 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
1906 mxvar_sdriver->init_termios = tty_std_termios;
1907 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
1908 tty_set_operations(mxvar_sdriver, &mxser_ops);
1910 retval = tty_register_driver(mxvar_sdriver);
1912 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family "
1917 retval = pci_register_driver(&mxser_driver);
1919 printk(KERN_ERR "mxser: can't register pci driver\n");
1925 tty_unregister_driver(mxvar_sdriver);
1927 tty_driver_kref_put(mxvar_sdriver);
1931 static void __exit mxser_module_exit(void)
1933 pci_unregister_driver(&mxser_driver);
1934 tty_unregister_driver(mxvar_sdriver);
1935 tty_driver_kref_put(mxvar_sdriver);
1938 module_init(mxser_module_init);
1939 module_exit(mxser_module_exit);