1 // SPDX-License-Identifier: GPL-2.0
3 * USB4 specific functionality
5 * Copyright (C) 2019, Intel Corporation
6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * Rajmohan Mani <rajmohan.mani@intel.com>
10 #include <linux/delay.h>
11 #include <linux/ktime.h>
16 #define USB4_DATA_DWORDS 16
17 #define USB4_DATA_RETRIES 3
20 USB4_SWITCH_OP_QUERY_DP_RESOURCE = 0x10,
21 USB4_SWITCH_OP_ALLOC_DP_RESOURCE = 0x11,
22 USB4_SWITCH_OP_DEALLOC_DP_RESOURCE = 0x12,
23 USB4_SWITCH_OP_NVM_WRITE = 0x20,
24 USB4_SWITCH_OP_NVM_AUTH = 0x21,
25 USB4_SWITCH_OP_NVM_READ = 0x22,
26 USB4_SWITCH_OP_NVM_SET_OFFSET = 0x23,
27 USB4_SWITCH_OP_DROM_READ = 0x24,
28 USB4_SWITCH_OP_NVM_SECTOR_SIZE = 0x25,
32 USB4_SB_TARGET_ROUTER,
33 USB4_SB_TARGET_PARTNER,
34 USB4_SB_TARGET_RETIMER,
37 #define USB4_NVM_READ_OFFSET_MASK GENMASK(23, 2)
38 #define USB4_NVM_READ_OFFSET_SHIFT 2
39 #define USB4_NVM_READ_LENGTH_MASK GENMASK(27, 24)
40 #define USB4_NVM_READ_LENGTH_SHIFT 24
42 #define USB4_NVM_SET_OFFSET_MASK USB4_NVM_READ_OFFSET_MASK
43 #define USB4_NVM_SET_OFFSET_SHIFT USB4_NVM_READ_OFFSET_SHIFT
45 #define USB4_DROM_ADDRESS_MASK GENMASK(14, 2)
46 #define USB4_DROM_ADDRESS_SHIFT 2
47 #define USB4_DROM_SIZE_MASK GENMASK(19, 15)
48 #define USB4_DROM_SIZE_SHIFT 15
50 #define USB4_NVM_SECTOR_SIZE_MASK GENMASK(23, 0)
52 typedef int (*read_block_fn)(void *, unsigned int, void *, size_t);
53 typedef int (*write_block_fn)(void *, const void *, size_t);
55 static int usb4_switch_wait_for_bit(struct tb_switch *sw, u32 offset, u32 bit,
56 u32 value, int timeout_msec)
58 ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec);
64 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, offset, 1);
68 if ((val & bit) == value)
71 usleep_range(50, 100);
72 } while (ktime_before(ktime_get(), timeout));
77 static int usb4_switch_op_read_data(struct tb_switch *sw, void *data,
80 if (dwords > USB4_DATA_DWORDS)
83 return tb_sw_read(sw, data, TB_CFG_SWITCH, ROUTER_CS_9, dwords);
86 static int usb4_switch_op_write_data(struct tb_switch *sw, const void *data,
89 if (dwords > USB4_DATA_DWORDS)
92 return tb_sw_write(sw, data, TB_CFG_SWITCH, ROUTER_CS_9, dwords);
95 static int usb4_switch_op_read_metadata(struct tb_switch *sw, u32 *metadata)
97 return tb_sw_read(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
100 static int usb4_switch_op_write_metadata(struct tb_switch *sw, u32 metadata)
102 return tb_sw_write(sw, &metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
105 static int usb4_do_read_data(u16 address, void *buf, size_t size,
106 read_block_fn read_block, void *read_block_data)
108 unsigned int retries = USB4_DATA_RETRIES;
111 offset = address & 3;
112 address = address & ~3;
115 size_t nbytes = min_t(size_t, size, USB4_DATA_DWORDS * 4);
116 unsigned int dwaddress, dwords;
117 u8 data[USB4_DATA_DWORDS * 4];
120 dwaddress = address / 4;
121 dwords = ALIGN(nbytes, 4) / 4;
123 ret = read_block(read_block_data, dwaddress, data, dwords);
125 if (ret != -ENODEV && retries--)
130 memcpy(buf, data + offset, nbytes);
140 static int usb4_do_write_data(unsigned int address, const void *buf, size_t size,
141 write_block_fn write_next_block, void *write_block_data)
143 unsigned int retries = USB4_DATA_RETRIES;
146 offset = address & 3;
147 address = address & ~3;
150 u32 nbytes = min_t(u32, size, USB4_DATA_DWORDS * 4);
151 u8 data[USB4_DATA_DWORDS * 4];
154 memcpy(data + offset, buf, nbytes);
156 ret = write_next_block(write_block_data, data, nbytes / 4);
158 if (ret == -ETIMEDOUT) {
174 static int usb4_switch_op(struct tb_switch *sw, u16 opcode, u8 *status)
179 val = opcode | ROUTER_CS_26_OV;
180 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
184 ret = usb4_switch_wait_for_bit(sw, ROUTER_CS_26, ROUTER_CS_26_OV, 0, 500);
188 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
192 if (val & ROUTER_CS_26_ONS)
195 *status = (val & ROUTER_CS_26_STATUS_MASK) >> ROUTER_CS_26_STATUS_SHIFT;
199 static void usb4_switch_check_wakes(struct tb_switch *sw)
201 struct tb_port *port;
205 if (!device_may_wakeup(&sw->dev))
209 if (tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1))
212 tb_sw_dbg(sw, "PCIe wake: %s, USB3 wake: %s\n",
213 (val & ROUTER_CS_6_WOPS) ? "yes" : "no",
214 (val & ROUTER_CS_6_WOUS) ? "yes" : "no");
216 wakeup = val & (ROUTER_CS_6_WOPS | ROUTER_CS_6_WOUS);
219 /* Check for any connected downstream ports for USB4 wake */
220 tb_switch_for_each_port(sw, port) {
221 if (!tb_port_has_remote(port))
224 if (tb_port_read(port, &val, TB_CFG_PORT,
225 port->cap_usb4 + PORT_CS_18, 1))
228 tb_port_dbg(port, "USB4 wake: %s\n",
229 (val & PORT_CS_18_WOU4S) ? "yes" : "no");
231 if (val & PORT_CS_18_WOU4S)
236 pm_wakeup_event(&sw->dev, 0);
239 static bool link_is_usb4(struct tb_port *port)
246 if (tb_port_read(port, &val, TB_CFG_PORT,
247 port->cap_usb4 + PORT_CS_18, 1))
250 return !(val & PORT_CS_18_TCM);
254 * usb4_switch_setup() - Additional setup for USB4 device
255 * @sw: USB4 router to setup
257 * USB4 routers need additional settings in order to enable all the
258 * tunneling. This function enables USB and PCIe tunneling if it can be
259 * enabled (e.g the parent switch also supports them). If USB tunneling
260 * is not available for some reason (like that there is Thunderbolt 3
261 * switch upstream) then the internal xHCI controller is enabled
264 int usb4_switch_setup(struct tb_switch *sw)
266 struct tb_port *downstream_port;
267 struct tb_switch *parent;
272 usb4_switch_check_wakes(sw);
277 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1);
281 parent = tb_switch_parent(sw);
282 downstream_port = tb_port_at(tb_route(sw), parent);
283 sw->link_usb4 = link_is_usb4(downstream_port);
284 tb_sw_dbg(sw, "link: %s\n", sw->link_usb4 ? "USB4" : "TBT3");
286 xhci = val & ROUTER_CS_6_HCI;
287 tbt3 = !(val & ROUTER_CS_6_TNS);
289 tb_sw_dbg(sw, "TBT3 support: %s, xHCI: %s\n",
290 tbt3 ? "yes" : "no", xhci ? "yes" : "no");
292 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
296 if (sw->link_usb4 && tb_switch_find_port(parent, TB_TYPE_USB3_DOWN)) {
297 val |= ROUTER_CS_5_UTO;
301 /* Only enable PCIe tunneling if the parent router supports it */
302 if (tb_switch_find_port(parent, TB_TYPE_PCIE_DOWN)) {
303 val |= ROUTER_CS_5_PTO;
305 * xHCI can be enabled if PCIe tunneling is supported
306 * and the parent does not have any USB3 dowstream
307 * adapters (so we cannot do USB 3.x tunneling).
310 val |= ROUTER_CS_5_HCO;
313 /* TBT3 supported by the CM */
314 val |= ROUTER_CS_5_C3S;
315 /* Tunneling configuration is ready now */
316 val |= ROUTER_CS_5_CV;
318 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
322 return usb4_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_CR,
327 * usb4_switch_read_uid() - Read UID from USB4 router
329 * @uid: UID is stored here
331 * Reads 64-bit UID from USB4 router config space.
333 int usb4_switch_read_uid(struct tb_switch *sw, u64 *uid)
335 return tb_sw_read(sw, uid, TB_CFG_SWITCH, ROUTER_CS_7, 2);
338 static int usb4_switch_drom_read_block(void *data,
339 unsigned int dwaddress, void *buf,
342 struct tb_switch *sw = data;
347 metadata = (dwords << USB4_DROM_SIZE_SHIFT) & USB4_DROM_SIZE_MASK;
348 metadata |= (dwaddress << USB4_DROM_ADDRESS_SHIFT) &
349 USB4_DROM_ADDRESS_MASK;
351 ret = usb4_switch_op_write_metadata(sw, metadata);
355 ret = usb4_switch_op(sw, USB4_SWITCH_OP_DROM_READ, &status);
362 return usb4_switch_op_read_data(sw, buf, dwords);
366 * usb4_switch_drom_read() - Read arbitrary bytes from USB4 router DROM
368 * @address: Byte address inside DROM to start reading
369 * @buf: Buffer where the DROM content is stored
370 * @size: Number of bytes to read from DROM
372 * Uses USB4 router operations to read router DROM. For devices this
373 * should always work but for hosts it may return %-EOPNOTSUPP in which
374 * case the host router does not have DROM.
376 int usb4_switch_drom_read(struct tb_switch *sw, unsigned int address, void *buf,
379 return usb4_do_read_data(address, buf, size,
380 usb4_switch_drom_read_block, sw);
384 * usb4_switch_lane_bonding_possible() - Are conditions met for lane bonding
387 * Checks whether conditions are met so that lane bonding can be
388 * established with the upstream router. Call only for device routers.
390 bool usb4_switch_lane_bonding_possible(struct tb_switch *sw)
396 up = tb_upstream_port(sw);
397 ret = tb_port_read(up, &val, TB_CFG_PORT, up->cap_usb4 + PORT_CS_18, 1);
401 return !!(val & PORT_CS_18_BE);
405 * usb4_switch_set_wake() - Enabled/disable wake
407 * @flags: Wakeup flags (%0 to disable)
409 * Enables/disables router to wake up from sleep.
411 int usb4_switch_set_wake(struct tb_switch *sw, unsigned int flags)
413 struct tb_port *port;
414 u64 route = tb_route(sw);
419 * Enable wakes coming from all USB4 downstream ports (from
420 * child routers). For device routers do this also for the
421 * upstream USB4 port.
423 tb_switch_for_each_port(sw, port) {
424 if (!tb_port_is_null(port))
426 if (!route && tb_is_upstream_port(port))
431 ret = tb_port_read(port, &val, TB_CFG_PORT,
432 port->cap_usb4 + PORT_CS_19, 1);
436 val &= ~(PORT_CS_19_WOC | PORT_CS_19_WOD | PORT_CS_19_WOU4);
438 if (flags & TB_WAKE_ON_CONNECT)
439 val |= PORT_CS_19_WOC;
440 if (flags & TB_WAKE_ON_DISCONNECT)
441 val |= PORT_CS_19_WOD;
442 if (flags & TB_WAKE_ON_USB4)
443 val |= PORT_CS_19_WOU4;
445 ret = tb_port_write(port, &val, TB_CFG_PORT,
446 port->cap_usb4 + PORT_CS_19, 1);
452 * Enable wakes from PCIe and USB 3.x on this router. Only
453 * needed for device routers.
456 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
460 val &= ~(ROUTER_CS_5_WOP | ROUTER_CS_5_WOU);
461 if (flags & TB_WAKE_ON_USB3)
462 val |= ROUTER_CS_5_WOU;
463 if (flags & TB_WAKE_ON_PCIE)
464 val |= ROUTER_CS_5_WOP;
466 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
475 * usb4_switch_set_sleep() - Prepare the router to enter sleep
478 * Sets sleep bit for the router. Returns when the router sleep ready
479 * bit has been asserted.
481 int usb4_switch_set_sleep(struct tb_switch *sw)
486 /* Set sleep bit and wait for sleep ready to be asserted */
487 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
491 val |= ROUTER_CS_5_SLP;
493 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
497 return usb4_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_SLPR,
498 ROUTER_CS_6_SLPR, 500);
502 * usb4_switch_nvm_sector_size() - Return router NVM sector size
505 * If the router supports NVM operations this function returns the NVM
506 * sector size in bytes. If NVM operations are not supported returns
509 int usb4_switch_nvm_sector_size(struct tb_switch *sw)
515 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SECTOR_SIZE, &status);
520 return status == 0x2 ? -EOPNOTSUPP : -EIO;
522 ret = usb4_switch_op_read_metadata(sw, &metadata);
526 return metadata & USB4_NVM_SECTOR_SIZE_MASK;
529 static int usb4_switch_nvm_read_block(void *data,
530 unsigned int dwaddress, void *buf, size_t dwords)
532 struct tb_switch *sw = data;
537 metadata = (dwords << USB4_NVM_READ_LENGTH_SHIFT) &
538 USB4_NVM_READ_LENGTH_MASK;
539 metadata |= (dwaddress << USB4_NVM_READ_OFFSET_SHIFT) &
540 USB4_NVM_READ_OFFSET_MASK;
542 ret = usb4_switch_op_write_metadata(sw, metadata);
546 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_READ, &status);
553 return usb4_switch_op_read_data(sw, buf, dwords);
557 * usb4_switch_nvm_read() - Read arbitrary bytes from router NVM
559 * @address: Starting address in bytes
560 * @buf: Read data is placed here
561 * @size: How many bytes to read
563 * Reads NVM contents of the router. If NVM is not supported returns
566 int usb4_switch_nvm_read(struct tb_switch *sw, unsigned int address, void *buf,
569 return usb4_do_read_data(address, buf, size,
570 usb4_switch_nvm_read_block, sw);
573 static int usb4_switch_nvm_set_offset(struct tb_switch *sw,
574 unsigned int address)
576 u32 metadata, dwaddress;
580 dwaddress = address / 4;
581 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
582 USB4_NVM_SET_OFFSET_MASK;
584 ret = usb4_switch_op_write_metadata(sw, metadata);
588 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SET_OFFSET, &status);
592 return status ? -EIO : 0;
595 static int usb4_switch_nvm_write_next_block(void *data, const void *buf,
598 struct tb_switch *sw = data;
602 ret = usb4_switch_op_write_data(sw, buf, dwords);
606 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_WRITE, &status);
610 return status ? -EIO : 0;
614 * usb4_switch_nvm_write() - Write to the router NVM
616 * @address: Start address where to write in bytes
617 * @buf: Pointer to the data to write
618 * @size: Size of @buf in bytes
620 * Writes @buf to the router NVM using USB4 router operations. If NVM
621 * write is not supported returns %-EOPNOTSUPP.
623 int usb4_switch_nvm_write(struct tb_switch *sw, unsigned int address,
624 const void *buf, size_t size)
628 ret = usb4_switch_nvm_set_offset(sw, address);
632 return usb4_do_write_data(address, buf, size,
633 usb4_switch_nvm_write_next_block, sw);
637 * usb4_switch_nvm_authenticate() - Authenticate new NVM
640 * After the new NVM has been written via usb4_switch_nvm_write(), this
641 * function triggers NVM authentication process. If the authentication
642 * is successful the router is power cycled and the new NVM starts
643 * running. In case of failure returns negative errno.
645 int usb4_switch_nvm_authenticate(struct tb_switch *sw)
650 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_AUTH, &status);
656 tb_sw_dbg(sw, "NVM authentication successful\n");
670 * usb4_switch_query_dp_resource() - Query availability of DP IN resource
674 * For DP tunneling this function can be used to query availability of
675 * DP IN resource. Returns true if the resource is available for DP
676 * tunneling, false otherwise.
678 bool usb4_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in)
683 ret = usb4_switch_op_write_metadata(sw, in->port);
687 ret = usb4_switch_op(sw, USB4_SWITCH_OP_QUERY_DP_RESOURCE, &status);
689 * If DP resource allocation is not supported assume it is
692 if (ret == -EOPNOTSUPP)
701 * usb4_switch_alloc_dp_resource() - Allocate DP IN resource
705 * Allocates DP IN resource for DP tunneling using USB4 router
706 * operations. If the resource was allocated returns %0. Otherwise
707 * returns negative errno, in particular %-EBUSY if the resource is
710 int usb4_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
715 ret = usb4_switch_op_write_metadata(sw, in->port);
719 ret = usb4_switch_op(sw, USB4_SWITCH_OP_ALLOC_DP_RESOURCE, &status);
720 if (ret == -EOPNOTSUPP)
725 return status ? -EBUSY : 0;
729 * usb4_switch_dealloc_dp_resource() - Releases allocated DP IN resource
733 * Releases the previously allocated DP IN resource.
735 int usb4_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
740 ret = usb4_switch_op_write_metadata(sw, in->port);
744 ret = usb4_switch_op(sw, USB4_SWITCH_OP_DEALLOC_DP_RESOURCE, &status);
745 if (ret == -EOPNOTSUPP)
750 return status ? -EIO : 0;
753 static int usb4_port_idx(const struct tb_switch *sw, const struct tb_port *port)
758 /* Assume port is primary */
759 tb_switch_for_each_port(sw, p) {
760 if (!tb_port_is_null(p))
762 if (tb_is_upstream_port(p))
775 * usb4_switch_map_pcie_down() - Map USB4 port to a PCIe downstream adapter
779 * USB4 routers have direct mapping between USB4 ports and PCIe
780 * downstream adapters where the PCIe topology is extended. This
781 * function returns the corresponding downstream PCIe adapter or %NULL
782 * if no such mapping was possible.
784 struct tb_port *usb4_switch_map_pcie_down(struct tb_switch *sw,
785 const struct tb_port *port)
787 int usb4_idx = usb4_port_idx(sw, port);
791 /* Find PCIe down port matching usb4_port */
792 tb_switch_for_each_port(sw, p) {
793 if (!tb_port_is_pcie_down(p))
796 if (pcie_idx == usb4_idx)
806 * usb4_switch_map_usb3_down() - Map USB4 port to a USB3 downstream adapter
810 * USB4 routers have direct mapping between USB4 ports and USB 3.x
811 * downstream adapters where the USB 3.x topology is extended. This
812 * function returns the corresponding downstream USB 3.x adapter or
813 * %NULL if no such mapping was possible.
815 struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw,
816 const struct tb_port *port)
818 int usb4_idx = usb4_port_idx(sw, port);
822 /* Find USB3 down port matching usb4_port */
823 tb_switch_for_each_port(sw, p) {
824 if (!tb_port_is_usb3_down(p))
827 if (usb_idx == usb4_idx)
837 * usb4_port_unlock() - Unlock USB4 downstream port
838 * @port: USB4 port to unlock
840 * Unlocks USB4 downstream port so that the connection manager can
841 * access the router below this port.
843 int usb4_port_unlock(struct tb_port *port)
848 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_4, 1);
852 val &= ~ADP_CS_4_LCK;
853 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_4, 1);
856 static int usb4_port_set_configured(struct tb_port *port, bool configured)
864 ret = tb_port_read(port, &val, TB_CFG_PORT,
865 port->cap_usb4 + PORT_CS_19, 1);
870 val |= PORT_CS_19_PC;
872 val &= ~PORT_CS_19_PC;
874 return tb_port_write(port, &val, TB_CFG_PORT,
875 port->cap_usb4 + PORT_CS_19, 1);
879 * usb4_port_configure() - Set USB4 port configured
882 * Sets the USB4 link to be configured for power management purposes.
884 int usb4_port_configure(struct tb_port *port)
886 return usb4_port_set_configured(port, true);
890 * usb4_port_unconfigure() - Set USB4 port unconfigured
893 * Sets the USB4 link to be unconfigured for power management purposes.
895 void usb4_port_unconfigure(struct tb_port *port)
897 usb4_port_set_configured(port, false);
900 static int usb4_set_xdomain_configured(struct tb_port *port, bool configured)
908 ret = tb_port_read(port, &val, TB_CFG_PORT,
909 port->cap_usb4 + PORT_CS_19, 1);
914 val |= PORT_CS_19_PID;
916 val &= ~PORT_CS_19_PID;
918 return tb_port_write(port, &val, TB_CFG_PORT,
919 port->cap_usb4 + PORT_CS_19, 1);
923 * usb4_port_configure_xdomain() - Configure port for XDomain
924 * @port: USB4 port connected to another host
926 * Marks the USB4 port as being connected to another host. Returns %0 in
927 * success and negative errno in failure.
929 int usb4_port_configure_xdomain(struct tb_port *port)
931 return usb4_set_xdomain_configured(port, true);
935 * usb4_port_unconfigure_xdomain() - Unconfigure port for XDomain
936 * @port: USB4 port that was connected to another host
938 * Clears USB4 port from being marked as XDomain.
940 void usb4_port_unconfigure_xdomain(struct tb_port *port)
942 usb4_set_xdomain_configured(port, false);
945 static int usb4_port_wait_for_bit(struct tb_port *port, u32 offset, u32 bit,
946 u32 value, int timeout_msec)
948 ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec);
954 ret = tb_port_read(port, &val, TB_CFG_PORT, offset, 1);
958 if ((val & bit) == value)
961 usleep_range(50, 100);
962 } while (ktime_before(ktime_get(), timeout));
967 static int usb4_port_read_data(struct tb_port *port, void *data, size_t dwords)
969 if (dwords > USB4_DATA_DWORDS)
972 return tb_port_read(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2,
976 static int usb4_port_write_data(struct tb_port *port, const void *data,
979 if (dwords > USB4_DATA_DWORDS)
982 return tb_port_write(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2,
986 static int usb4_port_sb_read(struct tb_port *port, enum usb4_sb_target target,
987 u8 index, u8 reg, void *buf, u8 size)
989 size_t dwords = DIV_ROUND_UP(size, 4);
997 val |= size << PORT_CS_1_LENGTH_SHIFT;
998 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK;
999 if (target == USB4_SB_TARGET_RETIMER)
1000 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT);
1001 val |= PORT_CS_1_PND;
1003 ret = tb_port_write(port, &val, TB_CFG_PORT,
1004 port->cap_usb4 + PORT_CS_1, 1);
1008 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1,
1009 PORT_CS_1_PND, 0, 500);
1013 ret = tb_port_read(port, &val, TB_CFG_PORT,
1014 port->cap_usb4 + PORT_CS_1, 1);
1018 if (val & PORT_CS_1_NR)
1020 if (val & PORT_CS_1_RC)
1023 return buf ? usb4_port_read_data(port, buf, dwords) : 0;
1026 static int usb4_port_sb_write(struct tb_port *port, enum usb4_sb_target target,
1027 u8 index, u8 reg, const void *buf, u8 size)
1029 size_t dwords = DIV_ROUND_UP(size, 4);
1033 if (!port->cap_usb4)
1037 ret = usb4_port_write_data(port, buf, dwords);
1043 val |= size << PORT_CS_1_LENGTH_SHIFT;
1044 val |= PORT_CS_1_WNR_WRITE;
1045 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK;
1046 if (target == USB4_SB_TARGET_RETIMER)
1047 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT);
1048 val |= PORT_CS_1_PND;
1050 ret = tb_port_write(port, &val, TB_CFG_PORT,
1051 port->cap_usb4 + PORT_CS_1, 1);
1055 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1,
1056 PORT_CS_1_PND, 0, 500);
1060 ret = tb_port_read(port, &val, TB_CFG_PORT,
1061 port->cap_usb4 + PORT_CS_1, 1);
1065 if (val & PORT_CS_1_NR)
1067 if (val & PORT_CS_1_RC)
1073 static int usb4_port_sb_op(struct tb_port *port, enum usb4_sb_target target,
1074 u8 index, enum usb4_sb_opcode opcode, int timeout_msec)
1081 ret = usb4_port_sb_write(port, target, index, USB4_SB_OPCODE, &val,
1086 timeout = ktime_add_ms(ktime_get(), timeout_msec);
1090 ret = usb4_port_sb_read(port, target, index, USB4_SB_OPCODE,
1099 case USB4_SB_OPCODE_ERR:
1102 case USB4_SB_OPCODE_ONS:
1110 } while (ktime_before(ktime_get(), timeout));
1116 * usb4_port_enumerate_retimers() - Send RT broadcast transaction
1119 * This forces the USB4 port to send broadcast RT transaction which
1120 * makes the retimers on the link to assign index to themselves. Returns
1121 * %0 in case of success and negative errno if there was an error.
1123 int usb4_port_enumerate_retimers(struct tb_port *port)
1127 val = USB4_SB_OPCODE_ENUMERATE_RETIMERS;
1128 return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1129 USB4_SB_OPCODE, &val, sizeof(val));
1132 static inline int usb4_port_retimer_op(struct tb_port *port, u8 index,
1133 enum usb4_sb_opcode opcode,
1136 return usb4_port_sb_op(port, USB4_SB_TARGET_RETIMER, index, opcode,
1141 * usb4_port_retimer_read() - Read from retimer sideband registers
1143 * @index: Retimer index
1144 * @reg: Sideband register to read
1145 * @buf: Data from @reg is stored here
1146 * @size: Number of bytes to read
1148 * Function reads retimer sideband registers starting from @reg. The
1149 * retimer is connected to @port at @index. Returns %0 in case of
1150 * success, and read data is copied to @buf. If there is no retimer
1151 * present at given @index returns %-ENODEV. In any other failure
1152 * returns negative errno.
1154 int usb4_port_retimer_read(struct tb_port *port, u8 index, u8 reg, void *buf,
1157 return usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index, reg, buf,
1162 * usb4_port_retimer_write() - Write to retimer sideband registers
1164 * @index: Retimer index
1165 * @reg: Sideband register to write
1166 * @buf: Data that is written starting from @reg
1167 * @size: Number of bytes to write
1169 * Writes retimer sideband registers starting from @reg. The retimer is
1170 * connected to @port at @index. Returns %0 in case of success. If there
1171 * is no retimer present at given @index returns %-ENODEV. In any other
1172 * failure returns negative errno.
1174 int usb4_port_retimer_write(struct tb_port *port, u8 index, u8 reg,
1175 const void *buf, u8 size)
1177 return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index, reg, buf,
1182 * usb4_port_retimer_is_last() - Is the retimer last on-board retimer
1184 * @index: Retimer index
1186 * If the retimer at @index is last one (connected directly to the
1187 * Type-C port) this function returns %1. If it is not returns %0. If
1188 * the retimer is not present returns %-ENODEV. Otherwise returns
1191 int usb4_port_retimer_is_last(struct tb_port *port, u8 index)
1196 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_QUERY_LAST_RETIMER,
1201 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata,
1203 return ret ? ret : metadata & 1;
1207 * usb4_port_retimer_nvm_sector_size() - Read retimer NVM sector size
1209 * @index: Retimer index
1211 * Reads NVM sector size (in bytes) of a retimer at @index. This
1212 * operation can be used to determine whether the retimer supports NVM
1213 * upgrade for example. Returns sector size in bytes or negative errno
1214 * in case of error. Specifically returns %-ENODEV if there is no
1215 * retimer at @index.
1217 int usb4_port_retimer_nvm_sector_size(struct tb_port *port, u8 index)
1222 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE,
1227 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata,
1229 return ret ? ret : metadata & USB4_NVM_SECTOR_SIZE_MASK;
1232 static int usb4_port_retimer_nvm_set_offset(struct tb_port *port, u8 index,
1233 unsigned int address)
1235 u32 metadata, dwaddress;
1238 dwaddress = address / 4;
1239 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
1240 USB4_NVM_SET_OFFSET_MASK;
1242 ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata,
1247 return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_SET_OFFSET,
1251 struct retimer_info {
1252 struct tb_port *port;
1256 static int usb4_port_retimer_nvm_write_next_block(void *data, const void *buf,
1260 const struct retimer_info *info = data;
1261 struct tb_port *port = info->port;
1262 u8 index = info->index;
1265 ret = usb4_port_retimer_write(port, index, USB4_SB_DATA,
1270 return usb4_port_retimer_op(port, index,
1271 USB4_SB_OPCODE_NVM_BLOCK_WRITE, 1000);
1275 * usb4_port_retimer_nvm_write() - Write to retimer NVM
1277 * @index: Retimer index
1278 * @address: Byte address where to start the write
1279 * @buf: Data to write
1280 * @size: Size in bytes how much to write
1282 * Writes @size bytes from @buf to the retimer NVM. Used for NVM
1283 * upgrade. Returns %0 if the data was written successfully and negative
1284 * errno in case of failure. Specifically returns %-ENODEV if there is
1285 * no retimer at @index.
1287 int usb4_port_retimer_nvm_write(struct tb_port *port, u8 index, unsigned int address,
1288 const void *buf, size_t size)
1290 struct retimer_info info = { .port = port, .index = index };
1293 ret = usb4_port_retimer_nvm_set_offset(port, index, address);
1297 return usb4_do_write_data(address, buf, size,
1298 usb4_port_retimer_nvm_write_next_block, &info);
1302 * usb4_port_retimer_nvm_authenticate() - Start retimer NVM upgrade
1304 * @index: Retimer index
1306 * After the new NVM image has been written via usb4_port_retimer_nvm_write()
1307 * this function can be used to trigger the NVM upgrade process. If
1308 * successful the retimer restarts with the new NVM and may not have the
1309 * index set so one needs to call usb4_port_enumerate_retimers() to
1310 * force index to be assigned.
1312 int usb4_port_retimer_nvm_authenticate(struct tb_port *port, u8 index)
1317 * We need to use the raw operation here because once the
1318 * authentication completes the retimer index is not set anymore
1319 * so we do not get back the status now.
1321 val = USB4_SB_OPCODE_NVM_AUTH_WRITE;
1322 return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index,
1323 USB4_SB_OPCODE, &val, sizeof(val));
1327 * usb4_port_retimer_nvm_authenticate_status() - Read status of NVM upgrade
1329 * @index: Retimer index
1330 * @status: Raw status code read from metadata
1332 * This can be called after usb4_port_retimer_nvm_authenticate() and
1333 * usb4_port_enumerate_retimers() to fetch status of the NVM upgrade.
1335 * Returns %0 if the authentication status was successfully read. The
1336 * completion metadata (the result) is then stored into @status. If
1337 * reading the status fails, returns negative errno.
1339 int usb4_port_retimer_nvm_authenticate_status(struct tb_port *port, u8 index,
1345 ret = usb4_port_retimer_read(port, index, USB4_SB_OPCODE, &val,
1355 case USB4_SB_OPCODE_ERR:
1356 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA,
1357 &metadata, sizeof(metadata));
1361 *status = metadata & USB4_SB_METADATA_NVM_AUTH_WRITE_MASK;
1364 case USB4_SB_OPCODE_ONS:
1372 static int usb4_port_retimer_nvm_read_block(void *data, unsigned int dwaddress,
1373 void *buf, size_t dwords)
1375 const struct retimer_info *info = data;
1376 struct tb_port *port = info->port;
1377 u8 index = info->index;
1381 metadata = dwaddress << USB4_NVM_READ_OFFSET_SHIFT;
1382 if (dwords < USB4_DATA_DWORDS)
1383 metadata |= dwords << USB4_NVM_READ_LENGTH_SHIFT;
1385 ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata,
1390 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_READ, 500);
1394 return usb4_port_retimer_read(port, index, USB4_SB_DATA, buf,
1399 * usb4_port_retimer_nvm_read() - Read contents of retimer NVM
1401 * @index: Retimer index
1402 * @address: NVM address (in bytes) to start reading
1403 * @buf: Data read from NVM is stored here
1404 * @size: Number of bytes to read
1406 * Reads retimer NVM and copies the contents to @buf. Returns %0 if the
1407 * read was successful and negative errno in case of failure.
1408 * Specifically returns %-ENODEV if there is no retimer at @index.
1410 int usb4_port_retimer_nvm_read(struct tb_port *port, u8 index,
1411 unsigned int address, void *buf, size_t size)
1413 struct retimer_info info = { .port = port, .index = index };
1415 return usb4_do_read_data(address, buf, size,
1416 usb4_port_retimer_nvm_read_block, &info);
1420 * usb4_usb3_port_max_link_rate() - Maximum support USB3 link rate
1421 * @port: USB3 adapter port
1423 * Return maximum supported link rate of a USB3 adapter in Mb/s.
1424 * Negative errno in case of error.
1426 int usb4_usb3_port_max_link_rate(struct tb_port *port)
1431 if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port))
1434 ret = tb_port_read(port, &val, TB_CFG_PORT,
1435 port->cap_adap + ADP_USB3_CS_4, 1);
1439 lr = (val & ADP_USB3_CS_4_MSLR_MASK) >> ADP_USB3_CS_4_MSLR_SHIFT;
1440 return lr == ADP_USB3_CS_4_MSLR_20G ? 20000 : 10000;
1444 * usb4_usb3_port_actual_link_rate() - Established USB3 link rate
1445 * @port: USB3 adapter port
1447 * Return actual established link rate of a USB3 adapter in Mb/s. If the
1448 * link is not up returns %0 and negative errno in case of failure.
1450 int usb4_usb3_port_actual_link_rate(struct tb_port *port)
1455 if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port))
1458 ret = tb_port_read(port, &val, TB_CFG_PORT,
1459 port->cap_adap + ADP_USB3_CS_4, 1);
1463 if (!(val & ADP_USB3_CS_4_ULV))
1466 lr = val & ADP_USB3_CS_4_ALR_MASK;
1467 return lr == ADP_USB3_CS_4_ALR_20G ? 20000 : 10000;
1470 static int usb4_usb3_port_cm_request(struct tb_port *port, bool request)
1475 if (!tb_port_is_usb3_down(port))
1477 if (tb_route(port->sw))
1480 ret = tb_port_read(port, &val, TB_CFG_PORT,
1481 port->cap_adap + ADP_USB3_CS_2, 1);
1486 val |= ADP_USB3_CS_2_CMR;
1488 val &= ~ADP_USB3_CS_2_CMR;
1490 ret = tb_port_write(port, &val, TB_CFG_PORT,
1491 port->cap_adap + ADP_USB3_CS_2, 1);
1496 * We can use val here directly as the CMR bit is in the same place
1497 * as HCA. Just mask out others.
1499 val &= ADP_USB3_CS_2_CMR;
1500 return usb4_port_wait_for_bit(port, port->cap_adap + ADP_USB3_CS_1,
1501 ADP_USB3_CS_1_HCA, val, 1500);
1504 static inline int usb4_usb3_port_set_cm_request(struct tb_port *port)
1506 return usb4_usb3_port_cm_request(port, true);
1509 static inline int usb4_usb3_port_clear_cm_request(struct tb_port *port)
1511 return usb4_usb3_port_cm_request(port, false);
1514 static unsigned int usb3_bw_to_mbps(u32 bw, u8 scale)
1516 unsigned long uframes;
1518 uframes = bw * 512UL << scale;
1519 return DIV_ROUND_CLOSEST(uframes * 8000, 1000 * 1000);
1522 static u32 mbps_to_usb3_bw(unsigned int mbps, u8 scale)
1524 unsigned long uframes;
1526 /* 1 uframe is 1/8 ms (125 us) -> 1 / 8000 s */
1527 uframes = ((unsigned long)mbps * 1000 * 1000) / 8000;
1528 return DIV_ROUND_UP(uframes, 512UL << scale);
1531 static int usb4_usb3_port_read_allocated_bandwidth(struct tb_port *port,
1538 ret = tb_port_read(port, &val, TB_CFG_PORT,
1539 port->cap_adap + ADP_USB3_CS_2, 1);
1543 ret = tb_port_read(port, &scale, TB_CFG_PORT,
1544 port->cap_adap + ADP_USB3_CS_3, 1);
1548 scale &= ADP_USB3_CS_3_SCALE_MASK;
1550 bw = val & ADP_USB3_CS_2_AUBW_MASK;
1551 *upstream_bw = usb3_bw_to_mbps(bw, scale);
1553 bw = (val & ADP_USB3_CS_2_ADBW_MASK) >> ADP_USB3_CS_2_ADBW_SHIFT;
1554 *downstream_bw = usb3_bw_to_mbps(bw, scale);
1560 * usb4_usb3_port_allocated_bandwidth() - Bandwidth allocated for USB3
1561 * @port: USB3 adapter port
1562 * @upstream_bw: Allocated upstream bandwidth is stored here
1563 * @downstream_bw: Allocated downstream bandwidth is stored here
1565 * Stores currently allocated USB3 bandwidth into @upstream_bw and
1566 * @downstream_bw in Mb/s. Returns %0 in case of success and negative
1569 int usb4_usb3_port_allocated_bandwidth(struct tb_port *port, int *upstream_bw,
1574 ret = usb4_usb3_port_set_cm_request(port);
1578 ret = usb4_usb3_port_read_allocated_bandwidth(port, upstream_bw,
1580 usb4_usb3_port_clear_cm_request(port);
1585 static int usb4_usb3_port_read_consumed_bandwidth(struct tb_port *port,
1592 ret = tb_port_read(port, &val, TB_CFG_PORT,
1593 port->cap_adap + ADP_USB3_CS_1, 1);
1597 ret = tb_port_read(port, &scale, TB_CFG_PORT,
1598 port->cap_adap + ADP_USB3_CS_3, 1);
1602 scale &= ADP_USB3_CS_3_SCALE_MASK;
1604 bw = val & ADP_USB3_CS_1_CUBW_MASK;
1605 *upstream_bw = usb3_bw_to_mbps(bw, scale);
1607 bw = (val & ADP_USB3_CS_1_CDBW_MASK) >> ADP_USB3_CS_1_CDBW_SHIFT;
1608 *downstream_bw = usb3_bw_to_mbps(bw, scale);
1613 static int usb4_usb3_port_write_allocated_bandwidth(struct tb_port *port,
1617 u32 val, ubw, dbw, scale;
1620 /* Read the used scale, hardware default is 0 */
1621 ret = tb_port_read(port, &scale, TB_CFG_PORT,
1622 port->cap_adap + ADP_USB3_CS_3, 1);
1626 scale &= ADP_USB3_CS_3_SCALE_MASK;
1627 ubw = mbps_to_usb3_bw(upstream_bw, scale);
1628 dbw = mbps_to_usb3_bw(downstream_bw, scale);
1630 ret = tb_port_read(port, &val, TB_CFG_PORT,
1631 port->cap_adap + ADP_USB3_CS_2, 1);
1635 val &= ~(ADP_USB3_CS_2_AUBW_MASK | ADP_USB3_CS_2_ADBW_MASK);
1636 val |= dbw << ADP_USB3_CS_2_ADBW_SHIFT;
1639 return tb_port_write(port, &val, TB_CFG_PORT,
1640 port->cap_adap + ADP_USB3_CS_2, 1);
1644 * usb4_usb3_port_allocate_bandwidth() - Allocate bandwidth for USB3
1645 * @port: USB3 adapter port
1646 * @upstream_bw: New upstream bandwidth
1647 * @downstream_bw: New downstream bandwidth
1649 * This can be used to set how much bandwidth is allocated for the USB3
1650 * tunneled isochronous traffic. @upstream_bw and @downstream_bw are the
1651 * new values programmed to the USB3 adapter allocation registers. If
1652 * the values are lower than what is currently consumed the allocation
1653 * is set to what is currently consumed instead (consumed bandwidth
1654 * cannot be taken away by CM). The actual new values are returned in
1655 * @upstream_bw and @downstream_bw.
1657 * Returns %0 in case of success and negative errno if there was a
1660 int usb4_usb3_port_allocate_bandwidth(struct tb_port *port, int *upstream_bw,
1663 int ret, consumed_up, consumed_down, allocate_up, allocate_down;
1665 ret = usb4_usb3_port_set_cm_request(port);
1669 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up,
1674 /* Don't allow it go lower than what is consumed */
1675 allocate_up = max(*upstream_bw, consumed_up);
1676 allocate_down = max(*downstream_bw, consumed_down);
1678 ret = usb4_usb3_port_write_allocated_bandwidth(port, allocate_up,
1683 *upstream_bw = allocate_up;
1684 *downstream_bw = allocate_down;
1687 usb4_usb3_port_clear_cm_request(port);
1692 * usb4_usb3_port_release_bandwidth() - Release allocated USB3 bandwidth
1693 * @port: USB3 adapter port
1694 * @upstream_bw: New allocated upstream bandwidth
1695 * @downstream_bw: New allocated downstream bandwidth
1697 * Releases USB3 allocated bandwidth down to what is actually consumed.
1698 * The new bandwidth is returned in @upstream_bw and @downstream_bw.
1700 * Returns 0% in success and negative errno in case of failure.
1702 int usb4_usb3_port_release_bandwidth(struct tb_port *port, int *upstream_bw,
1705 int ret, consumed_up, consumed_down;
1707 ret = usb4_usb3_port_set_cm_request(port);
1711 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up,
1717 * Always keep 1000 Mb/s to make sure xHCI has at least some
1718 * bandwidth available for isochronous traffic.
1720 if (consumed_up < 1000)
1722 if (consumed_down < 1000)
1723 consumed_down = 1000;
1725 ret = usb4_usb3_port_write_allocated_bandwidth(port, consumed_up,
1730 *upstream_bw = consumed_up;
1731 *downstream_bw = consumed_down;
1734 usb4_usb3_port_clear_cm_request(port);