drivers/thunderbolt/tb_regs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Thunderbolt driver - Port/Switch config area registers
   4  *
   5  * Every thunderbolt device consists (logically) of a switch with multiple
   6  * ports. Every port contains up to four config regions (HOPS, PORT, SWITCH,
   7  * COUNTERS) which are used to configure the device.
   8  *
   9  * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
  10  * Copyright (C) 2018, Intel Corporation
  11  */
  12
  13 #ifndef _TB_REGS
  14 #define _TB_REGS
  15
  16 #include <linux/types.h>
  17
  18
  19 #define TB_ROUTE_SHIFT 8  /* number of bits in a port entry of a route */
  20
  21
  22 /*
  23  * TODO: should be 63? But we do not know how to receive frames larger than 256
  24  * bytes at the frame level. (header + checksum = 16, 60*4 = 240)
  25  */
  26 #define TB_MAX_CONFIG_RW_LENGTH 60
  27
  28 enum tb_switch_cap {
  29         TB_SWITCH_CAP_TMU               = 0x03,
  30         TB_SWITCH_CAP_VSE               = 0x05,
  31 };
  32
  33 enum tb_switch_vse_cap {
  34         TB_VSE_CAP_PLUG_EVENTS          = 0x01, /* also EEPROM */
  35         TB_VSE_CAP_TIME2                = 0x03,
  36         TB_VSE_CAP_IECS                 = 0x04,
  37         TB_VSE_CAP_LINK_CONTROLLER      = 0x06, /* also IECS */
  38 };
  39
  40 enum tb_port_cap {
  41         TB_PORT_CAP_PHY                 = 0x01,
  42         TB_PORT_CAP_TIME1               = 0x03,
  43         TB_PORT_CAP_ADAP                = 0x04,
  44         TB_PORT_CAP_VSE                 = 0x05,
  45         TB_PORT_CAP_USB4                = 0x06,
  46 };
  47
  48 enum tb_port_state {
  49         TB_PORT_DISABLED        = 0, /* tb_cap_phy.disable == 1 */
  50         TB_PORT_CONNECTING      = 1, /* retry */
  51         TB_PORT_UP              = 2,
  52         TB_PORT_UNPLUGGED       = 7,
  53 };
  54
  55 /* capability headers */
  56
  57 struct tb_cap_basic {
  58         u8 next;
  59         /* enum tb_cap cap:8; prevent "narrower than values of its type" */
  60         u8 cap; /* if cap == 0x05 then we have a extended capability */
  61 } __packed;
  62
  63 /**
  64  * struct tb_cap_extended_short - Switch extended short capability
  65  * @next: Pointer to the next capability. If @next and @length are zero
  66  *        then we have a long cap.
  67  * @cap: Base capability ID (see &enum tb_switch_cap)
  68  * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap)
  69  * @length: Length of this capability
  70  */
  71 struct tb_cap_extended_short {
  72         u8 next;
  73         u8 cap;
  74         u8 vsec_id;
  75         u8 length;
  76 } __packed;
  77
  78 /**
  79  * struct tb_cap_extended_long - Switch extended long capability
  80  * @zero1: This field should be zero
  81  * @cap: Base capability ID (see &enum tb_switch_cap)
  82  * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap)
  83  * @zero2: This field should be zero
  84  * @next: Pointer to the next capability
  85  * @length: Length of this capability
  86  */
  87 struct tb_cap_extended_long {
  88         u8 zero1;
  89         u8 cap;
  90         u8 vsec_id;
  91         u8 zero2;
  92         u16 next;
  93         u16 length;
  94 } __packed;
  95
  96 /* capabilities */
  97
  98 struct tb_cap_link_controller {
  99         struct tb_cap_extended_long cap_header;
 100         u32 count:4; /* number of link controllers */
 101         u32 unknown1:4;
 102         u32 base_offset:8; /*
 103                             * offset (into this capability) of the configuration
 104                             * area of the first link controller
 105                             */
 106         u32 length:12; /* link controller configuration area length */
 107         u32 unknown2:4; /* TODO check that length is correct */
 108 } __packed;
 109
 110 struct tb_cap_phy {
 111         struct tb_cap_basic cap_header;
 112         u32 unknown1:16;
 113         u32 unknown2:14;
 114         bool disable:1;
 115         u32 unknown3:11;
 116         enum tb_port_state state:4;
 117         u32 unknown4:2;
 118 } __packed;
 119
 120 struct tb_eeprom_ctl {
 121         bool clock:1; /* send pulse to transfer one bit */
 122         bool access_low:1; /* set to 0 before access */
 123         bool data_out:1; /* to eeprom */
 124         bool data_in:1; /* from eeprom */
 125         bool access_high:1; /* set to 1 before access */
 126         bool not_present:1; /* should be 0 */
 127         bool unknown1:1;
 128         bool present:1; /* should be 1 */
 129         u32 unknown2:24;
 130 } __packed;
 131
 132 struct tb_cap_plug_events {
 133         struct tb_cap_extended_short cap_header;
 134         u32 __unknown1:2;
 135         u32 plug_events:5;
 136         u32 __unknown2:25;
 137         u32 __unknown3;
 138         u32 __unknown4;
 139         struct tb_eeprom_ctl eeprom_ctl;
 140         u32 __unknown5[7];
 141         u32 drom_offset; /* 32 bit register, but eeprom addresses are 16 bit */
 142 } __packed;
 143
 144 /* device headers */
 145
 146 /* Present on port 0 in TB_CFG_SWITCH at address zero. */
 147 struct tb_regs_switch_header {
 148         /* DWORD 0 */
 149         u16 vendor_id;
 150         u16 device_id;
 151         /* DWORD 1 */
 152         u32 first_cap_offset:8;
 153         u32 upstream_port_number:6;
 154         u32 max_port_number:6;
 155         u32 depth:3;
 156         u32 __unknown1:1;
 157         u32 revision:8;
 158         /* DWORD 2 */
 159         u32 route_lo;
 160         /* DWORD 3 */
 161         u32 route_hi:31;
 162         bool enabled:1;
 163         /* DWORD 4 */
 164         u32 plug_events_delay:8; /*
 165                                   * RW, pause between plug events in
 166                                   * milliseconds. Writing 0x00 is interpreted
 167                                   * as 255ms.
 168                                   */
 169         u32 cmuv:8;
 170         u32 __unknown4:8;
 171         u32 thunderbolt_version:8;
 172 } __packed;
 173
 174 /* USB4 version 1.0 */
 175 #define USB4_VERSION_1_0                        0x20
 176
 177 #define ROUTER_CS_1                             0x01
 178 #define ROUTER_CS_4                             0x04
 179 #define ROUTER_CS_5                             0x05
 180 #define ROUTER_CS_5_SLP                         BIT(0)
 181 #define ROUTER_CS_5_C3S                         BIT(23)
 182 #define ROUTER_CS_5_PTO                         BIT(24)
 183 #define ROUTER_CS_5_UTO                         BIT(25)
 184 #define ROUTER_CS_5_HCO                         BIT(26)
 185 #define ROUTER_CS_5_CV                          BIT(31)
 186 #define ROUTER_CS_6                             0x06
 187 #define ROUTER_CS_6_SLPR                        BIT(0)
 188 #define ROUTER_CS_6_TNS                         BIT(1)
 189 #define ROUTER_CS_6_HCI                         BIT(18)
 190 #define ROUTER_CS_6_CR                          BIT(25)
 191 #define ROUTER_CS_7                             0x07
 192 #define ROUTER_CS_9                             0x09
 193 #define ROUTER_CS_25                            0x19
 194 #define ROUTER_CS_26                            0x1a
 195 #define ROUTER_CS_26_STATUS_MASK                GENMASK(29, 24)
 196 #define ROUTER_CS_26_STATUS_SHIFT               24
 197 #define ROUTER_CS_26_ONS                        BIT(30)
 198 #define ROUTER_CS_26_OV                         BIT(31)
 199
 200 /* Router TMU configuration */
 201 #define TMU_RTR_CS_0                            0x00
 202 #define TMU_RTR_CS_0_TD                         BIT(27)
 203 #define TMU_RTR_CS_0_UCAP                       BIT(30)
 204 #define TMU_RTR_CS_1                            0x01
 205 #define TMU_RTR_CS_1_LOCAL_TIME_NS_MASK         GENMASK(31, 16)
 206 #define TMU_RTR_CS_1_LOCAL_TIME_NS_SHIFT        16
 207 #define TMU_RTR_CS_2                            0x02
 208 #define TMU_RTR_CS_3                            0x03
 209 #define TMU_RTR_CS_3_LOCAL_TIME_NS_MASK         GENMASK(15, 0)
 210 #define TMU_RTR_CS_3_TS_PACKET_INTERVAL_MASK    GENMASK(31, 16)
 211 #define TMU_RTR_CS_3_TS_PACKET_INTERVAL_SHIFT   16
 212 #define TMU_RTR_CS_22                           0x16
 213 #define TMU_RTR_CS_24                           0x18
 214
 215 enum tb_port_type {
 216         TB_TYPE_INACTIVE        = 0x000000,
 217         TB_TYPE_PORT            = 0x000001,
 218         TB_TYPE_NHI             = 0x000002,
 219         /* TB_TYPE_ETHERNET     = 0x020000, lower order bits are not known */
 220         /* TB_TYPE_SATA         = 0x080000, lower order bits are not known */
 221         TB_TYPE_DP_HDMI_IN      = 0x0e0101,
 222         TB_TYPE_DP_HDMI_OUT     = 0x0e0102,
 223         TB_TYPE_PCIE_DOWN       = 0x100101,
 224         TB_TYPE_PCIE_UP         = 0x100102,
 225         TB_TYPE_USB3_DOWN       = 0x200101,
 226         TB_TYPE_USB3_UP         = 0x200102,
 227 };
 228
 229 /* Present on every port in TB_CF_PORT at address zero. */
 230 struct tb_regs_port_header {
 231         /* DWORD 0 */
 232         u16 vendor_id;
 233         u16 device_id;
 234         /* DWORD 1 */
 235         u32 first_cap_offset:8;
 236         u32 max_counters:11;
 237         u32 __unknown1:5;
 238         u32 revision:8;
 239         /* DWORD 2 */
 240         enum tb_port_type type:24;
 241         u32 thunderbolt_version:8;
 242         /* DWORD 3 */
 243         u32 __unknown2:20;
 244         u32 port_number:6;
 245         u32 __unknown3:6;
 246         /* DWORD 4 */
 247         u32 nfc_credits;
 248         /* DWORD 5 */
 249         u32 max_in_hop_id:11;
 250         u32 max_out_hop_id:11;
 251         u32 __unknown4:10;
 252         /* DWORD 6 */
 253         u32 __unknown5;
 254         /* DWORD 7 */
 255         u32 __unknown6;
 256
 257 } __packed;
 258
 259 /* Basic adapter configuration registers */
 260 #define ADP_CS_4                                0x04
 261 #define ADP_CS_4_NFC_BUFFERS_MASK               GENMASK(9, 0)
 262 #define ADP_CS_4_TOTAL_BUFFERS_MASK             GENMASK(29, 20)
 263 #define ADP_CS_4_TOTAL_BUFFERS_SHIFT            20
 264 #define ADP_CS_4_LCK                            BIT(31)
 265 #define ADP_CS_5                                0x05
 266 #define ADP_CS_5_LCA_MASK                       GENMASK(28, 22)
 267 #define ADP_CS_5_LCA_SHIFT                      22
 268
 269 /* TMU adapter registers */
 270 #define TMU_ADP_CS_3                            0x03
 271 #define TMU_ADP_CS_3_UDM                        BIT(29)
 272
 273 /* Lane adapter registers */
 274 #define LANE_ADP_CS_0                           0x00
 275 #define LANE_ADP_CS_0_SUPPORTED_WIDTH_MASK      GENMASK(25, 20)
 276 #define LANE_ADP_CS_0_SUPPORTED_WIDTH_SHIFT     20
 277 #define LANE_ADP_CS_1                           0x01
 278 #define LANE_ADP_CS_1_TARGET_WIDTH_MASK         GENMASK(9, 4)
 279 #define LANE_ADP_CS_1_TARGET_WIDTH_SHIFT        4
 280 #define LANE_ADP_CS_1_TARGET_WIDTH_SINGLE       0x1
 281 #define LANE_ADP_CS_1_TARGET_WIDTH_DUAL         0x3
 282 #define LANE_ADP_CS_1_LB                        BIT(15)
 283 #define LANE_ADP_CS_1_CURRENT_SPEED_MASK        GENMASK(19, 16)
 284 #define LANE_ADP_CS_1_CURRENT_SPEED_SHIFT       16
 285 #define LANE_ADP_CS_1_CURRENT_SPEED_GEN2        0x8
 286 #define LANE_ADP_CS_1_CURRENT_SPEED_GEN3        0x4
 287 #define LANE_ADP_CS_1_CURRENT_WIDTH_MASK        GENMASK(25, 20)
 288 #define LANE_ADP_CS_1_CURRENT_WIDTH_SHIFT       20
 289
 290 /* USB4 port registers */
 291 #define PORT_CS_1                               0x01
 292 #define PORT_CS_1_LENGTH_SHIFT                  8
 293 #define PORT_CS_1_TARGET_MASK                   GENMASK(18, 16)
 294 #define PORT_CS_1_TARGET_SHIFT                  16
 295 #define PORT_CS_1_RETIMER_INDEX_SHIFT           20
 296 #define PORT_CS_1_WNR_WRITE                     BIT(24)
 297 #define PORT_CS_1_NR                            BIT(25)
 298 #define PORT_CS_1_RC                            BIT(26)
 299 #define PORT_CS_1_PND                           BIT(31)
 300 #define PORT_CS_2                               0x02
 301 #define PORT_CS_18                              0x12
 302 #define PORT_CS_18_BE                           BIT(8)
 303 #define PORT_CS_18_TCM                          BIT(9)
 304 #define PORT_CS_19                              0x13
 305 #define PORT_CS_19_PC                           BIT(3)
 306
 307 /* Display Port adapter registers */
 308 #define ADP_DP_CS_0                             0x00
 309 #define ADP_DP_CS_0_VIDEO_HOPID_MASK            GENMASK(26, 16)
 310 #define ADP_DP_CS_0_VIDEO_HOPID_SHIFT           16
 311 #define ADP_DP_CS_0_AE                          BIT(30)
 312 #define ADP_DP_CS_0_VE                          BIT(31)
 313 #define ADP_DP_CS_1_AUX_TX_HOPID_MASK           GENMASK(10, 0)
 314 #define ADP_DP_CS_1_AUX_RX_HOPID_MASK           GENMASK(21, 11)
 315 #define ADP_DP_CS_1_AUX_RX_HOPID_SHIFT          11
 316 #define ADP_DP_CS_2                             0x02
 317 #define ADP_DP_CS_2_HDP                         BIT(6)
 318 #define ADP_DP_CS_3                             0x03
 319 #define ADP_DP_CS_3_HDPC                        BIT(9)
 320 #define DP_LOCAL_CAP                            0x04
 321 #define DP_REMOTE_CAP                           0x05
 322 #define DP_STATUS_CTRL                          0x06
 323 #define DP_STATUS_CTRL_CMHS                     BIT(25)
 324 #define DP_STATUS_CTRL_UF                       BIT(26)
 325 #define DP_COMMON_CAP                           0x07
 326 /*
 327  * DP_COMMON_CAP offsets work also for DP_LOCAL_CAP and DP_REMOTE_CAP
 328  * with exception of DPRX done.
 329  */
 330 #define DP_COMMON_CAP_RATE_MASK                 GENMASK(11, 8)
 331 #define DP_COMMON_CAP_RATE_SHIFT                8
 332 #define DP_COMMON_CAP_RATE_RBR                  0x0
 333 #define DP_COMMON_CAP_RATE_HBR                  0x1
 334 #define DP_COMMON_CAP_RATE_HBR2                 0x2
 335 #define DP_COMMON_CAP_RATE_HBR3                 0x3
 336 #define DP_COMMON_CAP_LANES_MASK                GENMASK(14, 12)
 337 #define DP_COMMON_CAP_LANES_SHIFT               12
 338 #define DP_COMMON_CAP_1_LANE                    0x0
 339 #define DP_COMMON_CAP_2_LANES                   0x1
 340 #define DP_COMMON_CAP_4_LANES                   0x2
 341 #define DP_COMMON_CAP_DPRX_DONE                 BIT(31)
 342
 343 /* PCIe adapter registers */
 344 #define ADP_PCIE_CS_0                           0x00
 345 #define ADP_PCIE_CS_0_PE                        BIT(31)
 346
 347 /* USB adapter registers */
 348 #define ADP_USB3_CS_0                           0x00
 349 #define ADP_USB3_CS_0_V                         BIT(30)
 350 #define ADP_USB3_CS_0_PE                        BIT(31)
 351 #define ADP_USB3_CS_1                           0x01
 352 #define ADP_USB3_CS_1_CUBW_MASK                 GENMASK(11, 0)
 353 #define ADP_USB3_CS_1_CDBW_MASK                 GENMASK(23, 12)
 354 #define ADP_USB3_CS_1_CDBW_SHIFT                12
 355 #define ADP_USB3_CS_1_HCA                       BIT(31)
 356 #define ADP_USB3_CS_2                           0x02
 357 #define ADP_USB3_CS_2_AUBW_MASK                 GENMASK(11, 0)
 358 #define ADP_USB3_CS_2_ADBW_MASK                 GENMASK(23, 12)
 359 #define ADP_USB3_CS_2_ADBW_SHIFT                12
 360 #define ADP_USB3_CS_2_CMR                       BIT(31)
 361 #define ADP_USB3_CS_3                           0x03
 362 #define ADP_USB3_CS_3_SCALE_MASK                GENMASK(5, 0)
 363 #define ADP_USB3_CS_4                           0x04
 364 #define ADP_USB3_CS_4_ALR_MASK                  GENMASK(6, 0)
 365 #define ADP_USB3_CS_4_ALR_20G                   0x1
 366 #define ADP_USB3_CS_4_ULV                       BIT(7)
 367 #define ADP_USB3_CS_4_MSLR_MASK                 GENMASK(18, 12)
 368 #define ADP_USB3_CS_4_MSLR_SHIFT                12
 369 #define ADP_USB3_CS_4_MSLR_20G                  0x1
 370
 371 /* Hop register from TB_CFG_HOPS. 8 byte per entry. */
 372 struct tb_regs_hop {
 373         /* DWORD 0 */
 374         u32 next_hop:11; /*
 375                           * hop to take after sending the packet through
 376                           * out_port (on the incoming port of the next switch)
 377                           */
 378         u32 out_port:6; /* next port of the path (on the same switch) */
 379         u32 initial_credits:8;
 380         u32 unknown1:6; /* set to zero */
 381         bool enable:1;
 382
 383         /* DWORD 1 */
 384         u32 weight:4;
 385         u32 unknown2:4; /* set to zero */
 386         u32 priority:3;
 387         bool drop_packages:1;
 388         u32 counter:11; /* index into TB_CFG_COUNTERS on this port */
 389         bool counter_enable:1;
 390         bool ingress_fc:1;
 391         bool egress_fc:1;
 392         bool ingress_shared_buffer:1;
 393         bool egress_shared_buffer:1;
 394         bool pending:1;
 395         u32 unknown3:3; /* set to zero */
 396 } __packed;
 397
 398 /* Common link controller registers */
 399 #define TB_LC_DESC                      0x02
 400 #define TB_LC_DESC_NLC_MASK             GENMASK(3, 0)
 401 #define TB_LC_DESC_SIZE_SHIFT           8
 402 #define TB_LC_DESC_SIZE_MASK            GENMASK(15, 8)
 403 #define TB_LC_DESC_PORT_SIZE_SHIFT      16
 404 #define TB_LC_DESC_PORT_SIZE_MASK       GENMASK(27, 16)
 405 #define TB_LC_FUSE                      0x03
 406 #define TB_LC_SNK_ALLOCATION            0x10
 407 #define TB_LC_SNK_ALLOCATION_SNK0_MASK  GENMASK(3, 0)
 408 #define TB_LC_SNK_ALLOCATION_SNK0_CM    0x1
 409 #define TB_LC_SNK_ALLOCATION_SNK1_SHIFT 4
 410 #define TB_LC_SNK_ALLOCATION_SNK1_MASK  GENMASK(7, 4)
 411 #define TB_LC_SNK_ALLOCATION_SNK1_CM    0x1
 412 #define TB_LC_POWER                     0x740
 413
 414 /* Link controller registers */
 415 #define TB_LC_PORT_ATTR                 0x8d
 416 #define TB_LC_PORT_ATTR_BE              BIT(12)
 417
 418 #define TB_LC_SX_CTRL                   0x96
 419 #define TB_LC_SX_CTRL_L1C               BIT(16)
 420 #define TB_LC_SX_CTRL_L2C               BIT(20)
 421 #define TB_LC_SX_CTRL_UPSTREAM          BIT(30)
 422 #define TB_LC_SX_CTRL_SLP               BIT(31)
 423
 424 #endif