1 // SPDX-License-Identifier: GPL-2.0-only
3 * Thunderbolt driver - NHI driver
5 * The NHI (native host interface) is the pci device that allows us to send and
6 * receive frames from the thunderbolt bus.
8 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
9 * Copyright (C) 2018, Intel Corporation
12 #include <linux/pm_runtime.h>
13 #include <linux/slab.h>
14 #include <linux/errno.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/interrupt.h>
18 #include <linux/module.h>
19 #include <linux/delay.h>
20 #include <linux/property.h>
26 #define RING_TYPE(ring) ((ring)->is_tx ? "TX ring" : "RX ring")
28 #define RING_FIRST_USABLE_HOPID 1
31 * Minimal number of vectors when we use MSI-X. Two for control channel
32 * Rx/Tx and the rest four are for cross domain DMA paths.
34 #define MSIX_MIN_VECS 6
35 #define MSIX_MAX_VECS 16
37 #define NHI_MAILBOX_TIMEOUT 500 /* ms */
39 #define QUIRK_AUTO_CLEAR_INT BIT(0)
41 static int ring_interrupt_index(struct tb_ring *ring)
45 bit += ring->nhi->hop_count;
50 * ring_interrupt_active() - activate/deactivate interrupts for a single ring
52 * ring->nhi->lock must be held.
54 static void ring_interrupt_active(struct tb_ring *ring, bool active)
56 int reg = REG_RING_INTERRUPT_BASE +
57 ring_interrupt_index(ring) / 32 * 4;
58 int bit = ring_interrupt_index(ring) & 31;
63 u32 step, shift, ivr, misc;
64 void __iomem *ivr_base;
70 index = ring->hop + ring->nhi->hop_count;
72 if (ring->nhi->quirks & QUIRK_AUTO_CLEAR_INT) {
74 * Ask the hardware to clear interrupt status
75 * bits automatically since we already know
76 * which interrupt was triggered.
78 misc = ioread32(ring->nhi->iobase + REG_DMA_MISC);
79 if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) {
80 misc |= REG_DMA_MISC_INT_AUTO_CLEAR;
81 iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC);
85 ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE;
86 step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
87 shift = index % REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
88 ivr = ioread32(ivr_base + step);
89 ivr &= ~(REG_INT_VEC_ALLOC_MASK << shift);
91 ivr |= ring->vector << shift;
92 iowrite32(ivr, ivr_base + step);
95 old = ioread32(ring->nhi->iobase + reg);
101 dev_dbg(&ring->nhi->pdev->dev,
102 "%s interrupt at register %#x bit %d (%#x -> %#x)\n",
103 active ? "enabling" : "disabling", reg, bit, old, new);
106 dev_WARN(&ring->nhi->pdev->dev,
107 "interrupt for %s %d is already %s\n",
108 RING_TYPE(ring), ring->hop,
109 active ? "enabled" : "disabled");
110 iowrite32(new, ring->nhi->iobase + reg);
114 * nhi_disable_interrupts() - disable interrupts for all rings
116 * Use only during init and shutdown.
118 static void nhi_disable_interrupts(struct tb_nhi *nhi)
121 /* disable interrupts */
122 for (i = 0; i < RING_INTERRUPT_REG_COUNT(nhi); i++)
123 iowrite32(0, nhi->iobase + REG_RING_INTERRUPT_BASE + 4 * i);
125 /* clear interrupt status bits */
126 for (i = 0; i < RING_NOTIFY_REG_COUNT(nhi); i++)
127 ioread32(nhi->iobase + REG_RING_NOTIFY_BASE + 4 * i);
130 /* ring helper methods */
132 static void __iomem *ring_desc_base(struct tb_ring *ring)
134 void __iomem *io = ring->nhi->iobase;
135 io += ring->is_tx ? REG_TX_RING_BASE : REG_RX_RING_BASE;
136 io += ring->hop * 16;
140 static void __iomem *ring_options_base(struct tb_ring *ring)
142 void __iomem *io = ring->nhi->iobase;
143 io += ring->is_tx ? REG_TX_OPTIONS_BASE : REG_RX_OPTIONS_BASE;
144 io += ring->hop * 32;
148 static void ring_iowrite_cons(struct tb_ring *ring, u16 cons)
151 * The other 16-bits in the register is read-only and writes to it
152 * are ignored by the hardware so we can save one ioread32() by
153 * filling the read-only bits with zeroes.
155 iowrite32(cons, ring_desc_base(ring) + 8);
158 static void ring_iowrite_prod(struct tb_ring *ring, u16 prod)
160 /* See ring_iowrite_cons() above for explanation */
161 iowrite32(prod << 16, ring_desc_base(ring) + 8);
164 static void ring_iowrite32desc(struct tb_ring *ring, u32 value, u32 offset)
166 iowrite32(value, ring_desc_base(ring) + offset);
169 static void ring_iowrite64desc(struct tb_ring *ring, u64 value, u32 offset)
171 iowrite32(value, ring_desc_base(ring) + offset);
172 iowrite32(value >> 32, ring_desc_base(ring) + offset + 4);
175 static void ring_iowrite32options(struct tb_ring *ring, u32 value, u32 offset)
177 iowrite32(value, ring_options_base(ring) + offset);
180 static bool ring_full(struct tb_ring *ring)
182 return ((ring->head + 1) % ring->size) == ring->tail;
185 static bool ring_empty(struct tb_ring *ring)
187 return ring->head == ring->tail;
191 * ring_write_descriptors() - post frames from ring->queue to the controller
193 * ring->lock is held.
195 static void ring_write_descriptors(struct tb_ring *ring)
197 struct ring_frame *frame, *n;
198 struct ring_desc *descriptor;
199 list_for_each_entry_safe(frame, n, &ring->queue, list) {
202 list_move_tail(&frame->list, &ring->in_flight);
203 descriptor = &ring->descriptors[ring->head];
204 descriptor->phys = frame->buffer_phy;
205 descriptor->time = 0;
206 descriptor->flags = RING_DESC_POSTED | RING_DESC_INTERRUPT;
208 descriptor->length = frame->size;
209 descriptor->eof = frame->eof;
210 descriptor->sof = frame->sof;
212 ring->head = (ring->head + 1) % ring->size;
214 ring_iowrite_prod(ring, ring->head);
216 ring_iowrite_cons(ring, ring->head);
221 * ring_work() - progress completed frames
223 * If the ring is shutting down then all frames are marked as canceled and
224 * their callbacks are invoked.
226 * Otherwise we collect all completed frame from the ring buffer, write new
227 * frame to the ring buffer and invoke the callbacks for the completed frames.
229 static void ring_work(struct work_struct *work)
231 struct tb_ring *ring = container_of(work, typeof(*ring), work);
232 struct ring_frame *frame;
233 bool canceled = false;
237 spin_lock_irqsave(&ring->lock, flags);
239 if (!ring->running) {
240 /* Move all frames to done and mark them as canceled. */
241 list_splice_tail_init(&ring->in_flight, &done);
242 list_splice_tail_init(&ring->queue, &done);
244 goto invoke_callback;
247 while (!ring_empty(ring)) {
248 if (!(ring->descriptors[ring->tail].flags
249 & RING_DESC_COMPLETED))
251 frame = list_first_entry(&ring->in_flight, typeof(*frame),
253 list_move_tail(&frame->list, &done);
255 frame->size = ring->descriptors[ring->tail].length;
256 frame->eof = ring->descriptors[ring->tail].eof;
257 frame->sof = ring->descriptors[ring->tail].sof;
258 frame->flags = ring->descriptors[ring->tail].flags;
260 ring->tail = (ring->tail + 1) % ring->size;
262 ring_write_descriptors(ring);
265 /* allow callbacks to schedule new work */
266 spin_unlock_irqrestore(&ring->lock, flags);
267 while (!list_empty(&done)) {
268 frame = list_first_entry(&done, typeof(*frame), list);
270 * The callback may reenqueue or delete frame.
271 * Do not hold on to it.
273 list_del_init(&frame->list);
275 frame->callback(ring, frame, canceled);
279 int __tb_ring_enqueue(struct tb_ring *ring, struct ring_frame *frame)
284 spin_lock_irqsave(&ring->lock, flags);
286 list_add_tail(&frame->list, &ring->queue);
287 ring_write_descriptors(ring);
291 spin_unlock_irqrestore(&ring->lock, flags);
294 EXPORT_SYMBOL_GPL(__tb_ring_enqueue);
297 * tb_ring_poll() - Poll one completed frame from the ring
298 * @ring: Ring to poll
300 * This function can be called when @start_poll callback of the @ring
301 * has been called. It will read one completed frame from the ring and
302 * return it to the caller. Returns %NULL if there is no more completed
305 struct ring_frame *tb_ring_poll(struct tb_ring *ring)
307 struct ring_frame *frame = NULL;
310 spin_lock_irqsave(&ring->lock, flags);
313 if (ring_empty(ring))
316 if (ring->descriptors[ring->tail].flags & RING_DESC_COMPLETED) {
317 frame = list_first_entry(&ring->in_flight, typeof(*frame),
319 list_del_init(&frame->list);
322 frame->size = ring->descriptors[ring->tail].length;
323 frame->eof = ring->descriptors[ring->tail].eof;
324 frame->sof = ring->descriptors[ring->tail].sof;
325 frame->flags = ring->descriptors[ring->tail].flags;
328 ring->tail = (ring->tail + 1) % ring->size;
332 spin_unlock_irqrestore(&ring->lock, flags);
335 EXPORT_SYMBOL_GPL(tb_ring_poll);
337 static void __ring_interrupt_mask(struct tb_ring *ring, bool mask)
339 int idx = ring_interrupt_index(ring);
340 int reg = REG_RING_INTERRUPT_BASE + idx / 32 * 4;
344 val = ioread32(ring->nhi->iobase + reg);
349 iowrite32(val, ring->nhi->iobase + reg);
352 /* Both @nhi->lock and @ring->lock should be held */
353 static void __ring_interrupt(struct tb_ring *ring)
358 if (ring->start_poll) {
359 __ring_interrupt_mask(ring, true);
360 ring->start_poll(ring->poll_data);
362 schedule_work(&ring->work);
367 * tb_ring_poll_complete() - Re-start interrupt for the ring
368 * @ring: Ring to re-start the interrupt
370 * This will re-start (unmask) the ring interrupt once the user is done
373 void tb_ring_poll_complete(struct tb_ring *ring)
377 spin_lock_irqsave(&ring->nhi->lock, flags);
378 spin_lock(&ring->lock);
379 if (ring->start_poll)
380 __ring_interrupt_mask(ring, false);
381 spin_unlock(&ring->lock);
382 spin_unlock_irqrestore(&ring->nhi->lock, flags);
384 EXPORT_SYMBOL_GPL(tb_ring_poll_complete);
386 static void ring_clear_msix(const struct tb_ring *ring)
388 if (ring->nhi->quirks & QUIRK_AUTO_CLEAR_INT)
392 ioread32(ring->nhi->iobase + REG_RING_NOTIFY_BASE);
394 ioread32(ring->nhi->iobase + REG_RING_NOTIFY_BASE +
395 4 * (ring->nhi->hop_count / 32));
398 static irqreturn_t ring_msix(int irq, void *data)
400 struct tb_ring *ring = data;
402 spin_lock(&ring->nhi->lock);
403 ring_clear_msix(ring);
404 spin_lock(&ring->lock);
405 __ring_interrupt(ring);
406 spin_unlock(&ring->lock);
407 spin_unlock(&ring->nhi->lock);
412 static int ring_request_msix(struct tb_ring *ring, bool no_suspend)
414 struct tb_nhi *nhi = ring->nhi;
415 unsigned long irqflags;
418 if (!nhi->pdev->msix_enabled)
421 ret = ida_simple_get(&nhi->msix_ida, 0, MSIX_MAX_VECS, GFP_KERNEL);
427 ret = pci_irq_vector(ring->nhi->pdev, ring->vector);
433 irqflags = no_suspend ? IRQF_NO_SUSPEND : 0;
434 ret = request_irq(ring->irq, ring_msix, irqflags, "thunderbolt", ring);
441 ida_simple_remove(&nhi->msix_ida, ring->vector);
446 static void ring_release_msix(struct tb_ring *ring)
451 free_irq(ring->irq, ring);
452 ida_simple_remove(&ring->nhi->msix_ida, ring->vector);
457 static int nhi_alloc_hop(struct tb_nhi *nhi, struct tb_ring *ring)
461 spin_lock_irq(&nhi->lock);
467 * Automatically allocate HopID from the non-reserved
468 * range 1 .. hop_count - 1.
470 for (i = RING_FIRST_USABLE_HOPID; i < nhi->hop_count; i++) {
472 if (!nhi->tx_rings[i]) {
477 if (!nhi->rx_rings[i]) {
485 if (ring->hop < 0 || ring->hop >= nhi->hop_count) {
486 dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop);
490 if (ring->is_tx && nhi->tx_rings[ring->hop]) {
491 dev_warn(&nhi->pdev->dev, "TX hop %d already allocated\n",
495 } else if (!ring->is_tx && nhi->rx_rings[ring->hop]) {
496 dev_warn(&nhi->pdev->dev, "RX hop %d already allocated\n",
503 nhi->tx_rings[ring->hop] = ring;
505 nhi->rx_rings[ring->hop] = ring;
508 spin_unlock_irq(&nhi->lock);
513 static struct tb_ring *tb_ring_alloc(struct tb_nhi *nhi, u32 hop, int size,
514 bool transmit, unsigned int flags,
515 int e2e_tx_hop, u16 sof_mask, u16 eof_mask,
516 void (*start_poll)(void *),
519 struct tb_ring *ring = NULL;
521 dev_dbg(&nhi->pdev->dev, "allocating %s ring %d of size %d\n",
522 transmit ? "TX" : "RX", hop, size);
524 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
528 spin_lock_init(&ring->lock);
529 INIT_LIST_HEAD(&ring->queue);
530 INIT_LIST_HEAD(&ring->in_flight);
531 INIT_WORK(&ring->work, ring_work);
535 ring->is_tx = transmit;
538 ring->e2e_tx_hop = e2e_tx_hop;
539 ring->sof_mask = sof_mask;
540 ring->eof_mask = eof_mask;
543 ring->running = false;
544 ring->start_poll = start_poll;
545 ring->poll_data = poll_data;
547 ring->descriptors = dma_alloc_coherent(&ring->nhi->pdev->dev,
548 size * sizeof(*ring->descriptors),
549 &ring->descriptors_dma, GFP_KERNEL | __GFP_ZERO);
550 if (!ring->descriptors)
553 if (ring_request_msix(ring, flags & RING_FLAG_NO_SUSPEND))
556 if (nhi_alloc_hop(nhi, ring))
557 goto err_release_msix;
562 ring_release_msix(ring);
564 dma_free_coherent(&ring->nhi->pdev->dev,
565 ring->size * sizeof(*ring->descriptors),
566 ring->descriptors, ring->descriptors_dma);
574 * tb_ring_alloc_tx() - Allocate DMA ring for transmit
575 * @nhi: Pointer to the NHI the ring is to be allocated
576 * @hop: HopID (ring) to allocate
577 * @size: Number of entries in the ring
578 * @flags: Flags for the ring
580 struct tb_ring *tb_ring_alloc_tx(struct tb_nhi *nhi, int hop, int size,
583 return tb_ring_alloc(nhi, hop, size, true, flags, 0, 0, 0, NULL, NULL);
585 EXPORT_SYMBOL_GPL(tb_ring_alloc_tx);
588 * tb_ring_alloc_rx() - Allocate DMA ring for receive
589 * @nhi: Pointer to the NHI the ring is to be allocated
590 * @hop: HopID (ring) to allocate. Pass %-1 for automatic allocation.
591 * @size: Number of entries in the ring
592 * @flags: Flags for the ring
593 * @e2e_tx_hop: Transmit HopID when E2E is enabled in @flags
594 * @sof_mask: Mask of PDF values that start a frame
595 * @eof_mask: Mask of PDF values that end a frame
596 * @start_poll: If not %NULL the ring will call this function when an
597 * interrupt is triggered and masked, instead of callback
599 * @poll_data: Optional data passed to @start_poll
601 struct tb_ring *tb_ring_alloc_rx(struct tb_nhi *nhi, int hop, int size,
602 unsigned int flags, int e2e_tx_hop,
603 u16 sof_mask, u16 eof_mask,
604 void (*start_poll)(void *), void *poll_data)
606 return tb_ring_alloc(nhi, hop, size, false, flags, e2e_tx_hop, sof_mask, eof_mask,
607 start_poll, poll_data);
609 EXPORT_SYMBOL_GPL(tb_ring_alloc_rx);
612 * tb_ring_start() - enable a ring
613 * @ring: Ring to start
615 * Must not be invoked in parallel with tb_ring_stop().
617 void tb_ring_start(struct tb_ring *ring)
622 spin_lock_irq(&ring->nhi->lock);
623 spin_lock(&ring->lock);
624 if (ring->nhi->going_away)
627 dev_WARN(&ring->nhi->pdev->dev, "ring already started\n");
630 dev_dbg(&ring->nhi->pdev->dev, "starting %s %d\n",
631 RING_TYPE(ring), ring->hop);
633 if (ring->flags & RING_FLAG_FRAME) {
636 flags = RING_FLAG_ENABLE;
638 frame_size = TB_FRAME_SIZE;
639 flags = RING_FLAG_ENABLE | RING_FLAG_RAW;
642 ring_iowrite64desc(ring, ring->descriptors_dma, 0);
644 ring_iowrite32desc(ring, ring->size, 12);
645 ring_iowrite32options(ring, 0, 4); /* time releated ? */
646 ring_iowrite32options(ring, flags, 0);
648 u32 sof_eof_mask = ring->sof_mask << 16 | ring->eof_mask;
650 ring_iowrite32desc(ring, (frame_size << 16) | ring->size, 12);
651 ring_iowrite32options(ring, sof_eof_mask, 4);
652 ring_iowrite32options(ring, flags, 0);
656 * Now that the ring valid bit is set we can configure E2E if
657 * enabled for the ring.
659 if (ring->flags & RING_FLAG_E2E) {
663 hop = ring->e2e_tx_hop << REG_RX_OPTIONS_E2E_HOP_SHIFT;
664 hop &= REG_RX_OPTIONS_E2E_HOP_MASK;
667 dev_dbg(&ring->nhi->pdev->dev,
668 "enabling E2E for %s %d with TX HopID %d\n",
669 RING_TYPE(ring), ring->hop, ring->e2e_tx_hop);
671 dev_dbg(&ring->nhi->pdev->dev, "enabling E2E for %s %d\n",
672 RING_TYPE(ring), ring->hop);
675 flags |= RING_FLAG_E2E_FLOW_CONTROL;
676 ring_iowrite32options(ring, flags, 0);
679 ring_interrupt_active(ring, true);
680 ring->running = true;
682 spin_unlock(&ring->lock);
683 spin_unlock_irq(&ring->nhi->lock);
685 EXPORT_SYMBOL_GPL(tb_ring_start);
688 * tb_ring_stop() - shutdown a ring
689 * @ring: Ring to stop
691 * Must not be invoked from a callback.
693 * This method will disable the ring. Further calls to
694 * tb_ring_tx/tb_ring_rx will return -ESHUTDOWN until ring_stop has been
697 * All enqueued frames will be canceled and their callbacks will be executed
698 * with frame->canceled set to true (on the callback thread). This method
699 * returns only after all callback invocations have finished.
701 void tb_ring_stop(struct tb_ring *ring)
703 spin_lock_irq(&ring->nhi->lock);
704 spin_lock(&ring->lock);
705 dev_dbg(&ring->nhi->pdev->dev, "stopping %s %d\n",
706 RING_TYPE(ring), ring->hop);
707 if (ring->nhi->going_away)
709 if (!ring->running) {
710 dev_WARN(&ring->nhi->pdev->dev, "%s %d already stopped\n",
711 RING_TYPE(ring), ring->hop);
714 ring_interrupt_active(ring, false);
716 ring_iowrite32options(ring, 0, 0);
717 ring_iowrite64desc(ring, 0, 0);
718 ring_iowrite32desc(ring, 0, 8);
719 ring_iowrite32desc(ring, 0, 12);
722 ring->running = false;
725 spin_unlock(&ring->lock);
726 spin_unlock_irq(&ring->nhi->lock);
729 * schedule ring->work to invoke callbacks on all remaining frames.
731 schedule_work(&ring->work);
732 flush_work(&ring->work);
734 EXPORT_SYMBOL_GPL(tb_ring_stop);
737 * tb_ring_free() - free ring
739 * When this method returns all invocations of ring->callback will have
742 * Ring must be stopped.
744 * Must NOT be called from ring_frame->callback!
746 void tb_ring_free(struct tb_ring *ring)
748 spin_lock_irq(&ring->nhi->lock);
750 * Dissociate the ring from the NHI. This also ensures that
751 * nhi_interrupt_work cannot reschedule ring->work.
754 ring->nhi->tx_rings[ring->hop] = NULL;
756 ring->nhi->rx_rings[ring->hop] = NULL;
759 dev_WARN(&ring->nhi->pdev->dev, "%s %d still running\n",
760 RING_TYPE(ring), ring->hop);
762 spin_unlock_irq(&ring->nhi->lock);
764 ring_release_msix(ring);
766 dma_free_coherent(&ring->nhi->pdev->dev,
767 ring->size * sizeof(*ring->descriptors),
768 ring->descriptors, ring->descriptors_dma);
770 ring->descriptors = NULL;
771 ring->descriptors_dma = 0;
774 dev_dbg(&ring->nhi->pdev->dev, "freeing %s %d\n", RING_TYPE(ring),
778 * ring->work can no longer be scheduled (it is scheduled only
779 * by nhi_interrupt_work, ring_stop and ring_msix). Wait for it
780 * to finish before freeing the ring.
782 flush_work(&ring->work);
785 EXPORT_SYMBOL_GPL(tb_ring_free);
788 * nhi_mailbox_cmd() - Send a command through NHI mailbox
789 * @nhi: Pointer to the NHI structure
790 * @cmd: Command to send
791 * @data: Data to be send with the command
793 * Sends mailbox command to the firmware running on NHI. Returns %0 in
794 * case of success and negative errno in case of failure.
796 int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data)
801 iowrite32(data, nhi->iobase + REG_INMAIL_DATA);
803 val = ioread32(nhi->iobase + REG_INMAIL_CMD);
804 val &= ~(REG_INMAIL_CMD_MASK | REG_INMAIL_ERROR);
805 val |= REG_INMAIL_OP_REQUEST | cmd;
806 iowrite32(val, nhi->iobase + REG_INMAIL_CMD);
808 timeout = ktime_add_ms(ktime_get(), NHI_MAILBOX_TIMEOUT);
810 val = ioread32(nhi->iobase + REG_INMAIL_CMD);
811 if (!(val & REG_INMAIL_OP_REQUEST))
813 usleep_range(10, 20);
814 } while (ktime_before(ktime_get(), timeout));
816 if (val & REG_INMAIL_OP_REQUEST)
818 if (val & REG_INMAIL_ERROR)
825 * nhi_mailbox_mode() - Return current firmware operation mode
826 * @nhi: Pointer to the NHI structure
828 * The function reads current firmware operation mode using NHI mailbox
829 * registers and returns it to the caller.
831 enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi)
835 val = ioread32(nhi->iobase + REG_OUTMAIL_CMD);
836 val &= REG_OUTMAIL_CMD_OPMODE_MASK;
837 val >>= REG_OUTMAIL_CMD_OPMODE_SHIFT;
839 return (enum nhi_fw_mode)val;
842 static void nhi_interrupt_work(struct work_struct *work)
844 struct tb_nhi *nhi = container_of(work, typeof(*nhi), interrupt_work);
845 int value = 0; /* Suppress uninitialized usage warning. */
848 int type = 0; /* current interrupt type 0: TX, 1: RX, 2: RX overflow */
849 struct tb_ring *ring;
851 spin_lock_irq(&nhi->lock);
854 * Starting at REG_RING_NOTIFY_BASE there are three status bitfields
855 * (TX, RX, RX overflow). We iterate over the bits and read a new
856 * dwords as required. The registers are cleared on read.
858 for (bit = 0; bit < 3 * nhi->hop_count; bit++) {
860 value = ioread32(nhi->iobase
861 + REG_RING_NOTIFY_BASE
863 if (++hop == nhi->hop_count) {
867 if ((value & (1 << (bit % 32))) == 0)
870 dev_warn(&nhi->pdev->dev,
871 "RX overflow for ring %d\n",
876 ring = nhi->tx_rings[hop];
878 ring = nhi->rx_rings[hop];
880 dev_warn(&nhi->pdev->dev,
881 "got interrupt for inactive %s ring %d\n",
887 spin_lock(&ring->lock);
888 __ring_interrupt(ring);
889 spin_unlock(&ring->lock);
891 spin_unlock_irq(&nhi->lock);
894 static irqreturn_t nhi_msi(int irq, void *data)
896 struct tb_nhi *nhi = data;
897 schedule_work(&nhi->interrupt_work);
901 static int __nhi_suspend_noirq(struct device *dev, bool wakeup)
903 struct pci_dev *pdev = to_pci_dev(dev);
904 struct tb *tb = pci_get_drvdata(pdev);
905 struct tb_nhi *nhi = tb->nhi;
908 ret = tb_domain_suspend_noirq(tb);
912 if (nhi->ops && nhi->ops->suspend_noirq) {
913 ret = nhi->ops->suspend_noirq(tb->nhi, wakeup);
921 static int nhi_suspend_noirq(struct device *dev)
923 return __nhi_suspend_noirq(dev, device_may_wakeup(dev));
926 static int nhi_freeze_noirq(struct device *dev)
928 struct pci_dev *pdev = to_pci_dev(dev);
929 struct tb *tb = pci_get_drvdata(pdev);
931 return tb_domain_freeze_noirq(tb);
934 static int nhi_thaw_noirq(struct device *dev)
936 struct pci_dev *pdev = to_pci_dev(dev);
937 struct tb *tb = pci_get_drvdata(pdev);
939 return tb_domain_thaw_noirq(tb);
942 static bool nhi_wake_supported(struct pci_dev *pdev)
947 * If power rails are sustainable for wakeup from S4 this
948 * property is set by the BIOS.
950 if (device_property_read_u8(&pdev->dev, "WAKE_SUPPORTED", &val))
956 static int nhi_poweroff_noirq(struct device *dev)
958 struct pci_dev *pdev = to_pci_dev(dev);
961 wakeup = device_may_wakeup(dev) && nhi_wake_supported(pdev);
962 return __nhi_suspend_noirq(dev, wakeup);
965 static void nhi_enable_int_throttling(struct tb_nhi *nhi)
967 /* Throttling is specified in 256ns increments */
968 u32 throttle = DIV_ROUND_UP(128 * NSEC_PER_USEC, 256);
972 * Configure interrupt throttling for all vectors even if we
975 for (i = 0; i < MSIX_MAX_VECS; i++) {
976 u32 reg = REG_INT_THROTTLING_RATE + i * 4;
977 iowrite32(throttle, nhi->iobase + reg);
981 static int nhi_resume_noirq(struct device *dev)
983 struct pci_dev *pdev = to_pci_dev(dev);
984 struct tb *tb = pci_get_drvdata(pdev);
985 struct tb_nhi *nhi = tb->nhi;
989 * Check that the device is still there. It may be that the user
990 * unplugged last device which causes the host controller to go
993 if (!pci_device_is_present(pdev)) {
994 nhi->going_away = true;
996 if (nhi->ops && nhi->ops->resume_noirq) {
997 ret = nhi->ops->resume_noirq(nhi);
1001 nhi_enable_int_throttling(tb->nhi);
1004 return tb_domain_resume_noirq(tb);
1007 static int nhi_suspend(struct device *dev)
1009 struct pci_dev *pdev = to_pci_dev(dev);
1010 struct tb *tb = pci_get_drvdata(pdev);
1012 return tb_domain_suspend(tb);
1015 static void nhi_complete(struct device *dev)
1017 struct pci_dev *pdev = to_pci_dev(dev);
1018 struct tb *tb = pci_get_drvdata(pdev);
1021 * If we were runtime suspended when system suspend started,
1022 * schedule runtime resume now. It should bring the domain back
1023 * to functional state.
1025 if (pm_runtime_suspended(&pdev->dev))
1026 pm_runtime_resume(&pdev->dev);
1028 tb_domain_complete(tb);
1031 static int nhi_runtime_suspend(struct device *dev)
1033 struct pci_dev *pdev = to_pci_dev(dev);
1034 struct tb *tb = pci_get_drvdata(pdev);
1035 struct tb_nhi *nhi = tb->nhi;
1038 ret = tb_domain_runtime_suspend(tb);
1042 if (nhi->ops && nhi->ops->runtime_suspend) {
1043 ret = nhi->ops->runtime_suspend(tb->nhi);
1050 static int nhi_runtime_resume(struct device *dev)
1052 struct pci_dev *pdev = to_pci_dev(dev);
1053 struct tb *tb = pci_get_drvdata(pdev);
1054 struct tb_nhi *nhi = tb->nhi;
1057 if (nhi->ops && nhi->ops->runtime_resume) {
1058 ret = nhi->ops->runtime_resume(nhi);
1063 nhi_enable_int_throttling(nhi);
1064 return tb_domain_runtime_resume(tb);
1067 static void nhi_shutdown(struct tb_nhi *nhi)
1071 dev_dbg(&nhi->pdev->dev, "shutdown\n");
1073 for (i = 0; i < nhi->hop_count; i++) {
1074 if (nhi->tx_rings[i])
1075 dev_WARN(&nhi->pdev->dev,
1076 "TX ring %d is still active\n", i);
1077 if (nhi->rx_rings[i])
1078 dev_WARN(&nhi->pdev->dev,
1079 "RX ring %d is still active\n", i);
1081 nhi_disable_interrupts(nhi);
1083 * We have to release the irq before calling flush_work. Otherwise an
1084 * already executing IRQ handler could call schedule_work again.
1086 if (!nhi->pdev->msix_enabled) {
1087 devm_free_irq(&nhi->pdev->dev, nhi->pdev->irq, nhi);
1088 flush_work(&nhi->interrupt_work);
1090 ida_destroy(&nhi->msix_ida);
1092 if (nhi->ops && nhi->ops->shutdown)
1093 nhi->ops->shutdown(nhi);
1096 static void nhi_check_quirks(struct tb_nhi *nhi)
1099 * Intel hardware supports auto clear of the interrupt status
1100 * reqister right after interrupt is being issued.
1102 if (nhi->pdev->vendor == PCI_VENDOR_ID_INTEL)
1103 nhi->quirks |= QUIRK_AUTO_CLEAR_INT;
1106 static int nhi_init_msi(struct tb_nhi *nhi)
1108 struct pci_dev *pdev = nhi->pdev;
1111 /* In case someone left them on. */
1112 nhi_disable_interrupts(nhi);
1114 nhi_enable_int_throttling(nhi);
1116 ida_init(&nhi->msix_ida);
1119 * The NHI has 16 MSI-X vectors or a single MSI. We first try to
1120 * get all MSI-X vectors and if we succeed, each ring will have
1121 * one MSI-X. If for some reason that does not work out, we
1122 * fallback to a single MSI.
1124 nvec = pci_alloc_irq_vectors(pdev, MSIX_MIN_VECS, MSIX_MAX_VECS,
1127 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1131 INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work);
1133 irq = pci_irq_vector(nhi->pdev, 0);
1137 res = devm_request_irq(&pdev->dev, irq, nhi_msi,
1138 IRQF_NO_SUSPEND, "thunderbolt", nhi);
1140 dev_err(&pdev->dev, "request_irq failed, aborting\n");
1148 static bool nhi_imr_valid(struct pci_dev *pdev)
1152 if (!device_property_read_u8(&pdev->dev, "IMR_VALID", &val))
1158 static struct tb *nhi_select_cm(struct tb_nhi *nhi)
1163 * USB4 case is simple. If we got control of any of the
1164 * capabilities, we use software CM.
1166 if (tb_acpi_is_native())
1167 return tb_probe(nhi);
1170 * Either firmware based CM is running (we did not get control
1171 * from the firmware) or this is pre-USB4 PC so try first
1172 * firmware CM and then fallback to software CM.
1174 tb = icm_probe(nhi);
1181 static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1187 if (!nhi_imr_valid(pdev)) {
1188 dev_warn(&pdev->dev, "firmware image not valid, aborting\n");
1192 res = pcim_enable_device(pdev);
1194 dev_err(&pdev->dev, "cannot enable PCI device, aborting\n");
1198 res = pcim_iomap_regions(pdev, 1 << 0, "thunderbolt");
1200 dev_err(&pdev->dev, "cannot obtain PCI resources, aborting\n");
1204 nhi = devm_kzalloc(&pdev->dev, sizeof(*nhi), GFP_KERNEL);
1209 nhi->ops = (const struct tb_nhi_ops *)id->driver_data;
1210 /* cannot fail - table is allocated bin pcim_iomap_regions */
1211 nhi->iobase = pcim_iomap_table(pdev)[0];
1212 nhi->hop_count = ioread32(nhi->iobase + REG_HOP_COUNT) & 0x3ff;
1213 dev_dbg(&pdev->dev, "total paths: %d\n", nhi->hop_count);
1215 nhi->tx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
1216 sizeof(*nhi->tx_rings), GFP_KERNEL);
1217 nhi->rx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
1218 sizeof(*nhi->rx_rings), GFP_KERNEL);
1219 if (!nhi->tx_rings || !nhi->rx_rings)
1222 nhi_check_quirks(nhi);
1224 res = nhi_init_msi(nhi);
1226 dev_err(&pdev->dev, "cannot enable MSI, aborting\n");
1230 spin_lock_init(&nhi->lock);
1232 res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1234 dev_err(&pdev->dev, "failed to set DMA mask\n");
1238 pci_set_master(pdev);
1240 if (nhi->ops && nhi->ops->init) {
1241 res = nhi->ops->init(nhi);
1246 tb = nhi_select_cm(nhi);
1248 dev_err(&nhi->pdev->dev,
1249 "failed to determine connection manager, aborting\n");
1253 dev_dbg(&nhi->pdev->dev, "NHI initialized, starting thunderbolt\n");
1255 res = tb_domain_add(tb);
1258 * At this point the RX/TX rings might already have been
1259 * activated. Do a proper shutdown.
1265 pci_set_drvdata(pdev, tb);
1267 device_wakeup_enable(&pdev->dev);
1269 pm_runtime_allow(&pdev->dev);
1270 pm_runtime_set_autosuspend_delay(&pdev->dev, TB_AUTOSUSPEND_DELAY);
1271 pm_runtime_use_autosuspend(&pdev->dev);
1272 pm_runtime_put_autosuspend(&pdev->dev);
1277 static void nhi_remove(struct pci_dev *pdev)
1279 struct tb *tb = pci_get_drvdata(pdev);
1280 struct tb_nhi *nhi = tb->nhi;
1282 pm_runtime_get_sync(&pdev->dev);
1283 pm_runtime_dont_use_autosuspend(&pdev->dev);
1284 pm_runtime_forbid(&pdev->dev);
1286 tb_domain_remove(tb);
1291 * The tunneled pci bridges are siblings of us. Use resume_noirq to reenable
1292 * the tunnels asap. A corresponding pci quirk blocks the downstream bridges
1293 * resume_noirq until we are done.
1295 static const struct dev_pm_ops nhi_pm_ops = {
1296 .suspend_noirq = nhi_suspend_noirq,
1297 .resume_noirq = nhi_resume_noirq,
1298 .freeze_noirq = nhi_freeze_noirq, /*
1299 * we just disable hotplug, the
1300 * pci-tunnels stay alive.
1302 .thaw_noirq = nhi_thaw_noirq,
1303 .restore_noirq = nhi_resume_noirq,
1304 .suspend = nhi_suspend,
1305 .poweroff_noirq = nhi_poweroff_noirq,
1306 .poweroff = nhi_suspend,
1307 .complete = nhi_complete,
1308 .runtime_suspend = nhi_runtime_suspend,
1309 .runtime_resume = nhi_runtime_resume,
1312 static struct pci_device_id nhi_ids[] = {
1314 * We have to specify class, the TB bridges use the same device and
1315 * vendor (sub)id on gen 1 and gen 2 controllers.
1318 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1319 .vendor = PCI_VENDOR_ID_INTEL,
1320 .device = PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
1321 .subvendor = 0x2222, .subdevice = 0x1111,
1324 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1325 .vendor = PCI_VENDOR_ID_INTEL,
1326 .device = PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
1327 .subvendor = 0x2222, .subdevice = 0x1111,
1330 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1331 .vendor = PCI_VENDOR_ID_INTEL,
1332 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI,
1333 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
1336 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1337 .vendor = PCI_VENDOR_ID_INTEL,
1338 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI,
1339 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
1343 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI) },
1344 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI) },
1345 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) },
1346 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) },
1347 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) },
1348 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) },
1349 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) },
1350 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) },
1351 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI) },
1352 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI) },
1353 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI0),
1354 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1355 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI1),
1356 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1357 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI0),
1358 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1359 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI1),
1360 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1361 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI0),
1362 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1363 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI1),
1364 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1365 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI0),
1366 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1367 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI1),
1368 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1370 /* Any USB4 compliant host */
1371 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_USB4, ~0) },
1376 MODULE_DEVICE_TABLE(pci, nhi_ids);
1377 MODULE_LICENSE("GPL");
1379 static struct pci_driver nhi_driver = {
1380 .name = "thunderbolt",
1381 .id_table = nhi_ids,
1383 .remove = nhi_remove,
1384 .shutdown = nhi_remove,
1385 .driver.pm = &nhi_pm_ops,
1388 static int __init nhi_init(void)
1392 ret = tb_domain_init();
1395 ret = pci_register_driver(&nhi_driver);
1401 static void __exit nhi_unload(void)
1403 pci_unregister_driver(&nhi_driver);
1407 rootfs_initcall(nhi_init);
1408 module_exit(nhi_unload);