drivers/thunderbolt/nhi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Thunderbolt driver - NHI driver
   4  *
   5  * The NHI (native host interface) is the pci device that allows us to send and
   6  * receive frames from the thunderbolt bus.
   7  *
   8  * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
   9  * Copyright (C) 2018, Intel Corporation
  10  */
  11
  12 #include <linux/pm_runtime.h>
  13 #include <linux/slab.h>
  14 #include <linux/errno.h>
  15 #include <linux/pci.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/module.h>
  19 #include <linux/delay.h>
  20 #include <linux/property.h>
  21
  22 #include "nhi.h"
  23 #include "nhi_regs.h"
  24 #include "tb.h"
  25
  26 #define RING_TYPE(ring) ((ring)->is_tx ? "TX ring" : "RX ring")
  27
  28 #define RING_FIRST_USABLE_HOPID 1
  29
  30 /*
  31  * Minimal number of vectors when we use MSI-X. Two for control channel
  32  * Rx/Tx and the rest four are for cross domain DMA paths.
  33  */
  34 #define MSIX_MIN_VECS           6
  35 #define MSIX_MAX_VECS           16
  36
  37 #define NHI_MAILBOX_TIMEOUT     500 /* ms */
  38
  39 #define QUIRK_AUTO_CLEAR_INT    BIT(0)
  40
  41 static int ring_interrupt_index(struct tb_ring *ring)
  42 {
  43         int bit = ring->hop;
  44         if (!ring->is_tx)
  45                 bit += ring->nhi->hop_count;
  46         return bit;
  47 }
  48
  49 /*
  50  * ring_interrupt_active() - activate/deactivate interrupts for a single ring
  51  *
  52  * ring->nhi->lock must be held.
  53  */
  54 static void ring_interrupt_active(struct tb_ring *ring, bool active)
  55 {
  56         int reg = REG_RING_INTERRUPT_BASE +
  57                   ring_interrupt_index(ring) / 32 * 4;
  58         int bit = ring_interrupt_index(ring) & 31;
  59         int mask = 1 << bit;
  60         u32 old, new;
  61
  62         if (ring->irq > 0) {
  63                 u32 step, shift, ivr, misc;
  64                 void __iomem *ivr_base;
  65                 int index;
  66
  67                 if (ring->is_tx)
  68                         index = ring->hop;
  69                 else
  70                         index = ring->hop + ring->nhi->hop_count;
  71
  72                 if (ring->nhi->quirks & QUIRK_AUTO_CLEAR_INT) {
  73                         /*
  74                          * Ask the hardware to clear interrupt status
  75                          * bits automatically since we already know
  76                          * which interrupt was triggered.
  77                          */
  78                         misc = ioread32(ring->nhi->iobase + REG_DMA_MISC);
  79                         if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) {
  80                                 misc |= REG_DMA_MISC_INT_AUTO_CLEAR;
  81                                 iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC);
  82                         }
  83                 }
  84
  85                 ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE;
  86                 step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
  87                 shift = index % REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
  88                 ivr = ioread32(ivr_base + step);
  89                 ivr &= ~(REG_INT_VEC_ALLOC_MASK << shift);
  90                 if (active)
  91                         ivr |= ring->vector << shift;
  92                 iowrite32(ivr, ivr_base + step);
  93         }
  94
  95         old = ioread32(ring->nhi->iobase + reg);
  96         if (active)
  97                 new = old | mask;
  98         else
  99                 new = old & ~mask;
 100
 101         dev_dbg(&ring->nhi->pdev->dev,
 102                 "%s interrupt at register %#x bit %d (%#x -> %#x)\n",
 103                 active ? "enabling" : "disabling", reg, bit, old, new);
 104
 105         if (new == old)
 106                 dev_WARN(&ring->nhi->pdev->dev,
 107                                          "interrupt for %s %d is already %s\n",
 108                                          RING_TYPE(ring), ring->hop,
 109                                          active ? "enabled" : "disabled");
 110         iowrite32(new, ring->nhi->iobase + reg);
 111 }
 112
 113 /*
 114  * nhi_disable_interrupts() - disable interrupts for all rings
 115  *
 116  * Use only during init and shutdown.
 117  */
 118 static void nhi_disable_interrupts(struct tb_nhi *nhi)
 119 {
 120         int i = 0;
 121         /* disable interrupts */
 122         for (i = 0; i < RING_INTERRUPT_REG_COUNT(nhi); i++)
 123                 iowrite32(0, nhi->iobase + REG_RING_INTERRUPT_BASE + 4 * i);
 124
 125         /* clear interrupt status bits */
 126         for (i = 0; i < RING_NOTIFY_REG_COUNT(nhi); i++)
 127                 ioread32(nhi->iobase + REG_RING_NOTIFY_BASE + 4 * i);
 128 }
 129
 130 /* ring helper methods */
 131
 132 static void __iomem *ring_desc_base(struct tb_ring *ring)
 133 {
 134         void __iomem *io = ring->nhi->iobase;
 135         io += ring->is_tx ? REG_TX_RING_BASE : REG_RX_RING_BASE;
 136         io += ring->hop * 16;
 137         return io;
 138 }
 139
 140 static void __iomem *ring_options_base(struct tb_ring *ring)
 141 {
 142         void __iomem *io = ring->nhi->iobase;
 143         io += ring->is_tx ? REG_TX_OPTIONS_BASE : REG_RX_OPTIONS_BASE;
 144         io += ring->hop * 32;
 145         return io;
 146 }
 147
 148 static void ring_iowrite_cons(struct tb_ring *ring, u16 cons)
 149 {
 150         /*
 151          * The other 16-bits in the register is read-only and writes to it
 152          * are ignored by the hardware so we can save one ioread32() by
 153          * filling the read-only bits with zeroes.
 154          */
 155         iowrite32(cons, ring_desc_base(ring) + 8);
 156 }
 157
 158 static void ring_iowrite_prod(struct tb_ring *ring, u16 prod)
 159 {
 160         /* See ring_iowrite_cons() above for explanation */
 161         iowrite32(prod << 16, ring_desc_base(ring) + 8);
 162 }
 163
 164 static void ring_iowrite32desc(struct tb_ring *ring, u32 value, u32 offset)
 165 {
 166         iowrite32(value, ring_desc_base(ring) + offset);
 167 }
 168
 169 static void ring_iowrite64desc(struct tb_ring *ring, u64 value, u32 offset)
 170 {
 171         iowrite32(value, ring_desc_base(ring) + offset);
 172         iowrite32(value >> 32, ring_desc_base(ring) + offset + 4);
 173 }
 174
 175 static void ring_iowrite32options(struct tb_ring *ring, u32 value, u32 offset)
 176 {
 177         iowrite32(value, ring_options_base(ring) + offset);
 178 }
 179
 180 static bool ring_full(struct tb_ring *ring)
 181 {
 182         return ((ring->head + 1) % ring->size) == ring->tail;
 183 }
 184
 185 static bool ring_empty(struct tb_ring *ring)
 186 {
 187         return ring->head == ring->tail;
 188 }
 189
 190 /*
 191  * ring_write_descriptors() - post frames from ring->queue to the controller
 192  *
 193  * ring->lock is held.
 194  */
 195 static void ring_write_descriptors(struct tb_ring *ring)
 196 {
 197         struct ring_frame *frame, *n;
 198         struct ring_desc *descriptor;
 199         list_for_each_entry_safe(frame, n, &ring->queue, list) {
 200                 if (ring_full(ring))
 201                         break;
 202                 list_move_tail(&frame->list, &ring->in_flight);
 203                 descriptor = &ring->descriptors[ring->head];
 204                 descriptor->phys = frame->buffer_phy;
 205                 descriptor->time = 0;
 206                 descriptor->flags = RING_DESC_POSTED | RING_DESC_INTERRUPT;
 207                 if (ring->is_tx) {
 208                         descriptor->length = frame->size;
 209                         descriptor->eof = frame->eof;
 210                         descriptor->sof = frame->sof;
 211                 }
 212                 ring->head = (ring->head + 1) % ring->size;
 213                 if (ring->is_tx)
 214                         ring_iowrite_prod(ring, ring->head);
 215                 else
 216                         ring_iowrite_cons(ring, ring->head);
 217         }
 218 }
 219
 220 /*
 221  * ring_work() - progress completed frames
 222  *
 223  * If the ring is shutting down then all frames are marked as canceled and
 224  * their callbacks are invoked.
 225  *
 226  * Otherwise we collect all completed frame from the ring buffer, write new
 227  * frame to the ring buffer and invoke the callbacks for the completed frames.
 228  */
 229 static void ring_work(struct work_struct *work)
 230 {
 231         struct tb_ring *ring = container_of(work, typeof(*ring), work);
 232         struct ring_frame *frame;
 233         bool canceled = false;
 234         unsigned long flags;
 235         LIST_HEAD(done);
 236
 237         spin_lock_irqsave(&ring->lock, flags);
 238
 239         if (!ring->running) {
 240                 /*  Move all frames to done and mark them as canceled. */
 241                 list_splice_tail_init(&ring->in_flight, &done);
 242                 list_splice_tail_init(&ring->queue, &done);
 243                 canceled = true;
 244                 goto invoke_callback;
 245         }
 246
 247         while (!ring_empty(ring)) {
 248                 if (!(ring->descriptors[ring->tail].flags
 249                                 & RING_DESC_COMPLETED))
 250                         break;
 251                 frame = list_first_entry(&ring->in_flight, typeof(*frame),
 252                                          list);
 253                 list_move_tail(&frame->list, &done);
 254                 if (!ring->is_tx) {
 255                         frame->size = ring->descriptors[ring->tail].length;
 256                         frame->eof = ring->descriptors[ring->tail].eof;
 257                         frame->sof = ring->descriptors[ring->tail].sof;
 258                         frame->flags = ring->descriptors[ring->tail].flags;
 259                 }
 260                 ring->tail = (ring->tail + 1) % ring->size;
 261         }
 262         ring_write_descriptors(ring);
 263
 264 invoke_callback:
 265         /* allow callbacks to schedule new work */
 266         spin_unlock_irqrestore(&ring->lock, flags);
 267         while (!list_empty(&done)) {
 268                 frame = list_first_entry(&done, typeof(*frame), list);
 269                 /*
 270                  * The callback may reenqueue or delete frame.
 271                  * Do not hold on to it.
 272                  */
 273                 list_del_init(&frame->list);
 274                 if (frame->callback)
 275                         frame->callback(ring, frame, canceled);
 276         }
 277 }
 278
 279 int __tb_ring_enqueue(struct tb_ring *ring, struct ring_frame *frame)
 280 {
 281         unsigned long flags;
 282         int ret = 0;
 283
 284         spin_lock_irqsave(&ring->lock, flags);
 285         if (ring->running) {
 286                 list_add_tail(&frame->list, &ring->queue);
 287                 ring_write_descriptors(ring);
 288         } else {
 289                 ret = -ESHUTDOWN;
 290         }
 291         spin_unlock_irqrestore(&ring->lock, flags);
 292         return ret;
 293 }
 294 EXPORT_SYMBOL_GPL(__tb_ring_enqueue);
 295
 296 /**
 297  * tb_ring_poll() - Poll one completed frame from the ring
 298  * @ring: Ring to poll
 299  *
 300  * This function can be called when @start_poll callback of the @ring
 301  * has been called. It will read one completed frame from the ring and
 302  * return it to the caller. Returns %NULL if there is no more completed
 303  * frames.
 304  */
 305 struct ring_frame *tb_ring_poll(struct tb_ring *ring)
 306 {
 307         struct ring_frame *frame = NULL;
 308         unsigned long flags;
 309
 310         spin_lock_irqsave(&ring->lock, flags);
 311         if (!ring->running)
 312                 goto unlock;
 313         if (ring_empty(ring))
 314                 goto unlock;
 315
 316         if (ring->descriptors[ring->tail].flags & RING_DESC_COMPLETED) {
 317                 frame = list_first_entry(&ring->in_flight, typeof(*frame),
 318                                          list);
 319                 list_del_init(&frame->list);
 320
 321                 if (!ring->is_tx) {
 322                         frame->size = ring->descriptors[ring->tail].length;
 323                         frame->eof = ring->descriptors[ring->tail].eof;
 324                         frame->sof = ring->descriptors[ring->tail].sof;
 325                         frame->flags = ring->descriptors[ring->tail].flags;
 326                 }
 327
 328                 ring->tail = (ring->tail + 1) % ring->size;
 329         }
 330
 331 unlock:
 332         spin_unlock_irqrestore(&ring->lock, flags);
 333         return frame;
 334 }
 335 EXPORT_SYMBOL_GPL(tb_ring_poll);
 336
 337 static void __ring_interrupt_mask(struct tb_ring *ring, bool mask)
 338 {
 339         int idx = ring_interrupt_index(ring);
 340         int reg = REG_RING_INTERRUPT_BASE + idx / 32 * 4;
 341         int bit = idx % 32;
 342         u32 val;
 343
 344         val = ioread32(ring->nhi->iobase + reg);
 345         if (mask)
 346                 val &= ~BIT(bit);
 347         else
 348                 val |= BIT(bit);
 349         iowrite32(val, ring->nhi->iobase + reg);
 350 }
 351
 352 /* Both @nhi->lock and @ring->lock should be held */
 353 static void __ring_interrupt(struct tb_ring *ring)
 354 {
 355         if (!ring->running)
 356                 return;
 357
 358         if (ring->start_poll) {
 359                 __ring_interrupt_mask(ring, true);
 360                 ring->start_poll(ring->poll_data);
 361         } else {
 362                 schedule_work(&ring->work);
 363         }
 364 }
 365
 366 /**
 367  * tb_ring_poll_complete() - Re-start interrupt for the ring
 368  * @ring: Ring to re-start the interrupt
 369  *
 370  * This will re-start (unmask) the ring interrupt once the user is done
 371  * with polling.
 372  */
 373 void tb_ring_poll_complete(struct tb_ring *ring)
 374 {
 375         unsigned long flags;
 376
 377         spin_lock_irqsave(&ring->nhi->lock, flags);
 378         spin_lock(&ring->lock);
 379         if (ring->start_poll)
 380                 __ring_interrupt_mask(ring, false);
 381         spin_unlock(&ring->lock);
 382         spin_unlock_irqrestore(&ring->nhi->lock, flags);
 383 }
 384 EXPORT_SYMBOL_GPL(tb_ring_poll_complete);
 385
 386 static void ring_clear_msix(const struct tb_ring *ring)
 387 {
 388         if (ring->nhi->quirks & QUIRK_AUTO_CLEAR_INT)
 389                 return;
 390
 391         if (ring->is_tx)
 392                 ioread32(ring->nhi->iobase + REG_RING_NOTIFY_BASE);
 393         else
 394                 ioread32(ring->nhi->iobase + REG_RING_NOTIFY_BASE +
 395                          4 * (ring->nhi->hop_count / 32));
 396 }
 397
 398 static irqreturn_t ring_msix(int irq, void *data)
 399 {
 400         struct tb_ring *ring = data;
 401
 402         spin_lock(&ring->nhi->lock);
 403         ring_clear_msix(ring);
 404         spin_lock(&ring->lock);
 405         __ring_interrupt(ring);
 406         spin_unlock(&ring->lock);
 407         spin_unlock(&ring->nhi->lock);
 408
 409         return IRQ_HANDLED;
 410 }
 411
 412 static int ring_request_msix(struct tb_ring *ring, bool no_suspend)
 413 {
 414         struct tb_nhi *nhi = ring->nhi;
 415         unsigned long irqflags;
 416         int ret;
 417
 418         if (!nhi->pdev->msix_enabled)
 419                 return 0;
 420
 421         ret = ida_simple_get(&nhi->msix_ida, 0, MSIX_MAX_VECS, GFP_KERNEL);
 422         if (ret < 0)
 423                 return ret;
 424
 425         ring->vector = ret;
 426
 427         ret = pci_irq_vector(ring->nhi->pdev, ring->vector);
 428         if (ret < 0)
 429                 goto err_ida_remove;
 430
 431         ring->irq = ret;
 432
 433         irqflags = no_suspend ? IRQF_NO_SUSPEND : 0;
 434         ret = request_irq(ring->irq, ring_msix, irqflags, "thunderbolt", ring);
 435         if (ret)
 436                 goto err_ida_remove;
 437
 438         return 0;
 439
 440 err_ida_remove:
 441         ida_simple_remove(&nhi->msix_ida, ring->vector);
 442
 443         return ret;
 444 }
 445
 446 static void ring_release_msix(struct tb_ring *ring)
 447 {
 448         if (ring->irq <= 0)
 449                 return;
 450
 451         free_irq(ring->irq, ring);
 452         ida_simple_remove(&ring->nhi->msix_ida, ring->vector);
 453         ring->vector = 0;
 454         ring->irq = 0;
 455 }
 456
 457 static int nhi_alloc_hop(struct tb_nhi *nhi, struct tb_ring *ring)
 458 {
 459         int ret = 0;
 460
 461         spin_lock_irq(&nhi->lock);
 462
 463         if (ring->hop < 0) {
 464                 unsigned int i;
 465
 466                 /*
 467                  * Automatically allocate HopID from the non-reserved
 468                  * range 1 .. hop_count - 1.
 469                  */
 470                 for (i = RING_FIRST_USABLE_HOPID; i < nhi->hop_count; i++) {
 471                         if (ring->is_tx) {
 472                                 if (!nhi->tx_rings[i]) {
 473                                         ring->hop = i;
 474                                         break;
 475                                 }
 476                         } else {
 477                                 if (!nhi->rx_rings[i]) {
 478                                         ring->hop = i;
 479                                         break;
 480                                 }
 481                         }
 482                 }
 483         }
 484
 485         if (ring->hop < 0 || ring->hop >= nhi->hop_count) {
 486                 dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop);
 487                 ret = -EINVAL;
 488                 goto err_unlock;
 489         }
 490         if (ring->is_tx && nhi->tx_rings[ring->hop]) {
 491                 dev_warn(&nhi->pdev->dev, "TX hop %d already allocated\n",
 492                          ring->hop);
 493                 ret = -EBUSY;
 494                 goto err_unlock;
 495         } else if (!ring->is_tx && nhi->rx_rings[ring->hop]) {
 496                 dev_warn(&nhi->pdev->dev, "RX hop %d already allocated\n",
 497                          ring->hop);
 498                 ret = -EBUSY;
 499                 goto err_unlock;
 500         }
 501
 502         if (ring->is_tx)
 503                 nhi->tx_rings[ring->hop] = ring;
 504         else
 505                 nhi->rx_rings[ring->hop] = ring;
 506
 507 err_unlock:
 508         spin_unlock_irq(&nhi->lock);
 509
 510         return ret;
 511 }
 512
 513 static struct tb_ring *tb_ring_alloc(struct tb_nhi *nhi, u32 hop, int size,
 514                                      bool transmit, unsigned int flags,
 515                                      int e2e_tx_hop, u16 sof_mask, u16 eof_mask,
 516                                      void (*start_poll)(void *),
 517                                      void *poll_data)
 518 {
 519         struct tb_ring *ring = NULL;
 520
 521         dev_dbg(&nhi->pdev->dev, "allocating %s ring %d of size %d\n",
 522                 transmit ? "TX" : "RX", hop, size);
 523
 524         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 525         if (!ring)
 526                 return NULL;
 527
 528         spin_lock_init(&ring->lock);
 529         INIT_LIST_HEAD(&ring->queue);
 530         INIT_LIST_HEAD(&ring->in_flight);
 531         INIT_WORK(&ring->work, ring_work);
 532
 533         ring->nhi = nhi;
 534         ring->hop = hop;
 535         ring->is_tx = transmit;
 536         ring->size = size;
 537         ring->flags = flags;
 538         ring->e2e_tx_hop = e2e_tx_hop;
 539         ring->sof_mask = sof_mask;
 540         ring->eof_mask = eof_mask;
 541         ring->head = 0;
 542         ring->tail = 0;
 543         ring->running = false;
 544         ring->start_poll = start_poll;
 545         ring->poll_data = poll_data;
 546
 547         ring->descriptors = dma_alloc_coherent(&ring->nhi->pdev->dev,
 548                         size * sizeof(*ring->descriptors),
 549                         &ring->descriptors_dma, GFP_KERNEL | __GFP_ZERO);
 550         if (!ring->descriptors)
 551                 goto err_free_ring;
 552
 553         if (ring_request_msix(ring, flags & RING_FLAG_NO_SUSPEND))
 554                 goto err_free_descs;
 555
 556         if (nhi_alloc_hop(nhi, ring))
 557                 goto err_release_msix;
 558
 559         return ring;
 560
 561 err_release_msix:
 562         ring_release_msix(ring);
 563 err_free_descs:
 564         dma_free_coherent(&ring->nhi->pdev->dev,
 565                           ring->size * sizeof(*ring->descriptors),
 566                           ring->descriptors, ring->descriptors_dma);
 567 err_free_ring:
 568         kfree(ring);
 569
 570         return NULL;
 571 }
 572
 573 /**
 574  * tb_ring_alloc_tx() - Allocate DMA ring for transmit
 575  * @nhi: Pointer to the NHI the ring is to be allocated
 576  * @hop: HopID (ring) to allocate
 577  * @size: Number of entries in the ring
 578  * @flags: Flags for the ring
 579  */
 580 struct tb_ring *tb_ring_alloc_tx(struct tb_nhi *nhi, int hop, int size,
 581                                  unsigned int flags)
 582 {
 583         return tb_ring_alloc(nhi, hop, size, true, flags, 0, 0, 0, NULL, NULL);
 584 }
 585 EXPORT_SYMBOL_GPL(tb_ring_alloc_tx);
 586
 587 /**
 588  * tb_ring_alloc_rx() - Allocate DMA ring for receive
 589  * @nhi: Pointer to the NHI the ring is to be allocated
 590  * @hop: HopID (ring) to allocate. Pass %-1 for automatic allocation.
 591  * @size: Number of entries in the ring
 592  * @flags: Flags for the ring
 593  * @e2e_tx_hop: Transmit HopID when E2E is enabled in @flags
 594  * @sof_mask: Mask of PDF values that start a frame
 595  * @eof_mask: Mask of PDF values that end a frame
 596  * @start_poll: If not %NULL the ring will call this function when an
 597  *              interrupt is triggered and masked, instead of callback
 598  *              in each Rx frame.
 599  * @poll_data: Optional data passed to @start_poll
 600  */
 601 struct tb_ring *tb_ring_alloc_rx(struct tb_nhi *nhi, int hop, int size,
 602                                  unsigned int flags, int e2e_tx_hop,
 603                                  u16 sof_mask, u16 eof_mask,
 604                                  void (*start_poll)(void *), void *poll_data)
 605 {
 606         return tb_ring_alloc(nhi, hop, size, false, flags, e2e_tx_hop, sof_mask, eof_mask,
 607                              start_poll, poll_data);
 608 }
 609 EXPORT_SYMBOL_GPL(tb_ring_alloc_rx);
 610
 611 /**
 612  * tb_ring_start() - enable a ring
 613  * @ring: Ring to start
 614  *
 615  * Must not be invoked in parallel with tb_ring_stop().
 616  */
 617 void tb_ring_start(struct tb_ring *ring)
 618 {
 619         u16 frame_size;
 620         u32 flags;
 621
 622         spin_lock_irq(&ring->nhi->lock);
 623         spin_lock(&ring->lock);
 624         if (ring->nhi->going_away)
 625                 goto err;
 626         if (ring->running) {
 627                 dev_WARN(&ring->nhi->pdev->dev, "ring already started\n");
 628                 goto err;
 629         }
 630         dev_dbg(&ring->nhi->pdev->dev, "starting %s %d\n",
 631                 RING_TYPE(ring), ring->hop);
 632
 633         if (ring->flags & RING_FLAG_FRAME) {
 634                 /* Means 4096 */
 635                 frame_size = 0;
 636                 flags = RING_FLAG_ENABLE;
 637         } else {
 638                 frame_size = TB_FRAME_SIZE;
 639                 flags = RING_FLAG_ENABLE | RING_FLAG_RAW;
 640         }
 641
 642         ring_iowrite64desc(ring, ring->descriptors_dma, 0);
 643         if (ring->is_tx) {
 644                 ring_iowrite32desc(ring, ring->size, 12);
 645                 ring_iowrite32options(ring, 0, 4); /* time releated ? */
 646                 ring_iowrite32options(ring, flags, 0);
 647         } else {
 648                 u32 sof_eof_mask = ring->sof_mask << 16 | ring->eof_mask;
 649
 650                 ring_iowrite32desc(ring, (frame_size << 16) | ring->size, 12);
 651                 ring_iowrite32options(ring, sof_eof_mask, 4);
 652                 ring_iowrite32options(ring, flags, 0);
 653         }
 654
 655         /*
 656          * Now that the ring valid bit is set we can configure E2E if
 657          * enabled for the ring.
 658          */
 659         if (ring->flags & RING_FLAG_E2E) {
 660                 if (!ring->is_tx) {
 661                         u32 hop;
 662
 663                         hop = ring->e2e_tx_hop << REG_RX_OPTIONS_E2E_HOP_SHIFT;
 664                         hop &= REG_RX_OPTIONS_E2E_HOP_MASK;
 665                         flags |= hop;
 666
 667                         dev_dbg(&ring->nhi->pdev->dev,
 668                                 "enabling E2E for %s %d with TX HopID %d\n",
 669                                 RING_TYPE(ring), ring->hop, ring->e2e_tx_hop);
 670                 } else {
 671                         dev_dbg(&ring->nhi->pdev->dev, "enabling E2E for %s %d\n",
 672                                 RING_TYPE(ring), ring->hop);
 673                 }
 674
 675                 flags |= RING_FLAG_E2E_FLOW_CONTROL;
 676                 ring_iowrite32options(ring, flags, 0);
 677         }
 678
 679         ring_interrupt_active(ring, true);
 680         ring->running = true;
 681 err:
 682         spin_unlock(&ring->lock);
 683         spin_unlock_irq(&ring->nhi->lock);
 684 }
 685 EXPORT_SYMBOL_GPL(tb_ring_start);
 686
 687 /**
 688  * tb_ring_stop() - shutdown a ring
 689  * @ring: Ring to stop
 690  *
 691  * Must not be invoked from a callback.
 692  *
 693  * This method will disable the ring. Further calls to
 694  * tb_ring_tx/tb_ring_rx will return -ESHUTDOWN until ring_stop has been
 695  * called.
 696  *
 697  * All enqueued frames will be canceled and their callbacks will be executed
 698  * with frame->canceled set to true (on the callback thread). This method
 699  * returns only after all callback invocations have finished.
 700  */
 701 void tb_ring_stop(struct tb_ring *ring)
 702 {
 703         spin_lock_irq(&ring->nhi->lock);
 704         spin_lock(&ring->lock);
 705         dev_dbg(&ring->nhi->pdev->dev, "stopping %s %d\n",
 706                 RING_TYPE(ring), ring->hop);
 707         if (ring->nhi->going_away)
 708                 goto err;
 709         if (!ring->running) {
 710                 dev_WARN(&ring->nhi->pdev->dev, "%s %d already stopped\n",
 711                          RING_TYPE(ring), ring->hop);
 712                 goto err;
 713         }
 714         ring_interrupt_active(ring, false);
 715
 716         ring_iowrite32options(ring, 0, 0);
 717         ring_iowrite64desc(ring, 0, 0);
 718         ring_iowrite32desc(ring, 0, 8);
 719         ring_iowrite32desc(ring, 0, 12);
 720         ring->head = 0;
 721         ring->tail = 0;
 722         ring->running = false;
 723
 724 err:
 725         spin_unlock(&ring->lock);
 726         spin_unlock_irq(&ring->nhi->lock);
 727
 728         /*
 729          * schedule ring->work to invoke callbacks on all remaining frames.
 730          */
 731         schedule_work(&ring->work);
 732         flush_work(&ring->work);
 733 }
 734 EXPORT_SYMBOL_GPL(tb_ring_stop);
 735
 736 /*
 737  * tb_ring_free() - free ring
 738  *
 739  * When this method returns all invocations of ring->callback will have
 740  * finished.
 741  *
 742  * Ring must be stopped.
 743  *
 744  * Must NOT be called from ring_frame->callback!
 745  */
 746 void tb_ring_free(struct tb_ring *ring)
 747 {
 748         spin_lock_irq(&ring->nhi->lock);
 749         /*
 750          * Dissociate the ring from the NHI. This also ensures that
 751          * nhi_interrupt_work cannot reschedule ring->work.
 752          */
 753         if (ring->is_tx)
 754                 ring->nhi->tx_rings[ring->hop] = NULL;
 755         else
 756                 ring->nhi->rx_rings[ring->hop] = NULL;
 757
 758         if (ring->running) {
 759                 dev_WARN(&ring->nhi->pdev->dev, "%s %d still running\n",
 760                          RING_TYPE(ring), ring->hop);
 761         }
 762         spin_unlock_irq(&ring->nhi->lock);
 763
 764         ring_release_msix(ring);
 765
 766         dma_free_coherent(&ring->nhi->pdev->dev,
 767                           ring->size * sizeof(*ring->descriptors),
 768                           ring->descriptors, ring->descriptors_dma);
 769
 770         ring->descriptors = NULL;
 771         ring->descriptors_dma = 0;
 772
 773
 774         dev_dbg(&ring->nhi->pdev->dev, "freeing %s %d\n", RING_TYPE(ring),
 775                 ring->hop);
 776
 777         /*
 778          * ring->work can no longer be scheduled (it is scheduled only
 779          * by nhi_interrupt_work, ring_stop and ring_msix). Wait for it
 780          * to finish before freeing the ring.
 781          */
 782         flush_work(&ring->work);
 783         kfree(ring);
 784 }
 785 EXPORT_SYMBOL_GPL(tb_ring_free);
 786
 787 /**
 788  * nhi_mailbox_cmd() - Send a command through NHI mailbox
 789  * @nhi: Pointer to the NHI structure
 790  * @cmd: Command to send
 791  * @data: Data to be send with the command
 792  *
 793  * Sends mailbox command to the firmware running on NHI. Returns %0 in
 794  * case of success and negative errno in case of failure.
 795  */
 796 int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data)
 797 {
 798         ktime_t timeout;
 799         u32 val;
 800
 801         iowrite32(data, nhi->iobase + REG_INMAIL_DATA);
 802
 803         val = ioread32(nhi->iobase + REG_INMAIL_CMD);
 804         val &= ~(REG_INMAIL_CMD_MASK | REG_INMAIL_ERROR);
 805         val |= REG_INMAIL_OP_REQUEST | cmd;
 806         iowrite32(val, nhi->iobase + REG_INMAIL_CMD);
 807
 808         timeout = ktime_add_ms(ktime_get(), NHI_MAILBOX_TIMEOUT);
 809         do {
 810                 val = ioread32(nhi->iobase + REG_INMAIL_CMD);
 811                 if (!(val & REG_INMAIL_OP_REQUEST))
 812                         break;
 813                 usleep_range(10, 20);
 814         } while (ktime_before(ktime_get(), timeout));
 815
 816         if (val & REG_INMAIL_OP_REQUEST)
 817                 return -ETIMEDOUT;
 818         if (val & REG_INMAIL_ERROR)
 819                 return -EIO;
 820
 821         return 0;
 822 }
 823
 824 /**
 825  * nhi_mailbox_mode() - Return current firmware operation mode
 826  * @nhi: Pointer to the NHI structure
 827  *
 828  * The function reads current firmware operation mode using NHI mailbox
 829  * registers and returns it to the caller.
 830  */
 831 enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi)
 832 {
 833         u32 val;
 834
 835         val = ioread32(nhi->iobase + REG_OUTMAIL_CMD);
 836         val &= REG_OUTMAIL_CMD_OPMODE_MASK;
 837         val >>= REG_OUTMAIL_CMD_OPMODE_SHIFT;
 838
 839         return (enum nhi_fw_mode)val;
 840 }
 841
 842 static void nhi_interrupt_work(struct work_struct *work)
 843 {
 844         struct tb_nhi *nhi = container_of(work, typeof(*nhi), interrupt_work);
 845         int value = 0; /* Suppress uninitialized usage warning. */
 846         int bit;
 847         int hop = -1;
 848         int type = 0; /* current interrupt type 0: TX, 1: RX, 2: RX overflow */
 849         struct tb_ring *ring;
 850
 851         spin_lock_irq(&nhi->lock);
 852
 853         /*
 854          * Starting at REG_RING_NOTIFY_BASE there are three status bitfields
 855          * (TX, RX, RX overflow). We iterate over the bits and read a new
 856          * dwords as required. The registers are cleared on read.
 857          */
 858         for (bit = 0; bit < 3 * nhi->hop_count; bit++) {
 859                 if (bit % 32 == 0)
 860                         value = ioread32(nhi->iobase
 861                                          + REG_RING_NOTIFY_BASE
 862                                          + 4 * (bit / 32));
 863                 if (++hop == nhi->hop_count) {
 864                         hop = 0;
 865                         type++;
 866                 }
 867                 if ((value & (1 << (bit % 32))) == 0)
 868                         continue;
 869                 if (type == 2) {
 870                         dev_warn(&nhi->pdev->dev,
 871                                  "RX overflow for ring %d\n",
 872                                  hop);
 873                         continue;
 874                 }
 875                 if (type == 0)
 876                         ring = nhi->tx_rings[hop];
 877                 else
 878                         ring = nhi->rx_rings[hop];
 879                 if (ring == NULL) {
 880                         dev_warn(&nhi->pdev->dev,
 881                                  "got interrupt for inactive %s ring %d\n",
 882                                  type ? "RX" : "TX",
 883                                  hop);
 884                         continue;
 885                 }
 886
 887                 spin_lock(&ring->lock);
 888                 __ring_interrupt(ring);
 889                 spin_unlock(&ring->lock);
 890         }
 891         spin_unlock_irq(&nhi->lock);
 892 }
 893
 894 static irqreturn_t nhi_msi(int irq, void *data)
 895 {
 896         struct tb_nhi *nhi = data;
 897         schedule_work(&nhi->interrupt_work);
 898         return IRQ_HANDLED;
 899 }
 900
 901 static int __nhi_suspend_noirq(struct device *dev, bool wakeup)
 902 {
 903         struct pci_dev *pdev = to_pci_dev(dev);
 904         struct tb *tb = pci_get_drvdata(pdev);
 905         struct tb_nhi *nhi = tb->nhi;
 906         int ret;
 907
 908         ret = tb_domain_suspend_noirq(tb);
 909         if (ret)
 910                 return ret;
 911
 912         if (nhi->ops && nhi->ops->suspend_noirq) {
 913                 ret = nhi->ops->suspend_noirq(tb->nhi, wakeup);
 914                 if (ret)
 915                         return ret;
 916         }
 917
 918         return 0;
 919 }
 920
 921 static int nhi_suspend_noirq(struct device *dev)
 922 {
 923         return __nhi_suspend_noirq(dev, device_may_wakeup(dev));
 924 }
 925
 926 static int nhi_freeze_noirq(struct device *dev)
 927 {
 928         struct pci_dev *pdev = to_pci_dev(dev);
 929         struct tb *tb = pci_get_drvdata(pdev);
 930
 931         return tb_domain_freeze_noirq(tb);
 932 }
 933
 934 static int nhi_thaw_noirq(struct device *dev)
 935 {
 936         struct pci_dev *pdev = to_pci_dev(dev);
 937         struct tb *tb = pci_get_drvdata(pdev);
 938
 939         return tb_domain_thaw_noirq(tb);
 940 }
 941
 942 static bool nhi_wake_supported(struct pci_dev *pdev)
 943 {
 944         u8 val;
 945
 946         /*
 947          * If power rails are sustainable for wakeup from S4 this
 948          * property is set by the BIOS.
 949          */
 950         if (device_property_read_u8(&pdev->dev, "WAKE_SUPPORTED", &val))
 951                 return !!val;
 952
 953         return true;
 954 }
 955
 956 static int nhi_poweroff_noirq(struct device *dev)
 957 {
 958         struct pci_dev *pdev = to_pci_dev(dev);
 959         bool wakeup;
 960
 961         wakeup = device_may_wakeup(dev) && nhi_wake_supported(pdev);
 962         return __nhi_suspend_noirq(dev, wakeup);
 963 }
 964
 965 static void nhi_enable_int_throttling(struct tb_nhi *nhi)
 966 {
 967         /* Throttling is specified in 256ns increments */
 968         u32 throttle = DIV_ROUND_UP(128 * NSEC_PER_USEC, 256);
 969         unsigned int i;
 970
 971         /*
 972          * Configure interrupt throttling for all vectors even if we
 973          * only use few.
 974          */
 975         for (i = 0; i < MSIX_MAX_VECS; i++) {
 976                 u32 reg = REG_INT_THROTTLING_RATE + i * 4;
 977                 iowrite32(throttle, nhi->iobase + reg);
 978         }
 979 }
 980
 981 static int nhi_resume_noirq(struct device *dev)
 982 {
 983         struct pci_dev *pdev = to_pci_dev(dev);
 984         struct tb *tb = pci_get_drvdata(pdev);
 985         struct tb_nhi *nhi = tb->nhi;
 986         int ret;
 987
 988         /*
 989          * Check that the device is still there. It may be that the user
 990          * unplugged last device which causes the host controller to go
 991          * away on PCs.
 992          */
 993         if (!pci_device_is_present(pdev)) {
 994                 nhi->going_away = true;
 995         } else {
 996                 if (nhi->ops && nhi->ops->resume_noirq) {
 997                         ret = nhi->ops->resume_noirq(nhi);
 998                         if (ret)
 999                                 return ret;
1000                 }
1001                 nhi_enable_int_throttling(tb->nhi);
1002         }
1003
1004         return tb_domain_resume_noirq(tb);
1005 }
1006
1007 static int nhi_suspend(struct device *dev)
1008 {
1009         struct pci_dev *pdev = to_pci_dev(dev);
1010         struct tb *tb = pci_get_drvdata(pdev);
1011
1012         return tb_domain_suspend(tb);
1013 }
1014
1015 static void nhi_complete(struct device *dev)
1016 {
1017         struct pci_dev *pdev = to_pci_dev(dev);
1018         struct tb *tb = pci_get_drvdata(pdev);
1019
1020         /*
1021          * If we were runtime suspended when system suspend started,
1022          * schedule runtime resume now. It should bring the domain back
1023          * to functional state.
1024          */
1025         if (pm_runtime_suspended(&pdev->dev))
1026                 pm_runtime_resume(&pdev->dev);
1027         else
1028                 tb_domain_complete(tb);
1029 }
1030
1031 static int nhi_runtime_suspend(struct device *dev)
1032 {
1033         struct pci_dev *pdev = to_pci_dev(dev);
1034         struct tb *tb = pci_get_drvdata(pdev);
1035         struct tb_nhi *nhi = tb->nhi;
1036         int ret;
1037
1038         ret = tb_domain_runtime_suspend(tb);
1039         if (ret)
1040                 return ret;
1041
1042         if (nhi->ops && nhi->ops->runtime_suspend) {
1043                 ret = nhi->ops->runtime_suspend(tb->nhi);
1044                 if (ret)
1045                         return ret;
1046         }
1047         return 0;
1048 }
1049
1050 static int nhi_runtime_resume(struct device *dev)
1051 {
1052         struct pci_dev *pdev = to_pci_dev(dev);
1053         struct tb *tb = pci_get_drvdata(pdev);
1054         struct tb_nhi *nhi = tb->nhi;
1055         int ret;
1056
1057         if (nhi->ops && nhi->ops->runtime_resume) {
1058                 ret = nhi->ops->runtime_resume(nhi);
1059                 if (ret)
1060                         return ret;
1061         }
1062
1063         nhi_enable_int_throttling(nhi);
1064         return tb_domain_runtime_resume(tb);
1065 }
1066
1067 static void nhi_shutdown(struct tb_nhi *nhi)
1068 {
1069         int i;
1070
1071         dev_dbg(&nhi->pdev->dev, "shutdown\n");
1072
1073         for (i = 0; i < nhi->hop_count; i++) {
1074                 if (nhi->tx_rings[i])
1075                         dev_WARN(&nhi->pdev->dev,
1076                                  "TX ring %d is still active\n", i);
1077                 if (nhi->rx_rings[i])
1078                         dev_WARN(&nhi->pdev->dev,
1079                                  "RX ring %d is still active\n", i);
1080         }
1081         nhi_disable_interrupts(nhi);
1082         /*
1083          * We have to release the irq before calling flush_work. Otherwise an
1084          * already executing IRQ handler could call schedule_work again.
1085          */
1086         if (!nhi->pdev->msix_enabled) {
1087                 devm_free_irq(&nhi->pdev->dev, nhi->pdev->irq, nhi);
1088                 flush_work(&nhi->interrupt_work);
1089         }
1090         ida_destroy(&nhi->msix_ida);
1091
1092         if (nhi->ops && nhi->ops->shutdown)
1093                 nhi->ops->shutdown(nhi);
1094 }
1095
1096 static void nhi_check_quirks(struct tb_nhi *nhi)
1097 {
1098         /*
1099          * Intel hardware supports auto clear of the interrupt status
1100          * reqister right after interrupt is being issued.
1101          */
1102         if (nhi->pdev->vendor == PCI_VENDOR_ID_INTEL)
1103                 nhi->quirks |= QUIRK_AUTO_CLEAR_INT;
1104 }
1105
1106 static int nhi_init_msi(struct tb_nhi *nhi)
1107 {
1108         struct pci_dev *pdev = nhi->pdev;
1109         int res, irq, nvec;
1110
1111         /* In case someone left them on. */
1112         nhi_disable_interrupts(nhi);
1113
1114         nhi_enable_int_throttling(nhi);
1115
1116         ida_init(&nhi->msix_ida);
1117
1118         /*
1119          * The NHI has 16 MSI-X vectors or a single MSI. We first try to
1120          * get all MSI-X vectors and if we succeed, each ring will have
1121          * one MSI-X. If for some reason that does not work out, we
1122          * fallback to a single MSI.
1123          */
1124         nvec = pci_alloc_irq_vectors(pdev, MSIX_MIN_VECS, MSIX_MAX_VECS,
1125                                      PCI_IRQ_MSIX);
1126         if (nvec < 0) {
1127                 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1128                 if (nvec < 0)
1129                         return nvec;
1130
1131                 INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work);
1132
1133                 irq = pci_irq_vector(nhi->pdev, 0);
1134                 if (irq < 0)
1135                         return irq;
1136
1137                 res = devm_request_irq(&pdev->dev, irq, nhi_msi,
1138                                        IRQF_NO_SUSPEND, "thunderbolt", nhi);
1139                 if (res) {
1140                         dev_err(&pdev->dev, "request_irq failed, aborting\n");
1141                         return res;
1142                 }
1143         }
1144
1145         return 0;
1146 }
1147
1148 static bool nhi_imr_valid(struct pci_dev *pdev)
1149 {
1150         u8 val;
1151
1152         if (!device_property_read_u8(&pdev->dev, "IMR_VALID", &val))
1153                 return !!val;
1154
1155         return true;
1156 }
1157
1158 static struct tb *nhi_select_cm(struct tb_nhi *nhi)
1159 {
1160         struct tb *tb;
1161
1162         /*
1163          * USB4 case is simple. If we got control of any of the
1164          * capabilities, we use software CM.
1165          */
1166         if (tb_acpi_is_native())
1167                 return tb_probe(nhi);
1168
1169         /*
1170          * Either firmware based CM is running (we did not get control
1171          * from the firmware) or this is pre-USB4 PC so try first
1172          * firmware CM and then fallback to software CM.
1173          */
1174         tb = icm_probe(nhi);
1175         if (!tb)
1176                 tb = tb_probe(nhi);
1177
1178         return tb;
1179 }
1180
1181 static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1182 {
1183         struct tb_nhi *nhi;
1184         struct tb *tb;
1185         int res;
1186
1187         if (!nhi_imr_valid(pdev)) {
1188                 dev_warn(&pdev->dev, "firmware image not valid, aborting\n");
1189                 return -ENODEV;
1190         }
1191
1192         res = pcim_enable_device(pdev);
1193         if (res) {
1194                 dev_err(&pdev->dev, "cannot enable PCI device, aborting\n");
1195                 return res;
1196         }
1197
1198         res = pcim_iomap_regions(pdev, 1 << 0, "thunderbolt");
1199         if (res) {
1200                 dev_err(&pdev->dev, "cannot obtain PCI resources, aborting\n");
1201                 return res;
1202         }
1203
1204         nhi = devm_kzalloc(&pdev->dev, sizeof(*nhi), GFP_KERNEL);
1205         if (!nhi)
1206                 return -ENOMEM;
1207
1208         nhi->pdev = pdev;
1209         nhi->ops = (const struct tb_nhi_ops *)id->driver_data;
1210         /* cannot fail - table is allocated bin pcim_iomap_regions */
1211         nhi->iobase = pcim_iomap_table(pdev)[0];
1212         nhi->hop_count = ioread32(nhi->iobase + REG_HOP_COUNT) & 0x3ff;
1213         dev_dbg(&pdev->dev, "total paths: %d\n", nhi->hop_count);
1214
1215         nhi->tx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
1216                                      sizeof(*nhi->tx_rings), GFP_KERNEL);
1217         nhi->rx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
1218                                      sizeof(*nhi->rx_rings), GFP_KERNEL);
1219         if (!nhi->tx_rings || !nhi->rx_rings)
1220                 return -ENOMEM;
1221
1222         nhi_check_quirks(nhi);
1223
1224         res = nhi_init_msi(nhi);
1225         if (res) {
1226                 dev_err(&pdev->dev, "cannot enable MSI, aborting\n");
1227                 return res;
1228         }
1229
1230         spin_lock_init(&nhi->lock);
1231
1232         res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1233         if (res) {
1234                 dev_err(&pdev->dev, "failed to set DMA mask\n");
1235                 return res;
1236         }
1237
1238         pci_set_master(pdev);
1239
1240         if (nhi->ops && nhi->ops->init) {
1241                 res = nhi->ops->init(nhi);
1242                 if (res)
1243                         return res;
1244         }
1245
1246         tb = nhi_select_cm(nhi);
1247         if (!tb) {
1248                 dev_err(&nhi->pdev->dev,
1249                         "failed to determine connection manager, aborting\n");
1250                 return -ENODEV;
1251         }
1252
1253         dev_dbg(&nhi->pdev->dev, "NHI initialized, starting thunderbolt\n");
1254
1255         res = tb_domain_add(tb);
1256         if (res) {
1257                 /*
1258                  * At this point the RX/TX rings might already have been
1259                  * activated. Do a proper shutdown.
1260                  */
1261                 tb_domain_put(tb);
1262                 nhi_shutdown(nhi);
1263                 return res;
1264         }
1265         pci_set_drvdata(pdev, tb);
1266
1267         device_wakeup_enable(&pdev->dev);
1268
1269         pm_runtime_allow(&pdev->dev);
1270         pm_runtime_set_autosuspend_delay(&pdev->dev, TB_AUTOSUSPEND_DELAY);
1271         pm_runtime_use_autosuspend(&pdev->dev);
1272         pm_runtime_put_autosuspend(&pdev->dev);
1273
1274         return 0;
1275 }
1276
1277 static void nhi_remove(struct pci_dev *pdev)
1278 {
1279         struct tb *tb = pci_get_drvdata(pdev);
1280         struct tb_nhi *nhi = tb->nhi;
1281
1282         pm_runtime_get_sync(&pdev->dev);
1283         pm_runtime_dont_use_autosuspend(&pdev->dev);
1284         pm_runtime_forbid(&pdev->dev);
1285
1286         tb_domain_remove(tb);
1287         nhi_shutdown(nhi);
1288 }
1289
1290 /*
1291  * The tunneled pci bridges are siblings of us. Use resume_noirq to reenable
1292  * the tunnels asap. A corresponding pci quirk blocks the downstream bridges
1293  * resume_noirq until we are done.
1294  */
1295 static const struct dev_pm_ops nhi_pm_ops = {
1296         .suspend_noirq = nhi_suspend_noirq,
1297         .resume_noirq = nhi_resume_noirq,
1298         .freeze_noirq = nhi_freeze_noirq,  /*
1299                                             * we just disable hotplug, the
1300                                             * pci-tunnels stay alive.
1301                                             */
1302         .thaw_noirq = nhi_thaw_noirq,
1303         .restore_noirq = nhi_resume_noirq,
1304         .suspend = nhi_suspend,
1305         .poweroff_noirq = nhi_poweroff_noirq,
1306         .poweroff = nhi_suspend,
1307         .complete = nhi_complete,
1308         .runtime_suspend = nhi_runtime_suspend,
1309         .runtime_resume = nhi_runtime_resume,
1310 };
1311
1312 static struct pci_device_id nhi_ids[] = {
1313         /*
1314          * We have to specify class, the TB bridges use the same device and
1315          * vendor (sub)id on gen 1 and gen 2 controllers.
1316          */
1317         {
1318                 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1319                 .vendor = PCI_VENDOR_ID_INTEL,
1320                 .device = PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
1321                 .subvendor = 0x2222, .subdevice = 0x1111,
1322         },
1323         {
1324                 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1325                 .vendor = PCI_VENDOR_ID_INTEL,
1326                 .device = PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
1327                 .subvendor = 0x2222, .subdevice = 0x1111,
1328         },
1329         {
1330                 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1331                 .vendor = PCI_VENDOR_ID_INTEL,
1332                 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI,
1333                 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
1334         },
1335         {
1336                 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1337                 .vendor = PCI_VENDOR_ID_INTEL,
1338                 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI,
1339                 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
1340         },
1341
1342         /* Thunderbolt 3 */
1343         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI) },
1344         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI) },
1345         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) },
1346         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) },
1347         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) },
1348         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) },
1349         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) },
1350         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) },
1351         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI) },
1352         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI) },
1353         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI0),
1354           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1355         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI1),
1356           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1357         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI0),
1358           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1359         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI1),
1360           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1361         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI0),
1362           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1363         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI1),
1364           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1365         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI0),
1366           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1367         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI1),
1368           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1369
1370         /* Any USB4 compliant host */
1371         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_USB4, ~0) },
1372
1373         { 0,}
1374 };
1375
1376 MODULE_DEVICE_TABLE(pci, nhi_ids);
1377 MODULE_LICENSE("GPL");
1378
1379 static struct pci_driver nhi_driver = {
1380         .name = "thunderbolt",
1381         .id_table = nhi_ids,
1382         .probe = nhi_probe,
1383         .remove = nhi_remove,
1384         .shutdown = nhi_remove,
1385         .driver.pm = &nhi_pm_ops,
1386 };
1387
1388 static int __init nhi_init(void)
1389 {
1390         int ret;
1391
1392         ret = tb_domain_init();
1393         if (ret)
1394                 return ret;
1395         ret = pci_register_driver(&nhi_driver);
1396         if (ret)
1397                 tb_domain_exit();
1398         return ret;
1399 }
1400
1401 static void __exit nhi_unload(void)
1402 {
1403         pci_unregister_driver(&nhi_driver);
1404         tb_domain_exit();
1405 }
1406
1407 rootfs_initcall(nhi_init);
1408 module_exit(nhi_unload);