drivers/thunderbolt/nhi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Thunderbolt driver - NHI driver
   4  *
   5  * The NHI (native host interface) is the pci device that allows us to send and
   6  * receive frames from the thunderbolt bus.
   7  *
   8  * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
   9  * Copyright (C) 2018, Intel Corporation
  10  */
  11
  12 #include <linux/pm_runtime.h>
  13 #include <linux/slab.h>
  14 #include <linux/errno.h>
  15 #include <linux/pci.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/module.h>
  18 #include <linux/delay.h>
  19 #include <linux/property.h>
  20 #include <linux/platform_data/x86/apple.h>
  21
  22 #include "nhi.h"
  23 #include "nhi_regs.h"
  24 #include "tb.h"
  25
  26 #define RING_TYPE(ring) ((ring)->is_tx ? "TX ring" : "RX ring")
  27
  28 #define RING_FIRST_USABLE_HOPID 1
  29
  30 /*
  31  * Minimal number of vectors when we use MSI-X. Two for control channel
  32  * Rx/Tx and the rest four are for cross domain DMA paths.
  33  */
  34 #define MSIX_MIN_VECS           6
  35 #define MSIX_MAX_VECS           16
  36
  37 #define NHI_MAILBOX_TIMEOUT     500 /* ms */
  38
  39 static int ring_interrupt_index(struct tb_ring *ring)
  40 {
  41         int bit = ring->hop;
  42         if (!ring->is_tx)
  43                 bit += ring->nhi->hop_count;
  44         return bit;
  45 }
  46
  47 /**
  48  * ring_interrupt_active() - activate/deactivate interrupts for a single ring
  49  *
  50  * ring->nhi->lock must be held.
  51  */
  52 static void ring_interrupt_active(struct tb_ring *ring, bool active)
  53 {
  54         int reg = REG_RING_INTERRUPT_BASE +
  55                   ring_interrupt_index(ring) / 32 * 4;
  56         int bit = ring_interrupt_index(ring) & 31;
  57         int mask = 1 << bit;
  58         u32 old, new;
  59
  60         if (ring->irq > 0) {
  61                 u32 step, shift, ivr, misc;
  62                 void __iomem *ivr_base;
  63                 int index;
  64
  65                 if (ring->is_tx)
  66                         index = ring->hop;
  67                 else
  68                         index = ring->hop + ring->nhi->hop_count;
  69
  70                 /*
  71                  * Ask the hardware to clear interrupt status bits automatically
  72                  * since we already know which interrupt was triggered.
  73                  */
  74                 misc = ioread32(ring->nhi->iobase + REG_DMA_MISC);
  75                 if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) {
  76                         misc |= REG_DMA_MISC_INT_AUTO_CLEAR;
  77                         iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC);
  78                 }
  79
  80                 ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE;
  81                 step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
  82                 shift = index % REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
  83                 ivr = ioread32(ivr_base + step);
  84                 ivr &= ~(REG_INT_VEC_ALLOC_MASK << shift);
  85                 if (active)
  86                         ivr |= ring->vector << shift;
  87                 iowrite32(ivr, ivr_base + step);
  88         }
  89
  90         old = ioread32(ring->nhi->iobase + reg);
  91         if (active)
  92                 new = old | mask;
  93         else
  94                 new = old & ~mask;
  95
  96         dev_dbg(&ring->nhi->pdev->dev,
  97                 "%s interrupt at register %#x bit %d (%#x -> %#x)\n",
  98                 active ? "enabling" : "disabling", reg, bit, old, new);
  99
 100         if (new == old)
 101                 dev_WARN(&ring->nhi->pdev->dev,
 102                                          "interrupt for %s %d is already %s\n",
 103                                          RING_TYPE(ring), ring->hop,
 104                                          active ? "enabled" : "disabled");
 105         iowrite32(new, ring->nhi->iobase + reg);
 106 }
 107
 108 /**
 109  * nhi_disable_interrupts() - disable interrupts for all rings
 110  *
 111  * Use only during init and shutdown.
 112  */
 113 static void nhi_disable_interrupts(struct tb_nhi *nhi)
 114 {
 115         int i = 0;
 116         /* disable interrupts */
 117         for (i = 0; i < RING_INTERRUPT_REG_COUNT(nhi); i++)
 118                 iowrite32(0, nhi->iobase + REG_RING_INTERRUPT_BASE + 4 * i);
 119
 120         /* clear interrupt status bits */
 121         for (i = 0; i < RING_NOTIFY_REG_COUNT(nhi); i++)
 122                 ioread32(nhi->iobase + REG_RING_NOTIFY_BASE + 4 * i);
 123 }
 124
 125 /* ring helper methods */
 126
 127 static void __iomem *ring_desc_base(struct tb_ring *ring)
 128 {
 129         void __iomem *io = ring->nhi->iobase;
 130         io += ring->is_tx ? REG_TX_RING_BASE : REG_RX_RING_BASE;
 131         io += ring->hop * 16;
 132         return io;
 133 }
 134
 135 static void __iomem *ring_options_base(struct tb_ring *ring)
 136 {
 137         void __iomem *io = ring->nhi->iobase;
 138         io += ring->is_tx ? REG_TX_OPTIONS_BASE : REG_RX_OPTIONS_BASE;
 139         io += ring->hop * 32;
 140         return io;
 141 }
 142
 143 static void ring_iowrite_cons(struct tb_ring *ring, u16 cons)
 144 {
 145         /*
 146          * The other 16-bits in the register is read-only and writes to it
 147          * are ignored by the hardware so we can save one ioread32() by
 148          * filling the read-only bits with zeroes.
 149          */
 150         iowrite32(cons, ring_desc_base(ring) + 8);
 151 }
 152
 153 static void ring_iowrite_prod(struct tb_ring *ring, u16 prod)
 154 {
 155         /* See ring_iowrite_cons() above for explanation */
 156         iowrite32(prod << 16, ring_desc_base(ring) + 8);
 157 }
 158
 159 static void ring_iowrite32desc(struct tb_ring *ring, u32 value, u32 offset)
 160 {
 161         iowrite32(value, ring_desc_base(ring) + offset);
 162 }
 163
 164 static void ring_iowrite64desc(struct tb_ring *ring, u64 value, u32 offset)
 165 {
 166         iowrite32(value, ring_desc_base(ring) + offset);
 167         iowrite32(value >> 32, ring_desc_base(ring) + offset + 4);
 168 }
 169
 170 static void ring_iowrite32options(struct tb_ring *ring, u32 value, u32 offset)
 171 {
 172         iowrite32(value, ring_options_base(ring) + offset);
 173 }
 174
 175 static bool ring_full(struct tb_ring *ring)
 176 {
 177         return ((ring->head + 1) % ring->size) == ring->tail;
 178 }
 179
 180 static bool ring_empty(struct tb_ring *ring)
 181 {
 182         return ring->head == ring->tail;
 183 }
 184
 185 /**
 186  * ring_write_descriptors() - post frames from ring->queue to the controller
 187  *
 188  * ring->lock is held.
 189  */
 190 static void ring_write_descriptors(struct tb_ring *ring)
 191 {
 192         struct ring_frame *frame, *n;
 193         struct ring_desc *descriptor;
 194         list_for_each_entry_safe(frame, n, &ring->queue, list) {
 195                 if (ring_full(ring))
 196                         break;
 197                 list_move_tail(&frame->list, &ring->in_flight);
 198                 descriptor = &ring->descriptors[ring->head];
 199                 descriptor->phys = frame->buffer_phy;
 200                 descriptor->time = 0;
 201                 descriptor->flags = RING_DESC_POSTED | RING_DESC_INTERRUPT;
 202                 if (ring->is_tx) {
 203                         descriptor->length = frame->size;
 204                         descriptor->eof = frame->eof;
 205                         descriptor->sof = frame->sof;
 206                 }
 207                 ring->head = (ring->head + 1) % ring->size;
 208                 if (ring->is_tx)
 209                         ring_iowrite_prod(ring, ring->head);
 210                 else
 211                         ring_iowrite_cons(ring, ring->head);
 212         }
 213 }
 214
 215 /**
 216  * ring_work() - progress completed frames
 217  *
 218  * If the ring is shutting down then all frames are marked as canceled and
 219  * their callbacks are invoked.
 220  *
 221  * Otherwise we collect all completed frame from the ring buffer, write new
 222  * frame to the ring buffer and invoke the callbacks for the completed frames.
 223  */
 224 static void ring_work(struct work_struct *work)
 225 {
 226         struct tb_ring *ring = container_of(work, typeof(*ring), work);
 227         struct ring_frame *frame;
 228         bool canceled = false;
 229         unsigned long flags;
 230         LIST_HEAD(done);
 231
 232         spin_lock_irqsave(&ring->lock, flags);
 233
 234         if (!ring->running) {
 235                 /*  Move all frames to done and mark them as canceled. */
 236                 list_splice_tail_init(&ring->in_flight, &done);
 237                 list_splice_tail_init(&ring->queue, &done);
 238                 canceled = true;
 239                 goto invoke_callback;
 240         }
 241
 242         while (!ring_empty(ring)) {
 243                 if (!(ring->descriptors[ring->tail].flags
 244                                 & RING_DESC_COMPLETED))
 245                         break;
 246                 frame = list_first_entry(&ring->in_flight, typeof(*frame),
 247                                          list);
 248                 list_move_tail(&frame->list, &done);
 249                 if (!ring->is_tx) {
 250                         frame->size = ring->descriptors[ring->tail].length;
 251                         frame->eof = ring->descriptors[ring->tail].eof;
 252                         frame->sof = ring->descriptors[ring->tail].sof;
 253                         frame->flags = ring->descriptors[ring->tail].flags;
 254                 }
 255                 ring->tail = (ring->tail + 1) % ring->size;
 256         }
 257         ring_write_descriptors(ring);
 258
 259 invoke_callback:
 260         /* allow callbacks to schedule new work */
 261         spin_unlock_irqrestore(&ring->lock, flags);
 262         while (!list_empty(&done)) {
 263                 frame = list_first_entry(&done, typeof(*frame), list);
 264                 /*
 265                  * The callback may reenqueue or delete frame.
 266                  * Do not hold on to it.
 267                  */
 268                 list_del_init(&frame->list);
 269                 if (frame->callback)
 270                         frame->callback(ring, frame, canceled);
 271         }
 272 }
 273
 274 int __tb_ring_enqueue(struct tb_ring *ring, struct ring_frame *frame)
 275 {
 276         unsigned long flags;
 277         int ret = 0;
 278
 279         spin_lock_irqsave(&ring->lock, flags);
 280         if (ring->running) {
 281                 list_add_tail(&frame->list, &ring->queue);
 282                 ring_write_descriptors(ring);
 283         } else {
 284                 ret = -ESHUTDOWN;
 285         }
 286         spin_unlock_irqrestore(&ring->lock, flags);
 287         return ret;
 288 }
 289 EXPORT_SYMBOL_GPL(__tb_ring_enqueue);
 290
 291 /**
 292  * tb_ring_poll() - Poll one completed frame from the ring
 293  * @ring: Ring to poll
 294  *
 295  * This function can be called when @start_poll callback of the @ring
 296  * has been called. It will read one completed frame from the ring and
 297  * return it to the caller. Returns %NULL if there is no more completed
 298  * frames.
 299  */
 300 struct ring_frame *tb_ring_poll(struct tb_ring *ring)
 301 {
 302         struct ring_frame *frame = NULL;
 303         unsigned long flags;
 304
 305         spin_lock_irqsave(&ring->lock, flags);
 306         if (!ring->running)
 307                 goto unlock;
 308         if (ring_empty(ring))
 309                 goto unlock;
 310
 311         if (ring->descriptors[ring->tail].flags & RING_DESC_COMPLETED) {
 312                 frame = list_first_entry(&ring->in_flight, typeof(*frame),
 313                                          list);
 314                 list_del_init(&frame->list);
 315
 316                 if (!ring->is_tx) {
 317                         frame->size = ring->descriptors[ring->tail].length;
 318                         frame->eof = ring->descriptors[ring->tail].eof;
 319                         frame->sof = ring->descriptors[ring->tail].sof;
 320                         frame->flags = ring->descriptors[ring->tail].flags;
 321                 }
 322
 323                 ring->tail = (ring->tail + 1) % ring->size;
 324         }
 325
 326 unlock:
 327         spin_unlock_irqrestore(&ring->lock, flags);
 328         return frame;
 329 }
 330 EXPORT_SYMBOL_GPL(tb_ring_poll);
 331
 332 static void __ring_interrupt_mask(struct tb_ring *ring, bool mask)
 333 {
 334         int idx = ring_interrupt_index(ring);
 335         int reg = REG_RING_INTERRUPT_BASE + idx / 32 * 4;
 336         int bit = idx % 32;
 337         u32 val;
 338
 339         val = ioread32(ring->nhi->iobase + reg);
 340         if (mask)
 341                 val &= ~BIT(bit);
 342         else
 343                 val |= BIT(bit);
 344         iowrite32(val, ring->nhi->iobase + reg);
 345 }
 346
 347 /* Both @nhi->lock and @ring->lock should be held */
 348 static void __ring_interrupt(struct tb_ring *ring)
 349 {
 350         if (!ring->running)
 351                 return;
 352
 353         if (ring->start_poll) {
 354                 __ring_interrupt_mask(ring, true);
 355                 ring->start_poll(ring->poll_data);
 356         } else {
 357                 schedule_work(&ring->work);
 358         }
 359 }
 360
 361 /**
 362  * tb_ring_poll_complete() - Re-start interrupt for the ring
 363  * @ring: Ring to re-start the interrupt
 364  *
 365  * This will re-start (unmask) the ring interrupt once the user is done
 366  * with polling.
 367  */
 368 void tb_ring_poll_complete(struct tb_ring *ring)
 369 {
 370         unsigned long flags;
 371
 372         spin_lock_irqsave(&ring->nhi->lock, flags);
 373         spin_lock(&ring->lock);
 374         if (ring->start_poll)
 375                 __ring_interrupt_mask(ring, false);
 376         spin_unlock(&ring->lock);
 377         spin_unlock_irqrestore(&ring->nhi->lock, flags);
 378 }
 379 EXPORT_SYMBOL_GPL(tb_ring_poll_complete);
 380
 381 static irqreturn_t ring_msix(int irq, void *data)
 382 {
 383         struct tb_ring *ring = data;
 384
 385         spin_lock(&ring->nhi->lock);
 386         spin_lock(&ring->lock);
 387         __ring_interrupt(ring);
 388         spin_unlock(&ring->lock);
 389         spin_unlock(&ring->nhi->lock);
 390
 391         return IRQ_HANDLED;
 392 }
 393
 394 static int ring_request_msix(struct tb_ring *ring, bool no_suspend)
 395 {
 396         struct tb_nhi *nhi = ring->nhi;
 397         unsigned long irqflags;
 398         int ret;
 399
 400         if (!nhi->pdev->msix_enabled)
 401                 return 0;
 402
 403         ret = ida_simple_get(&nhi->msix_ida, 0, MSIX_MAX_VECS, GFP_KERNEL);
 404         if (ret < 0)
 405                 return ret;
 406
 407         ring->vector = ret;
 408
 409         ring->irq = pci_irq_vector(ring->nhi->pdev, ring->vector);
 410         if (ring->irq < 0)
 411                 return ring->irq;
 412
 413         irqflags = no_suspend ? IRQF_NO_SUSPEND : 0;
 414         return request_irq(ring->irq, ring_msix, irqflags, "thunderbolt", ring);
 415 }
 416
 417 static void ring_release_msix(struct tb_ring *ring)
 418 {
 419         if (ring->irq <= 0)
 420                 return;
 421
 422         free_irq(ring->irq, ring);
 423         ida_simple_remove(&ring->nhi->msix_ida, ring->vector);
 424         ring->vector = 0;
 425         ring->irq = 0;
 426 }
 427
 428 static int nhi_alloc_hop(struct tb_nhi *nhi, struct tb_ring *ring)
 429 {
 430         int ret = 0;
 431
 432         spin_lock_irq(&nhi->lock);
 433
 434         if (ring->hop < 0) {
 435                 unsigned int i;
 436
 437                 /*
 438                  * Automatically allocate HopID from the non-reserved
 439                  * range 1 .. hop_count - 1.
 440                  */
 441                 for (i = RING_FIRST_USABLE_HOPID; i < nhi->hop_count; i++) {
 442                         if (ring->is_tx) {
 443                                 if (!nhi->tx_rings[i]) {
 444                                         ring->hop = i;
 445                                         break;
 446                                 }
 447                         } else {
 448                                 if (!nhi->rx_rings[i]) {
 449                                         ring->hop = i;
 450                                         break;
 451                                 }
 452                         }
 453                 }
 454         }
 455
 456         if (ring->hop < 0 || ring->hop >= nhi->hop_count) {
 457                 dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop);
 458                 ret = -EINVAL;
 459                 goto err_unlock;
 460         }
 461         if (ring->is_tx && nhi->tx_rings[ring->hop]) {
 462                 dev_warn(&nhi->pdev->dev, "TX hop %d already allocated\n",
 463                          ring->hop);
 464                 ret = -EBUSY;
 465                 goto err_unlock;
 466         } else if (!ring->is_tx && nhi->rx_rings[ring->hop]) {
 467                 dev_warn(&nhi->pdev->dev, "RX hop %d already allocated\n",
 468                          ring->hop);
 469                 ret = -EBUSY;
 470                 goto err_unlock;
 471         }
 472
 473         if (ring->is_tx)
 474                 nhi->tx_rings[ring->hop] = ring;
 475         else
 476                 nhi->rx_rings[ring->hop] = ring;
 477
 478 err_unlock:
 479         spin_unlock_irq(&nhi->lock);
 480
 481         return ret;
 482 }
 483
 484 static struct tb_ring *tb_ring_alloc(struct tb_nhi *nhi, u32 hop, int size,
 485                                      bool transmit, unsigned int flags,
 486                                      u16 sof_mask, u16 eof_mask,
 487                                      void (*start_poll)(void *),
 488                                      void *poll_data)
 489 {
 490         struct tb_ring *ring = NULL;
 491
 492         dev_dbg(&nhi->pdev->dev, "allocating %s ring %d of size %d\n",
 493                 transmit ? "TX" : "RX", hop, size);
 494
 495         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 496         if (!ring)
 497                 return NULL;
 498
 499         spin_lock_init(&ring->lock);
 500         INIT_LIST_HEAD(&ring->queue);
 501         INIT_LIST_HEAD(&ring->in_flight);
 502         INIT_WORK(&ring->work, ring_work);
 503
 504         ring->nhi = nhi;
 505         ring->hop = hop;
 506         ring->is_tx = transmit;
 507         ring->size = size;
 508         ring->flags = flags;
 509         ring->sof_mask = sof_mask;
 510         ring->eof_mask = eof_mask;
 511         ring->head = 0;
 512         ring->tail = 0;
 513         ring->running = false;
 514         ring->start_poll = start_poll;
 515         ring->poll_data = poll_data;
 516
 517         ring->descriptors = dma_alloc_coherent(&ring->nhi->pdev->dev,
 518                         size * sizeof(*ring->descriptors),
 519                         &ring->descriptors_dma, GFP_KERNEL | __GFP_ZERO);
 520         if (!ring->descriptors)
 521                 goto err_free_ring;
 522
 523         if (ring_request_msix(ring, flags & RING_FLAG_NO_SUSPEND))
 524                 goto err_free_descs;
 525
 526         if (nhi_alloc_hop(nhi, ring))
 527                 goto err_release_msix;
 528
 529         return ring;
 530
 531 err_release_msix:
 532         ring_release_msix(ring);
 533 err_free_descs:
 534         dma_free_coherent(&ring->nhi->pdev->dev,
 535                           ring->size * sizeof(*ring->descriptors),
 536                           ring->descriptors, ring->descriptors_dma);
 537 err_free_ring:
 538         kfree(ring);
 539
 540         return NULL;
 541 }
 542
 543 /**
 544  * tb_ring_alloc_tx() - Allocate DMA ring for transmit
 545  * @nhi: Pointer to the NHI the ring is to be allocated
 546  * @hop: HopID (ring) to allocate
 547  * @size: Number of entries in the ring
 548  * @flags: Flags for the ring
 549  */
 550 struct tb_ring *tb_ring_alloc_tx(struct tb_nhi *nhi, int hop, int size,
 551                                  unsigned int flags)
 552 {
 553         return tb_ring_alloc(nhi, hop, size, true, flags, 0, 0, NULL, NULL);
 554 }
 555 EXPORT_SYMBOL_GPL(tb_ring_alloc_tx);
 556
 557 /**
 558  * tb_ring_alloc_rx() - Allocate DMA ring for receive
 559  * @nhi: Pointer to the NHI the ring is to be allocated
 560  * @hop: HopID (ring) to allocate. Pass %-1 for automatic allocation.
 561  * @size: Number of entries in the ring
 562  * @flags: Flags for the ring
 563  * @sof_mask: Mask of PDF values that start a frame
 564  * @eof_mask: Mask of PDF values that end a frame
 565  * @start_poll: If not %NULL the ring will call this function when an
 566  *              interrupt is triggered and masked, instead of callback
 567  *              in each Rx frame.
 568  * @poll_data: Optional data passed to @start_poll
 569  */
 570 struct tb_ring *tb_ring_alloc_rx(struct tb_nhi *nhi, int hop, int size,
 571                                  unsigned int flags, u16 sof_mask, u16 eof_mask,
 572                                  void (*start_poll)(void *), void *poll_data)
 573 {
 574         return tb_ring_alloc(nhi, hop, size, false, flags, sof_mask, eof_mask,
 575                              start_poll, poll_data);
 576 }
 577 EXPORT_SYMBOL_GPL(tb_ring_alloc_rx);
 578
 579 /**
 580  * tb_ring_start() - enable a ring
 581  *
 582  * Must not be invoked in parallel with tb_ring_stop().
 583  */
 584 void tb_ring_start(struct tb_ring *ring)
 585 {
 586         u16 frame_size;
 587         u32 flags;
 588
 589         spin_lock_irq(&ring->nhi->lock);
 590         spin_lock(&ring->lock);
 591         if (ring->nhi->going_away)
 592                 goto err;
 593         if (ring->running) {
 594                 dev_WARN(&ring->nhi->pdev->dev, "ring already started\n");
 595                 goto err;
 596         }
 597         dev_dbg(&ring->nhi->pdev->dev, "starting %s %d\n",
 598                 RING_TYPE(ring), ring->hop);
 599
 600         if (ring->flags & RING_FLAG_FRAME) {
 601                 /* Means 4096 */
 602                 frame_size = 0;
 603                 flags = RING_FLAG_ENABLE;
 604         } else {
 605                 frame_size = TB_FRAME_SIZE;
 606                 flags = RING_FLAG_ENABLE | RING_FLAG_RAW;
 607         }
 608
 609         ring_iowrite64desc(ring, ring->descriptors_dma, 0);
 610         if (ring->is_tx) {
 611                 ring_iowrite32desc(ring, ring->size, 12);
 612                 ring_iowrite32options(ring, 0, 4); /* time releated ? */
 613                 ring_iowrite32options(ring, flags, 0);
 614         } else {
 615                 u32 sof_eof_mask = ring->sof_mask << 16 | ring->eof_mask;
 616
 617                 ring_iowrite32desc(ring, (frame_size << 16) | ring->size, 12);
 618                 ring_iowrite32options(ring, sof_eof_mask, 4);
 619                 ring_iowrite32options(ring, flags, 0);
 620         }
 621         ring_interrupt_active(ring, true);
 622         ring->running = true;
 623 err:
 624         spin_unlock(&ring->lock);
 625         spin_unlock_irq(&ring->nhi->lock);
 626 }
 627 EXPORT_SYMBOL_GPL(tb_ring_start);
 628
 629 /**
 630  * tb_ring_stop() - shutdown a ring
 631  *
 632  * Must not be invoked from a callback.
 633  *
 634  * This method will disable the ring. Further calls to
 635  * tb_ring_tx/tb_ring_rx will return -ESHUTDOWN until ring_stop has been
 636  * called.
 637  *
 638  * All enqueued frames will be canceled and their callbacks will be executed
 639  * with frame->canceled set to true (on the callback thread). This method
 640  * returns only after all callback invocations have finished.
 641  */
 642 void tb_ring_stop(struct tb_ring *ring)
 643 {
 644         spin_lock_irq(&ring->nhi->lock);
 645         spin_lock(&ring->lock);
 646         dev_dbg(&ring->nhi->pdev->dev, "stopping %s %d\n",
 647                 RING_TYPE(ring), ring->hop);
 648         if (ring->nhi->going_away)
 649                 goto err;
 650         if (!ring->running) {
 651                 dev_WARN(&ring->nhi->pdev->dev, "%s %d already stopped\n",
 652                          RING_TYPE(ring), ring->hop);
 653                 goto err;
 654         }
 655         ring_interrupt_active(ring, false);
 656
 657         ring_iowrite32options(ring, 0, 0);
 658         ring_iowrite64desc(ring, 0, 0);
 659         ring_iowrite32desc(ring, 0, 8);
 660         ring_iowrite32desc(ring, 0, 12);
 661         ring->head = 0;
 662         ring->tail = 0;
 663         ring->running = false;
 664
 665 err:
 666         spin_unlock(&ring->lock);
 667         spin_unlock_irq(&ring->nhi->lock);
 668
 669         /*
 670          * schedule ring->work to invoke callbacks on all remaining frames.
 671          */
 672         schedule_work(&ring->work);
 673         flush_work(&ring->work);
 674 }
 675 EXPORT_SYMBOL_GPL(tb_ring_stop);
 676
 677 /*
 678  * tb_ring_free() - free ring
 679  *
 680  * When this method returns all invocations of ring->callback will have
 681  * finished.
 682  *
 683  * Ring must be stopped.
 684  *
 685  * Must NOT be called from ring_frame->callback!
 686  */
 687 void tb_ring_free(struct tb_ring *ring)
 688 {
 689         spin_lock_irq(&ring->nhi->lock);
 690         /*
 691          * Dissociate the ring from the NHI. This also ensures that
 692          * nhi_interrupt_work cannot reschedule ring->work.
 693          */
 694         if (ring->is_tx)
 695                 ring->nhi->tx_rings[ring->hop] = NULL;
 696         else
 697                 ring->nhi->rx_rings[ring->hop] = NULL;
 698
 699         if (ring->running) {
 700                 dev_WARN(&ring->nhi->pdev->dev, "%s %d still running\n",
 701                          RING_TYPE(ring), ring->hop);
 702         }
 703         spin_unlock_irq(&ring->nhi->lock);
 704
 705         ring_release_msix(ring);
 706
 707         dma_free_coherent(&ring->nhi->pdev->dev,
 708                           ring->size * sizeof(*ring->descriptors),
 709                           ring->descriptors, ring->descriptors_dma);
 710
 711         ring->descriptors = NULL;
 712         ring->descriptors_dma = 0;
 713
 714
 715         dev_dbg(&ring->nhi->pdev->dev, "freeing %s %d\n", RING_TYPE(ring),
 716                 ring->hop);
 717
 718         /**
 719          * ring->work can no longer be scheduled (it is scheduled only
 720          * by nhi_interrupt_work, ring_stop and ring_msix). Wait for it
 721          * to finish before freeing the ring.
 722          */
 723         flush_work(&ring->work);
 724         kfree(ring);
 725 }
 726 EXPORT_SYMBOL_GPL(tb_ring_free);
 727
 728 /**
 729  * nhi_mailbox_cmd() - Send a command through NHI mailbox
 730  * @nhi: Pointer to the NHI structure
 731  * @cmd: Command to send
 732  * @data: Data to be send with the command
 733  *
 734  * Sends mailbox command to the firmware running on NHI. Returns %0 in
 735  * case of success and negative errno in case of failure.
 736  */
 737 int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data)
 738 {
 739         ktime_t timeout;
 740         u32 val;
 741
 742         iowrite32(data, nhi->iobase + REG_INMAIL_DATA);
 743
 744         val = ioread32(nhi->iobase + REG_INMAIL_CMD);
 745         val &= ~(REG_INMAIL_CMD_MASK | REG_INMAIL_ERROR);
 746         val |= REG_INMAIL_OP_REQUEST | cmd;
 747         iowrite32(val, nhi->iobase + REG_INMAIL_CMD);
 748
 749         timeout = ktime_add_ms(ktime_get(), NHI_MAILBOX_TIMEOUT);
 750         do {
 751                 val = ioread32(nhi->iobase + REG_INMAIL_CMD);
 752                 if (!(val & REG_INMAIL_OP_REQUEST))
 753                         break;
 754                 usleep_range(10, 20);
 755         } while (ktime_before(ktime_get(), timeout));
 756
 757         if (val & REG_INMAIL_OP_REQUEST)
 758                 return -ETIMEDOUT;
 759         if (val & REG_INMAIL_ERROR)
 760                 return -EIO;
 761
 762         return 0;
 763 }
 764
 765 /**
 766  * nhi_mailbox_mode() - Return current firmware operation mode
 767  * @nhi: Pointer to the NHI structure
 768  *
 769  * The function reads current firmware operation mode using NHI mailbox
 770  * registers and returns it to the caller.
 771  */
 772 enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi)
 773 {
 774         u32 val;
 775
 776         val = ioread32(nhi->iobase + REG_OUTMAIL_CMD);
 777         val &= REG_OUTMAIL_CMD_OPMODE_MASK;
 778         val >>= REG_OUTMAIL_CMD_OPMODE_SHIFT;
 779
 780         return (enum nhi_fw_mode)val;
 781 }
 782
 783 static void nhi_interrupt_work(struct work_struct *work)
 784 {
 785         struct tb_nhi *nhi = container_of(work, typeof(*nhi), interrupt_work);
 786         int value = 0; /* Suppress uninitialized usage warning. */
 787         int bit;
 788         int hop = -1;
 789         int type = 0; /* current interrupt type 0: TX, 1: RX, 2: RX overflow */
 790         struct tb_ring *ring;
 791
 792         spin_lock_irq(&nhi->lock);
 793
 794         /*
 795          * Starting at REG_RING_NOTIFY_BASE there are three status bitfields
 796          * (TX, RX, RX overflow). We iterate over the bits and read a new
 797          * dwords as required. The registers are cleared on read.
 798          */
 799         for (bit = 0; bit < 3 * nhi->hop_count; bit++) {
 800                 if (bit % 32 == 0)
 801                         value = ioread32(nhi->iobase
 802                                          + REG_RING_NOTIFY_BASE
 803                                          + 4 * (bit / 32));
 804                 if (++hop == nhi->hop_count) {
 805                         hop = 0;
 806                         type++;
 807                 }
 808                 if ((value & (1 << (bit % 32))) == 0)
 809                         continue;
 810                 if (type == 2) {
 811                         dev_warn(&nhi->pdev->dev,
 812                                  "RX overflow for ring %d\n",
 813                                  hop);
 814                         continue;
 815                 }
 816                 if (type == 0)
 817                         ring = nhi->tx_rings[hop];
 818                 else
 819                         ring = nhi->rx_rings[hop];
 820                 if (ring == NULL) {
 821                         dev_warn(&nhi->pdev->dev,
 822                                  "got interrupt for inactive %s ring %d\n",
 823                                  type ? "RX" : "TX",
 824                                  hop);
 825                         continue;
 826                 }
 827
 828                 spin_lock(&ring->lock);
 829                 __ring_interrupt(ring);
 830                 spin_unlock(&ring->lock);
 831         }
 832         spin_unlock_irq(&nhi->lock);
 833 }
 834
 835 static irqreturn_t nhi_msi(int irq, void *data)
 836 {
 837         struct tb_nhi *nhi = data;
 838         schedule_work(&nhi->interrupt_work);
 839         return IRQ_HANDLED;
 840 }
 841
 842 static int __nhi_suspend_noirq(struct device *dev, bool wakeup)
 843 {
 844         struct pci_dev *pdev = to_pci_dev(dev);
 845         struct tb *tb = pci_get_drvdata(pdev);
 846         struct tb_nhi *nhi = tb->nhi;
 847         int ret;
 848
 849         ret = tb_domain_suspend_noirq(tb);
 850         if (ret)
 851                 return ret;
 852
 853         if (nhi->ops && nhi->ops->suspend_noirq) {
 854                 ret = nhi->ops->suspend_noirq(tb->nhi, wakeup);
 855                 if (ret)
 856                         return ret;
 857         }
 858
 859         return 0;
 860 }
 861
 862 static int nhi_suspend_noirq(struct device *dev)
 863 {
 864         return __nhi_suspend_noirq(dev, device_may_wakeup(dev));
 865 }
 866
 867 static int nhi_freeze_noirq(struct device *dev)
 868 {
 869         struct pci_dev *pdev = to_pci_dev(dev);
 870         struct tb *tb = pci_get_drvdata(pdev);
 871
 872         return tb_domain_freeze_noirq(tb);
 873 }
 874
 875 static int nhi_thaw_noirq(struct device *dev)
 876 {
 877         struct pci_dev *pdev = to_pci_dev(dev);
 878         struct tb *tb = pci_get_drvdata(pdev);
 879
 880         return tb_domain_thaw_noirq(tb);
 881 }
 882
 883 static bool nhi_wake_supported(struct pci_dev *pdev)
 884 {
 885         u8 val;
 886
 887         /*
 888          * If power rails are sustainable for wakeup from S4 this
 889          * property is set by the BIOS.
 890          */
 891         if (device_property_read_u8(&pdev->dev, "WAKE_SUPPORTED", &val))
 892                 return !!val;
 893
 894         return true;
 895 }
 896
 897 static int nhi_poweroff_noirq(struct device *dev)
 898 {
 899         struct pci_dev *pdev = to_pci_dev(dev);
 900         bool wakeup;
 901
 902         wakeup = device_may_wakeup(dev) && nhi_wake_supported(pdev);
 903         return __nhi_suspend_noirq(dev, wakeup);
 904 }
 905
 906 static void nhi_enable_int_throttling(struct tb_nhi *nhi)
 907 {
 908         /* Throttling is specified in 256ns increments */
 909         u32 throttle = DIV_ROUND_UP(128 * NSEC_PER_USEC, 256);
 910         unsigned int i;
 911
 912         /*
 913          * Configure interrupt throttling for all vectors even if we
 914          * only use few.
 915          */
 916         for (i = 0; i < MSIX_MAX_VECS; i++) {
 917                 u32 reg = REG_INT_THROTTLING_RATE + i * 4;
 918                 iowrite32(throttle, nhi->iobase + reg);
 919         }
 920 }
 921
 922 static int nhi_resume_noirq(struct device *dev)
 923 {
 924         struct pci_dev *pdev = to_pci_dev(dev);
 925         struct tb *tb = pci_get_drvdata(pdev);
 926         struct tb_nhi *nhi = tb->nhi;
 927         int ret;
 928
 929         /*
 930          * Check that the device is still there. It may be that the user
 931          * unplugged last device which causes the host controller to go
 932          * away on PCs.
 933          */
 934         if (!pci_device_is_present(pdev)) {
 935                 nhi->going_away = true;
 936         } else {
 937                 if (nhi->ops && nhi->ops->resume_noirq) {
 938                         ret = nhi->ops->resume_noirq(nhi);
 939                         if (ret)
 940                                 return ret;
 941                 }
 942                 nhi_enable_int_throttling(tb->nhi);
 943         }
 944
 945         return tb_domain_resume_noirq(tb);
 946 }
 947
 948 static int nhi_suspend(struct device *dev)
 949 {
 950         struct pci_dev *pdev = to_pci_dev(dev);
 951         struct tb *tb = pci_get_drvdata(pdev);
 952
 953         return tb_domain_suspend(tb);
 954 }
 955
 956 static void nhi_complete(struct device *dev)
 957 {
 958         struct pci_dev *pdev = to_pci_dev(dev);
 959         struct tb *tb = pci_get_drvdata(pdev);
 960
 961         /*
 962          * If we were runtime suspended when system suspend started,
 963          * schedule runtime resume now. It should bring the domain back
 964          * to functional state.
 965          */
 966         if (pm_runtime_suspended(&pdev->dev))
 967                 pm_runtime_resume(&pdev->dev);
 968         else
 969                 tb_domain_complete(tb);
 970 }
 971
 972 static int nhi_runtime_suspend(struct device *dev)
 973 {
 974         struct pci_dev *pdev = to_pci_dev(dev);
 975         struct tb *tb = pci_get_drvdata(pdev);
 976         struct tb_nhi *nhi = tb->nhi;
 977         int ret;
 978
 979         ret = tb_domain_runtime_suspend(tb);
 980         if (ret)
 981                 return ret;
 982
 983         if (nhi->ops && nhi->ops->runtime_suspend) {
 984                 ret = nhi->ops->runtime_suspend(tb->nhi);
 985                 if (ret)
 986                         return ret;
 987         }
 988         return 0;
 989 }
 990
 991 static int nhi_runtime_resume(struct device *dev)
 992 {
 993         struct pci_dev *pdev = to_pci_dev(dev);
 994         struct tb *tb = pci_get_drvdata(pdev);
 995         struct tb_nhi *nhi = tb->nhi;
 996         int ret;
 997
 998         if (nhi->ops && nhi->ops->runtime_resume) {
 999                 ret = nhi->ops->runtime_resume(nhi);
1000                 if (ret)
1001                         return ret;
1002         }
1003
1004         nhi_enable_int_throttling(nhi);
1005         return tb_domain_runtime_resume(tb);
1006 }
1007
1008 static void nhi_shutdown(struct tb_nhi *nhi)
1009 {
1010         int i;
1011
1012         dev_dbg(&nhi->pdev->dev, "shutdown\n");
1013
1014         for (i = 0; i < nhi->hop_count; i++) {
1015                 if (nhi->tx_rings[i])
1016                         dev_WARN(&nhi->pdev->dev,
1017                                  "TX ring %d is still active\n", i);
1018                 if (nhi->rx_rings[i])
1019                         dev_WARN(&nhi->pdev->dev,
1020                                  "RX ring %d is still active\n", i);
1021         }
1022         nhi_disable_interrupts(nhi);
1023         /*
1024          * We have to release the irq before calling flush_work. Otherwise an
1025          * already executing IRQ handler could call schedule_work again.
1026          */
1027         if (!nhi->pdev->msix_enabled) {
1028                 devm_free_irq(&nhi->pdev->dev, nhi->pdev->irq, nhi);
1029                 flush_work(&nhi->interrupt_work);
1030         }
1031         ida_destroy(&nhi->msix_ida);
1032
1033         if (nhi->ops && nhi->ops->shutdown)
1034                 nhi->ops->shutdown(nhi);
1035 }
1036
1037 static int nhi_init_msi(struct tb_nhi *nhi)
1038 {
1039         struct pci_dev *pdev = nhi->pdev;
1040         int res, irq, nvec;
1041
1042         /* In case someone left them on. */
1043         nhi_disable_interrupts(nhi);
1044
1045         nhi_enable_int_throttling(nhi);
1046
1047         ida_init(&nhi->msix_ida);
1048
1049         /*
1050          * The NHI has 16 MSI-X vectors or a single MSI. We first try to
1051          * get all MSI-X vectors and if we succeed, each ring will have
1052          * one MSI-X. If for some reason that does not work out, we
1053          * fallback to a single MSI.
1054          */
1055         nvec = pci_alloc_irq_vectors(pdev, MSIX_MIN_VECS, MSIX_MAX_VECS,
1056                                      PCI_IRQ_MSIX);
1057         if (nvec < 0) {
1058                 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1059                 if (nvec < 0)
1060                         return nvec;
1061
1062                 INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work);
1063
1064                 irq = pci_irq_vector(nhi->pdev, 0);
1065                 if (irq < 0)
1066                         return irq;
1067
1068                 res = devm_request_irq(&pdev->dev, irq, nhi_msi,
1069                                        IRQF_NO_SUSPEND, "thunderbolt", nhi);
1070                 if (res) {
1071                         dev_err(&pdev->dev, "request_irq failed, aborting\n");
1072                         return res;
1073                 }
1074         }
1075
1076         return 0;
1077 }
1078
1079 static bool nhi_imr_valid(struct pci_dev *pdev)
1080 {
1081         u8 val;
1082
1083         if (!device_property_read_u8(&pdev->dev, "IMR_VALID", &val))
1084                 return !!val;
1085
1086         return true;
1087 }
1088
1089 /*
1090  * During suspend the Thunderbolt controller is reset and all PCIe
1091  * tunnels are lost. The NHI driver will try to reestablish all tunnels
1092  * during resume. This adds device links between the tunneled PCIe
1093  * downstream ports and the NHI so that the device core will make sure
1094  * NHI is resumed first before the rest.
1095  */
1096 static void tb_apple_add_links(struct tb_nhi *nhi)
1097 {
1098         struct pci_dev *upstream, *pdev;
1099
1100         if (!x86_apple_machine)
1101                 return;
1102
1103         switch (nhi->pdev->device) {
1104         case PCI_DEVICE_ID_INTEL_LIGHT_RIDGE:
1105         case PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C:
1106         case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI:
1107         case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI:
1108                 break;
1109         default:
1110                 return;
1111         }
1112
1113         upstream = pci_upstream_bridge(nhi->pdev);
1114         while (upstream) {
1115                 if (!pci_is_pcie(upstream))
1116                         return;
1117                 if (pci_pcie_type(upstream) == PCI_EXP_TYPE_UPSTREAM)
1118                         break;
1119                 upstream = pci_upstream_bridge(upstream);
1120         }
1121
1122         if (!upstream)
1123                 return;
1124
1125         /*
1126          * For each hotplug downstream port, create add device link
1127          * back to NHI so that PCIe tunnels can be re-established after
1128          * sleep.
1129          */
1130         for_each_pci_bridge(pdev, upstream->subordinate) {
1131                 const struct device_link *link;
1132
1133                 if (!pci_is_pcie(pdev))
1134                         continue;
1135                 if (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM ||
1136                     !pdev->is_hotplug_bridge)
1137                         continue;
1138
1139                 link = device_link_add(&pdev->dev, &nhi->pdev->dev,
1140                                        DL_FLAG_AUTOREMOVE_SUPPLIER |
1141                                        DL_FLAG_PM_RUNTIME);
1142                 if (link) {
1143                         dev_dbg(&nhi->pdev->dev, "created link from %s\n",
1144                                 dev_name(&pdev->dev));
1145                 } else {
1146                         dev_warn(&nhi->pdev->dev, "device link creation from %s failed\n",
1147                                  dev_name(&pdev->dev));
1148                 }
1149         }
1150 }
1151
1152 static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1153 {
1154         struct tb_nhi *nhi;
1155         struct tb *tb;
1156         int res;
1157
1158         if (!nhi_imr_valid(pdev)) {
1159                 dev_warn(&pdev->dev, "firmware image not valid, aborting\n");
1160                 return -ENODEV;
1161         }
1162
1163         res = pcim_enable_device(pdev);
1164         if (res) {
1165                 dev_err(&pdev->dev, "cannot enable PCI device, aborting\n");
1166                 return res;
1167         }
1168
1169         res = pcim_iomap_regions(pdev, 1 << 0, "thunderbolt");
1170         if (res) {
1171                 dev_err(&pdev->dev, "cannot obtain PCI resources, aborting\n");
1172                 return res;
1173         }
1174
1175         nhi = devm_kzalloc(&pdev->dev, sizeof(*nhi), GFP_KERNEL);
1176         if (!nhi)
1177                 return -ENOMEM;
1178
1179         nhi->pdev = pdev;
1180         nhi->ops = (const struct tb_nhi_ops *)id->driver_data;
1181         /* cannot fail - table is allocated bin pcim_iomap_regions */
1182         nhi->iobase = pcim_iomap_table(pdev)[0];
1183         nhi->hop_count = ioread32(nhi->iobase + REG_HOP_COUNT) & 0x3ff;
1184         dev_dbg(&pdev->dev, "total paths: %d\n", nhi->hop_count);
1185
1186         nhi->tx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
1187                                      sizeof(*nhi->tx_rings), GFP_KERNEL);
1188         nhi->rx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
1189                                      sizeof(*nhi->rx_rings), GFP_KERNEL);
1190         if (!nhi->tx_rings || !nhi->rx_rings)
1191                 return -ENOMEM;
1192
1193         res = nhi_init_msi(nhi);
1194         if (res) {
1195                 dev_err(&pdev->dev, "cannot enable MSI, aborting\n");
1196                 return res;
1197         }
1198
1199         spin_lock_init(&nhi->lock);
1200
1201         res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1202         if (res)
1203                 res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1204         if (res) {
1205                 dev_err(&pdev->dev, "failed to set DMA mask\n");
1206                 return res;
1207         }
1208
1209         pci_set_master(pdev);
1210
1211         if (nhi->ops && nhi->ops->init) {
1212                 res = nhi->ops->init(nhi);
1213                 if (res)
1214                         return res;
1215         }
1216
1217         tb_apple_add_links(nhi);
1218         tb_acpi_add_links(nhi);
1219
1220         tb = icm_probe(nhi);
1221         if (!tb)
1222                 tb = tb_probe(nhi);
1223         if (!tb) {
1224                 dev_err(&nhi->pdev->dev,
1225                         "failed to determine connection manager, aborting\n");
1226                 return -ENODEV;
1227         }
1228
1229         dev_dbg(&nhi->pdev->dev, "NHI initialized, starting thunderbolt\n");
1230
1231         res = tb_domain_add(tb);
1232         if (res) {
1233                 /*
1234                  * At this point the RX/TX rings might already have been
1235                  * activated. Do a proper shutdown.
1236                  */
1237                 tb_domain_put(tb);
1238                 nhi_shutdown(nhi);
1239                 return res;
1240         }
1241         pci_set_drvdata(pdev, tb);
1242
1243         device_wakeup_enable(&pdev->dev);
1244
1245         pm_runtime_allow(&pdev->dev);
1246         pm_runtime_set_autosuspend_delay(&pdev->dev, TB_AUTOSUSPEND_DELAY);
1247         pm_runtime_use_autosuspend(&pdev->dev);
1248         pm_runtime_put_autosuspend(&pdev->dev);
1249
1250         return 0;
1251 }
1252
1253 static void nhi_remove(struct pci_dev *pdev)
1254 {
1255         struct tb *tb = pci_get_drvdata(pdev);
1256         struct tb_nhi *nhi = tb->nhi;
1257
1258         pm_runtime_get_sync(&pdev->dev);
1259         pm_runtime_dont_use_autosuspend(&pdev->dev);
1260         pm_runtime_forbid(&pdev->dev);
1261
1262         tb_domain_remove(tb);
1263         nhi_shutdown(nhi);
1264 }
1265
1266 /*
1267  * The tunneled pci bridges are siblings of us. Use resume_noirq to reenable
1268  * the tunnels asap. A corresponding pci quirk blocks the downstream bridges
1269  * resume_noirq until we are done.
1270  */
1271 static const struct dev_pm_ops nhi_pm_ops = {
1272         .suspend_noirq = nhi_suspend_noirq,
1273         .resume_noirq = nhi_resume_noirq,
1274         .freeze_noirq = nhi_freeze_noirq,  /*
1275                                             * we just disable hotplug, the
1276                                             * pci-tunnels stay alive.
1277                                             */
1278         .thaw_noirq = nhi_thaw_noirq,
1279         .restore_noirq = nhi_resume_noirq,
1280         .suspend = nhi_suspend,
1281         .poweroff_noirq = nhi_poweroff_noirq,
1282         .poweroff = nhi_suspend,
1283         .complete = nhi_complete,
1284         .runtime_suspend = nhi_runtime_suspend,
1285         .runtime_resume = nhi_runtime_resume,
1286 };
1287
1288 static struct pci_device_id nhi_ids[] = {
1289         /*
1290          * We have to specify class, the TB bridges use the same device and
1291          * vendor (sub)id on gen 1 and gen 2 controllers.
1292          */
1293         {
1294                 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1295                 .vendor = PCI_VENDOR_ID_INTEL,
1296                 .device = PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
1297                 .subvendor = 0x2222, .subdevice = 0x1111,
1298         },
1299         {
1300                 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1301                 .vendor = PCI_VENDOR_ID_INTEL,
1302                 .device = PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
1303                 .subvendor = 0x2222, .subdevice = 0x1111,
1304         },
1305         {
1306                 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1307                 .vendor = PCI_VENDOR_ID_INTEL,
1308                 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI,
1309                 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
1310         },
1311         {
1312                 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1313                 .vendor = PCI_VENDOR_ID_INTEL,
1314                 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI,
1315                 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
1316         },
1317
1318         /* Thunderbolt 3 */
1319         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI) },
1320         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI) },
1321         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) },
1322         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) },
1323         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) },
1324         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) },
1325         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) },
1326         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) },
1327         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI) },
1328         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI) },
1329         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI0),
1330           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1331         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI1),
1332           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1333         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI0),
1334           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1335         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI1),
1336           .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1337
1338         /* Any USB4 compliant host */
1339         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_USB4, ~0) },
1340
1341         { 0,}
1342 };
1343
1344 MODULE_DEVICE_TABLE(pci, nhi_ids);
1345 MODULE_LICENSE("GPL");
1346
1347 static struct pci_driver nhi_driver = {
1348         .name = "thunderbolt",
1349         .id_table = nhi_ids,
1350         .probe = nhi_probe,
1351         .remove = nhi_remove,
1352         .shutdown = nhi_remove,
1353         .driver.pm = &nhi_pm_ops,
1354 };
1355
1356 static int __init nhi_init(void)
1357 {
1358         int ret;
1359
1360         ret = tb_domain_init();
1361         if (ret)
1362                 return ret;
1363         ret = pci_register_driver(&nhi_driver);
1364         if (ret)
1365                 tb_domain_exit();
1366         return ret;
1367 }
1368
1369 static void __exit nhi_unload(void)
1370 {
1371         pci_unregister_driver(&nhi_driver);
1372         tb_domain_exit();
1373 }
1374
1375 rootfs_initcall(nhi_init);
1376 module_exit(nhi_unload);