1 // SPDX-License-Identifier: GPL-2.0
3 * Thunderbolt link controller support
5 * Copyright (C) 2019, Intel Corporation
6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
12 * tb_lc_read_uuid() - Read switch UUID from link controller common register
13 * @sw: Switch whose UUID is read
14 * @uuid: UUID is placed here
16 int tb_lc_read_uuid(struct tb_switch *sw, u32 *uuid)
20 return tb_sw_read(sw, uuid, TB_CFG_SWITCH, sw->cap_lc + TB_LC_FUSE, 4);
23 static int read_lc_desc(struct tb_switch *sw, u32 *desc)
27 return tb_sw_read(sw, desc, TB_CFG_SWITCH, sw->cap_lc + TB_LC_DESC, 1);
30 static int find_port_lc_cap(struct tb_port *port)
32 struct tb_switch *sw = port->sw;
33 int start, phys, ret, size;
36 ret = read_lc_desc(sw, &desc);
40 /* Start of port LC registers */
41 start = (desc & TB_LC_DESC_SIZE_MASK) >> TB_LC_DESC_SIZE_SHIFT;
42 size = (desc & TB_LC_DESC_PORT_SIZE_MASK) >> TB_LC_DESC_PORT_SIZE_SHIFT;
43 phys = tb_phy_port_from_link(port->port);
45 return sw->cap_lc + start + phys * size;
48 static int tb_lc_configure_lane(struct tb_port *port, bool configure)
50 bool upstream = tb_is_upstream_port(port);
51 struct tb_switch *sw = port->sw;
55 if (sw->generation < 2)
58 cap = find_port_lc_cap(port);
62 ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
66 /* Resolve correct lane */
68 lane = TB_LC_SX_CTRL_L1C;
70 lane = TB_LC_SX_CTRL_L2C;
75 ctrl |= TB_LC_SX_CTRL_UPSTREAM;
79 ctrl &= ~TB_LC_SX_CTRL_UPSTREAM;
82 return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
86 * tb_lc_configure_link() - Let LC know about configured link
87 * @sw: Switch that is being added
89 * Informs LC of both parent switch and @sw that there is established
90 * link between the two.
92 int tb_lc_configure_link(struct tb_switch *sw)
94 struct tb_port *up, *down;
97 if (!sw->config.enabled || !tb_route(sw))
100 up = tb_upstream_port(sw);
101 down = tb_port_at(tb_route(sw), tb_to_switch(sw->dev.parent));
103 /* Configure parent link toward this switch */
104 ret = tb_lc_configure_lane(down, true);
108 /* Configure upstream link from this switch to the parent */
109 ret = tb_lc_configure_lane(up, true);
111 tb_lc_configure_lane(down, false);
117 * tb_lc_unconfigure_link() - Let LC know about unconfigured link
118 * @sw: Switch to unconfigure
120 * Informs LC of both parent switch and @sw that the link between the
121 * two does not exist anymore.
123 void tb_lc_unconfigure_link(struct tb_switch *sw)
125 struct tb_port *up, *down;
127 if (sw->is_unplugged || !sw->config.enabled || !tb_route(sw))
130 up = tb_upstream_port(sw);
131 down = tb_port_at(tb_route(sw), tb_to_switch(sw->dev.parent));
133 tb_lc_configure_lane(up, false);
134 tb_lc_configure_lane(down, false);
138 * tb_lc_set_sleep() - Inform LC that the switch is going to sleep
139 * @sw: Switch to set sleep
141 * Let the switch link controllers know that the switch is going to
144 int tb_lc_set_sleep(struct tb_switch *sw)
146 int start, size, nlc, ret, i;
149 if (sw->generation < 2)
152 ret = read_lc_desc(sw, &desc);
156 /* Figure out number of link controllers */
157 nlc = desc & TB_LC_DESC_NLC_MASK;
158 start = (desc & TB_LC_DESC_SIZE_MASK) >> TB_LC_DESC_SIZE_SHIFT;
159 size = (desc & TB_LC_DESC_PORT_SIZE_MASK) >> TB_LC_DESC_PORT_SIZE_SHIFT;
161 /* For each link controller set sleep bit */
162 for (i = 0; i < nlc; i++) {
163 unsigned int offset = sw->cap_lc + start + i * size;
166 ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH,
167 offset + TB_LC_SX_CTRL, 1);
171 ctrl |= TB_LC_SX_CTRL_SLP;
172 ret = tb_sw_write(sw, &ctrl, TB_CFG_SWITCH,
173 offset + TB_LC_SX_CTRL, 1);