1 // SPDX-License-Identifier: GPL-2.0
3 * Tegra30 SoC Thermal Sensor driver
5 * Based on downstream HWMON driver from NVIDIA.
6 * Copyright (C) 2011 NVIDIA Corporation
8 * Author: Dmitry Osipenko <digetx@gmail.com>
9 * Copyright (C) 2021 GRATE-DRIVER project
12 #include <linux/bitfield.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/errno.h>
16 #include <linux/interrupt.h>
18 #include <linux/iopoll.h>
19 #include <linux/math.h>
20 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/platform_device.h>
24 #include <linux/reset.h>
25 #include <linux/slab.h>
26 #include <linux/thermal.h>
27 #include <linux/types.h>
29 #include <soc/tegra/fuse.h>
31 #include "../thermal_hwmon.h"
33 #define TSENSOR_SENSOR0_CONFIG0 0x0
34 #define TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP BIT(0)
35 #define TSENSOR_SENSOR0_CONFIG0_HW_FREQ_DIV_EN BIT(1)
36 #define TSENSOR_SENSOR0_CONFIG0_THERMAL_RST_EN BIT(2)
37 #define TSENSOR_SENSOR0_CONFIG0_DVFS_EN BIT(3)
38 #define TSENSOR_SENSOR0_CONFIG0_INTR_OVERFLOW_EN BIT(4)
39 #define TSENSOR_SENSOR0_CONFIG0_INTR_HW_FREQ_DIV_EN BIT(5)
40 #define TSENSOR_SENSOR0_CONFIG0_INTR_THERMAL_RST_EN BIT(6)
41 #define TSENSOR_SENSOR0_CONFIG0_M GENMASK(23, 8)
42 #define TSENSOR_SENSOR0_CONFIG0_N GENMASK(31, 24)
44 #define TSENSOR_SENSOR0_CONFIG1 0x8
45 #define TSENSOR_SENSOR0_CONFIG1_TH1 GENMASK(15, 0)
46 #define TSENSOR_SENSOR0_CONFIG1_TH2 GENMASK(31, 16)
48 #define TSENSOR_SENSOR0_CONFIG2 0xc
49 #define TSENSOR_SENSOR0_CONFIG2_TH3 GENMASK(15, 0)
51 #define TSENSOR_SENSOR0_STATUS0 0x18
52 #define TSENSOR_SENSOR0_STATUS0_STATE GENMASK(2, 0)
53 #define TSENSOR_SENSOR0_STATUS0_INTR BIT(8)
54 #define TSENSOR_SENSOR0_STATUS0_CURRENT_VALID BIT(9)
56 #define TSENSOR_SENSOR0_TS_STATUS1 0x1c
57 #define TSENSOR_SENSOR0_TS_STATUS1_CURRENT_COUNT GENMASK(31, 16)
59 #define TEGRA30_FUSE_TEST_PROG_VER 0x28
61 #define TEGRA30_FUSE_TSENSOR_CALIB 0x98
62 #define TEGRA30_FUSE_TSENSOR_CALIB_LOW GENMASK(15, 0)
63 #define TEGRA30_FUSE_TSENSOR_CALIB_HIGH GENMASK(31, 16)
65 #define TEGRA30_FUSE_SPARE_BIT 0x144
69 struct tegra_tsensor_calibration_data {
73 struct tegra_tsensor_channel {
76 struct tegra_tsensor *ts;
77 struct thermal_zone_device *tzd;
80 struct tegra_tsensor {
85 struct reset_control *rst;
86 struct tegra_tsensor_channel ch[2];
87 struct tegra_tsensor_calibration_data calib;
90 static int tegra_tsensor_hw_enable(const struct tegra_tsensor *ts)
95 err = reset_control_assert(ts->rst);
97 dev_err(ts->dev, "failed to assert hardware reset: %d\n", err);
101 err = clk_prepare_enable(ts->clk);
103 dev_err(ts->dev, "failed to enable clock: %d\n", err);
109 err = reset_control_deassert(ts->rst);
111 dev_err(ts->dev, "failed to deassert hardware reset: %d\n", err);
116 * Sensors are enabled after reset by default, but not gauging
117 * until clock counter is programmed.
119 * M: number of reference clock pulses after which every
120 * temperature / voltage measurement is made
122 * N: number of reference clock counts for which the counter runs
124 val = FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_M, 12500);
125 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_N, 255);
127 /* apply the same configuration to both channels */
128 writel_relaxed(val, ts->regs + 0x40 + TSENSOR_SENSOR0_CONFIG0);
129 writel_relaxed(val, ts->regs + 0x80 + TSENSOR_SENSOR0_CONFIG0);
134 clk_disable_unprepare(ts->clk);
139 static int tegra_tsensor_hw_disable(const struct tegra_tsensor *ts)
143 err = reset_control_assert(ts->rst);
145 dev_err(ts->dev, "failed to assert hardware reset: %d\n", err);
149 clk_disable_unprepare(ts->clk);
154 static void devm_tegra_tsensor_hw_disable(void *data)
156 const struct tegra_tsensor *ts = data;
158 tegra_tsensor_hw_disable(ts);
161 static int tegra_tsensor_get_temp(struct thermal_zone_device *tz, int *temp)
163 const struct tegra_tsensor_channel *tsc = tz->devdata;
164 const struct tegra_tsensor *ts = tsc->ts;
165 int err, c1, c2, c3, c4, counter;
169 * Counter will be invalid if hardware is misprogrammed or not enough
170 * time passed since the time when sensor was enabled.
172 err = readl_relaxed_poll_timeout(tsc->regs + TSENSOR_SENSOR0_STATUS0, val,
173 val & TSENSOR_SENSOR0_STATUS0_CURRENT_VALID,
175 21 * USEC_PER_MSEC * 50);
177 dev_err_once(ts->dev, "ch%u: counter invalid\n", tsc->id);
181 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_TS_STATUS1);
182 counter = FIELD_GET(TSENSOR_SENSOR0_TS_STATUS1_CURRENT_COUNT, val);
185 * This shouldn't happen with a valid counter status, nevertheless
186 * lets verify the value since it's in a separate (from status)
189 if (counter == 0xffff) {
190 dev_err_once(ts->dev, "ch%u: counter overflow\n", tsc->id);
195 * temperature = a * counter + b
196 * temperature = m * (temperature ^ 2) + n * temperature + p
198 c1 = DIV_ROUND_CLOSEST(ts->calib.a * counter + ts->calib.b, 1000000);
200 c2 = DIV_ROUND_CLOSEST(ts->calib.p, c1);
201 c3 = c1 * ts->calib.m;
204 *temp = DIV_ROUND_CLOSEST(c1 * (c2 + c3 + c4), 1000);
209 static int tegra_tsensor_temp_to_counter(const struct tegra_tsensor *ts, int temp)
213 c1 = DIV_ROUND_CLOSEST(ts->calib.p - temp * 1000, ts->calib.m);
214 c2 = -ts->calib.r - int_sqrt(ts->calib.r * ts->calib.r - c1);
216 return DIV_ROUND_CLOSEST(c2 * 1000000 - ts->calib.b, ts->calib.a);
219 static int tegra_tsensor_set_trips(struct thermal_zone_device *tz, int low, int high)
221 const struct tegra_tsensor_channel *tsc = tz->devdata;
222 const struct tegra_tsensor *ts = tsc->ts;
226 * TSENSOR doesn't trigger interrupt on the "low" temperature breach,
227 * hence bail out if high temperature is unspecified.
232 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG1);
233 val &= ~TSENSOR_SENSOR0_CONFIG1_TH1;
235 high = tegra_tsensor_temp_to_counter(ts, high);
236 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG1_TH1, high);
237 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1);
242 static const struct thermal_zone_device_ops ops = {
243 .get_temp = tegra_tsensor_get_temp,
244 .set_trips = tegra_tsensor_set_trips,
248 tegra_tsensor_handle_channel_interrupt(const struct tegra_tsensor *ts,
251 const struct tegra_tsensor_channel *tsc = &ts->ch[id];
254 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_STATUS0);
255 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_STATUS0);
257 if (FIELD_GET(TSENSOR_SENSOR0_STATUS0_STATE, val) == 5)
258 dev_err_ratelimited(ts->dev, "ch%u: counter overflowed\n", id);
260 if (!FIELD_GET(TSENSOR_SENSOR0_STATUS0_INTR, val))
263 thermal_zone_device_update(tsc->tzd, THERMAL_EVENT_UNSPECIFIED);
268 static irqreturn_t tegra_tsensor_isr(int irq, void *data)
270 const struct tegra_tsensor *ts = data;
271 bool handled = false;
274 for (i = 0; i < ARRAY_SIZE(ts->ch); i++)
275 handled |= tegra_tsensor_handle_channel_interrupt(ts, i);
277 return handled ? IRQ_HANDLED : IRQ_NONE;
280 static int tegra_tsensor_disable_hw_channel(const struct tegra_tsensor *ts,
283 const struct tegra_tsensor_channel *tsc = &ts->ch[id];
284 struct thermal_zone_device *tzd = tsc->tzd;
291 err = thermal_zone_device_disable(tzd);
293 dev_err(ts->dev, "ch%u: failed to disable zone: %d\n", id, err);
298 /* stop channel gracefully */
299 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0);
300 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP, 1);
301 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0);
306 static void tegra_tsensor_get_hw_channel_trips(struct thermal_zone_device *tzd,
307 int *hot_trip, int *crit_trip)
312 * 90C is the maximal critical temperature of all Tegra30 SoC variants,
313 * use it for the default trip if unspecified in a device-tree.
318 for (i = 0; i < thermal_zone_get_num_trips(tzd); i++) {
320 struct thermal_trip trip;
322 thermal_zone_get_trip(tzd, i, &trip);
324 if (trip.type == THERMAL_TRIP_HOT)
325 *hot_trip = trip.temperature;
327 if (trip.type == THERMAL_TRIP_CRITICAL)
328 *crit_trip = trip.temperature;
331 /* clamp hardware trips to the calibration limits */
332 *hot_trip = clamp(*hot_trip, 25000, 90000);
335 * Kernel will perform a normal system shut down if it will
336 * see that critical temperature is breached, hence set the
337 * hardware limit by 5C higher in order to allow system to
338 * shut down gracefully before sending signal to the Power
339 * Management controller.
341 *crit_trip = clamp(*crit_trip + 5000, 25000, 90000);
344 static int tegra_tsensor_enable_hw_channel(const struct tegra_tsensor *ts,
347 const struct tegra_tsensor_channel *tsc = &ts->ch[id];
348 struct thermal_zone_device *tzd = tsc->tzd;
349 int err, hot_trip = 0, crit_trip = 0;
353 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0);
354 val &= ~TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP;
355 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0);
360 tegra_tsensor_get_hw_channel_trips(tzd, &hot_trip, &crit_trip);
362 /* prevent potential racing with tegra_tsensor_set_trips() */
363 mutex_lock(&tzd->lock);
365 dev_info_once(ts->dev, "ch%u: PMC emergency shutdown trip set to %dC\n",
366 id, DIV_ROUND_CLOSEST(crit_trip, 1000));
368 hot_trip = tegra_tsensor_temp_to_counter(ts, hot_trip);
369 crit_trip = tegra_tsensor_temp_to_counter(ts, crit_trip);
371 /* program LEVEL2 counter threshold */
372 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG1);
373 val &= ~TSENSOR_SENSOR0_CONFIG1_TH2;
374 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG1_TH2, hot_trip);
375 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1);
377 /* program LEVEL3 counter threshold */
378 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG2);
379 val &= ~TSENSOR_SENSOR0_CONFIG2_TH3;
380 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG2_TH3, crit_trip);
381 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG2);
384 * Enable sensor, emergency shutdown, interrupts for level 1/2/3
385 * breaches and counter overflow condition.
387 * Disable DIV2 throttle for now since we need to figure out how
388 * to integrate it properly with the thermal framework.
390 * Thermal levels supported by hardware:
393 * Level 1 = passive cooling (cpufreq DVFS)
394 * Level 2 = passive cooling assisted by hardware (DIV2)
395 * Level 3 = emergency shutdown assisted by hardware (PMC)
397 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0);
398 val &= ~TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP;
399 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_DVFS_EN, 1);
400 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_HW_FREQ_DIV_EN, 0);
401 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_THERMAL_RST_EN, 1);
402 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_OVERFLOW_EN, 1);
403 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_HW_FREQ_DIV_EN, 1);
404 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_THERMAL_RST_EN, 1);
405 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0);
407 mutex_unlock(&tzd->lock);
409 err = thermal_zone_device_enable(tzd);
411 dev_err(ts->dev, "ch%u: failed to enable zone: %d\n", id, err);
418 static bool tegra_tsensor_fuse_read_spare(unsigned int spare)
422 tegra_fuse_readl(TEGRA30_FUSE_SPARE_BIT + spare * 4, &val);
427 static int tegra_tsensor_nvmem_setup(struct tegra_tsensor *ts)
429 u32 i, ate_ver = 0, cal = 0, t1_25C = 0, t2_90C = 0;
430 int err, c1_25C, c2_90C;
432 err = tegra_fuse_readl(TEGRA30_FUSE_TEST_PROG_VER, &ate_ver);
434 dev_err_probe(ts->dev, err, "failed to get ATE version\n");
439 dev_info(ts->dev, "unsupported ATE version: %u\n", ate_ver);
444 * We have two TSENSOR channels in a two different spots on SoC.
445 * Second channel provides more accurate data on older SoC versions,
446 * use it as a primary channel.
449 dev_info_once(ts->dev,
450 "older ATE version detected, channels remapped\n");
451 ts->swap_channels = true;
454 err = tegra_fuse_readl(TEGRA30_FUSE_TSENSOR_CALIB, &cal);
456 dev_err(ts->dev, "failed to get calibration data: %d\n", err);
460 /* get calibrated counter values for 25C/90C thresholds */
461 c1_25C = FIELD_GET(TEGRA30_FUSE_TSENSOR_CALIB_LOW, cal);
462 c2_90C = FIELD_GET(TEGRA30_FUSE_TSENSOR_CALIB_HIGH, cal);
464 /* and calibrated temperatures corresponding to the counter values */
465 for (i = 0; i < 7; i++) {
466 t1_25C |= tegra_tsensor_fuse_read_spare(14 + i) << i;
467 t1_25C |= tegra_tsensor_fuse_read_spare(21 + i) << i;
469 t2_90C |= tegra_tsensor_fuse_read_spare(0 + i) << i;
470 t2_90C |= tegra_tsensor_fuse_read_spare(7 + i) << i;
473 if (c2_90C - c1_25C <= t2_90C - t1_25C) {
474 dev_err(ts->dev, "invalid calibration data: %d %d %u %u\n",
475 c2_90C, c1_25C, t2_90C, t1_25C);
479 /* all calibration coefficients are premultiplied by 1000000 */
481 ts->calib.a = DIV_ROUND_CLOSEST((t2_90C - t1_25C) * 1000000,
484 ts->calib.b = t1_25C * 1000000 - ts->calib.a * c1_25C;
486 if (tegra_sku_info.revision == TEGRA_REVISION_A01) {
488 ts->calib.n = 1338811;
489 ts->calib.p = -7300000;
492 ts->calib.n = 1528943;
493 ts->calib.p = -11100000;
496 /* except the coefficient of a reduced quadratic equation */
497 ts->calib.r = DIV_ROUND_CLOSEST(ts->calib.n, ts->calib.m * 2);
499 dev_info_once(ts->dev,
500 "calibration: %d %d %u %u ATE ver: %u SoC rev: %u\n",
501 c2_90C, c1_25C, t2_90C, t1_25C, ate_ver,
502 tegra_sku_info.revision);
507 static int tegra_tsensor_register_channel(struct tegra_tsensor *ts,
510 struct tegra_tsensor_channel *tsc = &ts->ch[id];
511 unsigned int hw_id = ts->swap_channels ? !id : id;
515 tsc->regs = ts->regs + 0x40 * (hw_id + 1);
517 tsc->tzd = devm_thermal_of_zone_register(ts->dev, id, tsc, &ops);
518 if (IS_ERR(tsc->tzd)) {
519 if (PTR_ERR(tsc->tzd) != -ENODEV)
520 return dev_err_probe(ts->dev, PTR_ERR(tsc->tzd),
521 "failed to register thermal zone\n");
524 * It's okay if sensor isn't assigned to any thermal zone
531 if (devm_thermal_add_hwmon_sysfs(tsc->tzd))
532 dev_warn(ts->dev, "failed to add hwmon sysfs attributes\n");
537 static int tegra_tsensor_probe(struct platform_device *pdev)
539 struct tegra_tsensor *ts;
543 ts = devm_kzalloc(&pdev->dev, sizeof(*ts), GFP_KERNEL);
547 irq = platform_get_irq(pdev, 0);
551 ts->dev = &pdev->dev;
552 platform_set_drvdata(pdev, ts);
554 ts->regs = devm_platform_ioremap_resource(pdev, 0);
555 if (IS_ERR(ts->regs))
556 return PTR_ERR(ts->regs);
558 ts->clk = devm_clk_get(&pdev->dev, NULL);
560 return dev_err_probe(&pdev->dev, PTR_ERR(ts->clk),
561 "failed to get clock\n");
563 ts->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
565 return dev_err_probe(&pdev->dev, PTR_ERR(ts->rst),
566 "failed to get reset control\n");
568 err = tegra_tsensor_nvmem_setup(ts);
572 err = tegra_tsensor_hw_enable(ts);
576 err = devm_add_action_or_reset(&pdev->dev,
577 devm_tegra_tsensor_hw_disable,
582 for (i = 0; i < ARRAY_SIZE(ts->ch); i++) {
583 err = tegra_tsensor_register_channel(ts, i);
588 err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
589 tegra_tsensor_isr, IRQF_ONESHOT,
590 "tegra_tsensor", ts);
592 return dev_err_probe(&pdev->dev, err,
593 "failed to request interrupt\n");
595 for (i = 0; i < ARRAY_SIZE(ts->ch); i++) {
596 err = tegra_tsensor_enable_hw_channel(ts, i);
604 static int __maybe_unused tegra_tsensor_suspend(struct device *dev)
606 struct tegra_tsensor *ts = dev_get_drvdata(dev);
610 for (i = 0; i < ARRAY_SIZE(ts->ch); i++) {
611 err = tegra_tsensor_disable_hw_channel(ts, i);
616 err = tegra_tsensor_hw_disable(ts);
624 tegra_tsensor_enable_hw_channel(ts, i);
629 static int __maybe_unused tegra_tsensor_resume(struct device *dev)
631 struct tegra_tsensor *ts = dev_get_drvdata(dev);
635 err = tegra_tsensor_hw_enable(ts);
639 for (i = 0; i < ARRAY_SIZE(ts->ch); i++) {
640 err = tegra_tsensor_enable_hw_channel(ts, i);
648 static const struct dev_pm_ops tegra_tsensor_pm_ops = {
649 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_tsensor_suspend,
650 tegra_tsensor_resume)
653 static const struct of_device_id tegra_tsensor_of_match[] = {
654 { .compatible = "nvidia,tegra30-tsensor", },
657 MODULE_DEVICE_TABLE(of, tegra_tsensor_of_match);
659 static struct platform_driver tegra_tsensor_driver = {
660 .probe = tegra_tsensor_probe,
662 .name = "tegra30-tsensor",
663 .of_match_table = tegra_tsensor_of_match,
664 .pm = &tegra_tsensor_pm_ops,
667 module_platform_driver(tegra_tsensor_driver);
669 MODULE_DESCRIPTION("NVIDIA Tegra30 Thermal Sensor driver");
670 MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>");
671 MODULE_LICENSE("GPL");