drivers/thermal/samsung/exynos_tmu.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * exynos_tmu.c - Samsung Exynos TMU (Thermal Management Unit)
   4  *
   5  *  Copyright (C) 2014 Samsung Electronics
   6  *  Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
   7  *  Lukasz Majewski <l.majewski@samsung.com>
   8  *
   9  *  Copyright (C) 2011 Samsung Electronics
  10  *  Donggeun Kim <dg77.kim@samsung.com>
  11  *  Amit Daniel Kachhap <amit.kachhap@linaro.org>
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/io.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/thermal.h>
  24
  25 #include <dt-bindings/thermal/thermal_exynos.h>
  26
  27 /* Exynos generic registers */
  28 #define EXYNOS_TMU_REG_TRIMINFO         0x0
  29 #define EXYNOS_TMU_REG_CONTROL          0x20
  30 #define EXYNOS_TMU_REG_STATUS           0x28
  31 #define EXYNOS_TMU_REG_CURRENT_TEMP     0x40
  32 #define EXYNOS_TMU_REG_INTEN            0x70
  33 #define EXYNOS_TMU_REG_INTSTAT          0x74
  34 #define EXYNOS_TMU_REG_INTCLEAR         0x78
  35
  36 #define EXYNOS_TMU_TEMP_MASK            0xff
  37 #define EXYNOS_TMU_REF_VOLTAGE_SHIFT    24
  38 #define EXYNOS_TMU_REF_VOLTAGE_MASK     0x1f
  39 #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK   0xf
  40 #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT  8
  41 #define EXYNOS_TMU_CORE_EN_SHIFT        0
  42
  43 /* Exynos3250 specific registers */
  44 #define EXYNOS_TMU_TRIMINFO_CON1        0x10
  45
  46 /* Exynos4210 specific registers */
  47 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP       0x44
  48 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0  0x50
  49
  50 /* Exynos5250, Exynos4412, Exynos3250 specific registers */
  51 #define EXYNOS_TMU_TRIMINFO_CON2        0x14
  52 #define EXYNOS_THD_TEMP_RISE            0x50
  53 #define EXYNOS_THD_TEMP_FALL            0x54
  54 #define EXYNOS_EMUL_CON         0x80
  55
  56 #define EXYNOS_TRIMINFO_RELOAD_ENABLE   1
  57 #define EXYNOS_TRIMINFO_25_SHIFT        0
  58 #define EXYNOS_TRIMINFO_85_SHIFT        8
  59 #define EXYNOS_TMU_TRIP_MODE_SHIFT      13
  60 #define EXYNOS_TMU_TRIP_MODE_MASK       0x7
  61 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT  12
  62
  63 #define EXYNOS_TMU_INTEN_RISE0_SHIFT    0
  64 #define EXYNOS_TMU_INTEN_FALL0_SHIFT    16
  65
  66 #define EXYNOS_EMUL_TIME        0x57F0
  67 #define EXYNOS_EMUL_TIME_MASK   0xffff
  68 #define EXYNOS_EMUL_TIME_SHIFT  16
  69 #define EXYNOS_EMUL_DATA_SHIFT  8
  70 #define EXYNOS_EMUL_DATA_MASK   0xFF
  71 #define EXYNOS_EMUL_ENABLE      0x1
  72
  73 /* Exynos5260 specific */
  74 #define EXYNOS5260_TMU_REG_INTEN                0xC0
  75 #define EXYNOS5260_TMU_REG_INTSTAT              0xC4
  76 #define EXYNOS5260_TMU_REG_INTCLEAR             0xC8
  77 #define EXYNOS5260_EMUL_CON                     0x100
  78
  79 /* Exynos4412 specific */
  80 #define EXYNOS4412_MUX_ADDR_VALUE          6
  81 #define EXYNOS4412_MUX_ADDR_SHIFT          20
  82
  83 /* Exynos5433 specific registers */
  84 #define EXYNOS5433_THD_TEMP_RISE3_0             0x050
  85 #define EXYNOS5433_THD_TEMP_RISE7_4             0x054
  86 #define EXYNOS5433_THD_TEMP_FALL3_0             0x060
  87 #define EXYNOS5433_THD_TEMP_FALL7_4             0x064
  88 #define EXYNOS5433_TMU_REG_INTEN                0x0c0
  89 #define EXYNOS5433_TMU_REG_INTPEND              0x0c8
  90 #define EXYNOS5433_TMU_EMUL_CON                 0x110
  91 #define EXYNOS5433_TMU_PD_DET_EN                0x130
  92
  93 #define EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT     16
  94 #define EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT     23
  95 #define EXYNOS5433_TRIMINFO_SENSOR_ID_MASK      \
  96                         (0xf << EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT)
  97 #define EXYNOS5433_TRIMINFO_CALIB_SEL_MASK      BIT(23)
  98
  99 #define EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING  0
 100 #define EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING  1
 101
 102 #define EXYNOS5433_PD_DET_EN                    1
 103
 104 #define EXYNOS5433_G3D_BASE                     0x10070000
 105
 106 /* Exynos7 specific registers */
 107 #define EXYNOS7_THD_TEMP_RISE7_6                0x50
 108 #define EXYNOS7_THD_TEMP_FALL7_6                0x60
 109 #define EXYNOS7_TMU_REG_INTEN                   0x110
 110 #define EXYNOS7_TMU_REG_INTPEND                 0x118
 111 #define EXYNOS7_TMU_REG_EMUL_CON                0x160
 112
 113 #define EXYNOS7_TMU_TEMP_MASK                   0x1ff
 114 #define EXYNOS7_PD_DET_EN_SHIFT                 23
 115 #define EXYNOS7_TMU_INTEN_RISE0_SHIFT           0
 116 #define EXYNOS7_EMUL_DATA_SHIFT                 7
 117 #define EXYNOS7_EMUL_DATA_MASK                  0x1ff
 118
 119 #define EXYNOS_FIRST_POINT_TRIM                 25
 120 #define EXYNOS_SECOND_POINT_TRIM                85
 121
 122 #define EXYNOS_NOISE_CANCEL_MODE                4
 123
 124 #define MCELSIUS        1000
 125
 126 enum soc_type {
 127         SOC_ARCH_EXYNOS3250 = 1,
 128         SOC_ARCH_EXYNOS4210,
 129         SOC_ARCH_EXYNOS4412,
 130         SOC_ARCH_EXYNOS5250,
 131         SOC_ARCH_EXYNOS5260,
 132         SOC_ARCH_EXYNOS5420,
 133         SOC_ARCH_EXYNOS5420_TRIMINFO,
 134         SOC_ARCH_EXYNOS5433,
 135         SOC_ARCH_EXYNOS7,
 136 };
 137
 138 /**
 139  * struct exynos_tmu_data : A structure to hold the private data of the TMU
 140  *                          driver
 141  * @id: identifier of the one instance of the TMU controller.
 142  * @base: base address of the single instance of the TMU controller.
 143  * @base_second: base address of the common registers of the TMU controller.
 144  * @irq: irq number of the TMU controller.
 145  * @soc: id of the SOC type.
 146  * @irq_work: pointer to the irq work structure.
 147  * @lock: lock to implement synchronization.
 148  * @clk: pointer to the clock structure.
 149  * @clk_sec: pointer to the clock structure for accessing the base_second.
 150  * @sclk: pointer to the clock structure for accessing the tmu special clk.
 151  * @cal_type: calibration type for temperature
 152  * @efuse_value: SoC defined fuse value
 153  * @min_efuse_value: minimum valid trimming data
 154  * @max_efuse_value: maximum valid trimming data
 155  * @temp_error1: fused value of the first point trim.
 156  * @temp_error2: fused value of the second point trim.
 157  * @gain: gain of amplifier in the positive-TC generator block
 158  *      0 < gain <= 15
 159  * @reference_voltage: reference voltage of amplifier
 160  *      in the positive-TC generator block
 161  *      0 < reference_voltage <= 31
 162  * @regulator: pointer to the TMU regulator structure.
 163  * @tzd: pointer to thermal_zone_device structure
 164  * @ntrip: number of supported trip points.
 165  * @enabled: current status of TMU device
 166  * @tmu_set_trip_temp: SoC specific method to set trip (rising threshold)
 167  * @tmu_set_trip_hyst: SoC specific to set hysteresis (falling threshold)
 168  * @tmu_initialize: SoC specific TMU initialization method
 169  * @tmu_control: SoC specific TMU control method
 170  * @tmu_read: SoC specific TMU temperature read method
 171  * @tmu_set_emulation: SoC specific TMU emulation setting method
 172  * @tmu_clear_irqs: SoC specific TMU interrupts clearing method
 173  */
 174 struct exynos_tmu_data {
 175         int id;
 176         void __iomem *base;
 177         void __iomem *base_second;
 178         int irq;
 179         enum soc_type soc;
 180         struct work_struct irq_work;
 181         struct mutex lock;
 182         struct clk *clk, *clk_sec, *sclk;
 183         u32 cal_type;
 184         u32 efuse_value;
 185         u32 min_efuse_value;
 186         u32 max_efuse_value;
 187         u16 temp_error1, temp_error2;
 188         u8 gain;
 189         u8 reference_voltage;
 190         struct regulator *regulator;
 191         struct thermal_zone_device *tzd;
 192         unsigned int ntrip;
 193         bool enabled;
 194
 195         void (*tmu_set_trip_temp)(struct exynos_tmu_data *data, int trip,
 196                                  u8 temp);
 197         void (*tmu_set_trip_hyst)(struct exynos_tmu_data *data, int trip,
 198                                  u8 temp, u8 hyst);
 199         void (*tmu_initialize)(struct platform_device *pdev);
 200         void (*tmu_control)(struct platform_device *pdev, bool on);
 201         int (*tmu_read)(struct exynos_tmu_data *data);
 202         void (*tmu_set_emulation)(struct exynos_tmu_data *data, int temp);
 203         void (*tmu_clear_irqs)(struct exynos_tmu_data *data);
 204 };
 205
 206 /*
 207  * TMU treats temperature as a mapped temperature code.
 208  * The temperature is converted differently depending on the calibration type.
 209  */
 210 static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
 211 {
 212         if (data->cal_type == TYPE_ONE_POINT_TRIMMING)
 213                 return temp + data->temp_error1 - EXYNOS_FIRST_POINT_TRIM;
 214
 215         return (temp - EXYNOS_FIRST_POINT_TRIM) *
 216                 (data->temp_error2 - data->temp_error1) /
 217                 (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) +
 218                 data->temp_error1;
 219 }
 220
 221 /*
 222  * Calculate a temperature value from a temperature code.
 223  * The unit of the temperature is degree Celsius.
 224  */
 225 static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code)
 226 {
 227         if (data->cal_type == TYPE_ONE_POINT_TRIMMING)
 228                 return temp_code - data->temp_error1 + EXYNOS_FIRST_POINT_TRIM;
 229
 230         return (temp_code - data->temp_error1) *
 231                 (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) /
 232                 (data->temp_error2 - data->temp_error1) +
 233                 EXYNOS_FIRST_POINT_TRIM;
 234 }
 235
 236 static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info)
 237 {
 238         u16 tmu_temp_mask =
 239                 (data->soc == SOC_ARCH_EXYNOS7) ? EXYNOS7_TMU_TEMP_MASK
 240                                                 : EXYNOS_TMU_TEMP_MASK;
 241
 242         data->temp_error1 = trim_info & tmu_temp_mask;
 243         data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &
 244                                 EXYNOS_TMU_TEMP_MASK);
 245
 246         if (!data->temp_error1 ||
 247             (data->min_efuse_value > data->temp_error1) ||
 248             (data->temp_error1 > data->max_efuse_value))
 249                 data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK;
 250
 251         if (!data->temp_error2)
 252                 data->temp_error2 =
 253                         (data->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &
 254                         EXYNOS_TMU_TEMP_MASK;
 255 }
 256
 257 static int exynos_tmu_initialize(struct platform_device *pdev)
 258 {
 259         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
 260         struct thermal_zone_device *tzd = data->tzd;
 261         int num_trips = thermal_zone_get_num_trips(tzd);
 262         unsigned int status;
 263         int ret = 0, temp;
 264
 265         ret = thermal_zone_get_crit_temp(tzd, &temp);
 266         if (ret && data->soc != SOC_ARCH_EXYNOS5433) { /* FIXME */
 267                 dev_err(&pdev->dev,
 268                         "No CRITICAL trip point defined in device tree!\n");
 269                 goto out;
 270         }
 271
 272         if (num_trips > data->ntrip) {
 273                 dev_info(&pdev->dev,
 274                          "More trip points than supported by this TMU.\n");
 275                 dev_info(&pdev->dev,
 276                          "%d trip points should be configured in polling mode.\n",
 277                          num_trips - data->ntrip);
 278         }
 279
 280         mutex_lock(&data->lock);
 281         clk_enable(data->clk);
 282         if (!IS_ERR(data->clk_sec))
 283                 clk_enable(data->clk_sec);
 284
 285         status = readb(data->base + EXYNOS_TMU_REG_STATUS);
 286         if (!status) {
 287                 ret = -EBUSY;
 288         } else {
 289                 int i, ntrips =
 290                         min_t(int, num_trips, data->ntrip);
 291
 292                 data->tmu_initialize(pdev);
 293
 294                 /* Write temperature code for rising and falling threshold */
 295                 for (i = 0; i < ntrips; i++) {
 296
 297                         struct thermal_trip trip;
 298
 299                         ret = thermal_zone_get_trip(tzd, i, &trip);
 300                         if (ret)
 301                                 goto err;
 302
 303                         data->tmu_set_trip_temp(data, i, trip.temperature / MCELSIUS);
 304                         data->tmu_set_trip_hyst(data, i, trip.temperature / MCELSIUS,
 305                                                 trip.hysteresis / MCELSIUS);
 306                 }
 307
 308                 data->tmu_clear_irqs(data);
 309         }
 310 err:
 311         clk_disable(data->clk);
 312         mutex_unlock(&data->lock);
 313         if (!IS_ERR(data->clk_sec))
 314                 clk_disable(data->clk_sec);
 315 out:
 316         return ret;
 317 }
 318
 319 static u32 get_con_reg(struct exynos_tmu_data *data, u32 con)
 320 {
 321         if (data->soc == SOC_ARCH_EXYNOS4412 ||
 322             data->soc == SOC_ARCH_EXYNOS3250)
 323                 con |= (EXYNOS4412_MUX_ADDR_VALUE << EXYNOS4412_MUX_ADDR_SHIFT);
 324
 325         con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT);
 326         con |= data->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT;
 327
 328         con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
 329         con |= (data->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
 330
 331         con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << EXYNOS_TMU_TRIP_MODE_SHIFT);
 332         con |= (EXYNOS_NOISE_CANCEL_MODE << EXYNOS_TMU_TRIP_MODE_SHIFT);
 333
 334         return con;
 335 }
 336
 337 static void exynos_tmu_control(struct platform_device *pdev, bool on)
 338 {
 339         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
 340
 341         mutex_lock(&data->lock);
 342         clk_enable(data->clk);
 343         data->tmu_control(pdev, on);
 344         data->enabled = on;
 345         clk_disable(data->clk);
 346         mutex_unlock(&data->lock);
 347 }
 348
 349 static void exynos4210_tmu_set_trip_temp(struct exynos_tmu_data *data,
 350                                          int trip_id, u8 temp)
 351 {
 352         struct thermal_trip trip;
 353         u8 ref, th_code;
 354
 355         if (thermal_zone_get_trip(data->tzd, 0, &trip))
 356                 return;
 357
 358         ref = trip.temperature / MCELSIUS;
 359
 360         if (trip_id == 0) {
 361                 th_code = temp_to_code(data, ref);
 362                 writeb(th_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
 363         }
 364
 365         temp -= ref;
 366         writeb(temp, data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0 + trip_id * 4);
 367 }
 368
 369 /* failing thresholds are not supported on Exynos4210 */
 370 static void exynos4210_tmu_set_trip_hyst(struct exynos_tmu_data *data,
 371                                          int trip, u8 temp, u8 hyst)
 372 {
 373 }
 374
 375 static void exynos4210_tmu_initialize(struct platform_device *pdev)
 376 {
 377         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
 378
 379         sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO));
 380 }
 381
 382 static void exynos4412_tmu_set_trip_temp(struct exynos_tmu_data *data,
 383                                          int trip, u8 temp)
 384 {
 385         u32 th, con;
 386
 387         th = readl(data->base + EXYNOS_THD_TEMP_RISE);
 388         th &= ~(0xff << 8 * trip);
 389         th |= temp_to_code(data, temp) << 8 * trip;
 390         writel(th, data->base + EXYNOS_THD_TEMP_RISE);
 391
 392         if (trip == 3) {
 393                 con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
 394                 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
 395                 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
 396         }
 397 }
 398
 399 static void exynos4412_tmu_set_trip_hyst(struct exynos_tmu_data *data,
 400                                          int trip, u8 temp, u8 hyst)
 401 {
 402         u32 th;
 403
 404         th = readl(data->base + EXYNOS_THD_TEMP_FALL);
 405         th &= ~(0xff << 8 * trip);
 406         if (hyst)
 407                 th |= temp_to_code(data, temp - hyst) << 8 * trip;
 408         writel(th, data->base + EXYNOS_THD_TEMP_FALL);
 409 }
 410
 411 static void exynos4412_tmu_initialize(struct platform_device *pdev)
 412 {
 413         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
 414         unsigned int trim_info, ctrl;
 415
 416         if (data->soc == SOC_ARCH_EXYNOS3250 ||
 417             data->soc == SOC_ARCH_EXYNOS4412 ||
 418             data->soc == SOC_ARCH_EXYNOS5250) {
 419                 if (data->soc == SOC_ARCH_EXYNOS3250) {
 420                         ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1);
 421                         ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
 422                         writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1);
 423                 }
 424                 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2);
 425                 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
 426                 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2);
 427         }
 428
 429         /* On exynos5420 the triminfo register is in the shared space */
 430         if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
 431                 trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO);
 432         else
 433                 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
 434
 435         sanitize_temp_error(data, trim_info);
 436 }
 437
 438 static void exynos5433_tmu_set_trip_temp(struct exynos_tmu_data *data,
 439                                          int trip, u8 temp)
 440 {
 441         unsigned int reg_off, j;
 442         u32 th;
 443
 444         if (trip > 3) {
 445                 reg_off = EXYNOS5433_THD_TEMP_RISE7_4;
 446                 j = trip - 4;
 447         } else {
 448                 reg_off = EXYNOS5433_THD_TEMP_RISE3_0;
 449                 j = trip;
 450         }
 451
 452         th = readl(data->base + reg_off);
 453         th &= ~(0xff << j * 8);
 454         th |= (temp_to_code(data, temp) << j * 8);
 455         writel(th, data->base + reg_off);
 456 }
 457
 458 static void exynos5433_tmu_set_trip_hyst(struct exynos_tmu_data *data,
 459                                          int trip, u8 temp, u8 hyst)
 460 {
 461         unsigned int reg_off, j;
 462         u32 th;
 463
 464         if (trip > 3) {
 465                 reg_off = EXYNOS5433_THD_TEMP_FALL7_4;
 466                 j = trip - 4;
 467         } else {
 468                 reg_off = EXYNOS5433_THD_TEMP_FALL3_0;
 469                 j = trip;
 470         }
 471
 472         th = readl(data->base + reg_off);
 473         th &= ~(0xff << j * 8);
 474         th |= (temp_to_code(data, temp - hyst) << j * 8);
 475         writel(th, data->base + reg_off);
 476 }
 477
 478 static void exynos5433_tmu_initialize(struct platform_device *pdev)
 479 {
 480         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
 481         unsigned int trim_info;
 482         int sensor_id, cal_type;
 483
 484         trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
 485         sanitize_temp_error(data, trim_info);
 486
 487         /* Read the temperature sensor id */
 488         sensor_id = (trim_info & EXYNOS5433_TRIMINFO_SENSOR_ID_MASK)
 489                                 >> EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT;
 490         dev_info(&pdev->dev, "Temperature sensor ID: 0x%x\n", sensor_id);
 491
 492         /* Read the calibration mode */
 493         writel(trim_info, data->base + EXYNOS_TMU_REG_TRIMINFO);
 494         cal_type = (trim_info & EXYNOS5433_TRIMINFO_CALIB_SEL_MASK)
 495                                 >> EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT;
 496
 497         switch (cal_type) {
 498         case EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING:
 499                 data->cal_type = TYPE_TWO_POINT_TRIMMING;
 500                 break;
 501         case EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING:
 502         default:
 503                 data->cal_type = TYPE_ONE_POINT_TRIMMING;
 504                 break;
 505         }
 506
 507         dev_info(&pdev->dev, "Calibration type is %d-point calibration\n",
 508                         cal_type ?  2 : 1);
 509 }
 510
 511 static void exynos7_tmu_set_trip_temp(struct exynos_tmu_data *data,
 512                                       int trip, u8 temp)
 513 {
 514         unsigned int reg_off, bit_off;
 515         u32 th;
 516
 517         reg_off = ((7 - trip) / 2) * 4;
 518         bit_off = ((8 - trip) % 2);
 519
 520         th = readl(data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off);
 521         th &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off));
 522         th |= temp_to_code(data, temp) << (16 * bit_off);
 523         writel(th, data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off);
 524 }
 525
 526 static void exynos7_tmu_set_trip_hyst(struct exynos_tmu_data *data,
 527                                       int trip, u8 temp, u8 hyst)
 528 {
 529         unsigned int reg_off, bit_off;
 530         u32 th;
 531
 532         reg_off = ((7 - trip) / 2) * 4;
 533         bit_off = ((8 - trip) % 2);
 534
 535         th = readl(data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off);
 536         th &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off));
 537         th |= temp_to_code(data, temp - hyst) << (16 * bit_off);
 538         writel(th, data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off);
 539 }
 540
 541 static void exynos7_tmu_initialize(struct platform_device *pdev)
 542 {
 543         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
 544         unsigned int trim_info;
 545
 546         trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
 547         sanitize_temp_error(data, trim_info);
 548 }
 549
 550 static void exynos4210_tmu_control(struct platform_device *pdev, bool on)
 551 {
 552         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
 553         struct thermal_zone_device *tz = data->tzd;
 554         struct thermal_trip trip;
 555         unsigned int con, interrupt_en = 0, i;
 556
 557         con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
 558
 559         if (on) {
 560                 for (i = 0; i < data->ntrip; i++) {
 561                         if (thermal_zone_get_trip(tz, i, &trip))
 562                                 continue;
 563
 564                         interrupt_en |=
 565                                 (1 << (EXYNOS_TMU_INTEN_RISE0_SHIFT + i * 4));
 566                 }
 567
 568                 if (data->soc != SOC_ARCH_EXYNOS4210)
 569                         interrupt_en |=
 570                                 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
 571
 572                 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
 573         } else {
 574                 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
 575         }
 576
 577         writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
 578         writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
 579 }
 580
 581 static void exynos5433_tmu_control(struct platform_device *pdev, bool on)
 582 {
 583         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
 584         struct thermal_zone_device *tz = data->tzd;
 585         struct thermal_trip trip;
 586         unsigned int con, interrupt_en = 0, pd_det_en, i;
 587
 588         con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
 589
 590         if (on) {
 591                 for (i = 0; i < data->ntrip; i++) {
 592                         if (thermal_zone_get_trip(tz, i, &trip))
 593                                 continue;
 594
 595                         interrupt_en |=
 596                                 (1 << (EXYNOS7_TMU_INTEN_RISE0_SHIFT + i));
 597                 }
 598
 599                 interrupt_en |=
 600                         interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
 601
 602                 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
 603         } else
 604                 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
 605
 606         pd_det_en = on ? EXYNOS5433_PD_DET_EN : 0;
 607
 608         writel(pd_det_en, data->base + EXYNOS5433_TMU_PD_DET_EN);
 609         writel(interrupt_en, data->base + EXYNOS5433_TMU_REG_INTEN);
 610         writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
 611 }
 612
 613 static void exynos7_tmu_control(struct platform_device *pdev, bool on)
 614 {
 615         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
 616         struct thermal_zone_device *tz = data->tzd;
 617         struct thermal_trip trip;
 618         unsigned int con, interrupt_en = 0, i;
 619
 620         con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
 621
 622         if (on) {
 623                 for (i = 0; i < data->ntrip; i++) {
 624                         if (thermal_zone_get_trip(tz, i, &trip))
 625                                 continue;
 626
 627                         interrupt_en |=
 628                                 (1 << (EXYNOS7_TMU_INTEN_RISE0_SHIFT + i));
 629                 }
 630
 631                 interrupt_en |=
 632                         interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
 633
 634                 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
 635                 con |= (1 << EXYNOS7_PD_DET_EN_SHIFT);
 636         } else {
 637                 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
 638                 con &= ~(1 << EXYNOS7_PD_DET_EN_SHIFT);
 639         }
 640
 641         writel(interrupt_en, data->base + EXYNOS7_TMU_REG_INTEN);
 642         writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
 643 }
 644
 645 static int exynos_get_temp(struct thermal_zone_device *tz, int *temp)
 646 {
 647         struct exynos_tmu_data *data = thermal_zone_device_priv(tz);
 648         int value, ret = 0;
 649
 650         if (!data || !data->tmu_read)
 651                 return -EINVAL;
 652         else if (!data->enabled)
 653                 /*
 654                  * Called too early, probably
 655                  * from thermal_zone_of_sensor_register().
 656                  */
 657                 return -EAGAIN;
 658
 659         mutex_lock(&data->lock);
 660         clk_enable(data->clk);
 661
 662         value = data->tmu_read(data);
 663         if (value < 0)
 664                 ret = value;
 665         else
 666                 *temp = code_to_temp(data, value) * MCELSIUS;
 667
 668         clk_disable(data->clk);
 669         mutex_unlock(&data->lock);
 670
 671         return ret;
 672 }
 673
 674 #ifdef CONFIG_THERMAL_EMULATION
 675 static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val,
 676                             int temp)
 677 {
 678         if (temp) {
 679                 temp /= MCELSIUS;
 680
 681                 val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT);
 682                 val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT);
 683                 if (data->soc == SOC_ARCH_EXYNOS7) {
 684                         val &= ~(EXYNOS7_EMUL_DATA_MASK <<
 685                                 EXYNOS7_EMUL_DATA_SHIFT);
 686                         val |= (temp_to_code(data, temp) <<
 687                                 EXYNOS7_EMUL_DATA_SHIFT) |
 688                                 EXYNOS_EMUL_ENABLE;
 689                 } else {
 690                         val &= ~(EXYNOS_EMUL_DATA_MASK <<
 691                                 EXYNOS_EMUL_DATA_SHIFT);
 692                         val |= (temp_to_code(data, temp) <<
 693                                 EXYNOS_EMUL_DATA_SHIFT) |
 694                                 EXYNOS_EMUL_ENABLE;
 695                 }
 696         } else {
 697                 val &= ~EXYNOS_EMUL_ENABLE;
 698         }
 699
 700         return val;
 701 }
 702
 703 static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data,
 704                                          int temp)
 705 {
 706         unsigned int val;
 707         u32 emul_con;
 708
 709         if (data->soc == SOC_ARCH_EXYNOS5260)
 710                 emul_con = EXYNOS5260_EMUL_CON;
 711         else if (data->soc == SOC_ARCH_EXYNOS5433)
 712                 emul_con = EXYNOS5433_TMU_EMUL_CON;
 713         else if (data->soc == SOC_ARCH_EXYNOS7)
 714                 emul_con = EXYNOS7_TMU_REG_EMUL_CON;
 715         else
 716                 emul_con = EXYNOS_EMUL_CON;
 717
 718         val = readl(data->base + emul_con);
 719         val = get_emul_con_reg(data, val, temp);
 720         writel(val, data->base + emul_con);
 721 }
 722
 723 static int exynos_tmu_set_emulation(struct thermal_zone_device *tz, int temp)
 724 {
 725         struct exynos_tmu_data *data = thermal_zone_device_priv(tz);
 726         int ret = -EINVAL;
 727
 728         if (data->soc == SOC_ARCH_EXYNOS4210)
 729                 goto out;
 730
 731         if (temp && temp < MCELSIUS)
 732                 goto out;
 733
 734         mutex_lock(&data->lock);
 735         clk_enable(data->clk);
 736         data->tmu_set_emulation(data, temp);
 737         clk_disable(data->clk);
 738         mutex_unlock(&data->lock);
 739         return 0;
 740 out:
 741         return ret;
 742 }
 743 #else
 744 #define exynos4412_tmu_set_emulation NULL
 745 static int exynos_tmu_set_emulation(struct thermal_zone_device *tz, int temp)
 746         { return -EINVAL; }
 747 #endif /* CONFIG_THERMAL_EMULATION */
 748
 749 static int exynos4210_tmu_read(struct exynos_tmu_data *data)
 750 {
 751         int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
 752
 753         /* "temp_code" should range between 75 and 175 */
 754         return (ret < 75 || ret > 175) ? -ENODATA : ret;
 755 }
 756
 757 static int exynos4412_tmu_read(struct exynos_tmu_data *data)
 758 {
 759         return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
 760 }
 761
 762 static int exynos7_tmu_read(struct exynos_tmu_data *data)
 763 {
 764         return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) &
 765                 EXYNOS7_TMU_TEMP_MASK;
 766 }
 767
 768 static void exynos_tmu_work(struct work_struct *work)
 769 {
 770         struct exynos_tmu_data *data = container_of(work,
 771                         struct exynos_tmu_data, irq_work);
 772
 773         thermal_zone_device_update(data->tzd, THERMAL_EVENT_UNSPECIFIED);
 774
 775         mutex_lock(&data->lock);
 776         clk_enable(data->clk);
 777
 778         /* TODO: take action based on particular interrupt */
 779         data->tmu_clear_irqs(data);
 780
 781         clk_disable(data->clk);
 782         mutex_unlock(&data->lock);
 783         enable_irq(data->irq);
 784 }
 785
 786 static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data)
 787 {
 788         unsigned int val_irq;
 789         u32 tmu_intstat, tmu_intclear;
 790
 791         if (data->soc == SOC_ARCH_EXYNOS5260) {
 792                 tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT;
 793                 tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR;
 794         } else if (data->soc == SOC_ARCH_EXYNOS7) {
 795                 tmu_intstat = EXYNOS7_TMU_REG_INTPEND;
 796                 tmu_intclear = EXYNOS7_TMU_REG_INTPEND;
 797         } else if (data->soc == SOC_ARCH_EXYNOS5433) {
 798                 tmu_intstat = EXYNOS5433_TMU_REG_INTPEND;
 799                 tmu_intclear = EXYNOS5433_TMU_REG_INTPEND;
 800         } else {
 801                 tmu_intstat = EXYNOS_TMU_REG_INTSTAT;
 802                 tmu_intclear = EXYNOS_TMU_REG_INTCLEAR;
 803         }
 804
 805         val_irq = readl(data->base + tmu_intstat);
 806         /*
 807          * Clear the interrupts.  Please note that the documentation for
 808          * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly
 809          * states that INTCLEAR register has a different placing of bits
 810          * responsible for FALL IRQs than INTSTAT register.  Exynos5420
 811          * and Exynos5440 documentation is correct (Exynos4210 doesn't
 812          * support FALL IRQs at all).
 813          */
 814         writel(val_irq, data->base + tmu_intclear);
 815 }
 816
 817 static irqreturn_t exynos_tmu_irq(int irq, void *id)
 818 {
 819         struct exynos_tmu_data *data = id;
 820
 821         disable_irq_nosync(irq);
 822         schedule_work(&data->irq_work);
 823
 824         return IRQ_HANDLED;
 825 }
 826
 827 static const struct of_device_id exynos_tmu_match[] = {
 828         {
 829                 .compatible = "samsung,exynos3250-tmu",
 830                 .data = (const void *)SOC_ARCH_EXYNOS3250,
 831         }, {
 832                 .compatible = "samsung,exynos4210-tmu",
 833                 .data = (const void *)SOC_ARCH_EXYNOS4210,
 834         }, {
 835                 .compatible = "samsung,exynos4412-tmu",
 836                 .data = (const void *)SOC_ARCH_EXYNOS4412,
 837         }, {
 838                 .compatible = "samsung,exynos5250-tmu",
 839                 .data = (const void *)SOC_ARCH_EXYNOS5250,
 840         }, {
 841                 .compatible = "samsung,exynos5260-tmu",
 842                 .data = (const void *)SOC_ARCH_EXYNOS5260,
 843         }, {
 844                 .compatible = "samsung,exynos5420-tmu",
 845                 .data = (const void *)SOC_ARCH_EXYNOS5420,
 846         }, {
 847                 .compatible = "samsung,exynos5420-tmu-ext-triminfo",
 848                 .data = (const void *)SOC_ARCH_EXYNOS5420_TRIMINFO,
 849         }, {
 850                 .compatible = "samsung,exynos5433-tmu",
 851                 .data = (const void *)SOC_ARCH_EXYNOS5433,
 852         }, {
 853                 .compatible = "samsung,exynos7-tmu",
 854                 .data = (const void *)SOC_ARCH_EXYNOS7,
 855         },
 856         { },
 857 };
 858 MODULE_DEVICE_TABLE(of, exynos_tmu_match);
 859
 860 static int exynos_map_dt_data(struct platform_device *pdev)
 861 {
 862         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
 863         struct resource res;
 864
 865         if (!data || !pdev->dev.of_node)
 866                 return -ENODEV;
 867
 868         data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl");
 869         if (data->id < 0)
 870                 data->id = 0;
 871
 872         data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
 873         if (data->irq <= 0) {
 874                 dev_err(&pdev->dev, "failed to get IRQ\n");
 875                 return -ENODEV;
 876         }
 877
 878         if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
 879                 dev_err(&pdev->dev, "failed to get Resource 0\n");
 880                 return -ENODEV;
 881         }
 882
 883         data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
 884         if (!data->base) {
 885                 dev_err(&pdev->dev, "Failed to ioremap memory\n");
 886                 return -EADDRNOTAVAIL;
 887         }
 888
 889         data->soc = (uintptr_t)of_device_get_match_data(&pdev->dev);
 890
 891         switch (data->soc) {
 892         case SOC_ARCH_EXYNOS4210:
 893                 data->tmu_set_trip_temp = exynos4210_tmu_set_trip_temp;
 894                 data->tmu_set_trip_hyst = exynos4210_tmu_set_trip_hyst;
 895                 data->tmu_initialize = exynos4210_tmu_initialize;
 896                 data->tmu_control = exynos4210_tmu_control;
 897                 data->tmu_read = exynos4210_tmu_read;
 898                 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
 899                 data->ntrip = 4;
 900                 data->gain = 15;
 901                 data->reference_voltage = 7;
 902                 data->efuse_value = 55;
 903                 data->min_efuse_value = 40;
 904                 data->max_efuse_value = 100;
 905                 break;
 906         case SOC_ARCH_EXYNOS3250:
 907         case SOC_ARCH_EXYNOS4412:
 908         case SOC_ARCH_EXYNOS5250:
 909         case SOC_ARCH_EXYNOS5260:
 910         case SOC_ARCH_EXYNOS5420:
 911         case SOC_ARCH_EXYNOS5420_TRIMINFO:
 912                 data->tmu_set_trip_temp = exynos4412_tmu_set_trip_temp;
 913                 data->tmu_set_trip_hyst = exynos4412_tmu_set_trip_hyst;
 914                 data->tmu_initialize = exynos4412_tmu_initialize;
 915                 data->tmu_control = exynos4210_tmu_control;
 916                 data->tmu_read = exynos4412_tmu_read;
 917                 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
 918                 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
 919                 data->ntrip = 4;
 920                 data->gain = 8;
 921                 data->reference_voltage = 16;
 922                 data->efuse_value = 55;
 923                 if (data->soc != SOC_ARCH_EXYNOS5420 &&
 924                     data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO)
 925                         data->min_efuse_value = 40;
 926                 else
 927                         data->min_efuse_value = 0;
 928                 data->max_efuse_value = 100;
 929                 break;
 930         case SOC_ARCH_EXYNOS5433:
 931                 data->tmu_set_trip_temp = exynos5433_tmu_set_trip_temp;
 932                 data->tmu_set_trip_hyst = exynos5433_tmu_set_trip_hyst;
 933                 data->tmu_initialize = exynos5433_tmu_initialize;
 934                 data->tmu_control = exynos5433_tmu_control;
 935                 data->tmu_read = exynos4412_tmu_read;
 936                 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
 937                 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
 938                 data->ntrip = 8;
 939                 data->gain = 8;
 940                 if (res.start == EXYNOS5433_G3D_BASE)
 941                         data->reference_voltage = 23;
 942                 else
 943                         data->reference_voltage = 16;
 944                 data->efuse_value = 75;
 945                 data->min_efuse_value = 40;
 946                 data->max_efuse_value = 150;
 947                 break;
 948         case SOC_ARCH_EXYNOS7:
 949                 data->tmu_set_trip_temp = exynos7_tmu_set_trip_temp;
 950                 data->tmu_set_trip_hyst = exynos7_tmu_set_trip_hyst;
 951                 data->tmu_initialize = exynos7_tmu_initialize;
 952                 data->tmu_control = exynos7_tmu_control;
 953                 data->tmu_read = exynos7_tmu_read;
 954                 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
 955                 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
 956                 data->ntrip = 8;
 957                 data->gain = 9;
 958                 data->reference_voltage = 17;
 959                 data->efuse_value = 75;
 960                 data->min_efuse_value = 15;
 961                 data->max_efuse_value = 100;
 962                 break;
 963         default:
 964                 dev_err(&pdev->dev, "Platform not supported\n");
 965                 return -EINVAL;
 966         }
 967
 968         data->cal_type = TYPE_ONE_POINT_TRIMMING;
 969
 970         /*
 971          * Check if the TMU shares some registers and then try to map the
 972          * memory of common registers.
 973          */
 974         if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO)
 975                 return 0;
 976
 977         if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
 978                 dev_err(&pdev->dev, "failed to get Resource 1\n");
 979                 return -ENODEV;
 980         }
 981
 982         data->base_second = devm_ioremap(&pdev->dev, res.start,
 983                                         resource_size(&res));
 984         if (!data->base_second) {
 985                 dev_err(&pdev->dev, "Failed to ioremap memory\n");
 986                 return -ENOMEM;
 987         }
 988
 989         return 0;
 990 }
 991
 992 static const struct thermal_zone_device_ops exynos_sensor_ops = {
 993         .get_temp = exynos_get_temp,
 994         .set_emul_temp = exynos_tmu_set_emulation,
 995 };
 996
 997 static int exynos_tmu_probe(struct platform_device *pdev)
 998 {
 999         struct exynos_tmu_data *data;
1000         int ret;
1001
1002         data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
1003                                         GFP_KERNEL);
1004         if (!data)
1005                 return -ENOMEM;
1006
1007         platform_set_drvdata(pdev, data);
1008         mutex_init(&data->lock);
1009
1010         /*
1011          * Try enabling the regulator if found
1012          * TODO: Add regulator as an SOC feature, so that regulator enable
1013          * is a compulsory call.
1014          */
1015         data->regulator = devm_regulator_get_optional(&pdev->dev, "vtmu");
1016         if (!IS_ERR(data->regulator)) {
1017                 ret = regulator_enable(data->regulator);
1018                 if (ret) {
1019                         dev_err(&pdev->dev, "failed to enable vtmu\n");
1020                         return ret;
1021                 }
1022         } else {
1023                 if (PTR_ERR(data->regulator) == -EPROBE_DEFER)
1024                         return -EPROBE_DEFER;
1025                 dev_info(&pdev->dev, "Regulator node (vtmu) not found\n");
1026         }
1027
1028         ret = exynos_map_dt_data(pdev);
1029         if (ret)
1030                 goto err_sensor;
1031
1032         INIT_WORK(&data->irq_work, exynos_tmu_work);
1033
1034         data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
1035         if (IS_ERR(data->clk)) {
1036                 dev_err(&pdev->dev, "Failed to get clock\n");
1037                 ret = PTR_ERR(data->clk);
1038                 goto err_sensor;
1039         }
1040
1041         data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif");
1042         if (IS_ERR(data->clk_sec)) {
1043                 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
1044                         dev_err(&pdev->dev, "Failed to get triminfo clock\n");
1045                         ret = PTR_ERR(data->clk_sec);
1046                         goto err_sensor;
1047                 }
1048         } else {
1049                 ret = clk_prepare(data->clk_sec);
1050                 if (ret) {
1051                         dev_err(&pdev->dev, "Failed to get clock\n");
1052                         goto err_sensor;
1053                 }
1054         }
1055
1056         ret = clk_prepare(data->clk);
1057         if (ret) {
1058                 dev_err(&pdev->dev, "Failed to get clock\n");
1059                 goto err_clk_sec;
1060         }
1061
1062         switch (data->soc) {
1063         case SOC_ARCH_EXYNOS5433:
1064         case SOC_ARCH_EXYNOS7:
1065                 data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk");
1066                 if (IS_ERR(data->sclk)) {
1067                         dev_err(&pdev->dev, "Failed to get sclk\n");
1068                         ret = PTR_ERR(data->sclk);
1069                         goto err_clk;
1070                 } else {
1071                         ret = clk_prepare_enable(data->sclk);
1072                         if (ret) {
1073                                 dev_err(&pdev->dev, "Failed to enable sclk\n");
1074                                 goto err_clk;
1075                         }
1076                 }
1077                 break;
1078         default:
1079                 break;
1080         }
1081
1082         /*
1083          * data->tzd must be registered before calling exynos_tmu_initialize(),
1084          * requesting irq and calling exynos_tmu_control().
1085          */
1086         data->tzd = devm_thermal_of_zone_register(&pdev->dev, 0, data,
1087                                                   &exynos_sensor_ops);
1088         if (IS_ERR(data->tzd)) {
1089                 ret = PTR_ERR(data->tzd);
1090                 if (ret != -EPROBE_DEFER)
1091                         dev_err(&pdev->dev, "Failed to register sensor: %d\n",
1092                                 ret);
1093                 goto err_sclk;
1094         }
1095
1096         ret = exynos_tmu_initialize(pdev);
1097         if (ret) {
1098                 dev_err(&pdev->dev, "Failed to initialize TMU\n");
1099                 goto err_sclk;
1100         }
1101
1102         ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
1103                 IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data);
1104         if (ret) {
1105                 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
1106                 goto err_sclk;
1107         }
1108
1109         exynos_tmu_control(pdev, true);
1110         return 0;
1111
1112 err_sclk:
1113         clk_disable_unprepare(data->sclk);
1114 err_clk:
1115         clk_unprepare(data->clk);
1116 err_clk_sec:
1117         if (!IS_ERR(data->clk_sec))
1118                 clk_unprepare(data->clk_sec);
1119 err_sensor:
1120         if (!IS_ERR(data->regulator))
1121                 regulator_disable(data->regulator);
1122
1123         return ret;
1124 }
1125
1126 static void exynos_tmu_remove(struct platform_device *pdev)
1127 {
1128         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
1129
1130         exynos_tmu_control(pdev, false);
1131
1132         clk_disable_unprepare(data->sclk);
1133         clk_unprepare(data->clk);
1134         if (!IS_ERR(data->clk_sec))
1135                 clk_unprepare(data->clk_sec);
1136
1137         if (!IS_ERR(data->regulator))
1138                 regulator_disable(data->regulator);
1139 }
1140
1141 #ifdef CONFIG_PM_SLEEP
1142 static int exynos_tmu_suspend(struct device *dev)
1143 {
1144         exynos_tmu_control(to_platform_device(dev), false);
1145
1146         return 0;
1147 }
1148
1149 static int exynos_tmu_resume(struct device *dev)
1150 {
1151         struct platform_device *pdev = to_platform_device(dev);
1152
1153         exynos_tmu_initialize(pdev);
1154         exynos_tmu_control(pdev, true);
1155
1156         return 0;
1157 }
1158
1159 static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
1160                          exynos_tmu_suspend, exynos_tmu_resume);
1161 #define EXYNOS_TMU_PM   (&exynos_tmu_pm)
1162 #else
1163 #define EXYNOS_TMU_PM   NULL
1164 #endif
1165
1166 static struct platform_driver exynos_tmu_driver = {
1167         .driver = {
1168                 .name   = "exynos-tmu",
1169                 .pm     = EXYNOS_TMU_PM,
1170                 .of_match_table = exynos_tmu_match,
1171         },
1172         .probe = exynos_tmu_probe,
1173         .remove_new = exynos_tmu_remove,
1174 };
1175
1176 module_platform_driver(exynos_tmu_driver);
1177
1178 MODULE_DESCRIPTION("Exynos TMU Driver");
1179 MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
1180 MODULE_LICENSE("GPL");
1181 MODULE_ALIAS("platform:exynos-tmu");