1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Hanyi Wu <hanyi.wu@mediatek.com>
5 * Sascha Hauer <s.hauer@pengutronix.de>
6 * Dawei Chien <dawei.chien@mediatek.com>
7 * Louis Yu <louis.yu@mediatek.com>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/nvmem-consumer.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/slab.h>
22 #include <linux/thermal.h>
23 #include <linux/reset.h>
24 #include <linux/types.h>
26 #include "../thermal_hwmon.h"
28 /* AUXADC Registers */
29 #define AUXADC_CON1_SET_V 0x008
30 #define AUXADC_CON1_CLR_V 0x00c
31 #define AUXADC_CON2_V 0x010
32 #define AUXADC_DATA(channel) (0x14 + (channel) * 4)
34 #define APMIXED_SYS_TS_CON1 0x604
36 /* Thermal Controller Registers */
37 #define TEMP_MONCTL0 0x000
38 #define TEMP_MONCTL1 0x004
39 #define TEMP_MONCTL2 0x008
40 #define TEMP_MONIDET0 0x014
41 #define TEMP_MONIDET1 0x018
42 #define TEMP_MSRCTL0 0x038
43 #define TEMP_MSRCTL1 0x03c
44 #define TEMP_AHBPOLL 0x040
45 #define TEMP_AHBTO 0x044
46 #define TEMP_ADCPNP0 0x048
47 #define TEMP_ADCPNP1 0x04c
48 #define TEMP_ADCPNP2 0x050
49 #define TEMP_ADCPNP3 0x0b4
51 #define TEMP_ADCMUX 0x054
52 #define TEMP_ADCEN 0x060
53 #define TEMP_PNPMUXADDR 0x064
54 #define TEMP_ADCMUXADDR 0x068
55 #define TEMP_ADCENADDR 0x074
56 #define TEMP_ADCVALIDADDR 0x078
57 #define TEMP_ADCVOLTADDR 0x07c
58 #define TEMP_RDCTRL 0x080
59 #define TEMP_ADCVALIDMASK 0x084
60 #define TEMP_ADCVOLTAGESHIFT 0x088
61 #define TEMP_ADCWRITECTRL 0x08c
62 #define TEMP_MSR0 0x090
63 #define TEMP_MSR1 0x094
64 #define TEMP_MSR2 0x098
65 #define TEMP_MSR3 0x0B8
67 #define TEMP_SPARE0 0x0f0
69 #define TEMP_ADCPNP0_1 0x148
70 #define TEMP_ADCPNP1_1 0x14c
71 #define TEMP_ADCPNP2_1 0x150
72 #define TEMP_MSR0_1 0x190
73 #define TEMP_MSR1_1 0x194
74 #define TEMP_MSR2_1 0x198
75 #define TEMP_ADCPNP3_1 0x1b4
76 #define TEMP_MSR3_1 0x1B8
78 #define PTPCORESEL 0x400
80 #define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff)
82 #define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
83 #define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
85 #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x)
87 #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0)
88 #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1)
90 #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5)
91 #define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit)
93 /* MT8173 thermal sensors */
98 #define MT8173_TSABB 4
100 /* AUXADC channel 11 is used for the temperature sensors */
101 #define MT8173_TEMP_AUXADC_CHANNEL 11
103 /* The total number of temperature sensors in the MT8173 */
104 #define MT8173_NUM_SENSORS 5
106 /* The number of banks in the MT8173 */
107 #define MT8173_NUM_ZONES 4
109 /* The number of sensing points per bank */
110 #define MT8173_NUM_SENSORS_PER_ZONE 4
112 /* The number of controller in the MT8173 */
113 #define MT8173_NUM_CONTROLLER 1
115 /* The calibration coefficient of sensor */
116 #define MT8173_CALIBRATION 165
119 * Layout of the fuses providing the calibration data
120 * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
121 * MT8183 has 6 sensors and needs 6 VTS calibration data.
122 * MT8173 has 5 sensors and needs 5 VTS calibration data.
123 * MT2701 has 3 sensors and needs 3 VTS calibration data.
124 * MT2712 has 4 sensors and needs 4 VTS calibration data.
126 #define CALIB_BUF0_VALID_V1 BIT(0)
127 #define CALIB_BUF1_ADC_GE_V1(x) (((x) >> 22) & 0x3ff)
128 #define CALIB_BUF0_VTS_TS1_V1(x) (((x) >> 17) & 0x1ff)
129 #define CALIB_BUF0_VTS_TS2_V1(x) (((x) >> 8) & 0x1ff)
130 #define CALIB_BUF1_VTS_TS3_V1(x) (((x) >> 0) & 0x1ff)
131 #define CALIB_BUF2_VTS_TS4_V1(x) (((x) >> 23) & 0x1ff)
132 #define CALIB_BUF2_VTS_TS5_V1(x) (((x) >> 5) & 0x1ff)
133 #define CALIB_BUF2_VTS_TSABB_V1(x) (((x) >> 14) & 0x1ff)
134 #define CALIB_BUF0_DEGC_CALI_V1(x) (((x) >> 1) & 0x3f)
135 #define CALIB_BUF0_O_SLOPE_V1(x) (((x) >> 26) & 0x3f)
136 #define CALIB_BUF0_O_SLOPE_SIGN_V1(x) (((x) >> 7) & 0x1)
137 #define CALIB_BUF1_ID_V1(x) (((x) >> 9) & 0x1)
140 * Layout of the fuses providing the calibration data
141 * These macros could be used for MT7622.
143 #define CALIB_BUF0_ADC_OE_V2(x) (((x) >> 22) & 0x3ff)
144 #define CALIB_BUF0_ADC_GE_V2(x) (((x) >> 12) & 0x3ff)
145 #define CALIB_BUF0_DEGC_CALI_V2(x) (((x) >> 6) & 0x3f)
146 #define CALIB_BUF0_O_SLOPE_V2(x) (((x) >> 0) & 0x3f)
147 #define CALIB_BUF1_VTS_TS1_V2(x) (((x) >> 23) & 0x1ff)
148 #define CALIB_BUF1_VTS_TS2_V2(x) (((x) >> 14) & 0x1ff)
149 #define CALIB_BUF1_VTS_TSABB_V2(x) (((x) >> 5) & 0x1ff)
150 #define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1)
151 #define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1)
154 * Layout of the fuses providing the calibration data
155 * These macros can be used for MT7981 and MT7986.
157 #define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff)
158 #define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f)
159 #define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f)
160 #define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff)
161 #define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff)
162 #define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff)
163 #define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1)
164 #define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1)
165 #define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1)
177 enum mtk_thermal_version {
183 /* MT2701 thermal sensors */
186 #define MT2701_TSABB 2
188 /* AUXADC channel 11 is used for the temperature sensors */
189 #define MT2701_TEMP_AUXADC_CHANNEL 11
191 /* The total number of temperature sensors in the MT2701 */
192 #define MT2701_NUM_SENSORS 3
194 /* The number of sensing points per bank */
195 #define MT2701_NUM_SENSORS_PER_ZONE 3
197 /* The number of controller in the MT2701 */
198 #define MT2701_NUM_CONTROLLER 1
200 /* The calibration coefficient of sensor */
201 #define MT2701_CALIBRATION 165
203 /* MT2712 thermal sensors */
209 /* AUXADC channel 11 is used for the temperature sensors */
210 #define MT2712_TEMP_AUXADC_CHANNEL 11
212 /* The total number of temperature sensors in the MT2712 */
213 #define MT2712_NUM_SENSORS 4
215 /* The number of sensing points per bank */
216 #define MT2712_NUM_SENSORS_PER_ZONE 4
218 /* The number of controller in the MT2712 */
219 #define MT2712_NUM_CONTROLLER 1
221 /* The calibration coefficient of sensor */
222 #define MT2712_CALIBRATION 165
224 #define MT7622_TEMP_AUXADC_CHANNEL 11
225 #define MT7622_NUM_SENSORS 1
226 #define MT7622_NUM_ZONES 1
227 #define MT7622_NUM_SENSORS_PER_ZONE 1
229 #define MT7622_NUM_CONTROLLER 1
231 /* The maximum number of banks */
232 #define MAX_NUM_ZONES 8
234 /* The calibration coefficient of sensor */
235 #define MT7622_CALIBRATION 165
237 /* MT8183 thermal sensors */
243 #define MT8183_TSABB 5
245 /* AUXADC channel is used for the temperature sensors */
246 #define MT8183_TEMP_AUXADC_CHANNEL 11
248 /* The total number of temperature sensors in the MT8183 */
249 #define MT8183_NUM_SENSORS 6
251 /* The number of banks in the MT8183 */
252 #define MT8183_NUM_ZONES 1
254 /* The number of sensing points per bank */
255 #define MT8183_NUM_SENSORS_PER_ZONE 6
257 /* The number of controller in the MT8183 */
258 #define MT8183_NUM_CONTROLLER 2
260 /* The calibration coefficient of sensor */
261 #define MT8183_CALIBRATION 153
263 /* AUXADC channel 11 is used for the temperature sensors */
264 #define MT7986_TEMP_AUXADC_CHANNEL 11
266 /* The total number of temperature sensors in the MT7986 */
267 #define MT7986_NUM_SENSORS 1
269 /* The number of banks in the MT7986 */
270 #define MT7986_NUM_ZONES 1
272 /* The number of sensing points per bank */
273 #define MT7986_NUM_SENSORS_PER_ZONE 1
275 /* MT7986 thermal sensors */
278 /* The number of controller in the MT7986 */
279 #define MT7986_NUM_CONTROLLER 1
281 /* The calibration coefficient of sensor */
282 #define MT7986_CALIBRATION 165
286 struct thermal_bank_cfg {
287 unsigned int num_sensors;
291 struct mtk_thermal_bank {
292 struct mtk_thermal *mt;
296 struct mtk_thermal_data {
300 const int *vts_index;
301 const int *sensor_mux_values;
305 const int num_controller;
306 const int *controller_offset;
307 bool need_switch_bank;
308 struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
309 enum mtk_thermal_version version;
314 void __iomem *thermal_base;
316 struct clk *clk_peri_therm;
317 struct clk *clk_auxadc;
318 /* lock: for getting and putting banks */
321 /* Calibration values */
327 s32 vts[MAX_NUM_VTS];
329 const struct mtk_thermal_data *conf;
330 struct mtk_thermal_bank banks[MAX_NUM_ZONES];
332 int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw);
335 /* MT8183 thermal sensor data */
336 static const int mt8183_bank_data[MT8183_NUM_SENSORS] = {
337 MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB
340 static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = {
341 TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1
344 static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = {
345 TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1,
346 TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1
349 static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
350 static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
352 static const int mt8183_vts_index[MT8183_NUM_SENSORS] = {
353 VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB
356 /* MT8173 thermal sensor data */
357 static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
358 { MT8173_TS2, MT8173_TS3 },
359 { MT8173_TS2, MT8173_TS4 },
360 { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
364 static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
365 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
368 static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
369 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
372 static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
373 static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
375 static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
376 VTS1, VTS2, VTS3, VTS4, VTSABB
379 /* MT2701 thermal sensor data */
380 static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
381 MT2701_TS1, MT2701_TS2, MT2701_TSABB
384 static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
385 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
388 static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
389 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
392 static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
393 static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
395 static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
399 /* MT2712 thermal sensor data */
400 static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
401 MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
404 static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
405 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
408 static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
409 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
412 static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
413 static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
415 static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
416 VTS1, VTS2, VTS3, VTS4
419 /* MT7622 thermal sensor data */
420 static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
421 static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
422 static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
423 static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
424 static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
425 static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
427 /* MT7986 thermal sensor data */
428 static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
429 static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
430 static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
431 static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
432 static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
433 static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
436 * The MT8173 thermal controller has four banks. Each bank can read up to
437 * four temperature sensors simultaneously. The MT8173 has a total of 5
438 * temperature sensors. We use each bank to measure a certain area of the
439 * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
440 * areas, hence is used in different banks.
442 * The thermal core only gets the maximum temperature of all banks, so
443 * the bank concept wouldn't be necessary here. However, the SVS (Smart
444 * Voltage Scaling) unit makes its decisions based on the same bank
445 * data, and this indeed needs the temperatures of the individual banks
446 * for making better decisions.
448 static const struct mtk_thermal_data mt8173_thermal_data = {
449 .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
450 .num_banks = MT8173_NUM_ZONES,
451 .num_sensors = MT8173_NUM_SENSORS,
452 .vts_index = mt8173_vts_index,
453 .cali_val = MT8173_CALIBRATION,
454 .num_controller = MT8173_NUM_CONTROLLER,
455 .controller_offset = mt8173_tc_offset,
456 .need_switch_bank = true,
460 .sensors = mt8173_bank_data[0],
463 .sensors = mt8173_bank_data[1],
466 .sensors = mt8173_bank_data[2],
469 .sensors = mt8173_bank_data[3],
473 .adcpnp = mt8173_adcpnp,
474 .sensor_mux_values = mt8173_mux_values,
475 .version = MTK_THERMAL_V1,
479 * The MT2701 thermal controller has one bank, which can read up to
480 * three temperature sensors simultaneously. The MT2701 has a total of 3
481 * temperature sensors.
483 * The thermal core only gets the maximum temperature of this one bank,
484 * so the bank concept wouldn't be necessary here. However, the SVS (Smart
485 * Voltage Scaling) unit makes its decisions based on the same bank
488 static const struct mtk_thermal_data mt2701_thermal_data = {
489 .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
491 .num_sensors = MT2701_NUM_SENSORS,
492 .vts_index = mt2701_vts_index,
493 .cali_val = MT2701_CALIBRATION,
494 .num_controller = MT2701_NUM_CONTROLLER,
495 .controller_offset = mt2701_tc_offset,
496 .need_switch_bank = true,
500 .sensors = mt2701_bank_data,
504 .adcpnp = mt2701_adcpnp,
505 .sensor_mux_values = mt2701_mux_values,
506 .version = MTK_THERMAL_V1,
510 * The MT2712 thermal controller has one bank, which can read up to
511 * four temperature sensors simultaneously. The MT2712 has a total of 4
512 * temperature sensors.
514 * The thermal core only gets the maximum temperature of this one bank,
515 * so the bank concept wouldn't be necessary here. However, the SVS (Smart
516 * Voltage Scaling) unit makes its decisions based on the same bank
519 static const struct mtk_thermal_data mt2712_thermal_data = {
520 .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
522 .num_sensors = MT2712_NUM_SENSORS,
523 .vts_index = mt2712_vts_index,
524 .cali_val = MT2712_CALIBRATION,
525 .num_controller = MT2712_NUM_CONTROLLER,
526 .controller_offset = mt2712_tc_offset,
527 .need_switch_bank = true,
531 .sensors = mt2712_bank_data,
535 .adcpnp = mt2712_adcpnp,
536 .sensor_mux_values = mt2712_mux_values,
537 .version = MTK_THERMAL_V1,
541 * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data
544 static const struct mtk_thermal_data mt7622_thermal_data = {
545 .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
546 .num_banks = MT7622_NUM_ZONES,
547 .num_sensors = MT7622_NUM_SENSORS,
548 .vts_index = mt7622_vts_index,
549 .cali_val = MT7622_CALIBRATION,
550 .num_controller = MT7622_NUM_CONTROLLER,
551 .controller_offset = mt7622_tc_offset,
552 .need_switch_bank = true,
556 .sensors = mt7622_bank_data,
560 .adcpnp = mt7622_adcpnp,
561 .sensor_mux_values = mt7622_mux_values,
562 .version = MTK_THERMAL_V2,
566 * The MT8183 thermal controller has one bank for the current SW framework.
567 * The MT8183 has a total of 6 temperature sensors.
568 * There are two thermal controller to control the six sensor.
569 * The first one bind 2 sensor, and the other bind 4 sensors.
570 * The thermal core only gets the maximum temperature of all sensor, so
571 * the bank concept wouldn't be necessary here. However, the SVS (Smart
572 * Voltage Scaling) unit makes its decisions based on the same bank
573 * data, and this indeed needs the temperatures of the individual banks
574 * for making better decisions.
576 static const struct mtk_thermal_data mt8183_thermal_data = {
577 .auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL,
578 .num_banks = MT8183_NUM_ZONES,
579 .num_sensors = MT8183_NUM_SENSORS,
580 .vts_index = mt8183_vts_index,
581 .cali_val = MT8183_CALIBRATION,
582 .num_controller = MT8183_NUM_CONTROLLER,
583 .controller_offset = mt8183_tc_offset,
584 .need_switch_bank = false,
588 .sensors = mt8183_bank_data,
593 .adcpnp = mt8183_adcpnp,
594 .sensor_mux_values = mt8183_mux_values,
595 .version = MTK_THERMAL_V1,
599 * MT7986 uses AUXADC Channel 11 for raw data access.
601 static const struct mtk_thermal_data mt7986_thermal_data = {
602 .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
603 .num_banks = MT7986_NUM_ZONES,
604 .num_sensors = MT7986_NUM_SENSORS,
605 .vts_index = mt7986_vts_index,
606 .cali_val = MT7986_CALIBRATION,
607 .num_controller = MT7986_NUM_CONTROLLER,
608 .controller_offset = mt7986_tc_offset,
609 .need_switch_bank = true,
613 .sensors = mt7986_bank_data,
617 .adcpnp = mt7986_adcpnp,
618 .sensor_mux_values = mt7986_mux_values,
619 .version = MTK_THERMAL_V3,
623 * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
624 * @mt: The thermal controller
625 * @sensno: sensor number
626 * @raw: raw ADC value
628 * This converts the raw ADC value to mcelsius using the SoC specific
629 * calibration constants
631 static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw)
637 tmp = 203450520 << 3;
638 tmp /= mt->conf->cali_val + mt->o_slope;
639 tmp /= 10000 + mt->adc_ge;
640 tmp *= raw - mt->vts[sensno] - 3350;
643 return mt->degc_cali * 500 - tmp;
646 static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw)
659 g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12);
660 g_oe = mt->adc_oe - 512;
661 format_1 = mt->vts[VTS2] + 3105 - g_oe;
662 format_2 = (mt->degc_cali * 10) >> 1;
663 g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain;
665 tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt;
666 tmp = tmp * 10 * 100 / 11;
668 if (mt->o_slope_sign == 0)
669 tmp = tmp / (165 - mt->o_slope);
671 tmp = tmp / (165 + mt->o_slope);
673 return (format_2 - tmp) * 100;
676 static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
684 tmp = 100000 * 15 / 16 * 10000;
685 tmp /= 4096 - 512 + mt->adc_ge;
687 tmp *= raw - mt->vts[sensno] - 2900;
689 return mt->degc_cali * 500 - tmp;
693 * mtk_thermal_get_bank - get bank
696 * The bank registers are banked, we have to select a bank in the
697 * PTPCORESEL register to access it.
699 static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
701 struct mtk_thermal *mt = bank->mt;
704 if (mt->conf->need_switch_bank) {
705 mutex_lock(&mt->lock);
707 val = readl(mt->thermal_base + PTPCORESEL);
710 writel(val, mt->thermal_base + PTPCORESEL);
715 * mtk_thermal_put_bank - release bank
718 * release a bank previously taken with mtk_thermal_get_bank,
720 static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
722 struct mtk_thermal *mt = bank->mt;
724 if (mt->conf->need_switch_bank)
725 mutex_unlock(&mt->lock);
729 * mtk_thermal_bank_temperature - get the temperature of a bank
732 * The temperature of a bank is considered the maximum temperature of
733 * the sensors associated to the bank.
735 static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
737 struct mtk_thermal *mt = bank->mt;
738 const struct mtk_thermal_data *conf = mt->conf;
739 int i, temp = INT_MIN, max = INT_MIN;
742 for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
743 raw = readl(mt->thermal_base + conf->msr[i]);
745 temp = mt->raw_to_mcelsius(
746 mt, conf->bank_data[bank->id].sensors[i], raw);
750 * The first read of a sensor often contains very high bogus
751 * temperature value. Filter these out so that the system does
752 * not immediately shut down.
764 static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature)
766 struct mtk_thermal *mt = thermal_zone_device_priv(tz);
768 int tempmax = INT_MIN;
770 for (i = 0; i < mt->conf->num_banks; i++) {
771 struct mtk_thermal_bank *bank = &mt->banks[i];
773 mtk_thermal_get_bank(bank);
775 tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
777 mtk_thermal_put_bank(bank);
780 *temperature = tempmax;
785 static const struct thermal_zone_device_ops mtk_thermal_ops = {
786 .get_temp = mtk_read_temp,
789 static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
790 u32 apmixed_phys_base, u32 auxadc_phys_base,
793 struct mtk_thermal_bank *bank = &mt->banks[num];
794 const struct mtk_thermal_data *conf = mt->conf;
797 int offset = mt->conf->controller_offset[ctrl_id];
798 void __iomem *controller_base = mt->thermal_base + offset;
803 mtk_thermal_get_bank(bank);
805 /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
806 writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
809 * filt interval is 1 * 46.540us = 46.54us,
810 * sen interval is 429 * 46.540us = 19.96ms
812 writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
813 TEMP_MONCTL2_SENSOR_INTERVAL(429),
814 controller_base + TEMP_MONCTL2);
816 /* poll is set to 10u */
817 writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
818 controller_base + TEMP_AHBPOLL);
820 /* temperature sampling control, 1 sample */
821 writel(0x0, controller_base + TEMP_MSRCTL0);
823 /* exceed this polling time, IRQ would be inserted */
824 writel(0xffffffff, controller_base + TEMP_AHBTO);
826 /* number of interrupts per event, 1 is enough */
827 writel(0x0, controller_base + TEMP_MONIDET0);
828 writel(0x0, controller_base + TEMP_MONIDET1);
831 * The MT8173 thermal controller does not have its own ADC. Instead it
832 * uses AHB bus accesses to control the AUXADC. To do this the thermal
833 * controller has to be programmed with the physical addresses of the
834 * AUXADC registers and with the various bit positions in the AUXADC.
835 * Also the thermal controller controls a mux in the APMIXEDSYS register
840 * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
841 * automatically by hw
843 writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
845 /* AHB address for auxadc mux selection */
846 writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
847 controller_base + TEMP_ADCMUXADDR);
849 if (mt->conf->version == MTK_THERMAL_V1) {
850 /* AHB address for pnp sensor mux selection */
851 writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
852 controller_base + TEMP_PNPMUXADDR);
855 /* AHB value for auxadc enable */
856 writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
858 /* AHB address for auxadc enable (channel 0 immediate mode selected) */
859 writel(auxadc_phys_base + AUXADC_CON1_SET_V,
860 controller_base + TEMP_ADCENADDR);
862 /* AHB address for auxadc valid bit */
863 writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
864 controller_base + TEMP_ADCVALIDADDR);
866 /* AHB address for auxadc voltage output */
867 writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
868 controller_base + TEMP_ADCVOLTADDR);
870 /* read valid & voltage are at the same register */
871 writel(0x0, controller_base + TEMP_RDCTRL);
873 /* indicate where the valid bit is */
874 writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
875 controller_base + TEMP_ADCVALIDMASK);
878 writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
880 /* enable auxadc mux write transaction */
881 writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
882 controller_base + TEMP_ADCWRITECTRL);
884 for (i = 0; i < conf->bank_data[num].num_sensors; i++)
885 writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
886 mt->thermal_base + conf->adcpnp[i]);
888 writel((1 << conf->bank_data[num].num_sensors) - 1,
889 controller_base + TEMP_MONCTL0);
891 writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
892 TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
893 controller_base + TEMP_ADCWRITECTRL);
895 mtk_thermal_put_bank(bank);
898 static u64 of_get_phys_base(struct device_node *np)
901 const __be32 *regaddr_p;
903 regaddr_p = of_get_address(np, 0, &size64, NULL);
907 return of_translate_address(np, regaddr_p);
910 static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
914 if (!(buf[0] & CALIB_BUF0_VALID_V1))
917 mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]);
919 for (i = 0; i < mt->conf->num_sensors; i++) {
920 switch (mt->conf->vts_index[i]) {
922 mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);
925 mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);
928 mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]);
931 mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]);
934 mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]);
938 CALIB_BUF2_VTS_TSABB_V1(buf[2]);
945 mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);
946 if (CALIB_BUF1_ID_V1(buf[1]) &
947 CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0]))
948 mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);
950 mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);
955 static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf)
957 if (!CALIB_BUF1_VALID_V2(buf[1]))
960 mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);
961 mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);
962 mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);
963 mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);
964 mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]);
965 mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]);
966 mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]);
967 mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]);
972 static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
974 if (!CALIB_BUF1_VALID_V3(buf[1]))
977 mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
978 mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
979 mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
980 mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
981 mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
982 mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
983 mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
985 if (CALIB_BUF1_ID_V3(buf[1]) == 0)
991 static int mtk_thermal_get_calibration_data(struct device *dev,
992 struct mtk_thermal *mt)
994 struct nvmem_cell *cell;
999 /* Start with default values */
1002 for (i = 0; i < mt->conf->num_sensors; i++)
1007 cell = nvmem_cell_get(dev, "calibration-data");
1009 if (PTR_ERR(cell) == -EPROBE_DEFER)
1010 return PTR_ERR(cell);
1014 buf = (u32 *)nvmem_cell_read(cell, &len);
1016 nvmem_cell_put(cell);
1019 return PTR_ERR(buf);
1021 if (len < 3 * sizeof(u32)) {
1022 dev_warn(dev, "invalid calibration data\n");
1027 switch (mt->conf->version) {
1028 case MTK_THERMAL_V1:
1029 ret = mtk_thermal_extract_efuse_v1(mt, buf);
1031 case MTK_THERMAL_V2:
1032 ret = mtk_thermal_extract_efuse_v2(mt, buf);
1034 case MTK_THERMAL_V3:
1035 ret = mtk_thermal_extract_efuse_v3(mt, buf);
1043 dev_info(dev, "Device not calibrated, using default calibration values\n");
1053 static const struct of_device_id mtk_thermal_of_match[] = {
1055 .compatible = "mediatek,mt8173-thermal",
1056 .data = (void *)&mt8173_thermal_data,
1059 .compatible = "mediatek,mt2701-thermal",
1060 .data = (void *)&mt2701_thermal_data,
1063 .compatible = "mediatek,mt2712-thermal",
1064 .data = (void *)&mt2712_thermal_data,
1067 .compatible = "mediatek,mt7622-thermal",
1068 .data = (void *)&mt7622_thermal_data,
1071 .compatible = "mediatek,mt7986-thermal",
1072 .data = (void *)&mt7986_thermal_data,
1075 .compatible = "mediatek,mt8183-thermal",
1076 .data = (void *)&mt8183_thermal_data,
1080 MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
1082 static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base)
1086 tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1);
1089 writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1);
1093 static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt,
1094 void __iomem *auxadc_base)
1098 writel(0x800, auxadc_base + AUXADC_CON1_SET_V);
1099 writel(0x1, mt->thermal_base + TEMP_MONCTL0);
1100 tmp = readl(mt->thermal_base + TEMP_MSRCTL1);
1101 writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);
1104 static int mtk_thermal_probe(struct platform_device *pdev)
1106 int ret, i, ctrl_id;
1107 struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
1108 struct mtk_thermal *mt;
1109 u64 auxadc_phys_base, apmixed_phys_base;
1110 struct thermal_zone_device *tzdev;
1111 void __iomem *apmixed_base, *auxadc_base;
1113 mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
1117 mt->conf = of_device_get_match_data(&pdev->dev);
1119 mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
1120 if (IS_ERR(mt->clk_peri_therm))
1121 return PTR_ERR(mt->clk_peri_therm);
1123 mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
1124 if (IS_ERR(mt->clk_auxadc))
1125 return PTR_ERR(mt->clk_auxadc);
1127 mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
1128 if (IS_ERR(mt->thermal_base))
1129 return PTR_ERR(mt->thermal_base);
1131 ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
1135 mutex_init(&mt->lock);
1137 mt->dev = &pdev->dev;
1139 auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
1141 dev_err(&pdev->dev, "missing auxadc node\n");
1145 auxadc_base = of_iomap(auxadc, 0);
1146 auxadc_phys_base = of_get_phys_base(auxadc);
1148 of_node_put(auxadc);
1150 if (auxadc_phys_base == OF_BAD_ADDR) {
1151 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
1155 apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
1157 dev_err(&pdev->dev, "missing apmixedsys node\n");
1161 apmixed_base = of_iomap(apmixedsys, 0);
1162 apmixed_phys_base = of_get_phys_base(apmixedsys);
1164 of_node_put(apmixedsys);
1166 if (apmixed_phys_base == OF_BAD_ADDR) {
1167 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
1171 ret = device_reset_optional(&pdev->dev);
1175 ret = clk_prepare_enable(mt->clk_auxadc);
1177 dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
1181 ret = clk_prepare_enable(mt->clk_peri_therm);
1183 dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
1184 goto err_disable_clk_auxadc;
1187 if (mt->conf->version != MTK_THERMAL_V1) {
1188 mtk_thermal_turn_on_buffer(apmixed_base);
1189 mtk_thermal_release_periodic_ts(mt, auxadc_base);
1192 if (mt->conf->version == MTK_THERMAL_V1)
1193 mt->raw_to_mcelsius = raw_to_mcelsius_v1;
1194 else if (mt->conf->version == MTK_THERMAL_V2)
1195 mt->raw_to_mcelsius = raw_to_mcelsius_v2;
1197 mt->raw_to_mcelsius = raw_to_mcelsius_v3;
1199 for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
1200 for (i = 0; i < mt->conf->num_banks; i++)
1201 mtk_thermal_init_bank(mt, i, apmixed_phys_base,
1202 auxadc_phys_base, ctrl_id);
1204 platform_set_drvdata(pdev, mt);
1206 tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
1208 if (IS_ERR(tzdev)) {
1209 ret = PTR_ERR(tzdev);
1210 goto err_disable_clk_peri_therm;
1213 ret = devm_thermal_add_hwmon_sysfs(tzdev);
1215 dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
1219 err_disable_clk_peri_therm:
1220 clk_disable_unprepare(mt->clk_peri_therm);
1221 err_disable_clk_auxadc:
1222 clk_disable_unprepare(mt->clk_auxadc);
1227 static int mtk_thermal_remove(struct platform_device *pdev)
1229 struct mtk_thermal *mt = platform_get_drvdata(pdev);
1231 clk_disable_unprepare(mt->clk_peri_therm);
1232 clk_disable_unprepare(mt->clk_auxadc);
1237 static struct platform_driver mtk_thermal_driver = {
1238 .probe = mtk_thermal_probe,
1239 .remove = mtk_thermal_remove,
1241 .name = "mtk-thermal",
1242 .of_match_table = mtk_thermal_of_match,
1246 module_platform_driver(mtk_thermal_driver);
1248 MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
1249 MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
1250 MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
1251 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1252 MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
1253 MODULE_DESCRIPTION("Mediatek thermal driver");
1254 MODULE_LICENSE("GPL v2");