1 // SPDX-License-Identifier: GPL-2.0-only
3 * Marvell EBU Armada SoCs thermal sensor driver
5 * Copyright (C) 2013 Marvell
7 #include <linux/device.h>
10 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/platform_device.h>
15 #include <linux/of_device.h>
16 #include <linux/thermal.h>
17 #include <linux/iopoll.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/regmap.h>
20 #include <linux/interrupt.h>
22 #include "thermal_core.h"
24 #define TO_MCELSIUS(c) ((c) * 1000)
26 /* Thermal Manager Control and Status Register */
27 #define PMU_TDC0_SW_RST_MASK (0x1 << 1)
28 #define PMU_TM_DISABLE_OFFS 0
29 #define PMU_TM_DISABLE_MASK (0x1 << PMU_TM_DISABLE_OFFS)
30 #define PMU_TDC0_REF_CAL_CNT_OFFS 11
31 #define PMU_TDC0_REF_CAL_CNT_MASK (0x1ff << PMU_TDC0_REF_CAL_CNT_OFFS)
32 #define PMU_TDC0_OTF_CAL_MASK (0x1 << 30)
33 #define PMU_TDC0_START_CAL_MASK (0x1 << 25)
35 #define A375_UNIT_CONTROL_SHIFT 27
36 #define A375_UNIT_CONTROL_MASK 0x7
37 #define A375_READOUT_INVERT BIT(15)
38 #define A375_HW_RESETn BIT(8)
41 #define CONTROL0_TSEN_TC_TRIM_MASK 0x7
42 #define CONTROL0_TSEN_TC_TRIM_VAL 0x3
44 #define CONTROL0_TSEN_START BIT(0)
45 #define CONTROL0_TSEN_RESET BIT(1)
46 #define CONTROL0_TSEN_ENABLE BIT(2)
47 #define CONTROL0_TSEN_AVG_BYPASS BIT(6)
48 #define CONTROL0_TSEN_CHAN_SHIFT 13
49 #define CONTROL0_TSEN_CHAN_MASK 0xF
50 #define CONTROL0_TSEN_OSR_SHIFT 24
51 #define CONTROL0_TSEN_OSR_MAX 0x3
52 #define CONTROL0_TSEN_MODE_SHIFT 30
53 #define CONTROL0_TSEN_MODE_EXTERNAL 0x2
54 #define CONTROL0_TSEN_MODE_MASK 0x3
56 #define CONTROL1_TSEN_AVG_MASK 0x7
57 #define CONTROL1_EXT_TSEN_SW_RESET BIT(7)
58 #define CONTROL1_EXT_TSEN_HW_RESETn BIT(8)
59 #define CONTROL1_TSEN_INT_EN BIT(25)
60 #define CONTROL1_TSEN_SELECT_OFF 21
61 #define CONTROL1_TSEN_SELECT_MASK 0x3
63 #define STATUS_POLL_PERIOD_US 1000
64 #define STATUS_POLL_TIMEOUT_US 100000
65 #define OVERHEAT_INT_POLL_DELAY_MS 1000
67 struct armada_thermal_data;
69 /* Marvell EBU Thermal Sensor Dev Structure */
70 struct armada_thermal_priv {
72 struct regmap *syscon;
73 char zone_name[THERMAL_NAME_LENGTH];
74 /* serialize temperature reads/updates */
75 struct mutex update_lock;
76 struct armada_thermal_data *data;
77 struct thermal_zone_device *overheat_sensor;
80 long current_threshold;
81 long current_hysteresis;
84 struct armada_thermal_data {
85 /* Initialize the thermal IC */
86 void (*init)(struct platform_device *pdev,
87 struct armada_thermal_priv *priv);
89 /* Formula coeficients: temp = (b - m * reg) / div */
96 /* Register shift and mask to access the sensor temperature */
97 unsigned int temp_shift;
98 unsigned int temp_mask;
99 unsigned int thresh_shift;
100 unsigned int hyst_shift;
101 unsigned int hyst_mask;
105 unsigned int syscon_control0_off;
106 unsigned int syscon_control1_off;
107 unsigned int syscon_status_off;
108 unsigned int dfx_irq_cause_off;
109 unsigned int dfx_irq_mask_off;
110 unsigned int dfx_overheat_irq;
111 unsigned int dfx_server_irq_mask_off;
112 unsigned int dfx_server_irq_en;
114 /* One sensor is in the thermal IC, the others are in the CPUs if any */
118 struct armada_drvdata {
124 struct armada_thermal_priv *priv;
125 struct thermal_zone_device *tz;
130 * struct armada_thermal_sensor - hold the information of one thermal sensor
131 * @thermal: pointer to the local private structure
132 * @tzd: pointer to the thermal zone device
133 * @id: identifier of the thermal sensor
135 struct armada_thermal_sensor {
136 struct armada_thermal_priv *priv;
140 static void armadaxp_init(struct platform_device *pdev,
141 struct armada_thermal_priv *priv)
143 struct armada_thermal_data *data = priv->data;
146 regmap_read(priv->syscon, data->syscon_control1_off, ®);
147 reg |= PMU_TDC0_OTF_CAL_MASK;
149 /* Reference calibration value */
150 reg &= ~PMU_TDC0_REF_CAL_CNT_MASK;
151 reg |= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS);
153 /* Reset the sensor */
154 reg |= PMU_TDC0_SW_RST_MASK;
156 regmap_write(priv->syscon, data->syscon_control1_off, reg);
158 reg &= ~PMU_TDC0_SW_RST_MASK;
159 regmap_write(priv->syscon, data->syscon_control1_off, reg);
161 /* Enable the sensor */
162 regmap_read(priv->syscon, data->syscon_status_off, ®);
163 reg &= ~PMU_TM_DISABLE_MASK;
164 regmap_write(priv->syscon, data->syscon_status_off, reg);
167 static void armada370_init(struct platform_device *pdev,
168 struct armada_thermal_priv *priv)
170 struct armada_thermal_data *data = priv->data;
173 regmap_read(priv->syscon, data->syscon_control1_off, ®);
174 reg |= PMU_TDC0_OTF_CAL_MASK;
176 /* Reference calibration value */
177 reg &= ~PMU_TDC0_REF_CAL_CNT_MASK;
178 reg |= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS);
180 /* Reset the sensor */
181 reg &= ~PMU_TDC0_START_CAL_MASK;
183 regmap_write(priv->syscon, data->syscon_control1_off, reg);
188 static void armada375_init(struct platform_device *pdev,
189 struct armada_thermal_priv *priv)
191 struct armada_thermal_data *data = priv->data;
194 regmap_read(priv->syscon, data->syscon_control1_off, ®);
195 reg &= ~(A375_UNIT_CONTROL_MASK << A375_UNIT_CONTROL_SHIFT);
196 reg &= ~A375_READOUT_INVERT;
197 reg &= ~A375_HW_RESETn;
198 regmap_write(priv->syscon, data->syscon_control1_off, reg);
202 reg |= A375_HW_RESETn;
203 regmap_write(priv->syscon, data->syscon_control1_off, reg);
208 static int armada_wait_sensor_validity(struct armada_thermal_priv *priv)
212 return regmap_read_poll_timeout(priv->syscon,
213 priv->data->syscon_status_off, reg,
214 reg & priv->data->is_valid_bit,
215 STATUS_POLL_PERIOD_US,
216 STATUS_POLL_TIMEOUT_US);
219 static void armada380_init(struct platform_device *pdev,
220 struct armada_thermal_priv *priv)
222 struct armada_thermal_data *data = priv->data;
225 /* Disable the HW/SW reset */
226 regmap_read(priv->syscon, data->syscon_control1_off, ®);
227 reg |= CONTROL1_EXT_TSEN_HW_RESETn;
228 reg &= ~CONTROL1_EXT_TSEN_SW_RESET;
229 regmap_write(priv->syscon, data->syscon_control1_off, reg);
231 /* Set Tsen Tc Trim to correct default value (errata #132698) */
232 regmap_read(priv->syscon, data->syscon_control0_off, ®);
233 reg &= ~CONTROL0_TSEN_TC_TRIM_MASK;
234 reg |= CONTROL0_TSEN_TC_TRIM_VAL;
235 regmap_write(priv->syscon, data->syscon_control0_off, reg);
238 static void armada_ap806_init(struct platform_device *pdev,
239 struct armada_thermal_priv *priv)
241 struct armada_thermal_data *data = priv->data;
244 regmap_read(priv->syscon, data->syscon_control0_off, ®);
245 reg &= ~CONTROL0_TSEN_RESET;
246 reg |= CONTROL0_TSEN_START | CONTROL0_TSEN_ENABLE;
248 /* Sample every ~2ms */
249 reg |= CONTROL0_TSEN_OSR_MAX << CONTROL0_TSEN_OSR_SHIFT;
251 /* Enable average (2 samples by default) */
252 reg &= ~CONTROL0_TSEN_AVG_BYPASS;
254 regmap_write(priv->syscon, data->syscon_control0_off, reg);
257 static void armada_cp110_init(struct platform_device *pdev,
258 struct armada_thermal_priv *priv)
260 struct armada_thermal_data *data = priv->data;
263 armada380_init(pdev, priv);
265 /* Sample every ~2ms */
266 regmap_read(priv->syscon, data->syscon_control0_off, ®);
267 reg |= CONTROL0_TSEN_OSR_MAX << CONTROL0_TSEN_OSR_SHIFT;
268 regmap_write(priv->syscon, data->syscon_control0_off, reg);
270 /* Average the output value over 2^1 = 2 samples */
271 regmap_read(priv->syscon, data->syscon_control1_off, ®);
272 reg &= ~CONTROL1_TSEN_AVG_MASK;
274 regmap_write(priv->syscon, data->syscon_control1_off, reg);
277 static bool armada_is_valid(struct armada_thermal_priv *priv)
281 if (!priv->data->is_valid_bit)
284 regmap_read(priv->syscon, priv->data->syscon_status_off, ®);
286 return reg & priv->data->is_valid_bit;
289 static void armada_enable_overheat_interrupt(struct armada_thermal_priv *priv)
291 struct armada_thermal_data *data = priv->data;
294 /* Clear DFX temperature IRQ cause */
295 regmap_read(priv->syscon, data->dfx_irq_cause_off, ®);
297 /* Enable DFX Temperature IRQ */
298 regmap_read(priv->syscon, data->dfx_irq_mask_off, ®);
299 reg |= data->dfx_overheat_irq;
300 regmap_write(priv->syscon, data->dfx_irq_mask_off, reg);
302 /* Enable DFX server IRQ */
303 regmap_read(priv->syscon, data->dfx_server_irq_mask_off, ®);
304 reg |= data->dfx_server_irq_en;
305 regmap_write(priv->syscon, data->dfx_server_irq_mask_off, reg);
307 /* Enable overheat interrupt */
308 regmap_read(priv->syscon, data->syscon_control1_off, ®);
309 reg |= CONTROL1_TSEN_INT_EN;
310 regmap_write(priv->syscon, data->syscon_control1_off, reg);
313 static void __maybe_unused
314 armada_disable_overheat_interrupt(struct armada_thermal_priv *priv)
316 struct armada_thermal_data *data = priv->data;
319 regmap_read(priv->syscon, data->syscon_control1_off, ®);
320 reg &= ~CONTROL1_TSEN_INT_EN;
321 regmap_write(priv->syscon, data->syscon_control1_off, reg);
324 /* There is currently no board with more than one sensor per channel */
325 static int armada_select_channel(struct armada_thermal_priv *priv, int channel)
327 struct armada_thermal_data *data = priv->data;
330 if (channel < 0 || channel > priv->data->cpu_nr)
333 if (priv->current_channel == channel)
336 /* Stop the measurements */
337 regmap_read(priv->syscon, data->syscon_control0_off, &ctrl0);
338 ctrl0 &= ~CONTROL0_TSEN_START;
339 regmap_write(priv->syscon, data->syscon_control0_off, ctrl0);
341 /* Reset the mode, internal sensor will be automatically selected */
342 ctrl0 &= ~(CONTROL0_TSEN_MODE_MASK << CONTROL0_TSEN_MODE_SHIFT);
344 /* Other channels are external and should be selected accordingly */
346 /* Change the mode to external */
347 ctrl0 |= CONTROL0_TSEN_MODE_EXTERNAL <<
348 CONTROL0_TSEN_MODE_SHIFT;
349 /* Select the sensor */
350 ctrl0 &= ~(CONTROL0_TSEN_CHAN_MASK << CONTROL0_TSEN_CHAN_SHIFT);
351 ctrl0 |= (channel - 1) << CONTROL0_TSEN_CHAN_SHIFT;
354 /* Actually set the mode/channel */
355 regmap_write(priv->syscon, data->syscon_control0_off, ctrl0);
356 priv->current_channel = channel;
358 /* Re-start the measurements */
359 ctrl0 |= CONTROL0_TSEN_START;
360 regmap_write(priv->syscon, data->syscon_control0_off, ctrl0);
363 * The IP has a latency of ~15ms, so after updating the selected source,
364 * we must absolutely wait for the sensor validity bit to ensure we read
367 if (armada_wait_sensor_validity(priv)) {
369 "Temperature sensor reading not valid\n");
376 static int armada_read_sensor(struct armada_thermal_priv *priv, int *temp)
381 regmap_read(priv->syscon, priv->data->syscon_status_off, ®);
382 reg = (reg >> priv->data->temp_shift) & priv->data->temp_mask;
383 if (priv->data->signed_sample)
384 /* The most significant bit is the sign bit */
385 sample = sign_extend32(reg, fls(priv->data->temp_mask) - 1);
389 /* Get formula coeficients */
390 b = priv->data->coef_b;
391 m = priv->data->coef_m;
392 div = priv->data->coef_div;
394 if (priv->data->inverted)
395 *temp = div_s64((m * sample) - b, div);
397 *temp = div_s64(b - (m * sample), div);
402 static int armada_get_temp_legacy(struct thermal_zone_device *thermal,
405 struct armada_thermal_priv *priv = thermal->devdata;
409 if (!armada_is_valid(priv)) {
411 "Temperature sensor reading not valid\n");
415 /* Do the actual reading */
416 ret = armada_read_sensor(priv, temp);
421 static struct thermal_zone_device_ops legacy_ops = {
422 .get_temp = armada_get_temp_legacy,
425 static int armada_get_temp(void *_sensor, int *temp)
427 struct armada_thermal_sensor *sensor = _sensor;
428 struct armada_thermal_priv *priv = sensor->priv;
431 mutex_lock(&priv->update_lock);
433 /* Select the desired channel */
434 ret = armada_select_channel(priv, sensor->id);
438 /* Do the actual reading */
439 ret = armada_read_sensor(priv, temp);
444 * Select back the interrupt source channel from which a potential
445 * critical trip point has been set.
447 ret = armada_select_channel(priv, priv->interrupt_source);
450 mutex_unlock(&priv->update_lock);
455 static const struct thermal_zone_of_device_ops of_ops = {
456 .get_temp = armada_get_temp,
459 static unsigned int armada_mc_to_reg_temp(struct armada_thermal_data *data,
460 unsigned int temp_mc)
462 s64 b = data->coef_b;
463 s64 m = data->coef_m;
464 s64 div = data->coef_div;
468 sample = div_s64(((temp_mc * div) + b), m);
470 sample = div_s64((b - (temp_mc * div)), m);
472 return sample & data->temp_mask;
476 * The documentation states:
477 * high/low watermark = threshold +/- 0.4761 * 2^(hysteresis + 2)
478 * which is the mathematical derivation for:
479 * 0x0 <=> 1.9°C, 0x1 <=> 3.8°C, 0x2 <=> 7.6°C, 0x3 <=> 15.2°C
481 static unsigned int hyst_levels_mc[] = {1900, 3800, 7600, 15200};
483 static unsigned int armada_mc_to_reg_hyst(struct armada_thermal_data *data,
484 unsigned int hyst_mc)
489 * We will always take the smallest possible hysteresis to avoid risking
490 * the hardware integrity by enlarging the threshold by +8°C in the
493 for (i = ARRAY_SIZE(hyst_levels_mc) - 1; i > 0; i--)
494 if (hyst_mc >= hyst_levels_mc[i])
497 return i & data->hyst_mask;
500 static void armada_set_overheat_thresholds(struct armada_thermal_priv *priv,
501 int thresh_mc, int hyst_mc)
503 struct armada_thermal_data *data = priv->data;
504 unsigned int threshold = armada_mc_to_reg_temp(data, thresh_mc);
505 unsigned int hysteresis = armada_mc_to_reg_hyst(data, hyst_mc);
508 regmap_read(priv->syscon, data->syscon_control1_off, &ctrl1);
511 if (thresh_mc >= 0) {
512 ctrl1 &= ~(data->temp_mask << data->thresh_shift);
513 ctrl1 |= threshold << data->thresh_shift;
514 priv->current_threshold = thresh_mc;
519 ctrl1 &= ~(data->hyst_mask << data->hyst_shift);
520 ctrl1 |= hysteresis << data->hyst_shift;
521 priv->current_hysteresis = hyst_mc;
524 regmap_write(priv->syscon, data->syscon_control1_off, ctrl1);
527 static irqreturn_t armada_overheat_isr(int irq, void *blob)
530 * Disable the IRQ and continue in thread context (thermal core
531 * notification and temperature monitoring).
533 disable_irq_nosync(irq);
535 return IRQ_WAKE_THREAD;
538 static irqreturn_t armada_overheat_isr_thread(int irq, void *blob)
540 struct armada_thermal_priv *priv = blob;
541 int low_threshold = priv->current_threshold - priv->current_hysteresis;
546 /* Notify the core in thread context */
547 thermal_zone_device_update(priv->overheat_sensor,
548 THERMAL_EVENT_UNSPECIFIED);
551 * The overheat interrupt must be cleared by reading the DFX interrupt
552 * cause _after_ the temperature has fallen down to the low threshold.
553 * Otherwise future interrupts might not be served.
556 msleep(OVERHEAT_INT_POLL_DELAY_MS);
557 mutex_lock(&priv->update_lock);
558 ret = armada_read_sensor(priv, &temperature);
559 mutex_unlock(&priv->update_lock);
562 } while (temperature >= low_threshold);
564 regmap_read(priv->syscon, priv->data->dfx_irq_cause_off, &dummy);
566 /* Notify the thermal core that the temperature is acceptable again */
567 thermal_zone_device_update(priv->overheat_sensor,
568 THERMAL_EVENT_UNSPECIFIED);
576 static const struct armada_thermal_data armadaxp_data = {
577 .init = armadaxp_init,
580 .coef_b = 3153000000ULL,
581 .coef_m = 10000000ULL,
583 .syscon_status_off = 0xb0,
584 .syscon_control1_off = 0x2d0,
587 static const struct armada_thermal_data armada370_data = {
588 .init = armada370_init,
589 .is_valid_bit = BIT(9),
592 .coef_b = 3153000000ULL,
593 .coef_m = 10000000ULL,
595 .syscon_status_off = 0x0,
596 .syscon_control1_off = 0x4,
599 static const struct armada_thermal_data armada375_data = {
600 .init = armada375_init,
601 .is_valid_bit = BIT(10),
604 .coef_b = 3171900000ULL,
605 .coef_m = 10000000ULL,
607 .syscon_status_off = 0x78,
608 .syscon_control0_off = 0x7c,
609 .syscon_control1_off = 0x80,
612 static const struct armada_thermal_data armada380_data = {
613 .init = armada380_init,
614 .is_valid_bit = BIT(10),
617 .coef_b = 1172499100ULL,
618 .coef_m = 2000096ULL,
621 .syscon_control0_off = 0x70,
622 .syscon_control1_off = 0x74,
623 .syscon_status_off = 0x78,
626 static const struct armada_thermal_data armada_ap806_data = {
627 .init = armada_ap806_init,
628 .is_valid_bit = BIT(16),
638 .signed_sample = true,
639 .syscon_control0_off = 0x84,
640 .syscon_control1_off = 0x88,
641 .syscon_status_off = 0x8C,
642 .dfx_irq_cause_off = 0x108,
643 .dfx_irq_mask_off = 0x10C,
644 .dfx_overheat_irq = BIT(22),
645 .dfx_server_irq_mask_off = 0x104,
646 .dfx_server_irq_en = BIT(1),
650 static const struct armada_thermal_data armada_cp110_data = {
651 .init = armada_cp110_init,
652 .is_valid_bit = BIT(10),
658 .coef_b = 1172499100ULL,
659 .coef_m = 2000096ULL,
662 .syscon_control0_off = 0x70,
663 .syscon_control1_off = 0x74,
664 .syscon_status_off = 0x78,
665 .dfx_irq_cause_off = 0x108,
666 .dfx_irq_mask_off = 0x10C,
667 .dfx_overheat_irq = BIT(20),
668 .dfx_server_irq_mask_off = 0x104,
669 .dfx_server_irq_en = BIT(1),
672 static const struct of_device_id armada_thermal_id_table[] = {
674 .compatible = "marvell,armadaxp-thermal",
675 .data = &armadaxp_data,
678 .compatible = "marvell,armada370-thermal",
679 .data = &armada370_data,
682 .compatible = "marvell,armada375-thermal",
683 .data = &armada375_data,
686 .compatible = "marvell,armada380-thermal",
687 .data = &armada380_data,
690 .compatible = "marvell,armada-ap806-thermal",
691 .data = &armada_ap806_data,
694 .compatible = "marvell,armada-cp110-thermal",
695 .data = &armada_cp110_data,
701 MODULE_DEVICE_TABLE(of, armada_thermal_id_table);
703 static const struct regmap_config armada_thermal_regmap_config = {
710 static int armada_thermal_probe_legacy(struct platform_device *pdev,
711 struct armada_thermal_priv *priv)
713 struct armada_thermal_data *data = priv->data;
714 struct resource *res;
717 /* First memory region points towards the status register */
718 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
719 base = devm_ioremap_resource(&pdev->dev, res);
721 return PTR_ERR(base);
724 * Fix up from the old individual DT register specification to
725 * cover all the registers. We do this by adjusting the ioremap()
726 * result, which should be fine as ioremap() deals with pages.
727 * However, validate that we do not cross a page boundary while
728 * making this adjustment.
730 if (((unsigned long)base & ~PAGE_MASK) < data->syscon_status_off)
732 base -= data->syscon_status_off;
734 priv->syscon = devm_regmap_init_mmio(&pdev->dev, base,
735 &armada_thermal_regmap_config);
736 return PTR_ERR_OR_ZERO(priv->syscon);
739 static int armada_thermal_probe_syscon(struct platform_device *pdev,
740 struct armada_thermal_priv *priv)
742 priv->syscon = syscon_node_to_regmap(pdev->dev.parent->of_node);
743 return PTR_ERR_OR_ZERO(priv->syscon);
746 static void armada_set_sane_name(struct platform_device *pdev,
747 struct armada_thermal_priv *priv)
749 const char *name = dev_name(&pdev->dev);
752 if (strlen(name) > THERMAL_NAME_LENGTH) {
754 * When inside a system controller, the device name has the
755 * form: f06f8000.system-controller:ap-thermal so stripping
756 * after the ':' should give us a shorter but meaningful name.
758 name = strrchr(name, ':');
760 name = "armada_thermal";
765 /* Save the name locally */
766 strncpy(priv->zone_name, name, THERMAL_NAME_LENGTH - 1);
767 priv->zone_name[THERMAL_NAME_LENGTH - 1] = '\0';
769 /* Then check there are no '-' or hwmon core will complain */
771 insane_char = strpbrk(priv->zone_name, "-");
774 } while (insane_char);
778 * The IP can manage to trigger interrupts on overheat situation from all the
779 * sensors. However, the interrupt source changes along with the last selected
780 * source (ie. the last read sensor), which is an inconsistent behavior. Avoid
781 * possible glitches by always selecting back only one channel (arbitrarily: the
782 * first in the DT which has a critical trip point). We also disable sensor
783 * switch during overheat situations.
785 static int armada_configure_overheat_int(struct armada_thermal_priv *priv,
786 struct thermal_zone_device *tz,
789 /* Retrieve the critical trip point to enable the overheat interrupt */
790 const struct thermal_trip *trips = of_thermal_get_trip_points(tz);
797 for (i = 0; i < of_thermal_get_ntrips(tz); i++)
798 if (trips[i].type == THERMAL_TRIP_CRITICAL)
801 if (i == of_thermal_get_ntrips(tz))
804 ret = armada_select_channel(priv, sensor_id);
808 armada_set_overheat_thresholds(priv,
809 trips[i].temperature,
810 trips[i].hysteresis);
811 priv->overheat_sensor = tz;
812 priv->interrupt_source = sensor_id;
814 armada_enable_overheat_interrupt(priv);
819 static int armada_thermal_probe(struct platform_device *pdev)
821 struct thermal_zone_device *tz;
822 struct armada_thermal_sensor *sensor;
823 struct armada_drvdata *drvdata;
824 const struct of_device_id *match;
825 struct armada_thermal_priv *priv;
829 match = of_match_device(armada_thermal_id_table, &pdev->dev);
833 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
837 drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
841 priv->dev = &pdev->dev;
842 priv->data = (struct armada_thermal_data *)match->data;
844 mutex_init(&priv->update_lock);
847 * Legacy DT bindings only described "control1" register (also referred
848 * as "control MSB" on old documentation). Then, bindings moved to cover
849 * "control0/control LSB" and "control1/control MSB" registers within
850 * the same resource, which was then of size 8 instead of 4.
852 * The logic of defining sporadic registers is broken. For instance, it
853 * blocked the addition of the overheat interrupt feature that needed
854 * another resource somewhere else in the same memory area. One solution
855 * is to define an overall system controller and put the thermal node
856 * into it, which requires the use of regmaps across all the driver.
858 if (IS_ERR(syscon_node_to_regmap(pdev->dev.parent->of_node))) {
859 /* Ensure device name is correct for the thermal core */
860 armada_set_sane_name(pdev, priv);
862 ret = armada_thermal_probe_legacy(pdev, priv);
866 priv->data->init(pdev, priv);
868 /* Wait the sensors to be valid */
869 armada_wait_sensor_validity(priv);
871 tz = thermal_zone_device_register(priv->zone_name, 0, 0, priv,
872 &legacy_ops, NULL, 0, 0);
875 "Failed to register thermal zone device\n");
879 drvdata->type = LEGACY;
880 drvdata->data.tz = tz;
881 platform_set_drvdata(pdev, drvdata);
886 ret = armada_thermal_probe_syscon(pdev, priv);
890 priv->current_channel = -1;
891 priv->data->init(pdev, priv);
892 drvdata->type = SYSCON;
893 drvdata->data.priv = priv;
894 platform_set_drvdata(pdev, drvdata);
896 irq = platform_get_irq(pdev, 0);
897 if (irq == -EPROBE_DEFER)
900 /* The overheat interrupt feature is not mandatory */
902 ret = devm_request_threaded_irq(&pdev->dev, irq,
904 armada_overheat_isr_thread,
907 dev_err(&pdev->dev, "Cannot request threaded IRQ %d\n",
914 * There is one channel for the IC and one per CPU (if any), each
915 * channel has one sensor.
917 for (sensor_id = 0; sensor_id <= priv->data->cpu_nr; sensor_id++) {
918 sensor = devm_kzalloc(&pdev->dev,
919 sizeof(struct armada_thermal_sensor),
924 /* Register the sensor */
926 sensor->id = sensor_id;
927 tz = devm_thermal_zone_of_sensor_register(&pdev->dev,
931 dev_info(&pdev->dev, "Thermal sensor %d unavailable\n",
933 devm_kfree(&pdev->dev, sensor);
938 * The first channel that has a critical trip point registered
939 * in the DT will serve as interrupt source. Others possible
940 * critical trip points will simply be ignored by the driver.
942 if (irq > 0 && !priv->overheat_sensor)
943 armada_configure_overheat_int(priv, tz, sensor->id);
946 /* Just complain if no overheat interrupt was set up */
947 if (!priv->overheat_sensor)
948 dev_warn(&pdev->dev, "Overheat interrupt not available\n");
953 static int armada_thermal_exit(struct platform_device *pdev)
955 struct armada_drvdata *drvdata = platform_get_drvdata(pdev);
957 if (drvdata->type == LEGACY)
958 thermal_zone_device_unregister(drvdata->data.tz);
963 static struct platform_driver armada_thermal_driver = {
964 .probe = armada_thermal_probe,
965 .remove = armada_thermal_exit,
967 .name = "armada_thermal",
968 .of_match_table = armada_thermal_id_table,
972 module_platform_driver(armada_thermal_driver);
974 MODULE_AUTHOR("Ezequiel Garcia <ezequiel.garcia@free-electrons.com>");
975 MODULE_DESCRIPTION("Marvell EBU Armada SoCs thermal driver");
976 MODULE_LICENSE("GPL v2");