1 #include <linux/delay.h>
2 #include <linux/vmalloc.h>
7 #include "vb_setmode.h"
9 static const unsigned short XGINew_DDRDRAM_TYPE340[4][2] = {
15 static const unsigned short XGINew_DDRDRAM_TYPE20[12][2] = {
29 #define XGIFB_ROM_SIZE 65536
32 XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
33 struct vb_device_info *pVBInfo)
35 unsigned char data, temp;
37 if (HwDeviceExtension->jChipType < XG20) {
38 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
40 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
43 } else if (HwDeviceExtension->jChipType == XG27) {
44 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
45 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
46 if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08))
51 } else if (HwDeviceExtension->jChipType == XG21) {
52 /* Independent GPIO control */
53 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
54 usleep_range(800, 1800);
55 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
56 /* GPIOF 0:DVI 1:DVO */
57 data = xgifb_reg_get(pVBInfo->P3d4, 0x48);
60 * for current XG20 & XG21, GPIOH is floating, driver will
64 data &= 0x01; /* 1=DDRII, 0=DDR */
65 /* ~HOTPLUG_SUPPORT */
66 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
69 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
77 static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
78 struct vb_device_info *pVBInfo)
80 xgifb_reg_set(P3c4, 0x18, 0x01);
81 xgifb_reg_set(P3c4, 0x19, 0x20);
82 xgifb_reg_set(P3c4, 0x16, 0x00);
83 xgifb_reg_set(P3c4, 0x16, 0x80);
85 usleep_range(3, 1003);
86 xgifb_reg_set(P3c4, 0x18, 0x00);
87 xgifb_reg_set(P3c4, 0x19, 0x20);
88 xgifb_reg_set(P3c4, 0x16, 0x00);
89 xgifb_reg_set(P3c4, 0x16, 0x80);
91 usleep_range(60, 1060);
92 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
93 xgifb_reg_set(P3c4, 0x19, 0x01);
94 xgifb_reg_set(P3c4, 0x16, 0x03);
95 xgifb_reg_set(P3c4, 0x16, 0x83);
96 usleep_range(1, 1001);
97 xgifb_reg_set(P3c4, 0x1B, 0x03);
98 usleep_range(500, 1500);
99 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
100 xgifb_reg_set(P3c4, 0x19, 0x00);
101 xgifb_reg_set(P3c4, 0x16, 0x03);
102 xgifb_reg_set(P3c4, 0x16, 0x83);
103 xgifb_reg_set(P3c4, 0x1B, 0x00);
106 static void XGINew_SetMemoryClock(struct vb_device_info *pVBInfo)
108 xgifb_reg_set(pVBInfo->P3c4,
110 pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
111 xgifb_reg_set(pVBInfo->P3c4,
113 pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
114 xgifb_reg_set(pVBInfo->P3c4,
116 pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
118 xgifb_reg_set(pVBInfo->P3c4,
120 XGI340_ECLKData[pVBInfo->ram_type].SR2E);
121 xgifb_reg_set(pVBInfo->P3c4,
123 XGI340_ECLKData[pVBInfo->ram_type].SR2F);
124 xgifb_reg_set(pVBInfo->P3c4,
126 XGI340_ECLKData[pVBInfo->ram_type].SR30);
129 static void XGINew_DDRII_Bootup_XG27(
130 struct xgi_hw_device_info *HwDeviceExtension,
131 unsigned long P3c4, struct vb_device_info *pVBInfo)
133 unsigned long P3d4 = P3c4 + 0x10;
135 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
136 XGINew_SetMemoryClock(pVBInfo);
138 /* Set Double Frequency */
139 xgifb_reg_set(P3d4, 0x97, pVBInfo->XGINew_CR97); /* CR97 */
141 usleep_range(200, 1200);
143 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
144 xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
145 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
146 usleep_range(15, 1015);
147 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
148 usleep_range(15, 1015);
150 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
151 xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
152 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
153 usleep_range(15, 1015);
154 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
155 usleep_range(15, 1015);
157 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
158 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
159 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
160 usleep_range(30, 1030);
161 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
162 usleep_range(15, 1015);
164 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
165 xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
166 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
167 usleep_range(30, 1030);
168 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
169 xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
171 xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
172 usleep_range(60, 1060);
173 xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
175 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
176 xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
177 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
179 usleep_range(30, 1030);
180 xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
181 usleep_range(15, 1015);
183 xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
184 xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
185 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
186 usleep_range(30, 1030);
187 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
188 usleep_range(15, 1015);
190 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
191 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
192 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
193 usleep_range(30, 1030);
194 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
195 usleep_range(15, 1015);
197 /* Set SR1B refresh control 000:close; 010:open */
198 xgifb_reg_set(P3c4, 0x1B, 0x04);
199 usleep_range(200, 1200);
202 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
204 struct vb_device_info *pVBInfo)
206 unsigned long P3d4 = P3c4 + 0x10;
208 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
209 XGINew_SetMemoryClock(pVBInfo);
211 xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
213 usleep_range(200, 1200);
214 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
215 xgifb_reg_set(P3c4, 0x19, 0x80);
216 xgifb_reg_set(P3c4, 0x16, 0x05);
217 xgifb_reg_set(P3c4, 0x16, 0x85);
219 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
220 xgifb_reg_set(P3c4, 0x19, 0xC0);
221 xgifb_reg_set(P3c4, 0x16, 0x05);
222 xgifb_reg_set(P3c4, 0x16, 0x85);
224 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
225 xgifb_reg_set(P3c4, 0x19, 0x40);
226 xgifb_reg_set(P3c4, 0x16, 0x05);
227 xgifb_reg_set(P3c4, 0x16, 0x85);
229 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
230 xgifb_reg_set(P3c4, 0x19, 0x02);
231 xgifb_reg_set(P3c4, 0x16, 0x05);
232 xgifb_reg_set(P3c4, 0x16, 0x85);
234 usleep_range(15, 1015);
235 xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
236 usleep_range(30, 1030);
237 xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
238 usleep_range(100, 1100);
240 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
241 xgifb_reg_set(P3c4, 0x19, 0x00);
242 xgifb_reg_set(P3c4, 0x16, 0x05);
243 xgifb_reg_set(P3c4, 0x16, 0x85);
245 usleep_range(200, 1200);
248 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
249 struct vb_device_info *pVBInfo)
251 xgifb_reg_set(P3c4, 0x18, 0x01);
252 xgifb_reg_set(P3c4, 0x19, 0x40);
253 xgifb_reg_set(P3c4, 0x16, 0x00);
254 xgifb_reg_set(P3c4, 0x16, 0x80);
255 usleep_range(60, 1060);
257 xgifb_reg_set(P3c4, 0x18, 0x00);
258 xgifb_reg_set(P3c4, 0x19, 0x40);
259 xgifb_reg_set(P3c4, 0x16, 0x00);
260 xgifb_reg_set(P3c4, 0x16, 0x80);
261 usleep_range(60, 1060);
262 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
263 xgifb_reg_set(P3c4, 0x19, 0x01);
264 xgifb_reg_set(P3c4, 0x16, 0x03);
265 xgifb_reg_set(P3c4, 0x16, 0x83);
266 usleep_range(1, 1001);
267 xgifb_reg_set(P3c4, 0x1B, 0x03);
268 usleep_range(500, 1500);
269 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
270 xgifb_reg_set(P3c4, 0x19, 0x00);
271 xgifb_reg_set(P3c4, 0x16, 0x03);
272 xgifb_reg_set(P3c4, 0x16, 0x83);
273 xgifb_reg_set(P3c4, 0x1B, 0x00);
276 static void XGINew_DDR1x_DefaultRegister(
277 struct xgi_hw_device_info *HwDeviceExtension,
278 unsigned long Port, struct vb_device_info *pVBInfo)
280 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
282 if (HwDeviceExtension->jChipType >= XG20) {
283 XGINew_SetMemoryClock(pVBInfo);
286 pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
289 pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
292 pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
294 xgifb_reg_set(P3d4, 0x98, 0x01);
295 xgifb_reg_set(P3d4, 0x9A, 0x02);
297 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
299 XGINew_SetMemoryClock(pVBInfo);
301 switch (HwDeviceExtension->jChipType) {
306 pVBInfo->CR40[11][pVBInfo->ram_type]);
310 pVBInfo->CR40[12][pVBInfo->ram_type]);
314 pVBInfo->CR40[13][pVBInfo->ram_type]);
317 xgifb_reg_set(P3d4, 0x82, 0x88);
318 xgifb_reg_set(P3d4, 0x86, 0x00);
319 /* Insert read command for delay */
320 xgifb_reg_get(P3d4, 0x86);
321 xgifb_reg_set(P3d4, 0x86, 0x88);
322 xgifb_reg_get(P3d4, 0x86);
325 pVBInfo->CR40[13][pVBInfo->ram_type]);
326 xgifb_reg_set(P3d4, 0x82, 0x77);
327 xgifb_reg_set(P3d4, 0x85, 0x00);
329 /* Insert read command for delay */
330 xgifb_reg_get(P3d4, 0x85);
331 xgifb_reg_set(P3d4, 0x85, 0x88);
333 /* Insert read command for delay */
334 xgifb_reg_get(P3d4, 0x85);
338 pVBInfo->CR40[12][pVBInfo->ram_type]);
342 pVBInfo->CR40[11][pVBInfo->ram_type]);
346 xgifb_reg_set(P3d4, 0x97, 0x00);
347 xgifb_reg_set(P3d4, 0x98, 0x01);
348 xgifb_reg_set(P3d4, 0x9A, 0x02);
349 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
353 static void XGINew_DDR2_DefaultRegister(
354 struct xgi_hw_device_info *HwDeviceExtension,
355 unsigned long Port, struct vb_device_info *pVBInfo)
357 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
359 * keep following setting sequence, each setting in
360 * the same reg insert idle
362 xgifb_reg_set(P3d4, 0x82, 0x77);
363 xgifb_reg_set(P3d4, 0x86, 0x00);
364 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
365 xgifb_reg_set(P3d4, 0x86, 0x88);
366 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
368 xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
369 xgifb_reg_set(P3d4, 0x82, 0x77);
370 xgifb_reg_set(P3d4, 0x85, 0x00);
371 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
372 xgifb_reg_set(P3d4, 0x85, 0x88);
373 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
376 pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
377 if (HwDeviceExtension->jChipType == XG27)
379 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
381 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
383 xgifb_reg_set(P3d4, 0x98, 0x01);
384 xgifb_reg_set(P3d4, 0x9A, 0x02);
385 if (HwDeviceExtension->jChipType == XG27)
386 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
388 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
391 static void XGI_SetDRAM_Helper(unsigned long P3d4, u8 seed, u8 temp2, u8 reg,
392 u8 shift_factor, u8 mask1, u8 mask2)
396 for (j = 0; j < 4; j++) {
397 temp2 |= (((seed >> (2 * j)) & 0x03) << shift_factor);
398 xgifb_reg_set(P3d4, reg, temp2);
399 xgifb_reg_get(P3d4, reg);
405 static void XGINew_SetDRAMDefaultRegister340(
406 struct xgi_hw_device_info *HwDeviceExtension,
407 unsigned long Port, struct vb_device_info *pVBInfo)
409 unsigned char temp, temp1, temp2, temp3, j, k;
411 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
413 xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
414 xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
415 xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
416 xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
418 /* CR6B DQS fine tune delay */
420 XGI_SetDRAM_Helper(P3d4, temp, 0, 0x6B, 2, 0xF0, 0x10);
422 /* CR6E DQM fine tune delay */
423 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6E, 2, 0xF0, 0x10);
426 for (k = 0; k < 4; k++) {
427 /* CR6E_D[1:0] select channel */
428 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
429 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6F, 0, 0xF8, 0x08);
435 pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
438 pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
441 /* CR89 terminator type select */
442 XGI_SetDRAM_Helper(P3d4, 0, temp2, 0x89, 0, 0xF0, 0x10);
447 xgifb_reg_set(P3d4, 0x89, temp2);
449 temp = pVBInfo->CR40[3][pVBInfo->ram_type];
451 temp2 = (temp >> 4) & 0x07;
453 xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
454 xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
455 xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
458 pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
460 if (HwDeviceExtension->jChipType == XG27)
461 xgifb_reg_set(P3d4, 0x8F, XG27_CR8F); /* CR8F */
463 for (j = 0; j <= 6; j++) /* CR90 - CR96 */
464 xgifb_reg_set(P3d4, (0x90 + j),
465 pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
467 for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
468 xgifb_reg_set(P3d4, (0xC3 + j),
469 pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
471 for (j = 0; j < 2; j++) /* CR8A - CR8B */
472 xgifb_reg_set(P3d4, (0x8A + j),
473 pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
475 if (HwDeviceExtension->jChipType == XG42)
476 xgifb_reg_set(P3d4, 0x8C, 0x87);
480 pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
482 xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
483 xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
484 xgifb_reg_set(P3d4, 0xCF, XG40_CRCF); /* CRCF */
485 if (pVBInfo->ram_type) {
486 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
487 if (HwDeviceExtension->jChipType == XG27)
488 xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
491 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
493 xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
495 temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
497 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
499 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
500 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
502 xgifb_reg_set(P3c4, 0x1B, 0x03); /* SR1B */
505 static unsigned short XGINew_SetDRAMSize20Reg(
506 unsigned short dram_size,
507 struct vb_device_info *pVBInfo)
509 unsigned short data = 0, memsize = 0;
511 unsigned char ChannelNo;
513 RankSize = dram_size * pVBInfo->ram_bus / 8;
514 data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
522 if (pVBInfo->ram_channel == 3)
525 ChannelNo = pVBInfo->ram_channel;
527 if (ChannelNo * RankSize <= 256) {
528 while ((RankSize >>= 1) > 0)
533 /* Fix DRAM Sizing Error */
534 xgifb_reg_set(pVBInfo->P3c4,
536 (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
538 usleep_range(15, 1015);
543 static int XGINew_ReadWriteRest(unsigned short StopAddr,
544 unsigned short StartAddr,
545 struct vb_device_info *pVBInfo)
548 unsigned long Position = 0;
549 void __iomem *fbaddr = pVBInfo->FBAddr;
551 writel(Position, fbaddr + Position);
553 for (i = StartAddr; i <= StopAddr; i++) {
555 writel(Position, fbaddr + Position);
558 /* Fix #1759 Memory Size error in Multi-Adapter. */
559 usleep_range(500, 1500);
563 if (readl(fbaddr + Position) != Position)
566 for (i = StartAddr; i <= StopAddr; i++) {
568 if (readl(fbaddr + Position) != Position)
574 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
578 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
580 if ((data & 0x10) == 0) {
581 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
582 data = (data & 0x02) >> 1;
588 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
589 struct vb_device_info *pVBInfo)
593 switch (HwDeviceExtension->jChipType) {
596 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
598 pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
600 if (data == 0) { /* Single_32_16 */
602 if ((HwDeviceExtension->ulVideoMemorySize - 1)
604 pVBInfo->ram_bus = 32; /* 32 bits */
605 /* 22bit + 2 rank + 32bit */
606 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
607 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
608 usleep_range(15, 1015);
610 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
613 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
615 /* 22bit + 1 rank + 32bit */
616 xgifb_reg_set(pVBInfo->P3c4,
619 xgifb_reg_set(pVBInfo->P3c4,
622 usleep_range(15, 1015);
624 if (XGINew_ReadWriteRest(23,
631 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
633 pVBInfo->ram_bus = 16; /* 16 bits */
634 /* 22bit + 2 rank + 16bit */
635 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
636 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
637 usleep_range(15, 1015);
639 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
641 xgifb_reg_set(pVBInfo->P3c4,
644 usleep_range(15, 1015);
647 } else { /* Dual_16_8 */
648 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
650 pVBInfo->ram_bus = 16; /* 16 bits */
651 /* (0x31:12x8x2) 22bit + 2 rank */
652 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
653 /* 0x41:16Mx16 bit */
654 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
655 usleep_range(15, 1015);
657 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
660 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
662 /* (0x31:12x8x2) 22bit + 1 rank */
663 xgifb_reg_set(pVBInfo->P3c4,
667 xgifb_reg_set(pVBInfo->P3c4,
670 usleep_range(15, 1015);
672 if (XGINew_ReadWriteRest(22,
679 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
681 pVBInfo->ram_bus = 8; /* 8 bits */
682 /* (0x31:12x8x2) 22bit + 2 rank */
683 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
685 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
686 usleep_range(15, 1015);
688 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
691 /* (0x31:12x8x2) 22bit + 1 rank */
692 xgifb_reg_set(pVBInfo->P3c4,
695 usleep_range(15, 1015);
701 pVBInfo->ram_bus = 16; /* 16 bits */
702 pVBInfo->ram_channel = 1; /* Single channel */
703 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit */
707 * XG42 SR14 D[3] Reserve
708 * D[2] = 1, Dual Channel
709 * = 0, Single Channel
711 * It's Different from Other XG40 Series.
713 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
714 pVBInfo->ram_bus = 32; /* 32 bits */
715 pVBInfo->ram_channel = 2; /* 2 Channel */
716 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
717 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
719 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
722 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
723 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
724 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
727 pVBInfo->ram_channel = 1; /* Single Channel */
728 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
729 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
731 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
733 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
734 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
736 pVBInfo->ram_bus = 64; /* 64 bits */
737 pVBInfo->ram_channel = 1; /* 1 channels */
738 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
739 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
741 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
743 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
744 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
751 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
752 pVBInfo->ram_bus = 32; /* 32 bits */
753 pVBInfo->ram_channel = 3;
754 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
755 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
757 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
760 pVBInfo->ram_channel = 2; /* 2 channels */
761 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
763 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
766 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
767 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
769 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
770 pVBInfo->ram_channel = 3; /* 4 channels */
772 pVBInfo->ram_channel = 2; /* 2 channels */
773 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
776 pVBInfo->ram_bus = 64; /* 64 bits */
777 pVBInfo->ram_channel = 2; /* 2 channels */
778 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
779 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
781 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
783 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
784 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
790 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
791 struct vb_device_info *pVBInfo)
794 unsigned short memsize, start_addr;
795 const unsigned short (*dram_table)[2];
797 xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
798 xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
799 XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
801 if (HwDeviceExtension->jChipType >= XG20) {
802 dram_table = XGINew_DDRDRAM_TYPE20;
803 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE20);
806 dram_table = XGINew_DDRDRAM_TYPE340;
807 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE340);
811 for (i = 0; i < size; i++) {
812 /* SetDRAMSizingType */
813 xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, dram_table[i][1]);
814 usleep_range(50, 1050); /* should delay 50 ns */
816 memsize = XGINew_SetDRAMSize20Reg(dram_table[i][0], pVBInfo);
821 memsize += (pVBInfo->ram_channel - 2) + 20;
822 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
823 (unsigned long)(1 << memsize))
826 if (XGINew_ReadWriteRest(memsize, start_addr, pVBInfo) == 1)
832 static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info,
833 struct xgi_hw_device_info *HwDeviceExtension,
834 struct vb_device_info *pVBInfo)
838 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
840 XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e);
842 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
843 /* disable read cache */
844 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short)(data & 0xDF));
845 XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo);
847 XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
848 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
849 /* enable read cache */
850 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short)(data | 0x20));
853 static u8 *xgifb_copy_rom(struct pci_dev *dev, size_t *rom_size)
855 void __iomem *rom_address;
858 rom_address = pci_map_rom(dev, rom_size);
862 rom_copy = vzalloc(XGIFB_ROM_SIZE);
866 *rom_size = min_t(size_t, *rom_size, XGIFB_ROM_SIZE);
867 memcpy_fromio(rom_copy, rom_address, *rom_size);
870 pci_unmap_rom(dev, rom_address);
874 static bool xgifb_read_vbios(struct pci_dev *pdev)
876 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
880 struct XGI21_LVDSCapStruct *lvds;
884 vbios = xgifb_copy_rom(pdev, &vbios_size);
886 dev_err(&pdev->dev, "Video BIOS not available\n");
889 if (vbios_size <= 0x65)
892 * The user can ignore the LVDS bit in the BIOS and force the display
895 if (!(vbios[0x65] & 0x1) &&
896 (!xgifb_info->display2_force ||
897 xgifb_info->display2 != XGIFB_DISP_LCD)) {
901 if (vbios_size <= 0x317)
903 i = vbios[0x316] | (vbios[0x317] << 8);
904 if (vbios_size <= i - 1)
912 /* Read the LVDS table index scratch register set by the BIOS. */
914 entry = xgifb_reg_get(xgifb_info->dev_info.P3d4, 0x36);
918 lvds = &xgifb_info->lvds_data;
919 if (vbios_size <= i + 24)
921 lvds->LVDS_Capability = vbios[i] | (vbios[i + 1] << 8);
922 lvds->LVDSHT = vbios[i + 2] | (vbios[i + 3] << 8);
923 lvds->LVDSVT = vbios[i + 4] | (vbios[i + 5] << 8);
924 lvds->LVDSHDE = vbios[i + 6] | (vbios[i + 7] << 8);
925 lvds->LVDSVDE = vbios[i + 8] | (vbios[i + 9] << 8);
926 lvds->LVDSHFP = vbios[i + 10] | (vbios[i + 11] << 8);
927 lvds->LVDSVFP = vbios[i + 12] | (vbios[i + 13] << 8);
928 lvds->LVDSHSYNC = vbios[i + 14] | (vbios[i + 15] << 8);
929 lvds->LVDSVSYNC = vbios[i + 16] | (vbios[i + 17] << 8);
930 lvds->VCLKData1 = vbios[i + 18];
931 lvds->VCLKData2 = vbios[i + 19];
932 lvds->PSC_S1 = vbios[i + 20];
933 lvds->PSC_S2 = vbios[i + 21];
934 lvds->PSC_S3 = vbios[i + 22];
935 lvds->PSC_S4 = vbios[i + 23];
936 lvds->PSC_S5 = vbios[i + 24];
940 dev_err(&pdev->dev, "Video BIOS corrupted\n");
945 static void XGINew_ChkSenseStatus(struct vb_device_info *pVBInfo)
947 unsigned short tempbx = 0, temp, tempcx, CR3CData;
949 temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
951 if (temp & Monitor1Sense)
952 tempbx |= ActiveCRT1;
955 if (temp & Monitor2Sense)
956 tempbx |= ActiveCRT2;
957 if (temp & TVSense) {
959 if (temp & AVIDEOSense)
960 tempbx |= (ActiveAVideo << 8);
961 if (temp & SVIDEOSense)
962 tempbx |= (ActiveSVideo << 8);
963 if (temp & SCARTSense)
964 tempbx |= (ActiveSCART << 8);
965 if (temp & HiTVSense)
966 tempbx |= (ActiveHiTV << 8);
967 if (temp & YPbPrSense)
968 tempbx |= (ActiveYPbPr << 8);
971 tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
972 tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
974 if (tempbx & tempcx) {
975 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
976 if (!(CR3CData & DisplayDeviceFromCMOS))
983 xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
984 xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
987 static void XGINew_SetModeScratch(struct vb_device_info *pVBInfo)
989 unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
991 temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
992 temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
993 temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
995 if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
996 if (temp & ActiveCRT2)
997 tempcl = SetCRT2ToRAMDAC;
1000 if (temp & ActiveLCD) {
1001 tempcl |= SetCRT2ToLCD;
1002 if (temp & DriverMode) {
1003 if (temp & ActiveTV) {
1004 tempch = SetToLCDA | EnableDualEdge;
1005 temp ^= SetCRT2ToLCD;
1007 if ((temp >> 8) & ActiveAVideo)
1008 tempcl |= SetCRT2ToAVIDEO;
1009 if ((temp >> 8) & ActiveSVideo)
1010 tempcl |= SetCRT2ToSVIDEO;
1011 if ((temp >> 8) & ActiveSCART)
1012 tempcl |= SetCRT2ToSCART;
1014 if (pVBInfo->IF_DEF_HiVision == 1) {
1015 if ((temp >> 8) & ActiveHiTV)
1016 tempcl |= SetCRT2ToHiVision;
1019 if (pVBInfo->IF_DEF_YPbPr == 1) {
1020 if ((temp >> 8) & ActiveYPbPr)
1026 if ((temp >> 8) & ActiveAVideo)
1027 tempcl |= SetCRT2ToAVIDEO;
1028 if ((temp >> 8) & ActiveSVideo)
1029 tempcl |= SetCRT2ToSVIDEO;
1030 if ((temp >> 8) & ActiveSCART)
1031 tempcl |= SetCRT2ToSCART;
1033 if (pVBInfo->IF_DEF_HiVision == 1) {
1034 if ((temp >> 8) & ActiveHiTV)
1035 tempcl |= SetCRT2ToHiVision;
1038 if (pVBInfo->IF_DEF_YPbPr == 1) {
1039 if ((temp >> 8) & ActiveYPbPr)
1044 tempcl |= SetSimuScanMode;
1045 if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) ||
1046 (temp & ActiveTV) ||
1047 (temp & ActiveCRT2)))
1048 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1049 if ((temp & ActiveLCD) && (temp & ActiveTV))
1050 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1051 xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
1053 CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
1054 CR31Data &= ~(SetNotSimuMode >> 8);
1055 if (!(temp & ActiveCRT1))
1056 CR31Data |= (SetNotSimuMode >> 8);
1057 CR31Data &= ~(DisableCRT2Display >> 8);
1058 if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1059 CR31Data |= (DisableCRT2Display >> 8);
1060 xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
1062 CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1063 CR38Data &= ~SetYPbPr;
1065 xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
1068 static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
1070 struct vb_device_info *pVBInfo)
1072 unsigned short temp = HwDeviceExtension->ulCRT2LCDType;
1074 switch (HwDeviceExtension->ulCRT2LCDType) {
1082 temp = 0; /* overwrite used ulCRT2LCDType */
1084 case LCD_UNKNOWN: /* unknown lcd, do nothing */
1087 xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp);
1091 static void XGINew_GetXG21Sense(struct pci_dev *pdev,
1092 struct vb_device_info *pVBInfo)
1094 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1097 if (xgifb_read_vbios(pdev)) { /* For XG21 LVDS */
1098 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1100 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1102 /* Enable GPIOA/B read */
1103 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1104 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1105 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1106 XGINew_SenseLCD(&xgifb_info->hw_info, pVBInfo);
1107 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1108 /* Enable read GPIOF */
1109 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1110 if (xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04)
1111 Temp = 0xA0; /* Only DVO on chip */
1113 Temp = 0x80; /* TMDS on chip */
1114 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, Temp);
1115 /* Disable read GPIOF */
1116 xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1121 static void XGINew_GetXG27Sense(struct vb_device_info *pVBInfo)
1123 unsigned char Temp, bCR4A;
1125 bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1126 /* Enable GPIOA/B/C read */
1127 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1128 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1129 xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1133 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1134 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1136 /* TMDS/DVO setting */
1137 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1139 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1142 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1144 unsigned char CR38, CR4A, temp;
1146 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1147 /* enable GPIOE read */
1148 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1149 CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1151 if ((CR38 & 0xE0) > 0x80) {
1152 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1157 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1162 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1164 unsigned char CR4A, temp;
1166 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1167 /* enable GPIOA/B/C read */
1168 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1169 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1171 temp = ((temp & 0x04) >> 1) | ((~temp) & 0x01);
1173 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1178 static bool xgifb_bridge_is_on(struct vb_device_info *vb_info)
1182 flag = xgifb_reg_get(vb_info->Part4Port, 0x00);
1183 return flag == 1 || flag == 2;
1186 unsigned char XGIInitNew(struct pci_dev *pdev)
1188 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1189 struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
1190 struct vb_device_info VBINF;
1191 struct vb_device_info *pVBInfo = &VBINF;
1192 unsigned char i, temp = 0, temp1;
1194 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1196 if (!pVBInfo->FBAddr) {
1197 dev_dbg(&pdev->dev, "pVBInfo->FBAddr == 0\n");
1201 XGIRegInit(pVBInfo, xgifb_info->vga_base);
1203 outb(0x67, pVBInfo->P3c2);
1205 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1208 xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1210 /* GetXG21Sense (GPIO) */
1211 if (HwDeviceExtension->jChipType == XG21)
1212 XGINew_GetXG21Sense(pdev, pVBInfo);
1214 if (HwDeviceExtension->jChipType == XG27)
1215 XGINew_GetXG27Sense(pVBInfo);
1217 /* Reset Extended register */
1219 for (i = 0x06; i < 0x20; i++)
1220 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1222 for (i = 0x21; i <= 0x27; i++)
1223 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1225 for (i = 0x31; i <= 0x3B; i++)
1226 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1228 /* Auto over driver for XG42 */
1229 if (HwDeviceExtension->jChipType == XG42)
1230 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1232 for (i = 0x79; i <= 0x7C; i++)
1233 xgifb_reg_set(pVBInfo->P3d4, i, 0);
1235 if (HwDeviceExtension->jChipType >= XG20)
1236 xgifb_reg_set(pVBInfo->P3d4, 0x97, pVBInfo->XGINew_CR97);
1238 /* SetDefExt1Regs begin */
1239 xgifb_reg_set(pVBInfo->P3c4, 0x07, XGI330_SR07);
1240 if (HwDeviceExtension->jChipType == XG27) {
1241 xgifb_reg_set(pVBInfo->P3c4, 0x40, XG27_SR40);
1242 xgifb_reg_set(pVBInfo->P3c4, 0x41, XG27_SR41);
1244 xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1245 xgifb_reg_set(pVBInfo->P3c4, 0x1F, XGI330_SR1F);
1246 /* Frame buffer can read/write SR20 */
1247 xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1248 /* H/W request for slow corner chip */
1249 xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1250 if (HwDeviceExtension->jChipType == XG27)
1251 xgifb_reg_set(pVBInfo->P3c4, 0x36, XG27_SR36);
1253 if (HwDeviceExtension->jChipType < XG20) {
1256 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1257 for (i = 0x47; i <= 0x4C; i++)
1258 xgifb_reg_set(pVBInfo->P3d4,
1260 XGI340_AGPReg[i - 0x47]);
1262 for (i = 0x70; i <= 0x71; i++)
1263 xgifb_reg_set(pVBInfo->P3d4,
1265 XGI340_AGPReg[6 + i - 0x70]);
1267 for (i = 0x74; i <= 0x77; i++)
1268 xgifb_reg_set(pVBInfo->P3d4,
1270 XGI340_AGPReg[8 + i - 0x74]);
1272 pci_read_config_dword(pdev, 0x50, &Temp);
1277 xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1281 xgifb_reg_set(pVBInfo->P3c4, 0x23, XGI330_SR23);
1282 xgifb_reg_set(pVBInfo->P3c4, 0x24, XGI330_SR24);
1283 xgifb_reg_set(pVBInfo->P3c4, 0x25, 0);
1285 if (HwDeviceExtension->jChipType < XG20) {
1287 XGI_UnLockCRT2(pVBInfo);
1288 /* disable VideoCapture */
1289 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1290 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1291 /* chk if BCLK>=100MHz */
1292 temp1 = xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1294 xgifb_reg_set(pVBInfo->Part1Port,
1295 0x02, XGI330_CRT2Data_1_2);
1297 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1300 xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1302 if ((HwDeviceExtension->jChipType == XG42) &&
1303 XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1305 xgifb_reg_set(pVBInfo->P3c4,
1307 (XGI330_SR31 & 0x3F) | 0x40);
1308 xgifb_reg_set(pVBInfo->P3c4,
1310 (XGI330_SR32 & 0xFC) | 0x01);
1312 xgifb_reg_set(pVBInfo->P3c4, 0x31, XGI330_SR31);
1313 xgifb_reg_set(pVBInfo->P3c4, 0x32, XGI330_SR32);
1315 xgifb_reg_set(pVBInfo->P3c4, 0x33, XGI330_SR33);
1317 if (HwDeviceExtension->jChipType < XG20) {
1318 if (xgifb_bridge_is_on(pVBInfo)) {
1319 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1320 xgifb_reg_set(pVBInfo->Part4Port,
1321 0x0D, XGI330_CRT2Data_4_D);
1322 xgifb_reg_set(pVBInfo->Part4Port,
1323 0x0E, XGI330_CRT2Data_4_E);
1324 xgifb_reg_set(pVBInfo->Part4Port,
1325 0x10, XGI330_CRT2Data_4_10);
1326 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1327 XGI_LockCRT2(pVBInfo);
1331 XGI_SenseCRT1(pVBInfo);
1333 if (HwDeviceExtension->jChipType == XG21) {
1334 xgifb_reg_and_or(pVBInfo->P3d4,
1337 Monitor1Sense); /* Z9 default has CRT */
1338 temp = GetXG21FPBits(pVBInfo);
1339 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1341 if (HwDeviceExtension->jChipType == XG27) {
1342 xgifb_reg_and_or(pVBInfo->P3d4,
1345 Monitor1Sense); /* Z9 default has CRT */
1346 temp = GetXG27FPBits(pVBInfo);
1347 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1350 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1352 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1356 XGINew_SetDRAMSize_340(xgifb_info, HwDeviceExtension, pVBInfo);
1358 xgifb_reg_set(pVBInfo->P3c4, 0x22, 0xfa);
1359 xgifb_reg_set(pVBInfo->P3c4, 0x21, 0xa3);
1361 XGINew_ChkSenseStatus(pVBInfo);
1362 XGINew_SetModeScratch(pVBInfo);
1364 xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);