1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
10 #include <linux/types.h>
12 /********************************************
14 * Mac eth header length
16 ********************************************/
17 #define MAX_MAC_HDR_LEN 26 /* QOS_MAC_HDR_LEN */
18 #define SUB_MSDU_HEADER_LENGTH 14
19 #define SNAP_HDR_LEN 8
20 #define ETHERNET_HDR_LEN 14
21 #define WORD_ALIGNMENT_PAD 0
23 #define ETH_ETHERNET_HDR_OFFSET (MAX_MAC_HDR_LEN + \
24 SUB_MSDU_HEADER_LENGTH + \
29 #define HOST_HDR_OFFSET 4
30 #define ETHERNET_HDR_LEN 14
32 #define IP_HDR_OFFSET ETHERNET_HDR_LEN
33 #define UDP_HDR_OFFSET (IP_HDR_LEN + IP_HDR_OFFSET)
35 #define UDP_DATA_OFFSET (UDP_HDR_OFFSET + UDP_HDR_LEN)
36 #define ETH_CONFIG_PKT_HDR_LEN UDP_DATA_OFFSET
38 #define ETH_CONFIG_PKT_HDR_OFFSET (ETH_ETHERNET_HDR_OFFSET + \
39 ETH_CONFIG_PKT_HDR_LEN)
41 /********************************************
45 ********************************************/
46 #define WILC_PERIPH_REG_BASE 0x1000
47 #define WILC_CHANGING_VIR_IF 0x108c
48 #define WILC_CHIPID WILC_PERIPH_REG_BASE
49 #define WILC_GLB_RESET_0 (WILC_PERIPH_REG_BASE + 0x400)
50 #define WILC_PIN_MUX_0 (WILC_PERIPH_REG_BASE + 0x408)
51 #define WILC_HOST_TX_CTRL (WILC_PERIPH_REG_BASE + 0x6c)
52 #define WILC_HOST_RX_CTRL_0 (WILC_PERIPH_REG_BASE + 0x70)
53 #define WILC_HOST_RX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x74)
54 #define WILC_HOST_VMM_CTL (WILC_PERIPH_REG_BASE + 0x78)
55 #define WILC_HOST_RX_CTRL (WILC_PERIPH_REG_BASE + 0x80)
56 #define WILC_HOST_RX_EXTRA_SIZE (WILC_PERIPH_REG_BASE + 0x84)
57 #define WILC_HOST_TX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x88)
58 #define WILC_MISC (WILC_PERIPH_REG_BASE + 0x428)
59 #define WILC_INTR_REG_BASE (WILC_PERIPH_REG_BASE + 0xa00)
60 #define WILC_INTR_ENABLE WILC_INTR_REG_BASE
61 #define WILC_INTR2_ENABLE (WILC_INTR_REG_BASE + 4)
63 #define WILC_INTR_POLARITY (WILC_INTR_REG_BASE + 0x10)
64 #define WILC_INTR_TYPE (WILC_INTR_REG_BASE + 0x20)
65 #define WILC_INTR_CLEAR (WILC_INTR_REG_BASE + 0x30)
66 #define WILC_INTR_STATUS (WILC_INTR_REG_BASE + 0x40)
68 #define WILC_VMM_TBL_SIZE 64
69 #define WILC_VMM_TX_TBL_BASE 0x150400
70 #define WILC_VMM_RX_TBL_BASE 0x150500
72 #define WILC_VMM_BASE 0x150000
73 #define WILC_VMM_CORE_CTL WILC_VMM_BASE
74 #define WILC_VMM_TBL_CTL (WILC_VMM_BASE + 0x4)
75 #define WILC_VMM_TBL_ENTRY (WILC_VMM_BASE + 0x8)
76 #define WILC_VMM_TBL0_SIZE (WILC_VMM_BASE + 0xc)
77 #define WILC_VMM_TO_HOST_SIZE (WILC_VMM_BASE + 0x10)
78 #define WILC_VMM_CORE_CFG (WILC_VMM_BASE + 0x14)
79 #define WILC_VMM_TBL_ACTIVE (WILC_VMM_BASE + 040)
80 #define WILC_VMM_TBL_STATUS (WILC_VMM_BASE + 0x44)
82 #define WILC_SPI_REG_BASE 0xe800
83 #define WILC_SPI_CTL WILC_SPI_REG_BASE
84 #define WILC_SPI_MASTER_DMA_ADDR (WILC_SPI_REG_BASE + 0x4)
85 #define WILC_SPI_MASTER_DMA_COUNT (WILC_SPI_REG_BASE + 0x8)
86 #define WILC_SPI_SLAVE_DMA_ADDR (WILC_SPI_REG_BASE + 0xc)
87 #define WILC_SPI_SLAVE_DMA_COUNT (WILC_SPI_REG_BASE + 0x10)
88 #define WILC_SPI_TX_MODE (WILC_SPI_REG_BASE + 0x20)
89 #define WILC_SPI_PROTOCOL_CONFIG (WILC_SPI_REG_BASE + 0x24)
90 #define WILC_SPI_INTR_CTL (WILC_SPI_REG_BASE + 0x2c)
92 #define WILC_SPI_PROTOCOL_OFFSET (WILC_SPI_PROTOCOL_CONFIG - \
95 #define WILC_AHB_DATA_MEM_BASE 0x30000
96 #define WILC_AHB_SHARE_MEM_BASE 0xd0000
98 #define WILC_VMM_TBL_RX_SHADOW_BASE WILC_AHB_SHARE_MEM_BASE
99 #define WILC_VMM_TBL_RX_SHADOW_SIZE 256
101 #define WILC_FW_HOST_COMM 0x13c0
102 #define WILC_GP_REG_0 0x149c
103 #define WILC_GP_REG_1 0x14a0
105 #define WILC_HAVE_SDIO_IRQ_GPIO BIT(0)
106 #define WILC_HAVE_USE_PMU BIT(1)
107 #define WILC_HAVE_SLEEP_CLK_SRC_RTC BIT(2)
108 #define WILC_HAVE_SLEEP_CLK_SRC_XO BIT(3)
109 #define WILC_HAVE_EXT_PA_INV_TX_RX BIT(4)
110 #define WILC_HAVE_LEGACY_RF_SETTINGS BIT(5)
111 #define WILC_HAVE_XTAL_24 BIT(6)
112 #define WILC_HAVE_DISABLE_WILC_UART BIT(7)
113 #define WILC_HAVE_USE_IRQ_AS_HOST_WAKE BIT(8)
115 /********************************************
119 ********************************************/
120 #define WILC_CFG_PKT 1
121 #define WILC_NET_PKT 0
122 #define WILC_MGMT_PKT 2
124 #define WILC_CFG_SET 1
125 #define WILC_CFG_QUERY 0
127 #define WILC_CFG_RSP 1
128 #define WILC_CFG_RSP_STATUS 2
129 #define WILC_CFG_RSP_SCAN 3
131 #define WILC_ABORT_REQ_BIT BIT(31)
133 #define WILC_RX_BUFF_SIZE (96 * 1024)
134 #define WILC_TX_BUFF_SIZE (64 * 1024)
136 #define MODALIAS "WILC_SPI"
137 #define GPIO_NUM 0x44
138 /*******************************************/
139 /* E0 and later Interrupt flags. */
140 /*******************************************/
141 /*******************************************/
142 /* E0 and later Interrupt flags. */
143 /* IRQ Status word */
144 /* 15:0 = DMA count in words. */
151 /*******************************************/
152 #define IRG_FLAGS_OFFSET 16
153 #define IRQ_DMA_WD_CNT_MASK ((1ul << IRG_FLAGS_OFFSET) - 1)
154 #define INT_0 BIT(IRG_FLAGS_OFFSET)
155 #define INT_1 BIT(IRG_FLAGS_OFFSET + 1)
156 #define INT_2 BIT(IRG_FLAGS_OFFSET + 2)
157 #define INT_3 BIT(IRG_FLAGS_OFFSET + 3)
158 #define INT_4 BIT(IRG_FLAGS_OFFSET + 4)
159 #define INT_5 BIT(IRG_FLAGS_OFFSET + 5)
160 #define MAX_NUM_INT 6
162 /*******************************************/
163 /* E0 and later Interrupt flags. */
171 /* 6: Select VMM table 1 */
172 /* 7: Select VMM table 2 */
174 /*******************************************/
175 #define CLR_INT0 BIT(0)
176 #define CLR_INT1 BIT(1)
177 #define CLR_INT2 BIT(2)
178 #define CLR_INT3 BIT(3)
179 #define CLR_INT4 BIT(4)
180 #define CLR_INT5 BIT(5)
181 #define SEL_VMM_TBL0 BIT(6)
182 #define SEL_VMM_TBL1 BIT(7)
183 #define EN_VMM BIT(8)
185 #define DATA_INT_EXT INT_0
186 #define ALL_INT_EXT DATA_INT_EXT
187 #define NUM_INT_EXT 1
189 #define DATA_INT_CLR CLR_INT0
191 #define ENABLE_RX_VMM (SEL_VMM_TBL1 | EN_VMM)
192 #define ENABLE_TX_VMM (SEL_VMM_TBL0 | EN_VMM)
193 /* time for expiring the completion of cfg packets */
194 #define WILC_CFG_PKTS_TIMEOUT msecs_to_jiffies(2000)
196 #define IS_MANAGMEMENT 0x100
197 #define IS_MANAGMEMENT_CALLBACK 0x080
198 #define IS_MGMT_STATUS_SUCCES 0x040
200 #define WILC_WID_TYPE GENMASK(15, 12)
201 #define WILC_VMM_ENTRY_FULL_RETRY 1
202 /********************************************
204 * Tx/Rx Queue Structure
206 ********************************************/
209 struct list_head list;
216 struct wilc_vif *vif;
217 void (*tx_complete_func)(void *priv, int status);
221 struct list_head list;
226 /********************************************
230 ********************************************/
232 struct wilc_hif_func {
233 int (*hif_init)(struct wilc *wilc, bool resume);
234 int (*hif_deinit)(struct wilc *wilc);
235 int (*hif_read_reg)(struct wilc *wilc, u32 addr, u32 *data);
236 int (*hif_write_reg)(struct wilc *wilc, u32 addr, u32 data);
237 int (*hif_block_rx)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
238 int (*hif_block_tx)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
239 int (*hif_read_int)(struct wilc *wilc, u32 *int_status);
240 int (*hif_clear_int_ext)(struct wilc *wilc, u32 val);
241 int (*hif_read_size)(struct wilc *wilc, u32 *size);
242 int (*hif_block_tx_ext)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
243 int (*hif_block_rx_ext)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
244 int (*hif_sync_ext)(struct wilc *wilc, int nint);
245 int (*enable_interrupt)(struct wilc *nic);
246 void (*disable_interrupt)(struct wilc *nic);
249 #define WILC_MAX_CFG_FRAME_SIZE 1468
251 struct tx_complete_data {
257 struct wilc_cfg_cmd_hdr {
261 __le32 driver_handler;
264 struct wilc_cfg_frame {
265 struct wilc_cfg_cmd_hdr hdr;
266 u8 frame[WILC_MAX_CFG_FRAME_SIZE];
269 struct wilc_cfg_rsp {
277 int wilc_wlan_firmware_download(struct wilc *wilc, const u8 *buffer,
279 int wilc_wlan_start(struct wilc *wilc);
280 int wilc_wlan_stop(struct wilc *wilc, struct wilc_vif *vif);
281 int wilc_wlan_txq_add_net_pkt(struct net_device *dev, void *priv, u8 *buffer,
283 void (*tx_complete_fn)(void *, int));
284 int wilc_wlan_handle_txq(struct wilc *wl, u32 *txq_count);
285 void wilc_handle_isr(struct wilc *wilc);
286 void wilc_wlan_cleanup(struct net_device *dev);
287 int wilc_wlan_cfg_set(struct wilc_vif *vif, int start, u16 wid, u8 *buffer,
288 u32 buffer_size, int commit, u32 drv_handler);
289 int wilc_wlan_cfg_get(struct wilc_vif *vif, int start, u16 wid, int commit,
291 int wilc_wlan_txq_add_mgmt_pkt(struct net_device *dev, void *priv, u8 *buffer,
292 u32 buffer_size, void (*func)(void *, int));
293 void wilc_enable_tcp_ack_filter(struct wilc_vif *vif, bool value);
294 int wilc_wlan_get_num_conn_ifcs(struct wilc *wilc);
295 netdev_tx_t wilc_mac_xmit(struct sk_buff *skb, struct net_device *dev);
297 void wilc_wfi_p2p_rx(struct wilc_vif *vif, u8 *buff, u32 size);
298 void host_wakeup_notify(struct wilc *wilc);
299 void host_sleep_notify(struct wilc *wilc);
300 void chip_allow_sleep(struct wilc *wilc);
301 void chip_wakeup(struct wilc *wilc);
302 int wilc_send_config_pkt(struct wilc_vif *vif, u8 mode, struct wid *wids,
304 int wilc_wlan_init(struct net_device *dev);
305 u32 wilc_get_chipid(struct wilc *wilc, bool update);