drivers/staging/wfx/hif_api_general.h

   1 /* SPDX-License-Identifier: Apache-2.0 */
   2 /*
   3  * WFx hardware interface definitions
   4  *
   5  * Copyright (c) 2018-2020, Silicon Laboratories Inc.
   6  */
   7
   8 #ifndef WFX_HIF_API_GENERAL_H
   9 #define WFX_HIF_API_GENERAL_H
  10
  11 #define HIF_ID_IS_INDICATION      0x80
  12 #define HIF_COUNTER_MAX           7
  13
  14 struct hif_msg {
  15         __le16 len;
  16         u8     id;
  17         u8     reserved:1;
  18         u8     interface:2;
  19         u8     seqnum:3;
  20         u8     encrypted:2;
  21         u8     body[];
  22 } __packed;
  23
  24 enum hif_general_requests_ids {
  25         HIF_REQ_ID_CONFIGURATION        = 0x09,
  26         HIF_REQ_ID_CONTROL_GPIO         = 0x26,
  27         HIF_REQ_ID_SET_SL_MAC_KEY       = 0x27,
  28         HIF_REQ_ID_SL_EXCHANGE_PUB_KEYS = 0x28,
  29         HIF_REQ_ID_SL_CONFIGURE         = 0x29,
  30         HIF_REQ_ID_PREVENT_ROLLBACK     = 0x2a,
  31         HIF_REQ_ID_PTA_SETTINGS         = 0x2b,
  32         HIF_REQ_ID_PTA_PRIORITY         = 0x2c,
  33         HIF_REQ_ID_PTA_STATE            = 0x2d,
  34         HIF_REQ_ID_SHUT_DOWN            = 0x32,
  35 };
  36
  37 enum hif_general_confirmations_ids {
  38         HIF_CNF_ID_CONFIGURATION        = 0x09,
  39         HIF_CNF_ID_CONTROL_GPIO         = 0x26,
  40         HIF_CNF_ID_SET_SL_MAC_KEY       = 0x27,
  41         HIF_CNF_ID_SL_EXCHANGE_PUB_KEYS = 0x28,
  42         HIF_CNF_ID_SL_CONFIGURE         = 0x29,
  43         HIF_CNF_ID_PREVENT_ROLLBACK     = 0x2a,
  44         HIF_CNF_ID_PTA_SETTINGS         = 0x2b,
  45         HIF_CNF_ID_PTA_PRIORITY         = 0x2c,
  46         HIF_CNF_ID_PTA_STATE            = 0x2d,
  47         HIF_CNF_ID_SHUT_DOWN            = 0x32,
  48 };
  49
  50 enum hif_general_indications_ids {
  51         HIF_IND_ID_EXCEPTION            = 0xe0,
  52         HIF_IND_ID_STARTUP              = 0xe1,
  53         HIF_IND_ID_WAKEUP               = 0xe2,
  54         HIF_IND_ID_GENERIC              = 0xe3,
  55         HIF_IND_ID_ERROR                = 0xe4,
  56         HIF_IND_ID_SL_EXCHANGE_PUB_KEYS = 0xe5
  57 };
  58
  59 #define HIF_STATUS_SUCCESS                         (cpu_to_le32(0x0000))
  60 #define HIF_STATUS_FAIL                            (cpu_to_le32(0x0001))
  61 #define HIF_STATUS_INVALID_PARAMETER               (cpu_to_le32(0x0002))
  62 #define HIF_STATUS_WARNING                         (cpu_to_le32(0x0003))
  63 #define HIF_STATUS_UNKNOWN_REQUEST                 (cpu_to_le32(0x0004))
  64 #define HIF_STATUS_RX_FAIL_DECRYPT                 (cpu_to_le32(0x0010))
  65 #define HIF_STATUS_RX_FAIL_MIC                     (cpu_to_le32(0x0011))
  66 #define HIF_STATUS_RX_FAIL_NO_KEY                  (cpu_to_le32(0x0012))
  67 #define HIF_STATUS_TX_FAIL_RETRIES                 (cpu_to_le32(0x0013))
  68 #define HIF_STATUS_TX_FAIL_TIMEOUT                 (cpu_to_le32(0x0014))
  69 #define HIF_STATUS_TX_FAIL_REQUEUE                 (cpu_to_le32(0x0015))
  70 #define HIF_STATUS_REFUSED                         (cpu_to_le32(0x0016))
  71 #define HIF_STATUS_BUSY                            (cpu_to_le32(0x0017))
  72 #define HIF_STATUS_SLK_SET_KEY_SUCCESS             (cpu_to_le32(0x005A))
  73 #define HIF_STATUS_SLK_SET_KEY_ALREADY_BURNED      (cpu_to_le32(0x006B))
  74 #define HIF_STATUS_SLK_SET_KEY_DISALLOWED_MODE     (cpu_to_le32(0x007C))
  75 #define HIF_STATUS_SLK_SET_KEY_UNKNOWN_MODE        (cpu_to_le32(0x008D))
  76 #define HIF_STATUS_SLK_NEGO_SUCCESS                (cpu_to_le32(0x009E))
  77 #define HIF_STATUS_SLK_NEGO_FAILED                 (cpu_to_le32(0x00AF))
  78 #define HIF_STATUS_ROLLBACK_SUCCESS                (cpu_to_le32(0x1234))
  79 #define HIF_STATUS_ROLLBACK_FAIL                   (cpu_to_le32(0x1256))
  80
  81 enum hif_api_rate_index {
  82         API_RATE_INDEX_B_1MBPS     = 0,
  83         API_RATE_INDEX_B_2MBPS     = 1,
  84         API_RATE_INDEX_B_5P5MBPS   = 2,
  85         API_RATE_INDEX_B_11MBPS    = 3,
  86         API_RATE_INDEX_PBCC_22MBPS = 4,
  87         API_RATE_INDEX_PBCC_33MBPS = 5,
  88         API_RATE_INDEX_G_6MBPS     = 6,
  89         API_RATE_INDEX_G_9MBPS     = 7,
  90         API_RATE_INDEX_G_12MBPS    = 8,
  91         API_RATE_INDEX_G_18MBPS    = 9,
  92         API_RATE_INDEX_G_24MBPS    = 10,
  93         API_RATE_INDEX_G_36MBPS    = 11,
  94         API_RATE_INDEX_G_48MBPS    = 12,
  95         API_RATE_INDEX_G_54MBPS    = 13,
  96         API_RATE_INDEX_N_6P5MBPS   = 14,
  97         API_RATE_INDEX_N_13MBPS    = 15,
  98         API_RATE_INDEX_N_19P5MBPS  = 16,
  99         API_RATE_INDEX_N_26MBPS    = 17,
 100         API_RATE_INDEX_N_39MBPS    = 18,
 101         API_RATE_INDEX_N_52MBPS    = 19,
 102         API_RATE_INDEX_N_58P5MBPS  = 20,
 103         API_RATE_INDEX_N_65MBPS    = 21,
 104         API_RATE_NUM_ENTRIES       = 22
 105 };
 106
 107 enum hif_fw_type {
 108         HIF_FW_TYPE_ETF  = 0x0,
 109         HIF_FW_TYPE_WFM  = 0x1,
 110         HIF_FW_TYPE_WSM  = 0x2
 111 };
 112
 113 struct hif_ind_startup {
 114         // As the others, this struct is interpreted as little endian by the
 115         // device. However, this struct is also used by the driver. We prefer to
 116         // declare it in native order and doing byte swap on reception.
 117         __le32 status;
 118         u16    hardware_id;
 119         u8     opn[14];
 120         u8     uid[8];
 121         u16    num_inp_ch_bufs;
 122         u16    size_inp_ch_buf;
 123         u8     num_links_ap;
 124         u8     num_interfaces;
 125         u8     mac_addr[2][ETH_ALEN];
 126         u8     api_version_minor;
 127         u8     api_version_major;
 128         u8     link_mode:2;
 129         u8     reserved1:6;
 130         u8     reserved2;
 131         u8     reserved3;
 132         u8     reserved4;
 133         u8     firmware_build;
 134         u8     firmware_minor;
 135         u8     firmware_major;
 136         u8     firmware_type;
 137         u8     disabled_channel_list[2];
 138         u8     region_sel_mode:4;
 139         u8     reserved5:4;
 140         u8     phy1_region:3;
 141         u8     phy0_region:3;
 142         u8     otp_phy_ver:2;
 143         u32    supported_rate_mask;
 144         u8     firmware_label[128];
 145 } __packed;
 146
 147 struct hif_ind_wakeup {
 148 } __packed;
 149
 150 struct hif_req_configuration {
 151         __le16 length;
 152         u8     pds_data[];
 153 } __packed;
 154
 155 struct hif_cnf_configuration {
 156         __le32 status;
 157 } __packed;
 158
 159 enum hif_gpio_mode {
 160         HIF_GPIO_MODE_D0       = 0x0,
 161         HIF_GPIO_MODE_D1       = 0x1,
 162         HIF_GPIO_MODE_OD0      = 0x2,
 163         HIF_GPIO_MODE_OD1      = 0x3,
 164         HIF_GPIO_MODE_TRISTATE = 0x4,
 165         HIF_GPIO_MODE_TOGGLE   = 0x5,
 166         HIF_GPIO_MODE_READ     = 0x6
 167 };
 168
 169 struct hif_req_control_gpio {
 170         u8     gpio_label;
 171         u8     gpio_mode;
 172 } __packed;
 173
 174 struct hif_cnf_control_gpio {
 175         __le32 status;
 176         __le32 value;
 177 } __packed;
 178
 179 enum hif_generic_indication_type {
 180         HIF_GENERIC_INDICATION_TYPE_RAW                = 0x0,
 181         HIF_GENERIC_INDICATION_TYPE_STRING             = 0x1,
 182         HIF_GENERIC_INDICATION_TYPE_RX_STATS           = 0x2,
 183         HIF_GENERIC_INDICATION_TYPE_TX_POWER_LOOP_INFO = 0x3,
 184 };
 185
 186 struct hif_rx_stats {
 187         __le32 nb_rx_frame;
 188         __le32 nb_crc_frame;
 189         __le32 per_total;
 190         __le32 throughput;
 191         __le32 nb_rx_by_rate[API_RATE_NUM_ENTRIES];
 192         __le16 per[API_RATE_NUM_ENTRIES];
 193         __le16 snr[API_RATE_NUM_ENTRIES];  // signed value
 194         __le16 rssi[API_RATE_NUM_ENTRIES]; // signed value
 195         __le16 cfo[API_RATE_NUM_ENTRIES];  // signed value
 196         __le32 date;
 197         __le32 pwr_clk_freq;
 198         u8     is_ext_pwr_clk;
 199         s8     current_temp;
 200 } __packed;
 201
 202 struct hif_tx_power_loop_info {
 203         __le16 tx_gain_dig;
 204         __le16 tx_gain_pa;
 205         __le16 target_pout; // signed value
 206         __le16 p_estimation; // signed value
 207         __le16 vpdet;
 208         u8     measurement_index;
 209         u8     reserved;
 210 } __packed;
 211
 212 struct hif_ind_generic {
 213         __le32 type;
 214         union {
 215                 struct hif_rx_stats rx_stats;
 216                 struct hif_tx_power_loop_info tx_power_loop_info;
 217         } data;
 218 } __packed;
 219
 220 enum hif_error {
 221         HIF_ERROR_FIRMWARE_ROLLBACK           = 0x00,
 222         HIF_ERROR_FIRMWARE_DEBUG_ENABLED      = 0x01,
 223         HIF_ERROR_SLK_OUTDATED_SESSION_KEY    = 0x02,
 224         HIF_ERROR_SLK_SESSION_KEY             = 0x03,
 225         HIF_ERROR_OOR_VOLTAGE                 = 0x04,
 226         HIF_ERROR_PDS_PAYLOAD                 = 0x05,
 227         HIF_ERROR_OOR_TEMPERATURE             = 0x06,
 228         HIF_ERROR_SLK_REQ_DURING_KEY_EXCHANGE = 0x07,
 229         HIF_ERROR_SLK_MULTI_TX_UNSUPPORTED    = 0x08,
 230         HIF_ERROR_SLK_OVERFLOW                = 0x09,
 231         HIF_ERROR_SLK_DECRYPTION              = 0x0a,
 232         HIF_ERROR_SLK_WRONG_ENCRYPTION_STATE  = 0x0b,
 233         HIF_ERROR_HIF_BUS_FREQUENCY_TOO_LOW   = 0x0c,
 234         HIF_ERROR_HIF_RX_DATA_TOO_LARGE       = 0x0e,
 235         HIF_ERROR_HIF_TX_QUEUE_FULL           = 0x0d,
 236         HIF_ERROR_HIF_BUS                     = 0x0f,
 237         HIF_ERROR_PDS_TESTFEATURE             = 0x10,
 238         HIF_ERROR_SLK_UNCONFIGURED            = 0x11,
 239 };
 240
 241 struct hif_ind_error {
 242         __le32 type;
 243         u8     data[];
 244 } __packed;
 245
 246 struct hif_ind_exception {
 247         __le32 type;
 248         u8     data[];
 249 } __packed;
 250
 251 enum hif_secure_link_state {
 252         SEC_LINK_UNAVAILABLE = 0x0,
 253         SEC_LINK_RESERVED    = 0x1,
 254         SEC_LINK_EVAL        = 0x2,
 255         SEC_LINK_ENFORCED    = 0x3
 256 };
 257
 258 #endif