1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
6 * Purpose: MAC routines
13 * MACbIsRegBitsOff - Test if All test Bits Off
14 * MACbIsIntDisable - Test if MAC interrupt disable
15 * MACvSetShortRetryLimit - Set 802.11 Short Retry limit
16 * MACvSetLongRetryLimit - Set 802.11 Long Retry limit
17 * MACvSetLoopbackMode - Set MAC Loopback Mode
18 * MACvSaveContext - Save Context of MAC Registers
19 * MACvRestoreContext - Restore Context of MAC Registers
20 * MACbSoftwareReset - Software Reset MAC
21 * MACbSafeRxOff - Turn Off MAC Rx
22 * MACbSafeTxOff - Turn Off MAC Tx
23 * MACbSafeStop - Stop MAC function
24 * MACbShutdown - Shut down MAC
25 * MACvInitialize - Initialize MAC
26 * MACvSetCurrRxDescAddr - Set Rx Descriptors Address
27 * MACvSetCurrTx0DescAddr - Set Tx0 Descriptors Address
28 * MACvSetCurrTx1DescAddr - Set Tx1 Descriptors Address
29 * MACvTimer0MicroSDelay - Micro Second Delay Loop by MAC
32 * 08-22-2003 Kyle Hsu : Porting MAC functions from sim53
33 * 09-03-2003 Bryan YC Fan : Add MACvClearBusSusInd()&
34 * MACvEnableBusSusEn()
35 * 09-18-2003 Jerry Chen : Add MACvSetKeyEntry & MACvDisableKeyEntry
41 void vt6655_mac_reg_bits_on(void __iomem *iobase, const u8 reg_offset, const u8 bit_mask)
43 unsigned char reg_value;
45 reg_value = ioread8(iobase + reg_offset);
46 iowrite8(reg_value | bit_mask, iobase + reg_offset);
49 void vt6655_mac_word_reg_bits_on(void __iomem *iobase, const u8 reg_offset, const u16 bit_mask)
51 unsigned short reg_value;
53 reg_value = ioread16(iobase + reg_offset);
54 iowrite16(reg_value | (bit_mask), iobase + reg_offset);
57 void vt6655_mac_reg_bits_off(void __iomem *iobase, const u8 reg_offset, const u8 bit_mask)
59 unsigned char reg_value;
61 reg_value = ioread8(iobase + reg_offset);
62 iowrite8(reg_value & ~(bit_mask), iobase + reg_offset);
65 void vt6655_mac_word_reg_bits_off(void __iomem *iobase, const u8 reg_offset, const u16 bit_mask)
67 unsigned short reg_value;
69 reg_value = ioread16(iobase + reg_offset);
70 iowrite16(reg_value & ~(bit_mask), iobase + reg_offset);
73 static void vt6655_mac_clear_stck_ds(void __iomem *iobase)
77 reg_value = ioread8(iobase + MAC_REG_STICKHW);
78 reg_value = reg_value & 0xFC;
79 iowrite8(reg_value, iobase + MAC_REG_STICKHW);
84 * Test if all test bits off
88 * io_base - Base Address for MAC
89 * byRegOfs - Offset of MAC Register
90 * byTestBits - Test bits
94 * Return Value: true if all test bits Off; otherwise false
97 bool MACbIsRegBitsOff(struct vnt_private *priv, unsigned char byRegOfs,
98 unsigned char byTestBits)
100 void __iomem *io_base = priv->port_offset;
102 return !(ioread8(io_base + byRegOfs) & byTestBits);
107 * Test if MAC interrupt disable
111 * io_base - Base Address for MAC
115 * Return Value: true if interrupt is disable; otherwise false
118 bool MACbIsIntDisable(struct vnt_private *priv)
120 void __iomem *io_base = priv->port_offset;
122 if (ioread32(io_base + MAC_REG_IMR))
130 * Set 802.11 Short Retry Limit
134 * io_base - Base Address for MAC
135 * byRetryLimit- Retry Limit
142 void MACvSetShortRetryLimit(struct vnt_private *priv,
143 unsigned char byRetryLimit)
145 void __iomem *io_base = priv->port_offset;
147 iowrite8(byRetryLimit, io_base + MAC_REG_SRT);
152 * Set 802.11 Long Retry Limit
156 * io_base - Base Address for MAC
157 * byRetryLimit- Retry Limit
164 void MACvSetLongRetryLimit(struct vnt_private *priv,
165 unsigned char byRetryLimit)
167 void __iomem *io_base = priv->port_offset;
169 iowrite8(byRetryLimit, io_base + MAC_REG_LRT);
174 * Set MAC Loopback mode
178 * io_base - Base Address for MAC
179 * byLoopbackMode - Loopback Mode
186 void MACvSetLoopbackMode(struct vnt_private *priv, unsigned char byLoopbackMode)
188 void __iomem *io_base = priv->port_offset;
190 byLoopbackMode <<= 6;
192 iowrite8((ioread8(io_base + MAC_REG_TEST) & 0x3f) | byLoopbackMode,
193 io_base + MAC_REG_TEST);
198 * Save MAC registers to context buffer
202 * io_base - Base Address for MAC
204 * cxt_buf - Context buffer
209 void MACvSaveContext(struct vnt_private *priv, unsigned char *cxt_buf)
211 void __iomem *io_base = priv->port_offset;
213 /* read page0 register */
214 memcpy_fromio(cxt_buf, io_base, MAC_MAX_CONTEXT_SIZE_PAGE0);
216 MACvSelectPage1(io_base);
218 /* read page1 register */
219 memcpy_fromio(cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0, io_base,
220 MAC_MAX_CONTEXT_SIZE_PAGE1);
222 MACvSelectPage0(io_base);
227 * Restore MAC registers from context buffer
231 * io_base - Base Address for MAC
232 * cxt_buf - Context buffer
239 void MACvRestoreContext(struct vnt_private *priv, unsigned char *cxt_buf)
241 void __iomem *io_base = priv->port_offset;
243 MACvSelectPage1(io_base);
245 memcpy_toio(io_base, cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0,
246 MAC_MAX_CONTEXT_SIZE_PAGE1);
248 MACvSelectPage0(io_base);
250 /* restore RCR,TCR,IMR... */
251 memcpy_toio(io_base + MAC_REG_RCR, cxt_buf + MAC_REG_RCR,
252 MAC_REG_ISR - MAC_REG_RCR);
254 /* restore MAC Config. */
255 memcpy_toio(io_base + MAC_REG_LRT, cxt_buf + MAC_REG_LRT,
256 MAC_REG_PAGE1SEL - MAC_REG_LRT);
258 iowrite8(*(cxt_buf + MAC_REG_CFG), io_base + MAC_REG_CFG);
260 /* restore PS Config. */
261 memcpy_toio(io_base + MAC_REG_PSCFG, cxt_buf + MAC_REG_PSCFG,
262 MAC_REG_BBREGCTL - MAC_REG_PSCFG);
264 /* restore CURR_RX_DESC_ADDR, CURR_TX_DESC_ADDR */
265 iowrite32(*(u32 *)(cxt_buf + MAC_REG_TXDMAPTR0),
266 io_base + MAC_REG_TXDMAPTR0);
267 iowrite32(*(u32 *)(cxt_buf + MAC_REG_AC0DMAPTR),
268 io_base + MAC_REG_AC0DMAPTR);
269 iowrite32(*(u32 *)(cxt_buf + MAC_REG_BCNDMAPTR),
270 io_base + MAC_REG_BCNDMAPTR);
271 iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR0),
272 io_base + MAC_REG_RXDMAPTR0);
273 iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR1),
274 io_base + MAC_REG_RXDMAPTR1);
283 * io_base - Base Address for MAC
287 * Return Value: true if Reset Success; otherwise false
290 bool MACbSoftwareReset(struct vnt_private *priv)
292 void __iomem *io_base = priv->port_offset;
295 /* turn on HOSTCR_SOFTRST, just write 0x01 to reset */
296 iowrite8(0x01, io_base + MAC_REG_HOSTCR);
298 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
299 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_SOFTRST))
302 if (ww == W_MAX_TIMEOUT)
309 * save some important register's value, then do reset, then restore
314 * io_base - Base Address for MAC
318 * Return Value: true if success; otherwise false
321 bool MACbSafeSoftwareReset(struct vnt_private *priv)
323 unsigned char abyTmpRegData[MAC_MAX_CONTEXT_SIZE_PAGE0 + MAC_MAX_CONTEXT_SIZE_PAGE1];
327 * save some important register's value, then do
328 * reset, then restore register's value
330 /* save MAC context */
331 MACvSaveContext(priv, abyTmpRegData);
333 bRetVal = MACbSoftwareReset(priv);
334 /* restore MAC context, except CR0 */
335 MACvRestoreContext(priv, abyTmpRegData);
346 * io_base - Base Address for MAC
350 * Return Value: true if success; otherwise false
353 bool MACbSafeRxOff(struct vnt_private *priv)
355 void __iomem *io_base = priv->port_offset;
358 /* turn off wow temp for turn off Rx safely */
360 /* Clear RX DMA0,1 */
361 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL0);
362 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL1);
363 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
364 if (!(ioread32(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
367 if (ww == W_MAX_TIMEOUT) {
368 pr_debug(" DBG_PORT80(0x10)\n");
371 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
372 if (!(ioread32(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
375 if (ww == W_MAX_TIMEOUT) {
376 pr_debug(" DBG_PORT80(0x11)\n");
380 /* try to safe shutdown RX */
381 vt6655_mac_reg_bits_off(io_base, MAC_REG_HOSTCR, HOSTCR_RXON);
382 /* W_MAX_TIMEOUT is the timeout period */
383 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
384 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_RXONST))
387 if (ww == W_MAX_TIMEOUT) {
388 pr_debug(" DBG_PORT80(0x12)\n");
400 * io_base - Base Address for MAC
404 * Return Value: true if success; otherwise false
407 bool MACbSafeTxOff(struct vnt_private *priv)
409 void __iomem *io_base = priv->port_offset;
414 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_TXDMACTL0);
416 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_AC0DMACTL);
418 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
419 if (!(ioread32(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
422 if (ww == W_MAX_TIMEOUT) {
423 pr_debug(" DBG_PORT80(0x20)\n");
426 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
427 if (!(ioread32(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
430 if (ww == W_MAX_TIMEOUT) {
431 pr_debug(" DBG_PORT80(0x21)\n");
435 /* try to safe shutdown TX */
436 vt6655_mac_reg_bits_off(io_base, MAC_REG_HOSTCR, HOSTCR_TXON);
438 /* W_MAX_TIMEOUT is the timeout period */
439 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
440 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_TXONST))
443 if (ww == W_MAX_TIMEOUT) {
444 pr_debug(" DBG_PORT80(0x24)\n");
456 * io_base - Base Address for MAC
460 * Return Value: true if success; otherwise false
463 bool MACbSafeStop(struct vnt_private *priv)
465 void __iomem *io_base = priv->port_offset;
467 vt6655_mac_reg_bits_off(io_base, MAC_REG_TCR, TCR_AUTOBCNTX);
469 if (!MACbSafeRxOff(priv)) {
470 pr_debug(" MACbSafeRxOff == false)\n");
471 MACbSafeSoftwareReset(priv);
474 if (!MACbSafeTxOff(priv)) {
475 pr_debug(" MACbSafeTxOff == false)\n");
476 MACbSafeSoftwareReset(priv);
480 vt6655_mac_reg_bits_off(io_base, MAC_REG_HOSTCR, HOSTCR_MACEN);
491 * io_base - Base Address for MAC
495 * Return Value: true if success; otherwise false
498 bool MACbShutdown(struct vnt_private *priv)
500 void __iomem *io_base = priv->port_offset;
501 /* disable MAC IMR */
502 iowrite32(0, io_base + MAC_REG_IMR);
503 MACvSetLoopbackMode(priv, MAC_LB_INTERNAL);
504 /* stop the adapter */
505 if (!MACbSafeStop(priv)) {
506 MACvSetLoopbackMode(priv, MAC_LB_NONE);
509 MACvSetLoopbackMode(priv, MAC_LB_NONE);
519 * io_base - Base Address for MAC
526 void MACvInitialize(struct vnt_private *priv)
528 void __iomem *io_base = priv->port_offset;
529 /* clear sticky bits */
530 vt6655_mac_clear_stck_ds(io_base);
531 /* disable force PME-enable */
532 iowrite8(PME_OVR, io_base + MAC_REG_PMC1);
536 MACbSoftwareReset(priv);
538 /* reset TSF counter */
539 iowrite8(TFTCTL_TSFCNTRST, io_base + MAC_REG_TFTCTL);
540 /* enable TSF counter */
541 iowrite8(TFTCTL_TSFCNTREN, io_base + MAC_REG_TFTCTL);
546 * Set the chip with current rx descriptor address
550 * io_base - Base Address for MAC
551 * curr_desc_addr - Descriptor Address
558 void MACvSetCurrRx0DescAddr(struct vnt_private *priv, u32 curr_desc_addr)
560 void __iomem *io_base = priv->port_offset;
562 unsigned char org_dma_ctl;
564 org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL0);
565 if (org_dma_ctl & DMACTL_RUN)
566 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0 + 2);
568 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
569 if (!(ioread8(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
573 iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR0);
574 if (org_dma_ctl & DMACTL_RUN)
575 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0);
580 * Set the chip with current rx descriptor address
584 * io_base - Base Address for MAC
585 * curr_desc_addr - Descriptor Address
592 void MACvSetCurrRx1DescAddr(struct vnt_private *priv, u32 curr_desc_addr)
594 void __iomem *io_base = priv->port_offset;
596 unsigned char org_dma_ctl;
598 org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL1);
599 if (org_dma_ctl & DMACTL_RUN)
600 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1 + 2);
602 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
603 if (!(ioread8(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
607 iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR1);
608 if (org_dma_ctl & DMACTL_RUN)
609 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1);
614 * Set the chip with current tx0 descriptor address
618 * io_base - Base Address for MAC
619 * curr_desc_addr - Descriptor Address
626 void MACvSetCurrTx0DescAddrEx(struct vnt_private *priv,
629 void __iomem *io_base = priv->port_offset;
631 unsigned char org_dma_ctl;
633 org_dma_ctl = ioread8(io_base + MAC_REG_TXDMACTL0);
634 if (org_dma_ctl & DMACTL_RUN)
635 iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0 + 2);
637 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
638 if (!(ioread8(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
642 iowrite32(curr_desc_addr, io_base + MAC_REG_TXDMAPTR0);
643 if (org_dma_ctl & DMACTL_RUN)
644 iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0);
649 * Set the chip with current AC0 descriptor address
653 * io_base - Base Address for MAC
654 * curr_desc_addr - Descriptor Address
661 /* TxDMA1 = AC0DMA */
662 void MACvSetCurrAC0DescAddrEx(struct vnt_private *priv,
665 void __iomem *io_base = priv->port_offset;
667 unsigned char org_dma_ctl;
669 org_dma_ctl = ioread8(io_base + MAC_REG_AC0DMACTL);
670 if (org_dma_ctl & DMACTL_RUN)
671 iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL + 2);
673 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
674 if (!(ioread8(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
677 if (ww == W_MAX_TIMEOUT)
678 pr_debug(" DBG_PORT80(0x26)\n");
679 iowrite32(curr_desc_addr, io_base + MAC_REG_AC0DMAPTR);
680 if (org_dma_ctl & DMACTL_RUN)
681 iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL);
684 void MACvSetCurrTXDescAddr(int iTxType, struct vnt_private *priv,
687 if (iTxType == TYPE_AC0DMA)
688 MACvSetCurrAC0DescAddrEx(priv, curr_desc_addr);
689 else if (iTxType == TYPE_TXDMA0)
690 MACvSetCurrTx0DescAddrEx(priv, curr_desc_addr);
695 * Micro Second Delay via MAC
699 * io_base - Base Address for MAC
700 * uDelay - Delay time (timer resolution is 4 us)
707 void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay)
709 void __iomem *io_base = priv->port_offset;
710 unsigned char byValue;
713 iowrite8(0, io_base + MAC_REG_TMCTL0);
714 iowrite32(uDelay, io_base + MAC_REG_TMDATA0);
715 iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL0);
716 for (ii = 0; ii < 66; ii++) { /* assume max PCI clock is 66Mhz */
717 for (uu = 0; uu < uDelay; uu++) {
718 byValue = ioread8(io_base + MAC_REG_TMCTL0);
719 if ((byValue == 0) ||
720 (byValue & TMCTL_TSUSP)) {
721 iowrite8(0, io_base + MAC_REG_TMCTL0);
726 iowrite8(0, io_base + MAC_REG_TMCTL0);
731 * Micro Second One shot timer via MAC
735 * io_base - Base Address for MAC
736 * uDelay - Delay time
743 void MACvOneShotTimer1MicroSec(struct vnt_private *priv,
744 unsigned int uDelayTime)
746 void __iomem *io_base = priv->port_offset;
748 iowrite8(0, io_base + MAC_REG_TMCTL1);
749 iowrite32(uDelayTime, io_base + MAC_REG_TMDATA1);
750 iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL1);
753 void MACvSetMISCFifo(struct vnt_private *priv, unsigned short offset,
756 void __iomem *io_base = priv->port_offset;
760 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
761 iowrite32(data, io_base + MAC_REG_MISCFFDATA);
762 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
765 bool MACbPSWakeup(struct vnt_private *priv)
767 void __iomem *io_base = priv->port_offset;
770 if (MACbIsRegBitsOff(priv, MAC_REG_PSCTL, PSCTL_PS))
774 vt6655_mac_reg_bits_off(io_base, MAC_REG_PSCTL, PSCTL_PSEN);
776 /* Check if SyncFlushOK */
777 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
778 if (ioread8(io_base + MAC_REG_PSCTL) & PSCTL_WAKEDONE)
781 if (ww == W_MAX_TIMEOUT) {
782 pr_debug(" DBG_PORT80(0x33)\n");
790 * Set the Key by MISCFIFO
794 * io_base - Base Address for MAC
803 void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl,
804 unsigned int uEntryIdx, unsigned int uKeyIdx,
805 unsigned char *pbyAddr, u32 *pdwKey,
806 unsigned char local_id)
808 void __iomem *io_base = priv->port_offset;
809 unsigned short offset;
816 offset = MISCFIFO_KEYETRY0;
817 offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
822 data |= MAKEWORD(*(pbyAddr + 4), *(pbyAddr + 5));
823 pr_debug("1. offset: %d, Data: %X, KeyCtl:%X\n",
824 offset, data, wKeyCtl);
826 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
827 iowrite32(data, io_base + MAC_REG_MISCFFDATA);
828 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
832 data |= *(pbyAddr + 3);
834 data |= *(pbyAddr + 2);
836 data |= *(pbyAddr + 1);
839 pr_debug("2. offset: %d, Data: %X\n", offset, data);
841 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
842 iowrite32(data, io_base + MAC_REG_MISCFFDATA);
843 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
846 offset += (uKeyIdx * 4);
847 for (ii = 0; ii < 4; ii++) {
848 /* always push 128 bits */
849 pr_debug("3.(%d) offset: %d, Data: %X\n",
850 ii, offset + ii, *pdwKey);
851 iowrite16(offset + ii, io_base + MAC_REG_MISCFFNDEX);
852 iowrite32(*pdwKey++, io_base + MAC_REG_MISCFFDATA);
853 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
859 * Disable the Key Entry by MISCFIFO
863 * io_base - Base Address for MAC
871 void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx)
873 void __iomem *io_base = priv->port_offset;
874 unsigned short offset;
876 offset = MISCFIFO_KEYETRY0;
877 offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
879 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
880 iowrite32(0, io_base + MAC_REG_MISCFFDATA);
881 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);