1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
8 * Purpose: Implement functions to access baseband
15 * bb_get_frame_time - Calculate data frame transmitting time
16 * bb_read_embedded - Embedded read baseband register via MAC
17 * bb_write_embedded - Embedded write baseband register via MAC
18 * bb_vt3253_init - VIA VT3253 baseband chip init code
21 * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
22 * 08-07-2003 Bryan YC Fan: Add MAXIM2827/2825 and RFMD2959 support.
23 * 08-26-2003 Kyle Hsu : Modify BBuGetFrameTime() and
24 * BBvCalculateParameter().
25 * cancel the setting of MAC_REG_SOFTPWRCTL on
28 * 09-01-2003 Bryan YC Fan: RF & BB tables updated.
29 * Modified BBvLoopbackOn & BBvLoopbackOff().
40 /*--------------------- Static Classes ----------------------------*/
42 /*--------------------- Static Variables --------------------------*/
44 /*--------------------- Static Functions --------------------------*/
46 /*--------------------- Export Variables --------------------------*/
48 /*--------------------- Static Definitions -------------------------*/
50 /*--------------------- Static Classes ----------------------------*/
52 /*--------------------- Static Variables --------------------------*/
54 #define CB_VT3253_INIT_FOR_RFMD 446
55 static const unsigned char by_vt3253_init_tab_rfmd[CB_VT3253_INIT_FOR_RFMD][2] = {
504 #define CB_VT3253B0_INIT_FOR_RFMD 256
505 static const unsigned char byVT3253B0_RFMD[CB_VT3253B0_INIT_FOR_RFMD][2] = {
764 #define CB_VT3253B0_AGC_FOR_RFMD2959 195
767 unsigned char byVT3253B0_AGC4_RFMD2959[CB_VT3253B0_AGC_FOR_RFMD2959][2] = {
965 #define CB_VT3253B0_INIT_FOR_AIROHA2230 256
968 unsigned char byVT3253B0_AIROHA2230[CB_VT3253B0_INIT_FOR_AIROHA2230][2] = {
1077 {0x6c, 0x00}, /* RobertYu:20050125, request by JJSue */
1227 #define CB_VT3253B0_INIT_FOR_UW2451 256
1229 static unsigned char byVT3253B0_UW2451[CB_VT3253B0_INIT_FOR_UW2451][2] = {
1338 {0x6c, 0x00}, /* RobertYu:20050125, request by JJSue */
1488 #define CB_VT3253B0_AGC 193
1490 static unsigned char byVT3253B0_AGC[CB_VT3253B0_AGC][2] = {
1686 static const unsigned short awc_frame_time[MAX_RATE] = {
1687 10, 20, 55, 110, 24, 36, 48, 72, 96, 144, 192, 216
1690 /*--------------------- Export Variables --------------------------*/
1692 * Description: Calculate data frame transmitting time
1696 * by_preamble_type - Preamble Type
1697 * by_pkt_type - PK_TYPE_11A, PK_TYPE_11B, PK_TYPE_11GB, PK_TYPE_11GA
1698 * cb_frame_length - Baseband Type
1702 * Return Value: FrameTime
1705 unsigned int bb_get_frame_time(unsigned char by_preamble_type,
1706 unsigned char by_pkt_type,
1707 unsigned int cb_frame_length,
1708 unsigned short tx_rate)
1710 unsigned int frame_time;
1711 unsigned int preamble;
1713 unsigned int rate_idx = (unsigned int)tx_rate;
1714 unsigned int rate = 0;
1716 if (rate_idx > RATE_54M)
1719 rate = (unsigned int)awc_frame_time[rate_idx];
1721 if (rate_idx <= 3) { /* CCK mode */
1722 if (by_preamble_type == 1) /* Short */
1726 frame_time = (cb_frame_length * 80) / rate; /* ????? */
1727 tmp = (frame_time * rate) / 80;
1728 if (cb_frame_length != tmp)
1731 return preamble + frame_time;
1733 frame_time = (cb_frame_length * 8 + 22) / rate; /* ???????? */
1734 tmp = ((frame_time * rate) - 22) / 8;
1735 if (cb_frame_length != tmp)
1738 frame_time = frame_time * 4; /* ??????? */
1739 if (by_pkt_type != PK_TYPE_11A)
1740 frame_time += 6; /* ?????? */
1742 return 20 + frame_time; /* ?????? */
1746 * Description: Calculate Length, Service, and Signal fields of Phy for Tx
1750 * priv - Device Structure
1751 * frame_length - Tx Frame Length
1754 * struct vnt_phy_field *phy
1755 * - pointer to Phy Length field
1756 * - pointer to Phy Service field
1757 * - pointer to Phy Signal field
1759 * Return Value: none
1762 void vnt_get_phy_field(struct vnt_private *priv, u32 frame_length,
1763 u16 tx_rate, u8 pkt_type, struct vnt_phy_field *phy)
1769 u8 preamble_type = priv->byPreambleType;
1771 bit_count = frame_length * 8;
1782 count = bit_count / 2;
1784 if (preamble_type == 1)
1791 count = (bit_count * 10) / 55;
1792 tmp = (count * 55) / 10;
1794 if (tmp != bit_count)
1797 if (preamble_type == 1)
1804 count = bit_count / 11;
1807 if (tmp != bit_count) {
1810 if ((bit_count - tmp) <= 3)
1814 if (preamble_type == 1)
1821 if (pkt_type == PK_TYPE_11A)
1828 if (pkt_type == PK_TYPE_11A)
1835 if (pkt_type == PK_TYPE_11A)
1842 if (pkt_type == PK_TYPE_11A)
1849 if (pkt_type == PK_TYPE_11A)
1856 if (pkt_type == PK_TYPE_11A)
1863 if (pkt_type == PK_TYPE_11A)
1870 if (pkt_type == PK_TYPE_11A)
1876 if (pkt_type == PK_TYPE_11A)
1883 if (pkt_type == PK_TYPE_11B) {
1884 phy->service = 0x00;
1886 phy->service |= 0x80;
1887 phy->len = cpu_to_le16((u16)count);
1889 phy->service = 0x00;
1890 phy->len = cpu_to_le16((u16)frame_length);
1895 * Description: Read a byte from BASEBAND, by embedded programming
1899 * iobase - I/O base address
1900 * by_bb_addr - address of register in Baseband
1902 * pby_data - data read
1904 * Return Value: true if succeeded; false if failed.
1907 bool bb_read_embedded(struct vnt_private *priv, unsigned char by_bb_addr,
1908 unsigned char *pby_data)
1910 void __iomem *iobase = priv->PortOffset;
1912 unsigned char by_value;
1915 VNSvOutPortB(iobase + MAC_REG_BBREGADR, by_bb_addr);
1918 MACvRegBitsOn(iobase, MAC_REG_BBREGCTL, BBREGCTL_REGR);
1919 /* W_MAX_TIMEOUT is the timeout period */
1920 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
1921 VNSvInPortB(iobase + MAC_REG_BBREGCTL, &by_value);
1922 if (by_value & BBREGCTL_DONE)
1927 VNSvInPortB(iobase + MAC_REG_BBREGDATA, pby_data);
1929 if (ww == W_MAX_TIMEOUT) {
1930 pr_debug(" DBG_PORT80(0x30)\n");
1937 * Description: Write a Byte to BASEBAND, by embedded programming
1941 * iobase - I/O base address
1942 * by_bb_addr - address of register in Baseband
1943 * by_data - data to write
1947 * Return Value: true if succeeded; false if failed.
1950 bool bb_write_embedded(struct vnt_private *priv, unsigned char by_bb_addr,
1951 unsigned char by_data)
1953 void __iomem *iobase = priv->PortOffset;
1955 unsigned char by_value;
1958 VNSvOutPortB(iobase + MAC_REG_BBREGADR, by_bb_addr);
1960 VNSvOutPortB(iobase + MAC_REG_BBREGDATA, by_data);
1962 /* turn on BBREGCTL_REGW */
1963 MACvRegBitsOn(iobase, MAC_REG_BBREGCTL, BBREGCTL_REGW);
1964 /* W_MAX_TIMEOUT is the timeout period */
1965 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
1966 VNSvInPortB(iobase + MAC_REG_BBREGCTL, &by_value);
1967 if (by_value & BBREGCTL_DONE)
1971 if (ww == W_MAX_TIMEOUT) {
1972 pr_debug(" DBG_PORT80(0x31)\n");
1979 * Description: VIA VT3253 Baseband chip init function
1983 * iobase - I/O base address
1984 * byRevId - Revision ID
1985 * byRFType - RF type
1989 * Return Value: true if succeeded; false if failed.
1993 bool bb_vt3253_init(struct vnt_private *priv)
1997 void __iomem *iobase = priv->PortOffset;
1998 unsigned char by_rf_type = priv->byRFType;
1999 unsigned char by_local_id = priv->byLocalID;
2001 if (by_rf_type == RF_RFMD2959) {
2002 if (by_local_id <= REV_ID_VT3253_A1) {
2003 for (ii = 0; ii < CB_VT3253_INIT_FOR_RFMD; ii++)
2004 result &= bb_write_embedded(priv,
2005 by_vt3253_init_tab_rfmd[ii][0],
2006 by_vt3253_init_tab_rfmd[ii][1]);
2009 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_RFMD; ii++)
2010 result &= bb_write_embedded(priv,
2011 byVT3253B0_RFMD[ii][0],
2012 byVT3253B0_RFMD[ii][1]);
2014 for (ii = 0; ii < CB_VT3253B0_AGC_FOR_RFMD2959; ii++)
2015 result &= bb_write_embedded(priv,
2016 byVT3253B0_AGC4_RFMD2959[ii][0],
2017 byVT3253B0_AGC4_RFMD2959[ii][1]);
2019 VNSvOutPortD(iobase + MAC_REG_ITRTMSET, 0x23);
2020 MACvRegBitsOn(iobase, MAC_REG_PAPEDELAY, BIT(0));
2022 priv->abyBBVGA[0] = 0x18;
2023 priv->abyBBVGA[1] = 0x0A;
2024 priv->abyBBVGA[2] = 0x0;
2025 priv->abyBBVGA[3] = 0x0;
2026 priv->ldBmThreshold[0] = -70;
2027 priv->ldBmThreshold[1] = -50;
2028 priv->ldBmThreshold[2] = 0;
2029 priv->ldBmThreshold[3] = 0;
2030 } else if ((by_rf_type == RF_AIROHA) || (by_rf_type == RF_AL2230S)) {
2031 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2032 result &= bb_write_embedded(priv,
2033 byVT3253B0_AIROHA2230[ii][0],
2034 byVT3253B0_AIROHA2230[ii][1]);
2036 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2037 result &= bb_write_embedded(priv,
2038 byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2040 priv->abyBBVGA[0] = 0x1C;
2041 priv->abyBBVGA[1] = 0x10;
2042 priv->abyBBVGA[2] = 0x0;
2043 priv->abyBBVGA[3] = 0x0;
2044 priv->ldBmThreshold[0] = -70;
2045 priv->ldBmThreshold[1] = -48;
2046 priv->ldBmThreshold[2] = 0;
2047 priv->ldBmThreshold[3] = 0;
2048 } else if (by_rf_type == RF_UW2451) {
2049 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++)
2050 result &= bb_write_embedded(priv,
2051 byVT3253B0_UW2451[ii][0],
2052 byVT3253B0_UW2451[ii][1]);
2054 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2055 result &= bb_write_embedded(priv,
2056 byVT3253B0_AGC[ii][0],
2057 byVT3253B0_AGC[ii][1]);
2059 VNSvOutPortB(iobase + MAC_REG_ITRTMSET, 0x23);
2060 MACvRegBitsOn(iobase, MAC_REG_PAPEDELAY, BIT(0));
2062 priv->abyBBVGA[0] = 0x14;
2063 priv->abyBBVGA[1] = 0x0A;
2064 priv->abyBBVGA[2] = 0x0;
2065 priv->abyBBVGA[3] = 0x0;
2066 priv->ldBmThreshold[0] = -60;
2067 priv->ldBmThreshold[1] = -50;
2068 priv->ldBmThreshold[2] = 0;
2069 priv->ldBmThreshold[3] = 0;
2070 } else if (by_rf_type == RF_UW2452) {
2071 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++)
2072 result &= bb_write_embedded(priv,
2073 byVT3253B0_UW2451[ii][0],
2074 byVT3253B0_UW2451[ii][1]);
2076 /* Init ANT B select,
2077 * TX Config CR09 = 0x61->0x45,
2078 * 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2081 /*bResult &= bb_write_embedded(iobase,0x09,0x41);*/
2083 /* Init ANT B select,
2084 * RX Config CR10 = 0x28->0x2A,
2085 * 0x2A->0x28(VC1/VC2 define,
2086 * make the ANT_A, ANT_B inverted)
2089 /*bResult &= bb_write_embedded(iobase,0x0a,0x28);*/
2090 /* Select VC1/VC2, CR215 = 0x02->0x06 */
2091 result &= bb_write_embedded(priv, 0xd7, 0x06);
2093 /* {{RobertYu:20050125, request by Jack */
2094 result &= bb_write_embedded(priv, 0x90, 0x20);
2095 result &= bb_write_embedded(priv, 0x97, 0xeb);
2098 /* {{RobertYu:20050221, request by Jack */
2099 result &= bb_write_embedded(priv, 0xa6, 0x00);
2100 result &= bb_write_embedded(priv, 0xa8, 0x30);
2102 result &= bb_write_embedded(priv, 0xb0, 0x58);
2104 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2105 result &= bb_write_embedded(priv,
2106 byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2108 priv->abyBBVGA[0] = 0x14;
2109 priv->abyBBVGA[1] = 0x0A;
2110 priv->abyBBVGA[2] = 0x0;
2111 priv->abyBBVGA[3] = 0x0;
2112 priv->ldBmThreshold[0] = -60;
2113 priv->ldBmThreshold[1] = -50;
2114 priv->ldBmThreshold[2] = 0;
2115 priv->ldBmThreshold[3] = 0;
2118 } else if (by_rf_type == RF_VT3226) {
2119 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2120 result &= bb_write_embedded(priv,
2121 byVT3253B0_AIROHA2230[ii][0],
2122 byVT3253B0_AIROHA2230[ii][1]);
2124 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2125 result &= bb_write_embedded(priv,
2126 byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2128 priv->abyBBVGA[0] = 0x1C;
2129 priv->abyBBVGA[1] = 0x10;
2130 priv->abyBBVGA[2] = 0x0;
2131 priv->abyBBVGA[3] = 0x0;
2132 priv->ldBmThreshold[0] = -70;
2133 priv->ldBmThreshold[1] = -48;
2134 priv->ldBmThreshold[2] = 0;
2135 priv->ldBmThreshold[3] = 0;
2136 /* Fix VT3226 DFC system timing issue */
2137 MACvSetRFLE_LatchBase(iobase);
2138 /* {{ RobertYu: 20050104 */
2139 } else if (by_rf_type == RF_AIROHA7230) {
2140 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2141 result &= bb_write_embedded(priv,
2142 byVT3253B0_AIROHA2230[ii][0],
2143 byVT3253B0_AIROHA2230[ii][1]);
2145 /* {{ RobertYu:20050223, request by JerryChung */
2146 /* Init ANT B select,TX Config CR09 = 0x61->0x45,
2147 * 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2149 /* bResult &= bb_write_embedded(iobase,0x09,0x41);*/
2150 /* Init ANT B select,RX Config CR10 = 0x28->0x2A,
2151 * 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2153 /* bResult &= BBbWriteEmbedded(iobase,0x0a,0x28);*/
2154 /* Select VC1/VC2, CR215 = 0x02->0x06 */
2155 result &= bb_write_embedded(priv, 0xd7, 0x06);
2158 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2159 result &= bb_write_embedded(priv,
2160 byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2162 priv->abyBBVGA[0] = 0x1C;
2163 priv->abyBBVGA[1] = 0x10;
2164 priv->abyBBVGA[2] = 0x0;
2165 priv->abyBBVGA[3] = 0x0;
2166 priv->ldBmThreshold[0] = -70;
2167 priv->ldBmThreshold[1] = -48;
2168 priv->ldBmThreshold[2] = 0;
2169 priv->ldBmThreshold[3] = 0;
2172 /* No VGA Table now */
2173 priv->bUpdateBBVGA = false;
2174 priv->abyBBVGA[0] = 0x1C;
2177 if (by_local_id > REV_ID_VT3253_A1) {
2178 bb_write_embedded(priv, 0x04, 0x7F);
2179 bb_write_embedded(priv, 0x0D, 0x01);
2186 * Description: Set ShortSlotTime mode
2190 * priv - Device Structure
2194 * Return Value: none
2198 bb_set_short_slot_time(struct vnt_private *priv)
2200 unsigned char by_bb_rx_conf = 0;
2201 unsigned char by_bb_vga = 0;
2203 bb_read_embedded(priv, 0x0A, &by_bb_rx_conf); /* CR10 */
2205 if (priv->bShortSlotTime)
2206 by_bb_rx_conf &= 0xDF; /* 1101 1111 */
2208 by_bb_rx_conf |= 0x20; /* 0010 0000 */
2210 /* patch for 3253B0 Baseband with Cardbus module */
2211 bb_read_embedded(priv, 0xE7, &by_bb_vga);
2212 if (by_bb_vga == priv->abyBBVGA[0])
2213 by_bb_rx_conf |= 0x20; /* 0010 0000 */
2215 bb_write_embedded(priv, 0x0A, by_bb_rx_conf); /* CR10 */
2218 void bb_set_vga_gain_offset(struct vnt_private *priv, unsigned char by_data)
2220 unsigned char by_bb_rx_conf = 0;
2222 bb_write_embedded(priv, 0xE7, by_data);
2224 bb_read_embedded(priv, 0x0A, &by_bb_rx_conf); /* CR10 */
2225 /* patch for 3253B0 Baseband with Cardbus module */
2226 if (by_data == priv->abyBBVGA[0])
2227 by_bb_rx_conf |= 0x20; /* 0010 0000 */
2228 else if (priv->bShortSlotTime)
2229 by_bb_rx_conf &= 0xDF; /* 1101 1111 */
2231 by_bb_rx_conf |= 0x20; /* 0010 0000 */
2232 priv->byBBVGACurrent = by_data;
2233 bb_write_embedded(priv, 0x0A, by_bb_rx_conf); /* CR10 */
2237 * Description: Baseband SoftwareReset
2241 * iobase - I/O base address
2245 * Return Value: none
2249 bb_software_reset(struct vnt_private *priv)
2251 bb_write_embedded(priv, 0x50, 0x40);
2252 bb_write_embedded(priv, 0x50, 0);
2253 bb_write_embedded(priv, 0x9C, 0x01);
2254 bb_write_embedded(priv, 0x9C, 0);
2258 * Description: Baseband Power Save Mode ON
2262 * iobase - I/O base address
2266 * Return Value: none
2270 bb_power_save_mode_on(struct vnt_private *priv)
2272 unsigned char by_org_data;
2274 bb_read_embedded(priv, 0x0D, &by_org_data);
2275 by_org_data |= BIT(0);
2276 bb_write_embedded(priv, 0x0D, by_org_data);
2280 * Description: Baseband Power Save Mode OFF
2284 * iobase - I/O base address
2288 * Return Value: none
2292 bb_power_save_mode_off(struct vnt_private *priv)
2294 unsigned char by_org_data;
2296 bb_read_embedded(priv, 0x0D, &by_org_data);
2297 by_org_data &= ~(BIT(0));
2298 bb_write_embedded(priv, 0x0D, by_org_data);
2302 * Description: Set Tx Antenna mode
2306 * priv - Device Structure
2307 * by_antenna_mode - Antenna Mode
2311 * Return Value: none
2316 bb_set_tx_antenna_mode(struct vnt_private *priv, unsigned char by_antenna_mode)
2318 unsigned char by_bb_tx_conf;
2320 bb_read_embedded(priv, 0x09, &by_bb_tx_conf); /* CR09 */
2321 if (by_antenna_mode == ANT_DIVERSITY) {
2322 /* bit 1 is diversity */
2323 by_bb_tx_conf |= 0x02;
2324 } else if (by_antenna_mode == ANT_A) {
2325 /* bit 2 is ANTSEL */
2326 by_bb_tx_conf &= 0xF9; /* 1111 1001 */
2327 } else if (by_antenna_mode == ANT_B) {
2328 by_bb_tx_conf &= 0xFD; /* 1111 1101 */
2329 by_bb_tx_conf |= 0x04;
2331 bb_write_embedded(priv, 0x09, by_bb_tx_conf); /* CR09 */
2335 * Description: Set Rx Antenna mode
2339 * priv - Device Structure
2340 * by_antenna_mode - Antenna Mode
2344 * Return Value: none
2349 bb_set_rx_antenna_mode(struct vnt_private *priv, unsigned char by_antenna_mode)
2351 unsigned char by_bb_rx_conf;
2353 bb_read_embedded(priv, 0x0A, &by_bb_rx_conf); /* CR10 */
2354 if (by_antenna_mode == ANT_DIVERSITY) {
2355 by_bb_rx_conf |= 0x01;
2357 } else if (by_antenna_mode == ANT_A) {
2358 by_bb_rx_conf &= 0xFC; /* 1111 1100 */
2359 } else if (by_antenna_mode == ANT_B) {
2360 by_bb_rx_conf &= 0xFE; /* 1111 1110 */
2361 by_bb_rx_conf |= 0x02;
2363 bb_write_embedded(priv, 0x0A, by_bb_rx_conf); /* CR10 */
2367 * Description: bb_set_deep_sleep
2371 * priv - Device Structure
2375 * Return Value: none
2379 bb_set_deep_sleep(struct vnt_private *priv, unsigned char by_local_id)
2381 bb_write_embedded(priv, 0x0C, 0x17); /* CR12 */
2382 bb_write_embedded(priv, 0x0D, 0xB9); /* CR13 */