4 #define PIO2_CARDS_MAX 32
6 #define PIO2_VARIANT_LENGTH 5
8 #define PIO2_NUM_CHANNELS 32
9 #define PIO2_NUM_IRQS 11
10 #define PIO2_NUM_CNTRS 6
12 #define PIO2_REGS_SIZE 0x40
14 #define PIO2_REGS_DATA0 0x0
15 #define PIO2_REGS_DATA1 0x1
16 #define PIO2_REGS_DATA2 0x2
17 #define PIO2_REGS_DATA3 0x3
19 static const int PIO2_REGS_DATA[4] = { PIO2_REGS_DATA0, PIO2_REGS_DATA1,
20 PIO2_REGS_DATA2, PIO2_REGS_DATA3 };
22 #define PIO2_REGS_INT_STAT0 0x8
23 #define PIO2_REGS_INT_STAT1 0x9
24 #define PIO2_REGS_INT_STAT2 0xa
25 #define PIO2_REGS_INT_STAT3 0xb
27 static const int PIO2_REGS_INT_STAT[4] = { PIO2_REGS_INT_STAT0,
30 PIO2_REGS_INT_STAT3 };
32 #define PIO2_REGS_INT_STAT_CNTR 0xc
33 #define PIO2_REGS_INT_MASK0 0x10
34 #define PIO2_REGS_INT_MASK1 0x11
35 #define PIO2_REGS_INT_MASK2 0x12
36 #define PIO2_REGS_INT_MASK3 0x13
37 #define PIO2_REGS_INT_MASK4 0x14
38 #define PIO2_REGS_INT_MASK5 0x15
39 #define PIO2_REGS_INT_MASK6 0x16
40 #define PIO2_REGS_INT_MASK7 0x17
42 static const int PIO2_REGS_INT_MASK[8] = { PIO2_REGS_INT_MASK0,
49 PIO2_REGS_INT_MASK7 };
51 #define PIO2_REGS_CTRL 0x18
52 #define PIO2_REGS_VME_VECTOR 0x19
53 #define PIO2_REGS_CNTR0 0x20
54 #define PIO2_REGS_CNTR1 0x22
55 #define PIO2_REGS_CNTR2 0x24
56 #define PIO2_REGS_CTRL_WRD0 0x26
57 #define PIO2_REGS_CNTR3 0x28
58 #define PIO2_REGS_CNTR4 0x2a
59 #define PIO2_REGS_CNTR5 0x2c
60 #define PIO2_REGS_CTRL_WRD1 0x2e
62 #define PIO2_REGS_ID 0x30
64 /* PIO2_REGS_DATAx (0x0 - 0x3) */
66 static const int PIO2_CHANNEL_BANK[32] = { 0, 0, 0, 0, 0, 0, 0, 0,
67 1, 1, 1, 1, 1, 1, 1, 1,
68 2, 2, 2, 2, 2, 2, 2, 2,
69 3, 3, 3, 3, 3, 3, 3, 3 };
71 #define PIO2_CHANNEL0_BIT BIT(0)
72 #define PIO2_CHANNEL1_BIT BIT(1)
73 #define PIO2_CHANNEL2_BIT BIT(2)
74 #define PIO2_CHANNEL3_BIT BIT(3)
75 #define PIO2_CHANNEL4_BIT BIT(4)
76 #define PIO2_CHANNEL5_BIT BIT(5)
77 #define PIO2_CHANNEL6_BIT BIT(6)
78 #define PIO2_CHANNEL7_BIT BIT(7)
79 #define PIO2_CHANNEL8_BIT BIT(0)
80 #define PIO2_CHANNEL9_BIT BIT(1)
81 #define PIO2_CHANNEL10_BIT BIT(2)
82 #define PIO2_CHANNEL11_BIT BIT(3)
83 #define PIO2_CHANNEL12_BIT BIT(4)
84 #define PIO2_CHANNEL13_BIT BIT(5)
85 #define PIO2_CHANNEL14_BIT BIT(6)
86 #define PIO2_CHANNEL15_BIT BIT(7)
87 #define PIO2_CHANNEL16_BIT BIT(0)
88 #define PIO2_CHANNEL17_BIT BIT(1)
89 #define PIO2_CHANNEL18_BIT BIT(2)
90 #define PIO2_CHANNEL19_BIT BIT(3)
91 #define PIO2_CHANNEL20_BIT BIT(4)
92 #define PIO2_CHANNEL21_BIT BIT(5)
93 #define PIO2_CHANNEL22_BIT BIT(6)
94 #define PIO2_CHANNEL23_BIT BIT(7)
95 #define PIO2_CHANNEL24_BIT BIT(0)
96 #define PIO2_CHANNEL25_BIT BIT(1)
97 #define PIO2_CHANNEL26_BIT BIT(2)
98 #define PIO2_CHANNEL27_BIT BIT(3)
99 #define PIO2_CHANNEL28_BIT BIT(4)
100 #define PIO2_CHANNEL29_BIT BIT(5)
101 #define PIO2_CHANNEL30_BIT BIT(6)
102 #define PIO2_CHANNEL31_BIT BIT(7)
104 static const int PIO2_CHANNEL_BIT[32] = { PIO2_CHANNEL0_BIT, PIO2_CHANNEL1_BIT,
105 PIO2_CHANNEL2_BIT, PIO2_CHANNEL3_BIT,
106 PIO2_CHANNEL4_BIT, PIO2_CHANNEL5_BIT,
107 PIO2_CHANNEL6_BIT, PIO2_CHANNEL7_BIT,
108 PIO2_CHANNEL8_BIT, PIO2_CHANNEL9_BIT,
109 PIO2_CHANNEL10_BIT, PIO2_CHANNEL11_BIT,
110 PIO2_CHANNEL12_BIT, PIO2_CHANNEL13_BIT,
111 PIO2_CHANNEL14_BIT, PIO2_CHANNEL15_BIT,
112 PIO2_CHANNEL16_BIT, PIO2_CHANNEL17_BIT,
113 PIO2_CHANNEL18_BIT, PIO2_CHANNEL19_BIT,
114 PIO2_CHANNEL20_BIT, PIO2_CHANNEL21_BIT,
115 PIO2_CHANNEL22_BIT, PIO2_CHANNEL23_BIT,
116 PIO2_CHANNEL24_BIT, PIO2_CHANNEL25_BIT,
117 PIO2_CHANNEL26_BIT, PIO2_CHANNEL27_BIT,
118 PIO2_CHANNEL28_BIT, PIO2_CHANNEL29_BIT,
119 PIO2_CHANNEL30_BIT, PIO2_CHANNEL31_BIT
122 /* PIO2_REGS_INT_STAT_CNTR (0xc) */
123 #define PIO2_COUNTER0 BIT(0)
124 #define PIO2_COUNTER1 BIT(1)
125 #define PIO2_COUNTER2 BIT(2)
126 #define PIO2_COUNTER3 BIT(3)
127 #define PIO2_COUNTER4 BIT(4)
128 #define PIO2_COUNTER5 BIT(5)
130 static const int PIO2_COUNTER[6] = { PIO2_COUNTER0, PIO2_COUNTER1,
131 PIO2_COUNTER2, PIO2_COUNTER3,
132 PIO2_COUNTER4, PIO2_COUNTER5 };
134 /* PIO2_REGS_CTRL (0x18) */
135 #define PIO2_VME_INT_MASK 0x7
136 #define PIO2_LED BIT(6)
137 #define PIO2_LOOP BIT(7)
139 /* PIO2_REGS_VME_VECTOR (0x19) */
140 #define PIO2_VME_VECTOR_SPUR 0x0
141 #define PIO2_VME_VECTOR_BANK0 0x1
142 #define PIO2_VME_VECTOR_BANK1 0x2
143 #define PIO2_VME_VECTOR_BANK2 0x3
144 #define PIO2_VME_VECTOR_BANK3 0x4
145 #define PIO2_VME_VECTOR_CNTR0 0x5
146 #define PIO2_VME_VECTOR_CNTR1 0x6
147 #define PIO2_VME_VECTOR_CNTR2 0x7
148 #define PIO2_VME_VECTOR_CNTR3 0x8
149 #define PIO2_VME_VECTOR_CNTR4 0x9
150 #define PIO2_VME_VECTOR_CNTR5 0xa
152 #define PIO2_VME_VECTOR_MASK 0xf0
154 static const int PIO2_VECTOR_BANK[4] = { PIO2_VME_VECTOR_BANK0,
155 PIO2_VME_VECTOR_BANK1,
156 PIO2_VME_VECTOR_BANK2,
157 PIO2_VME_VECTOR_BANK3 };
159 static const int PIO2_VECTOR_CNTR[6] = { PIO2_VME_VECTOR_CNTR0,
160 PIO2_VME_VECTOR_CNTR1,
161 PIO2_VME_VECTOR_CNTR2,
162 PIO2_VME_VECTOR_CNTR3,
163 PIO2_VME_VECTOR_CNTR4,
164 PIO2_VME_VECTOR_CNTR5 };
166 /* PIO2_REGS_CNTRx (0x20 - 0x24 & 0x28 - 0x2c) */
168 static const int PIO2_CNTR_DATA[6] = { PIO2_REGS_CNTR0, PIO2_REGS_CNTR1,
169 PIO2_REGS_CNTR2, PIO2_REGS_CNTR3,
170 PIO2_REGS_CNTR4, PIO2_REGS_CNTR5 };
172 /* PIO2_REGS_CTRL_WRDx (0x26 & 0x2e) */
174 static const int PIO2_CNTR_CTRL[6] = { PIO2_REGS_CTRL_WRD0,
179 PIO2_REGS_CTRL_WRD1 };
181 #define PIO2_CNTR_SC_DEV0 0
182 #define PIO2_CNTR_SC_DEV1 (1 << 6)
183 #define PIO2_CNTR_SC_DEV2 (2 << 6)
184 #define PIO2_CNTR_SC_RDBACK (3 << 6)
186 static const int PIO2_CNTR_SC_DEV[6] = { PIO2_CNTR_SC_DEV0, PIO2_CNTR_SC_DEV1,
187 PIO2_CNTR_SC_DEV2, PIO2_CNTR_SC_DEV0,
188 PIO2_CNTR_SC_DEV1, PIO2_CNTR_SC_DEV2 };
190 #define PIO2_CNTR_RW_LATCH 0
191 #define PIO2_CNTR_RW_LSB (1 << 4)
192 #define PIO2_CNTR_RW_MSB (2 << 4)
193 #define PIO2_CNTR_RW_BOTH (3 << 4)
195 #define PIO2_CNTR_MODE0 0
196 #define PIO2_CNTR_MODE1 (1 << 1)
197 #define PIO2_CNTR_MODE2 (2 << 1)
198 #define PIO2_CNTR_MODE3 (3 << 1)
199 #define PIO2_CNTR_MODE4 (4 << 1)
200 #define PIO2_CNTR_MODE5 (5 << 1)
202 #define PIO2_CNTR_BCD 1
204 enum pio2_bank_config { NOFIT, INPUT, OUTPUT, BOTH };
205 enum pio2_int_config { NONE = 0, LOW2HIGH = 1, HIGH2LOW = 2, EITHER = 4 };
207 /* Bank configuration structure */
208 struct pio2_io_bank {
209 enum pio2_bank_config config;
211 enum pio2_int_config irq[8];
214 /* Counter configuration structure */
229 struct vme_dev *vdev;
230 struct vme_resource *window;
233 struct pio2_io_bank bank[4];
235 struct pio2_cntr cntr[6];
238 int pio2_cntr_reset(struct pio2_card *card);
240 int pio2_gpio_reset(struct pio2_card *card);
241 int pio2_gpio_init(struct pio2_card *card);
242 void pio2_gpio_exit(struct pio2_card *card);
244 #endif /* _VME_PIO2_H_ */