1 /******************************************************************************
3 * Copyright(c) 2009-2010 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
30 #ifndef __RTL_WIFI_H__
31 #define __RTL_WIFI_H__
33 #include <linux/interrupt.h>
34 #include <linux/sched.h>
35 #include <linux/firmware.h>
36 #include <linux/version.h>
37 #include <linux/etherdevice.h>
38 #include <net/mac80211.h>
42 #define RF_CHANGE_BY_INIT 0
43 #define RF_CHANGE_BY_IPS BIT(28)
44 #define RF_CHANGE_BY_PS BIT(29)
45 #define RF_CHANGE_BY_HW BIT(30)
46 #define RF_CHANGE_BY_SW BIT(31)
48 #define IQK_ADDA_REG_NUM 16
49 #define IQK_MAC_REG_NUM 4
50 #define IQK_THRESHOLD 8
52 #define MAX_KEY_LEN 61
53 #define KEY_BUF_SIZE 5
56 /*aci: 0x00 Best Effort*/
57 /*aci: 0x01 Background*/
60 /*Max: define total number.*/
66 #define QOS_QUEUE_NUM 4
67 #define RTL_MAC80211_NUM_QUEUE 5
69 #define QBSS_LOAD_SIZE 5
70 #define MAX_WMMELE_LENGTH 64
72 #define TOTAL_CAM_ENTRY 32
74 /*slot time for 11g. */
75 #define RTL_SLOT_TIME_9 9
76 #define RTL_SLOT_TIME_20 20
78 /*related with tcp/ip. */
80 #define ETH_P_PAE 0x888E /*Port Access Entity
82 #define ETH_P_IP 0x0800 /*Internet Protocol packet */
83 #define ETH_P_ARP 0x0806 /*Address Resolution packet */
85 #define PROTOC_TYPE_SIZE 2
87 /*related with 802.11 frame*/
88 #define MAC80211_3ADDR_LEN 24
89 #define MAC80211_4ADDR_LEN 30
91 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max
93 #define CHANNEL_MAX_NUMBER_2G 14
94 #define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to
95 *"phy_GetChnlGroup8812A" and
96 * "Hal_ReadTxPowerInfo8812A"*/
97 #define CHANNEL_MAX_NUMBER_5G_80M 7
98 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, ch4~9, ch10~14
99 * total three groups */
100 #define MAX_PG_GROUP 13
101 #define CHANNEL_GROUP_MAX_2G 3
102 #define CHANNEL_GROUP_IDX_5GL 3
103 #define CHANNEL_GROUP_IDX_5GM 6
104 #define CHANNEL_GROUP_IDX_5GH 9
105 #define CHANNEL_GROUP_MAX_5G 9
106 #define CHANNEL_MAX_NUMBER_2G 14
107 #define AVG_THERMAL_NUM 8
108 #define AVG_THERMAL_NUM_92E 4
109 #define AVG_THERMAL_NUM_88E 4
110 #define AVG_THERMAL_NUM_8723BE 4
111 #define MAX_TID_COUNT 9
112 #define MAX_NUM_RATES 264
115 /*It must always set to 4, otherwise read efuse table secquence will be wrong.*/
116 #define MAX_TX_COUNT 4
117 #define MAX_RF_PATH 4
118 #define MAX_CHNL_GROUP_24G 6
119 #define MAX_CHNL_GROUP_5G 14
121 /* BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */
122 #define MAX_TX_QUEUE 9
124 #define TX_PWR_BY_RATE_NUM_BAND 2
125 #define TX_PWR_BY_RATE_NUM_RF 4
126 #define TX_PWR_BY_RATE_NUM_SECTION 12
127 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6
128 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5
130 #define DELTA_SWINGIDX_SIZE 30
132 /*Now, it's just for 8192ee
133 *not OK yet, keep it 0*/
134 #define DMA_IS_64BIT 0
135 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
137 struct txpower_info_2g {
138 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
139 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
140 /*If only one tx, only BW20 and OFDM are used.*/
141 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
142 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
143 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
144 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
147 struct txpower_info_5g {
148 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
149 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
150 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
151 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
152 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
153 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
154 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
162 #define MAX_VIRTUAL_MAC 1
168 RF_TX_NUM_NONIMPLEMENT,
192 enum rt_eeprom_type {
199 RTL_STATUS_INTERFACE_START = 0,
203 HARDWARE_TYPE_RTL8192E,
204 HARDWARE_TYPE_RTL8192U,
205 HARDWARE_TYPE_RTL8192SE,
206 HARDWARE_TYPE_RTL8192SU,
207 HARDWARE_TYPE_RTL8192CE,
208 HARDWARE_TYPE_RTL8192CU,
209 HARDWARE_TYPE_RTL8192DE,
210 HARDWARE_TYPE_RTL8192DU,
211 HARDWARE_TYPE_RTL8723AE,
212 HARDWARE_TYPE_RTL8188EE,
213 HARDWARE_TYPE_RTL8723BE,
214 HARDWARE_TYPE_RTL8192EE,
215 HARDWARE_TYPE_RTL8821AE,
216 HARDWARE_TYPE_RTL8812AE,
221 enum scan_operation_backup_opt {
222 SCAN_OPT_BACKUP_BAND0=0,
223 SCAN_OPT_BACKUP_BAND1,
245 u32 rfswitch_control;
248 u32 rfrxiq_imbalance;
250 u32 rftxiq_imbalance;
253 u32 rflssi_readbackpi;
257 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
258 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
259 IO_CMD_RESUME_DM_BY_SCAN = 2,
264 HW_VAR_MULTICAST_REG,
268 HW_VAR_SECURITY_CONF,
269 HW_VAR_BEACON_INTERVAL,
271 HW_VAR_LISTEN_INTERVAL,
284 HW_VAR_RATE_FALLBACK_CONTROL,
285 HW_VAR_CONTENTION_WINDOW,
290 HW_VAR_AMPDU_MIN_SPACE,
291 HW_VAR_SHORTGI_DENSITY,
293 HW_VAR_MCS_RATE_AVAILABLE,
296 HW_VAR_DIS_Req_Qsize,
297 HW_VAR_CCX_CHNL_LOAD,
298 HW_VAR_CCX_NOISE_HISTOGRAM,
305 HW_VAR_SET_DEV_POWER,
315 HW_VAR_USER_CONTROL_TURBO_MODE,
321 HW_VAR_AUTOLOAD_STATUS,
322 HW_VAR_RF_2R_DISABLE,
324 HW_VAR_H2C_FW_PWRMODE,
325 HW_VAR_H2C_FW_JOINBSSRPT,
326 HW_VAR_H2C_FW_MEDIASTATUSRPT,
327 HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
328 HW_VAR_FW_PSMODE_STATUS,
329 HW_VAR_RESUME_CLK_ON,
330 HW_VAR_FW_LPS_ACTION,
331 HW_VAR_1X1_RECV_COMBINE,
332 HW_VAR_STOP_SEND_BEACON,
337 HW_VAR_H2C_FW_UPDATE_GTK,
340 HW_VAR_WF_IS_MAC_ADDR,
341 HW_VAR_H2C_FW_OFFLOAD,
344 HW_VAR_HANDLE_FW_C2H,
345 HW_VAR_DL_FW_RSVD_PAGE,
347 HW_VAR_HW_SEQ_ENABLE,
352 HW_VAR_SWITCH_EPHY_WoWLAN,
353 HW_VAR_INT_MIGRATION,
363 enum rt_media_status {
364 RT_MEDIA_DISCONNECT = 0,
370 RT_CID_8187_ALPHA0 = 1,
371 RT_CID_8187_SERCOMM_PS = 2,
372 RT_CID_8187_HW_LED = 3,
373 RT_CID_8187_NETGEAR = 4,
375 RT_CID_819x_CAMEO = 6,
376 RT_CID_819x_RUNTOP = 7,
377 RT_CID_819x_Senao = 8,
379 RT_CID_819x_Netcore = 10,
380 RT_CID_Nettronix = 11,
384 RT_CID_819x_ALPHA = 15,
385 RT_CID_819x_Sitecom = 16,
387 RT_CID_819x_Lenovo = 18,
388 RT_CID_819x_QMI = 19,
389 RT_CID_819x_Edimax_Belkin = 20,
390 RT_CID_819x_Sercomm_Belkin = 21,
391 RT_CID_819x_CAMEO1 = 22,
392 RT_CID_819x_MSI = 23,
393 RT_CID_819x_Acer = 24,
395 RT_CID_819x_CLEVO = 28,
396 RT_CID_819x_Arcadyan_Belkin = 29,
397 RT_CID_819x_SAMSUNG = 30,
398 RT_CID_819x_WNC_COREGA = 31,
399 RT_CID_819x_Foxcoon = 32,
400 RT_CID_819x_DELL = 33,
401 RT_CID_819x_PRONETS = 34,
402 RT_CID_819x_Edimax_ASUS = 35,
411 HW_DESC_TX_NEXTDESC_ADDR,
420 PRIME_CHNL_OFFSET_DONT_CARE = 0,
421 PRIME_CHNL_OFFSET_LOWER = 1,
422 PRIME_CHNL_OFFSET_UPPER = 2,
432 enum ht_channel_width {
433 HT_CHANNEL_WIDTH_20 = 0,
434 HT_CHANNEL_WIDTH_20_40 = 1,
435 HT_CHANNEL_WIDTH_80 = 2,
438 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
439 Cipher Suites Encryption Algorithms */
442 WEP40_ENCRYPTION = 1,
444 RSERVED_ENCRYPTION = 3,
445 AESCCMP_ENCRYPTION = 4,
446 WEP104_ENCRYPTION = 5,
447 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
452 _HAL_STATE_START = 1,
478 EFUSE_HWSET_MAX_SIZE,
479 EFUSE_MAX_SECTION_MAP,
480 EFUSE_REAL_CONTENT_SIZE,
481 EFUSE_OOB_PROTECT_BYTES_LEN,
496 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
497 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
498 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
499 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
500 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
501 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
502 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
503 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
504 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
505 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
506 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
507 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
508 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
509 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
510 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
511 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
512 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
513 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
514 RTL_IMR_BcnInt, /*Beacon DMA Interrupt 0 */
515 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
516 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
517 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
518 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
519 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
520 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
521 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
522 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
523 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
524 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
525 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
526 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
527 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
528 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
529 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/
530 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BcnInt | RTL_IMR_TBDOK |
532 RTL_IMR_C2HCMD, /*fw interrupt*/
534 /*CCK Rates, TxHT = 0 */
540 /*OFDM Rates, TxHT = 0 */
557 /*Firmware PS mode for control LPS.*/
559 FW_PS_ACTIVE_MODE = 0,
564 FW_PS_UAPSD_WMM_MODE = 5,
565 FW_PS_UAPSD_MODE = 6,
567 FW_PS_WWLAN_MODE = 8,
568 FW_PS_PM_Radio_Off = 9,
569 FW_PS_PM_Card_Disable = 10,
573 EACTIVE, /*Active/Continuous access. */
574 EMAXPS, /*Max power save mode. */
575 EFASTPS, /*Fast power save mode. */
576 EAUTOPS, /*Auto power save mode. */
581 LED_CTL_POWER_ON = 1,
586 LED_CTL_SITE_SURVEY = 6,
587 LED_CTL_POWER_OFF = 7,
588 LED_CTL_START_TO_LINK = 8,
589 LED_CTL_START_WPS = 9,
590 LED_CTL_STOP_WPS = 10,
601 /*acm implementation method.*/
603 eAcmWay0_SwAndHw = 0,
609 SINGLEMAC_SINGLEPHY = 0,
622 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
636 WIRELESS_MODE_UNKNOWN = 0x00,
637 WIRELESS_MODE_A = 0x01,
638 WIRELESS_MODE_B = 0x02,
639 WIRELESS_MODE_G = 0x04,
640 WIRELESS_MODE_AUTO = 0x08,
641 WIRELESS_MODE_N_24G = 0x10,
642 WIRELESS_MODE_N_5G = 0x20,
643 WIRELESS_MODE_AC_5G = 0x40,
644 WIRELESS_MODE_AC_24G = 0x80
647 enum ratr_table_mode {
648 RATR_INX_WIRELESS_NGB = 0, // BGN 40 Mhz 2SS 1SS
649 RATR_INX_WIRELESS_NG = 1, // GN or N
650 RATR_INX_WIRELESS_NB = 2, // BGN 20 Mhz 2SS 1SS or BN
651 RATR_INX_WIRELESS_N = 3,
652 RATR_INX_WIRELESS_GB = 4,
653 RATR_INX_WIRELESS_G = 5,
654 RATR_INX_WIRELESS_B = 6,
655 RATR_INX_WIRELESS_MC = 7,
656 RATR_INX_WIRELESS_AC_5N = 8,
657 RATR_INX_WIRELESS_AC_24N = 9,
660 enum rtl_link_state {
662 MAC80211_LINKING = 1,
664 MAC80211_LINKED_SCANNING = 3,
681 enum rt_polarity_ctl {
682 RT_POLARITY_LOW_ACT = 0,
683 RT_POLARITY_HIGH_ACT = 1,
687 struct octet_string {
692 struct rtl_hdr_3addr {
702 struct rtl_info_element {
708 struct rtl_probe_rsp {
709 struct rtl_hdr_3addr header;
711 __le16 beacon_interval;
713 /*SSID, supported rates, FH params, DS params,
714 CF params, IBSS params, TIM (if beacon), RSN */
715 struct rtl_info_element info_element[0];
719 /*ledpin Identify how to implement this SW led.*/
722 enum rtl_led_pin ledpin;
728 struct rtl_led sw_led0;
729 struct rtl_led sw_led1;
732 struct rtl_qos_parameters {
740 struct rt_smooth_data {
741 u32 elements[100]; /*array to store values */
742 u32 index; /*index to current array to store */
743 u32 total_num; /*num of valid elements */
744 u32 total_val; /*sum of valid elements */
757 struct rtl_tid_data {
759 struct rtl_ht_agg agg;
763 long undecorated_smoothed_pwdb;
766 struct rtl_sta_info {
767 struct list_head list;
772 struct rtl_tid_data tids[MAX_TID_COUNT];
774 /* just used for ap adhoc or mesh*/
775 struct rssi_sta rssi_stat;
781 /* struct ieee80211_vif __rcu *vif; */
782 struct ieee80211_vif *vif;
785 struct rtl_vif_info {
786 struct list_head list;
789 struct sk_buff *beacon;
794 struct list_head vif_list;
796 /* interface mode settings */
797 unsigned long vif_bitmap;
799 struct rtl_vif vif[MAX_VIRTUAL_MAC];
802 spinlock_t beacon_lock;
803 unsigned int global_pretbtt;
804 unsigned int global_beacon_int;
805 /* struct rtl_vif_info __rcu *beacon_iter; */
806 struct rtl_vif_info *beacon_iter;
807 unsigned int beacon_enabled;
811 struct false_alarm_statistics {
813 u32 cnt_rate_illegal;
816 u32 cnt_fast_fsync_fail;
817 u32 cnt_sb_search_fail;
837 struct wireless_stats {
838 unsigned long txbytesunicast;
839 unsigned long txbytesmulticast;
840 unsigned long txbytesbroadcast;
841 unsigned long rxbytesunicast;
844 /*Correct smoothed ss in Dbm, only used
845 in driver to report real power now. */
846 long recv_signal_power;
848 long last_sigstrength_inpercent;
850 u32 rssi_calculate_cnt;
853 /*Transformed, in dbm. Beautified signal
854 strength for UI, not correct. */
855 long signal_strength;
857 u8 rx_rssi_percentage[4];
859 u8 rx_evm_percentage[2];
864 struct rt_smooth_data ui_rssi;
865 struct rt_smooth_data ui_link_quality;
868 struct rate_adaptive {
869 u8 rate_adaptive_disabled;
873 u32 high_rssi_thresh_for_ra;
874 u32 high2low_rssi_thresh_for_ra;
875 u8 low2high_rssi_thresh_for_ra;
876 u32 low_rssi_thresh_for_ra;
877 u32 upper_rssi_threshold_ratr;
878 u32 middleupper_rssi_threshold_ratr;
879 u32 middle_rssi_threshold_ratr;
880 u32 middlelow_rssi_threshold_ratr;
881 u32 low_rssi_threshold_ratr;
882 u32 ultralow_rssi_threshold_ratr;
883 u32 low_rssi_threshold_ratr_40m;
884 u32 low_rssi_threshold_ratr_20m;
887 u32 ping_rssi_thresh_for_ra;
893 bool is_special_data;
896 struct regd_pair_mapping {
902 struct dynamic_primary_cca{
912 struct rtl_regulatory {
920 struct regd_pair_mapping *regpair;
924 bool rfkill_state; /*0 is off, 1 is on */
928 #define P2P_MAX_NOA_NUM 2
931 P2P_ROLE_DISABLE = 0,
941 P2P_PS_SCAN_DONE = 3,
942 P2P_PS_ALLSTASLEEP = 4, // for P2P GO
949 P2P_PS_MIX = 3, // CTWindow and NoA
952 struct rtl_p2p_ps_info {
953 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
954 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
955 u8 noa_index; /* Identifies and instance of Notice of Absence timing. */
956 /* Client traffic window. A period of time in TU after TBTT. */
958 u8 opp_ps; /* opportunistic power save. */
959 u8 noa_num; /* number of NoA descriptor in P2P IE. */
960 /* Count for owner, Type of client. */
961 u8 noa_count_type[P2P_MAX_NOA_NUM];
962 /* Max duration for owner, preferred or
963 * min acceptable duration for client. */
964 u32 noa_duration[P2P_MAX_NOA_NUM];
965 /* Length of interval for owner, preferred or
966 * max acceptable interval of client. */
967 u32 noa_interval[P2P_MAX_NOA_NUM];
968 /* schedule expressed in terms of the lower 4 bytes of the TSF timer. */
969 u32 noa_start_time[P2P_MAX_NOA_NUM];
972 struct p2p_ps_offload_t {
974 u8 role:1; /* 1: Owner, 0: Client */
983 #define IQK_MATRIX_REG_NUM 8
984 #define IQK_MATRIX_SETTINGS_NUM (14+24+21) // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G
985 struct iqk_matrix_regs {
987 long value[1][IQK_MATRIX_REG_NUM];
991 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
992 struct init_gain initgain_backup;
993 enum io_type current_io_type;
998 u8 set_bwmode_inprogress;
999 u8 sw_chnl_inprogress;
1004 u8 set_io_inprogress;
1007 /* record for power tracking */
1019 u32 reg_c04, reg_c08, reg_874;
1020 u32 adda_backup[16];
1021 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1022 u32 iqk_bb_backup[10];
1023 bool iqk_initialized;
1025 bool rfpath_rx_enable[MAX_RF_PATH];
1030 struct iqk_matrix_regs iqk_matrix_regsetting[IQK_MATRIX_SETTINGS_NUM];
1034 bool b_iqk_in_progress;
1038 /* this is for 88E & 8723A */
1039 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1040 /* this is for 92EE */
1041 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1042 [TX_PWR_BY_RATE_NUM_RF]
1043 [TX_PWR_BY_RATE_NUM_RF]
1044 [TX_PWR_BY_RATE_NUM_SECTION];
1045 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1046 [TX_PWR_BY_RATE_NUM_RF]
1047 [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
1049 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1050 [TX_PWR_BY_RATE_NUM_RF]
1051 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
1052 u8 default_initialgain[4];
1054 /* the current Tx power level */
1055 u8 cur_cck_txpwridx;
1056 u8 cur_ofdm24g_txpwridx;
1057 u8 cur_bw20_txpwridx;
1058 u8 cur_bw40_txpwridx;
1060 u32 rfreg_chnlval[2];
1062 u32 reg_rf3c[2]; /* pathA / pathB */
1064 u32 backup_rf_0x1a;/*92ee*/
1069 u8 num_total_rfpath;
1072 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1074 enum rt_polarity_ctl polarity_ctl;
1077 #define RTL_AGG_STOP 0
1078 #define RTL_AGG_PROGRESS 1
1079 #define RTL_AGG_START 2
1080 #define RTL_AGG_OPERATIONAL 3
1081 #define RTL_RX_AGG_START 1
1082 #define RTL_RX_AGG_STOP 0
1089 unsigned long pci_mem_end; /*shared mem end */
1090 unsigned long pci_mem_start; /*shared mem start */
1093 unsigned long pci_base_addr; /*device I/O address */
1095 void (*write8_async) (struct rtl_priv * rtlpriv, u32 addr, u8 val);
1096 void (*write16_async) (struct rtl_priv * rtlpriv, u32 addr, u16 val);
1097 void (*write32_async) (struct rtl_priv * rtlpriv, u32 addr, u32 val);
1099 u8(*read8_sync) (struct rtl_priv * rtlpriv, u32 addr);
1100 u16(*read16_sync) (struct rtl_priv * rtlpriv, u32 addr);
1101 u32(*read32_sync) (struct rtl_priv * rtlpriv, u32 addr);
1106 u8 mac_addr[ETH_ALEN];
1107 u8 mac80211_registered;
1113 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1114 struct ieee80211_hw *hw;
1115 struct ieee80211_vif *vif;
1116 enum nl80211_iftype opmode;
1118 /*Probe Beacon management */
1119 enum rtl_link_state link_state;
1125 u8 p2p; /*using p2p role*/
1132 u8 cnt_after_linked;
1136 /* skb wait queue */
1137 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1145 u32 basic_rates; /* b/g rates */
1148 u8 mode; /* wireless mode */
1153 u8 cur_40_prime_sc_bk;
1162 int beacon_interval;
1165 u8 min_space_cfg; /*For Min spacing configurations */
1167 u8 current_ampdu_factor;
1168 u8 current_ampdu_density;
1171 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1172 struct rtl_qos_parameters ac[AC_MAX];
1176 struct ieee80211_hw *hw;
1178 bool driver_is_goingto_unload;
1181 bool being_init_adapter;
1183 bool b_mac_func_enable;
1184 bool b_pre_edcca_enable;
1186 enum intf_type interface;
1187 u16 hw_type; /*92c or 92d or 92s and so on */
1190 u32 version; /*version of chip */
1191 u8 state; /*stop 0, start 1 */
1199 bool b_h2c_setinprogress;
1203 /*Reserve page start offset except beacon in TxQ. */
1204 u8 fw_rsvdpage_startoffset;
1208 /* FW Cmd IO related */
1211 bool set_fwcmd_inprogress;
1212 u8 current_fwcmd_io;
1214 bool bfw_clk_change_in_progress;
1215 bool ballow_sw_to_change_hwclc;
1217 struct p2p_ps_offload_t p2p_ps_offload;
1219 bool driver_going2unload;
1221 /*AMPDU init min space*/
1222 u8 minspace_cfg; /*For Min spacing configurations */
1225 enum macphy_mode macphymode;
1226 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1227 enum band_type current_bandtypebackup;
1228 enum band_type bandset;
1229 /* dual MAC 0--Mac0 1--Mac1 */
1231 /* just for DulMac S3S4 */
1233 bool b_earlymode_enable;
1234 u8 max_earlymode_num;
1236 bool during_mac0init_radiob;
1237 bool during_mac1init_radioa;
1238 bool reloadtxpowerindex;
1239 /* True if IMR or IQK have done
1240 for 2.4G in scan progress */
1241 bool b_load_imrandiqk_setting_for2g;
1243 bool disable_amsdu_8k;
1244 bool bmaster_of_dmsp;
1245 bool bslave_of_dmsp;
1247 u16 rx_tag;/*for 92ee*/
1251 struct rtl_security {
1256 bool use_defaultkey;
1257 /*Encryption Algorithm for Unicast Packet */
1258 enum rt_enc_alg pairwise_enc_algorithm;
1259 /*Encryption Algorithm for Brocast/Multicast */
1260 enum rt_enc_alg group_enc_algorithm;
1261 /*Cam Entry Bitmap */
1262 u32 hwsec_cam_bitmap;
1263 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1264 /*local Key buffer, indx 0 is for
1265 pairwise key 1-4 is for agoup key. */
1266 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1267 u8 key_len[KEY_BUF_SIZE];
1269 /*The pointer of Pairwise Key,
1270 it always points to KeyBuf[4] */
1276 u8 dig_ext_port_stage;
1279 u32 rssi_highthresh;
1284 u8 cursta_connectstate;
1285 u8 presta_connectstate;
1286 u8 curmultista_connectstate;
1292 char backoff_val_range_max;
1293 char backoff_val_range_min;
1294 u8 rx_gain_range_max;
1295 u8 rx_gain_range_min;
1297 u8 min_undecorated_pwdb_for_dm;
1298 long last_min_undecorated_pwdb_for_dm;
1300 u8 pre_cck_pd_state;
1301 u8 cur_cck_pd_state;
1320 #define ASSOCIATE_ENTRY_NUM 32+1
1322 struct fast_ant_trainning{
1324 u8 antsel_rx_keep_0;
1325 u8 antsel_rx_keep_1;
1326 u8 antsel_rx_keep_2;
1327 u32 ant_sum_rssi[7];
1328 u32 ant_rssi_cnt[7];
1329 u32 ant_ave_rssi[7];
1332 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1333 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1334 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1335 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1336 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1337 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1338 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1340 bool b_becomelinked;
1343 struct dm_phy_dbg_info {
1345 u64 num_qry_phy_status;
1346 u64 num_qry_phy_status_cck;
1347 u64 num_qry_phy_status_ofdm;
1348 u16 num_qry_beacon_pkt;
1354 /*PHY status for DM */
1355 long entry_min_undecoratedsmoothed_pwdb;
1356 long undecorated_smoothed_pwdb; /*out dm */
1357 long entry_max_undecoratedsmoothed_pwdb;
1358 bool b_dm_initialgain_enable;
1359 bool bdynamic_txpower_enable;
1360 bool bcurrent_turbo_edca;
1361 bool bis_any_nonbepkts; /*out dm */
1362 bool bis_cur_rdlstate;
1363 bool btxpower_trackinginit;
1364 bool b_disable_framebursting;
1366 bool btxpower_tracking;
1368 bool brfpath_rxenable[4];
1369 bool binform_fw_driverctrldm;
1370 bool bcurrent_mrc_switch;
1373 u8 thermalvalue_rxgain;
1374 u8 thermalvalue_iqk;
1375 u8 thermalvalue_lck;
1377 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1378 u8 thermalvalue_avg_index;
1381 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1382 u8 dm_flag; /*Indicate if each dynamic mechanism's status. */
1384 u8 txpower_track_control;
1385 bool binterrupt_migration;
1386 bool bdisable_tx_int;
1387 char ofdm_index[MAX_RF_PATH];
1388 u8 default_ofdm_index;
1389 u8 default_cck_index;
1391 char delta_power_index[MAX_RF_PATH];
1392 char delta_power_index_last[MAX_RF_PATH];
1393 char power_index_offset[MAX_RF_PATH];
1394 char aboslute_ofdm_swing_idx[MAX_RF_PATH];
1395 char remnant_ofdm_swing_idx[MAX_RF_PATH];
1396 char remnant_cck_idx;
1397 bool modify_txagc_flag_path_a;
1398 bool modify_txagc_flag_path_b;
1400 bool b_one_entry_only;
1401 struct dm_phy_dbg_info dbginfo;
1402 /* Dynamic ATC switch */
1412 u32 packet_count_pre;
1416 /*88e tx power tracking*/
1417 u8 bb_swing_idx_ofdm[2];
1418 u8 bb_swing_idx_ofdm_current;
1419 u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
1420 bool bb_swing_flag_Ofdm;
1421 u8 bb_swing_idx_cck;
1422 u8 bb_swing_idx_cck_current;
1423 u8 bb_swing_idx_cck_base;
1424 bool bb_swing_flag_cck;
1426 char bb_swing_diff_2g;
1427 char bb_swing_diff_5g;
1429 u8 delta_swing_table_idx_24gccka_p[DELTA_SWINGIDX_SIZE];
1430 u8 delta_swing_table_idx_24gccka_n[DELTA_SWINGIDX_SIZE];
1431 u8 delta_swing_table_idx_24gcckb_p[DELTA_SWINGIDX_SIZE];
1432 u8 delta_swing_table_idx_24gcckb_n[DELTA_SWINGIDX_SIZE];
1433 u8 delta_swing_table_idx_24ga_p[DELTA_SWINGIDX_SIZE];
1434 u8 delta_swing_table_idx_24ga_n[DELTA_SWINGIDX_SIZE];
1435 u8 delta_swing_table_idx_24gb_p[DELTA_SWINGIDX_SIZE];
1436 u8 delta_swing_table_idx_24gb_n[DELTA_SWINGIDX_SIZE];
1437 u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
1438 u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
1439 u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
1440 u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
1441 u8 delta_swing_table_idx_24ga_p_8188e[DELTA_SWINGIDX_SIZE];
1442 u8 delta_swing_table_idx_24ga_n_8188e[DELTA_SWINGIDX_SIZE];
1446 bool supp_phymode_switch;
1449 struct rtl_dig dm_digtable;
1450 struct rtl_pstbl dm_pstable;
1451 struct fast_ant_trainning fat_table;
1468 #define EFUSE_MAX_LOGICAL_SIZE 256
1473 u16 max_physical_size;
1475 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1476 u16 efuse_usedbytes;
1477 u8 efuse_usedpercentage;
1478 #ifdef EFUSE_REPG_WORKAROUND
1479 bool efuse_re_pg_sec1flag;
1480 u8 efuse_re_pg_data[8];
1483 u8 autoload_failflag;
1492 u16 eeprom_channelplan;
1499 u8 antenna_div_type;
1501 bool b_txpwr_fromeprom;
1502 u8 eeprom_crystalcap;
1504 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1505 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1506 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1507 u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
1508 u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
1509 u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][CHANNEL_GROUP_MAX];
1512 u8 internal_pa_5g[2]; /* pathA / pathB */
1516 /*For power group */
1517 u8 eeprom_pwrgroup[2][3];
1518 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1519 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1521 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
1522 /*For HT 40MHZ pwr */
1523 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1524 /*For HT 40MHZ pwr */
1525 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1526 char txpwr_cckdiff[MAX_RF_PATH][MAX_TX_COUNT]; /*CCK_24G_Diff*/
1527 /*HT 20<->40 Pwr diff */
1528 char txpwr_ht20diff[MAX_RF_PATH][MAX_TX_COUNT]; /*BW20_24G_Diff*/
1529 char txpwr_ht40diff[MAX_RF_PATH][MAX_TX_COUNT];/*BW40_24G_Diff*/
1530 /*For HT<->legacy pwr diff */
1531 char txpwr_legacyhtdiff[MAX_RF_PATH][MAX_TX_COUNT];/*OFDM_24G_Diff*/
1533 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1534 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
1535 char txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
1536 char txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
1537 char txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
1538 char txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
1540 u8 txpwr_safetyflag; /* Band edge enable flag */
1541 u16 eeprom_txpowerdiff;
1542 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1543 u8 antenna_txpwdiff[3];
1545 u8 eeprom_regulatory;
1546 u8 eeprom_thermalmeter;
1547 u8 thermalmeter[2];/*ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
1549 u8 crystalcap; /* CrystalCap. */
1553 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1554 bool b_apk_thermalmeterignore;
1556 bool b1x1_recvcombine;
1564 bool pwrdomain_protect;
1565 bool b_in_powersavemode;
1566 bool rfchange_inprogress;
1567 bool b_swrf_processing;
1570 * just for PCIE ASPM
1571 * If it supports ASPM, Offset[560h] = 0x40,
1572 * otherwise Offset[560h] = 0x00.
1574 bool b_support_aspm;
1575 bool b_support_backdoor;
1578 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1582 /*For Fw control LPS mode */
1583 u8 b_reg_fwctrl_lps;
1584 /*Record Fw PS mode status. */
1585 bool b_fw_current_inpsmode;
1586 u8 reg_max_lps_awakeintvl;
1588 bool b_low_power_enable;/*for 32k*/
1599 /*just for PCIE ASPM */
1600 u8 const_amdpci_aspm;
1602 enum rf_pwrstate inactive_pwrstate;
1603 enum rf_pwrstate rfpwr_state; /*cur power state */
1609 bool multi_buffered;
1611 unsigned int dtim_counter;
1612 unsigned int sleep_ms;
1613 unsigned long last_sleep_jiffies;
1614 unsigned long last_awake_jiffies;
1615 unsigned long last_delaylps_stamp_jiffies;
1616 unsigned long last_dtim;
1617 unsigned long last_beacon;
1618 unsigned long last_action;
1619 unsigned long last_slept;
1622 struct rtl_p2p_ps_info p2p_ps_info;
1628 u8 psaddr[ETH_ALEN];
1633 u8 rate; /* hw desc rate */
1635 u8 received_channel;
1644 u8 signalquality; /*in 0-100 index. */
1646 * Real power in dBm for this packet,
1647 * no beautification and aggregation.
1649 s32 recvsignalpower;
1650 s8 rxpower; /*in dBm Translate from PWdB */
1651 u8 signalstrength; /*in 0-100 index. */
1655 u16 b_shortpreamble:1;
1666 bool b_isfirst_ampdu;
1667 bool rx_is40Mhzpacket;
1669 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1670 s8 rx_mimo_signalquality[4];
1671 u8 rx_mimo_evm_dbm[4];
1672 u16 cfo_short[4]; /* per-path's Cfo_short */
1675 u8 rx_pwr[4]; /* per-path's pwdb */
1676 u8 rx_snr[4]; /* per-path's SNR */
1678 u8 bt_coex_pwr_adjust;
1679 bool b_packet_matchbssid;
1682 bool b_packet_toself;
1683 bool b_packet_beacon; /*for rssi */
1684 char cck_adc_pwdb[4]; /*for rx path selection */
1686 u8 packet_report_type;
1690 u32 bt_rx_rssi_percentage;
1691 u32 macid_valid_entry[2];
1694 struct rt_link_detect {
1695 /* count for raoming */
1696 u32 bcn_rx_inperiod;
1699 u32 num_tx_in4period[4];
1700 u32 num_rx_in4period[4];
1702 u32 num_tx_inperiod;
1703 u32 num_rx_inperiod;
1706 bool b_tx_busy_traffic;
1707 bool b_rx_busy_traffic;
1708 bool b_higher_busytraffic;
1709 bool b_higher_busyrxtraffic;
1711 u32 tidtx_in4period[MAX_TID_COUNT][4];
1712 u32 tidtx_inperiod[MAX_TID_COUNT];
1713 bool higher_busytxtraffic[MAX_TID_COUNT];
1716 struct rtl_tcb_desc {
1724 u8 b_rts_use_shortpreamble:1;
1725 u8 b_rts_use_shortgi:1;
1731 u8 use_shortpreamble:1;
1732 u8 use_driver_rate:1;
1733 u8 disable_ratefallback:1;
1745 /* The max value by HW */
1747 bool btx_enable_sw_calc_duration;
1748 /* used for hal construct pkt,
1749 * we may set desc when tx */
1756 void *proximity_priv;
1757 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status,
1758 struct sk_buff *skb);
1759 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
1762 struct rtl_hal_ops {
1763 int (*init_sw_vars) (struct ieee80211_hw * hw);
1764 void (*deinit_sw_vars) (struct ieee80211_hw * hw);
1765 void (*read_eeprom_info) (struct ieee80211_hw * hw);
1766 void (*interrupt_recognized) (struct ieee80211_hw * hw,
1767 u32 * p_inta, u32 * p_intb);
1768 int (*hw_init) (struct ieee80211_hw * hw);
1769 void (*hw_disable) (struct ieee80211_hw * hw);
1770 void (*hw_suspend) (struct ieee80211_hw * hw);
1771 void (*hw_resume) (struct ieee80211_hw * hw);
1772 void (*enable_interrupt) (struct ieee80211_hw * hw);
1773 void (*disable_interrupt) (struct ieee80211_hw * hw);
1774 int (*set_network_type) (struct ieee80211_hw * hw,
1775 enum nl80211_iftype type);
1776 void (*set_chk_bssid)(struct ieee80211_hw *hw,
1778 void (*set_bw_mode) (struct ieee80211_hw * hw,
1779 enum nl80211_channel_type ch_type);
1780 u8(*switch_channel) (struct ieee80211_hw * hw);
1781 void (*set_qos) (struct ieee80211_hw * hw, int aci);
1782 void (*set_bcn_reg) (struct ieee80211_hw * hw);
1783 void (*set_bcn_intv) (struct ieee80211_hw * hw);
1784 void (*update_interrupt_mask) (struct ieee80211_hw * hw,
1785 u32 add_msr, u32 rm_msr);
1786 void (*get_hw_reg) (struct ieee80211_hw * hw, u8 variable, u8 * val);
1787 void (*set_hw_reg) (struct ieee80211_hw * hw, u8 variable, u8 * val);
1788 void (*update_rate_tbl) (struct ieee80211_hw * hw,
1789 struct ieee80211_sta *sta, u8 rssi_level);
1790 void (*pre_fill_tx_bd_desc) (struct ieee80211_hw *hw, u8 *tx_bd_desc,
1791 u8 *desc, u8 queue_index,
1792 struct sk_buff *skb, dma_addr_t addr);
1793 u16 (*rx_desc_buff_remained_cnt) (struct ieee80211_hw *hw,
1795 void (*rx_check_dma_ok) (struct ieee80211_hw *hw, u8 *header_desc,
1797 void (*fill_tx_desc) (struct ieee80211_hw * hw,
1798 struct ieee80211_hdr * hdr,
1799 u8 * pdesc_tx, u8 * pbd_desc,
1800 struct ieee80211_tx_info * info,
1801 /*<delete in kernel start>*/
1802 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0))
1803 /*<delete in kernel end>*/
1804 struct ieee80211_sta *sta,
1805 /*<delete in kernel start>*/
1807 /*<delete in kernel end>*/
1808 struct sk_buff * skb, u8 hw_queue,
1809 struct rtl_tcb_desc *ptcb_desc);
1810 void (*fill_tx_cmddesc) (struct ieee80211_hw * hw, u8 * pdesc,
1811 bool b_firstseg, bool b_lastseg,
1812 struct sk_buff * skb);
1813 bool(*query_rx_desc) (struct ieee80211_hw * hw,
1814 struct rtl_stats * status,
1815 struct ieee80211_rx_status * rx_status,
1816 u8 * pdesc, struct sk_buff * skb);
1817 void (*set_channel_access) (struct ieee80211_hw * hw);
1818 bool(*radio_onoff_checking) (struct ieee80211_hw * hw, u8 * valid);
1819 void (*dm_watchdog) (struct ieee80211_hw * hw);
1820 void (*scan_operation_backup) (struct ieee80211_hw * hw, u8 operation);
1821 bool(*set_rf_power_state) (struct ieee80211_hw * hw,
1822 enum rf_pwrstate rfpwr_state);
1823 void (*led_control) (struct ieee80211_hw * hw,
1824 enum led_ctl_mode ledaction);
1825 void (*set_desc) (struct ieee80211_hw *hw, u8 * pdesc, bool istx,
1826 u8 desc_name, u8 * val);
1827 u32(*get_desc) (u8 * pdesc, bool istx, u8 desc_name);
1828 bool (*is_tx_desc_closed) (struct ieee80211_hw *hw,
1829 u8 hw_queue, u16 index);
1830 void (*tx_polling) (struct ieee80211_hw * hw, u8 hw_queue);
1831 void (*enable_hw_sec) (struct ieee80211_hw * hw);
1832 void (*set_key) (struct ieee80211_hw * hw, u32 key_index,
1833 u8 * p_macaddr, bool is_group, u8 enc_algo,
1834 bool is_wepkey, bool clear_all);
1835 void (*init_sw_leds) (struct ieee80211_hw * hw);
1836 u32(*get_bbreg) (struct ieee80211_hw * hw, u32 regaddr, u32 bitmask);
1837 void (*set_bbreg) (struct ieee80211_hw * hw, u32 regaddr, u32 bitmask,
1839 u32(*get_rfreg) (struct ieee80211_hw * hw, enum radio_path rfpath,
1840 u32 regaddr, u32 bitmask);
1841 void (*set_rfreg) (struct ieee80211_hw * hw, enum radio_path rfpath,
1842 u32 regaddr, u32 bitmask, u32 data);
1843 void (*allow_all_destaddr)(struct ieee80211_hw *hw,
1844 bool allow_all_da, bool write_into_reg);
1845 void (*linked_set_reg) (struct ieee80211_hw * hw);
1846 void (*check_switch_to_dmdp) (struct ieee80211_hw * hw);
1847 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw);
1848 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw);
1849 void (*c2h_command_handle) (struct ieee80211_hw *hw);
1850 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw, bool mstate);
1851 void (*bt_turn_off_bt_coexist_before_enter_lps) (struct ieee80211_hw *hw);
1852 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
1853 u32 cmd_len, u8 *p_cmdbuffer);
1854 bool (*get_btc_status) (void);
1855 u32 (*rx_command_packet_handler)(struct ieee80211_hw *hw, struct rtl_stats status, struct sk_buff *skb);
1858 struct rtl_intf_ops {
1860 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
1861 int (*adapter_start) (struct ieee80211_hw * hw);
1862 void (*adapter_stop) (struct ieee80211_hw * hw);
1863 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
1864 struct rtl_priv **buddy_priv);
1866 /*<delete in kernel start>*/
1867 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
1868 int (*adapter_tx) (struct ieee80211_hw * hw, struct sk_buff * skb,
1869 struct rtl_tcb_desc *ptcb_desc);
1871 /*<delete in kernel end>*/
1872 int (*adapter_tx) (struct ieee80211_hw *hw,
1873 struct ieee80211_sta *sta,
1874 struct sk_buff *skb,
1875 struct rtl_tcb_desc *ptcb_desc);
1876 /*<delete in kernel start>*/
1878 /*<delete in kernel end>*/
1879 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0))
1880 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop);
1882 void (*flush)(struct ieee80211_hw *hw, bool drop);
1884 int (*reset_trx_ring) (struct ieee80211_hw * hw);
1885 /*<delete in kernel start>*/
1886 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
1887 bool (*waitq_insert) (struct ieee80211_hw *hw, struct sk_buff *skb);
1889 /*<delete in kernel end>*/
1890 bool (*waitq_insert) (struct ieee80211_hw *hw,
1891 struct ieee80211_sta *sta,
1892 struct sk_buff *skb);
1893 /*<delete in kernel start>*/
1895 /*<delete in kernel end>*/
1898 void (*disable_aspm) (struct ieee80211_hw * hw);
1899 void (*enable_aspm) (struct ieee80211_hw * hw);
1904 struct rtl_mod_params {
1905 /* default: 0 = using hardware encryption */
1908 /* default: 1 = using no linked power save */
1911 /* default: 1 = using linked sw power save */
1914 /* default: 1 = using linked fw power save */
1918 struct rtl_hal_cfg {
1920 bool write_readback;
1923 struct rtl_hal_ops *ops;
1924 struct rtl_mod_params *mod_params;
1926 /*this map used for some registers or vars
1927 defined int HAL but used in MAIN */
1928 u32 maps[RTL_VAR_MAP_MAX];
1934 struct mutex conf_mutex;
1937 spinlock_t ips_lock;
1938 spinlock_t irq_th_lock;
1939 spinlock_t h2c_lock;
1940 spinlock_t rf_ps_lock;
1942 spinlock_t lps_lock;
1943 spinlock_t waitq_lock;
1944 spinlock_t entry_list_lock;
1946 /*FW clock change */
1947 spinlock_t fw_ps_lock;
1950 spinlock_t cck_and_rw_pagea_lock;
1953 spinlock_t check_sendpkt_lock;
1955 spinlock_t iqk_lock;
1959 struct ieee80211_hw *hw;
1962 struct timer_list watchdog_timer;
1963 struct timer_list dualmac_easyconcurrent_retrytimer;
1964 struct timer_list fw_clockoff_timer;
1965 struct timer_list fast_antenna_trainning_timer;
1967 struct tasklet_struct irq_tasklet;
1968 struct tasklet_struct irq_prepare_bcn_tasklet;
1971 struct workqueue_struct *rtl_wq;
1972 struct delayed_work watchdog_wq;
1973 struct delayed_work ips_nic_off_wq;
1976 struct delayed_work ps_work;
1977 struct delayed_work ps_rfon_wq;
1978 struct delayed_work fwevt_wq;
1982 u32 dbgp_type[DBGP_TYPE_MAX];
1983 u32 global_debuglevel;
1984 u64 global_debugcomponents;
1986 /* add for proc debug */
1987 struct proc_dir_entry *proc_dir;
1991 #define MIMO_PS_STATIC 0
1992 #define MIMO_PS_DYNAMIC 1
1993 #define MIMO_PS_NOLIMIT 3
1995 struct rtl_dualmac_easy_concurrent_ctl {
1996 enum band_type currentbandtype_backfordmdp;
1997 bool bclose_bbandrf_for_dmsp;
1998 bool bchange_to_dmdp;
1999 bool bchange_to_dmsp;
2000 bool bswitch_in_process;
2003 struct rtl_dmsp_ctl {
2004 bool bactivescan_for_slaveofdmsp;
2005 bool bscan_for_anothermac_fordmsp;
2006 bool bscan_for_itself_fordmsp;
2007 bool bwritedig_for_anothermacofdmsp;
2008 u32 curdigvalue_for_anothermacofdmsp;
2009 bool bchangecckpdstate_for_anothermacofdmsp;
2010 u8 curcckpdstate_for_anothermacofdmsp;
2011 bool bchangetxhighpowerlvl_for_anothermacofdmsp;
2012 u8 curtxhighlvl_for_anothermacofdmsp;
2013 long rssivalmin_for_anothermacofdmsp;
2016 struct rtl_global_var {
2017 /* from this list we can get
2018 * other adapter's rtl_priv */
2019 struct list_head glb_priv_list;
2020 spinlock_t glb_list_lock;
2023 struct rtl_btc_info {
2029 struct rtl_btc_ops {
2030 void (*btc_init_variables) (struct rtl_priv *rtlpriv);
2031 void (*btc_init_hal_vars) (struct rtl_priv *rtlpriv);
2032 void (*btc_init_hw_config) (struct rtl_priv *rtlpriv);
2033 void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type);
2034 void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype);
2035 void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action);
2036 void (*btc_mediastatus_notify) (struct rtl_priv *rtlpriv,
2037 enum rt_media_status mstatus);
2038 void (*btc_periodical) (struct rtl_priv *rtlpriv);
2039 void (*btc_halt_notify) (void);
2040 void (*btc_btinfo_notify) (struct rtl_priv *rtlpriv,
2041 u8 * tmp_buf, u8 length);
2042 bool (*btc_is_limited_dig) (struct rtl_priv *rtlpriv);
2043 bool (*btc_is_disable_edca_turbo) (struct rtl_priv *rtlpriv);
2044 bool (*btc_is_bt_disabled) (struct rtl_priv *rtlpriv);
2047 struct rtl_bt_coexist {
2048 struct rtl_btc_ops *btc_ops;
2049 struct rtl_btc_info btc_info;
2054 struct list_head list;
2056 struct vif_priv vif_priv;
2058 struct rtl_priv *buddy_priv;
2059 struct rtl_global_var *glb_var;
2060 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
2061 struct rtl_dmsp_ctl dmsp_ctl;
2062 struct rtl_locks locks;
2063 struct rtl_works works;
2064 struct rtl_mac mac80211;
2065 struct rtl_hal rtlhal;
2066 struct rtl_regulatory regd;
2067 struct rtl_rfkill rfkill;
2071 struct rtl_security sec;
2072 struct rtl_efuse efuse;
2074 struct rtl_ps_ctl psc;
2075 struct rate_adaptive ra;
2076 struct dynamic_primary_cca primarycca;
2077 struct wireless_stats stats;
2078 struct rt_link_detect link_info;
2079 struct false_alarm_statistics falsealm_cnt;
2081 struct rtl_rate_priv *rate_priv;
2083 struct rtl_debug dbg;
2085 /* sta entry list for ap adhoc or mesh */
2086 struct list_head entry_list;
2089 *hal_cfg : for diff cards
2090 *intf_ops : for diff interrface usb/pcie
2092 struct rtl_hal_cfg *cfg;
2093 struct rtl_intf_ops *intf_ops;
2095 /*this var will be set by set_bit,
2096 and was used to indicate status of
2097 interface or hardware */
2098 unsigned long status;
2100 /* intel Proximity, should be alloc mem
2101 * in intel Proximity module and can only
2102 * be used in intel Proximity mode */
2103 struct proxim proximity;
2105 /*for bt coexist use*/
2106 struct rtl_bt_coexist btcoexist;
2108 /* seperate 92ee from other ICs,
2109 * 92ee use new trx flow. */
2110 bool use_new_trx_flow;
2111 /*This must be the last item so
2112 that it points to the data allocated
2113 beyond this structure like:
2114 rtl_pci_priv or rtl_usb_priv */
2118 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2119 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2120 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2121 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2122 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2123 #define rtl_sec(rtlpriv) (&((rtlpriv)->sec))
2124 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
2125 /***************************************
2126 Bluetooth Co-existance Related
2127 ****************************************/
2148 enum bt_total_ant_num{
2158 enum bt_service_type {
2165 BT_OTHER_ACTION = 6,
2171 enum bt_radio_shared {
2172 BT_RADIO_SHARED = 0,
2173 BT_RADIO_INDIVIDUAL = 1,
2176 struct bt_coexist_info {
2178 /* EEPROM BT info. */
2179 u8 eeprom_bt_coexist;
2181 u8 eeprom_bt_ant_num;
2182 u8 eeprom_bt_ant_isolation;
2183 u8 eeprom_bt_radio_shared;
2189 u8 bt_cur_state; /* 0:on, 1:off */
2190 u8 bt_ant_isolation; /* 0:good, 1:bad */
2191 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2193 u8 bt_radio_shared_type;
2194 u8 bt_rfreg_origin_1e;
2195 u8 bt_rfreg_origin_1f;
2203 bool b_bt_busy_traffic;
2204 bool b_bt_traffic_mode_set;
2205 bool b_bt_non_traffic_mode_set;
2207 bool b_fw_coexist_all_off;
2208 bool b_sw_coexist_all_off;
2209 bool b_hw_coexist_all_off;
2212 u32 current_state_h;
2213 u32 previous_state_h;
2215 u8 bt_pre_rssi_state;
2216 u8 bt_pre_rssi_state1;
2221 u8 bt_active_zero_cnt;
2222 bool b_cur_bt_disabled;
2223 bool b_pre_bt_disabled;
2226 u8 bt_profile_action;
2228 bool b_hold_for_bt_operation;
2233 /****************************************
2234 mem access macro define start
2235 Call endian free function when
2236 1. Read/write packet content.
2237 2. Before write integer to IO.
2238 3. After read integer from IO.
2239 ****************************************/
2240 /* Convert little data endian to host */
2241 #define EF1BYTE(_val) \
2243 #define EF2BYTE(_val) \
2245 #define EF4BYTE(_val) \
2248 /* Read data from memory */
2249 #define READEF1BYTE(_ptr) \
2250 EF1BYTE(*((u8 *)(_ptr)))
2251 #define READEF2BYTE(_ptr) \
2252 EF2BYTE(*((u16 *)(_ptr)))
2253 #define READEF4BYTE(_ptr) \
2254 EF4BYTE(*((u32 *)(_ptr)))
2256 /* Write data to memory */
2257 #define WRITEEF1BYTE(_ptr, _val) \
2258 (*((u8 *)(_ptr)))=EF1BYTE(_val)
2259 #define WRITEEF2BYTE(_ptr, _val) \
2260 (*((u16 *)(_ptr)))=EF2BYTE(_val)
2261 #define WRITEEF4BYTE(_ptr, _val) \
2262 (*((u32 *)(_ptr)))=EF4BYTE(_val)
2265 BIT_LEN_MASK_32(0) => 0x00000000
2266 BIT_LEN_MASK_32(1) => 0x00000001
2267 BIT_LEN_MASK_32(2) => 0x00000003
2268 BIT_LEN_MASK_32(32) => 0xFFFFFFFF*/
2269 #define BIT_LEN_MASK_32(__bitlen) \
2270 (0xFFFFFFFF >> (32 - (__bitlen)))
2271 #define BIT_LEN_MASK_16(__bitlen) \
2272 (0xFFFF >> (16 - (__bitlen)))
2273 #define BIT_LEN_MASK_8(__bitlen) \
2274 (0xFF >> (8 - (__bitlen)))
2277 BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
2278 BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000*/
2279 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
2280 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
2281 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
2282 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
2283 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
2284 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
2287 Return 4-byte value in host byte ordering from
2288 4-byte pointer in little-endian system.*/
2289 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
2290 (EF4BYTE(*((u32 *)(__pstart))))
2291 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
2292 (EF2BYTE(*((u16 *)(__pstart))))
2293 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
2294 (EF1BYTE(*((u8 *)(__pstart))))
2297 Translate subfield (continuous bits in little-endian) of 4-byte
2298 value to host byte ordering.*/
2299 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2301 ( LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset) ) & \
2302 BIT_LEN_MASK_32(__bitlen) \
2304 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2306 ( LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset) ) & \
2307 BIT_LEN_MASK_16(__bitlen) \
2309 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2311 ( LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset) ) & \
2312 BIT_LEN_MASK_8(__bitlen) \
2316 Mask subfield (continuous bits in little-endian) of 4-byte value
2317 and return the result in 4-byte value in host byte ordering.*/
2318 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2320 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
2321 ( ~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) ) \
2323 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2325 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
2326 ( ~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) ) \
2328 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2330 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
2331 ( ~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) ) \
2335 Set subfield of little-endian 4-byte value to specified value. */
2336 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
2337 *((u32 *)(__pstart)) = EF4BYTE \
2339 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
2340 ( (((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset) )\
2342 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
2343 *((u16 *)(__pstart)) = EF2BYTE \
2345 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
2346 ( (((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset) )\
2348 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
2349 *((u8 *)(__pstart)) = EF1BYTE \
2351 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
2352 ( (((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset) ) \
2355 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2356 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2358 /****************************************
2359 mem access macro define end
2360 ****************************************/
2362 #define byte(x,n) ((x >> (8 * n)) & 0xff)
2364 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2365 #define RTL_WATCH_DOG_TIME 2000
2366 #define MSECS(t) msecs_to_jiffies(t)
2367 #define WLAN_FC_GET_VERS(fc) ((fc) & IEEE80211_FCTL_VERS)
2368 #define WLAN_FC_GET_TYPE(fc) ((fc) & IEEE80211_FCTL_FTYPE)
2369 #define WLAN_FC_GET_STYPE(fc) ((fc) & IEEE80211_FCTL_STYPE)
2370 #define WLAN_FC_MORE_DATA(fc) ((fc) & IEEE80211_FCTL_MOREDATA)
2371 #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
2372 #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
2373 #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
2375 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
2376 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
2377 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
2378 /*NIC halt, re-initialize hw parameters*/
2379 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
2380 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
2381 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
2382 /*Always enable ASPM and Clock Req in initialization.*/
2383 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
2384 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2385 #define RT_PS_LEVEL_ASPM BIT(7)
2386 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
2387 #define RT_RF_LPS_DISALBE_2R BIT(30)
2388 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
2389 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
2390 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2391 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
2392 (ppsc->cur_ps_level &= (~(_ps_flg)))
2393 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
2394 (ppsc->cur_ps_level |= _ps_flg)
2396 #define container_of_dwork_rtl(x,y,z) \
2397 container_of(container_of(x, struct delayed_work, work), y, z)
2399 #define FILL_OCTET_STRING(_os,_octet,_len) \
2400 (_os).octet=(u8*)(_octet); \
2401 (_os).length=(_len);
2403 #define CP_MACADDR(des,src) \
2404 ((des)[0]=(src)[0],(des)[1]=(src)[1],\
2405 (des)[2]=(src)[2],(des)[3]=(src)[3],\
2406 (des)[4]=(src)[4],(des)[5]=(src)[5])
2408 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2410 return rtlpriv->io.read8_sync(rtlpriv, addr);
2413 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2415 return rtlpriv->io.read16_sync(rtlpriv, addr);
2418 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2420 return rtlpriv->io.read32_sync(rtlpriv, addr);
2423 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2425 rtlpriv->io.write8_async(rtlpriv, addr, val8);
2427 if (rtlpriv->cfg->write_readback)
2428 rtlpriv->io.read8_sync(rtlpriv, addr);
2431 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2433 rtlpriv->io.write16_async(rtlpriv, addr, val16);
2435 if (rtlpriv->cfg->write_readback)
2436 rtlpriv->io.read16_sync(rtlpriv, addr);
2439 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2440 u32 addr, u32 val32)
2442 rtlpriv->io.write32_async(rtlpriv, addr, val32);
2444 if (rtlpriv->cfg->write_readback)
2445 rtlpriv->io.read32_sync(rtlpriv, addr);
2448 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
2449 u32 regaddr, u32 bitmask)
2451 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_bbreg(hw,
2456 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
2457 u32 bitmask, u32 data)
2459 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_bbreg(hw,
2465 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
2466 enum radio_path rfpath, u32 regaddr,
2469 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_rfreg(hw,
2475 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
2476 enum radio_path rfpath, u32 regaddr,
2477 u32 bitmask, u32 data)
2479 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_rfreg(hw,
2484 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
2486 return (_HAL_STATE_STOP == rtlhal->state);
2489 static inline void set_hal_start(struct rtl_hal *rtlhal)
2491 rtlhal->state = _HAL_STATE_START;
2494 static inline void set_hal_stop(struct rtl_hal *rtlhal)
2496 rtlhal->state = _HAL_STATE_STOP;
2499 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
2501 return rtlphy->rf_type;
2504 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
2506 return (struct ieee80211_hdr *)(skb->data);
2509 static inline u16 rtl_get_fc(struct sk_buff *skb)
2511 return le16_to_cpu(rtl_get_hdr(skb)->frame_control);
2514 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
2516 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
2519 static inline u16 rtl_get_tid(struct sk_buff *skb)
2521 return rtl_get_tid_h(rtl_get_hdr(skb));
2524 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
2527 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2528 return ieee80211_find_sta(mac->vif, mac_addr);
2531 struct ieee80211_hw *rtl_pci_get_hw_pointer(void);