drivers/staging/rtl8723bs/hal/hal_com.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   5  *
   6  ******************************************************************************/
   7 #define _HAL_COM_C_
   8
   9 #include <linux/kernel.h>
  10 #include <drv_types.h>
  11 #include <rtw_debug.h>
  12 #include "hal_com_h2c.h"
  13
  14 #include "odm_precomp.h"
  15
  16 u8 rtw_hal_data_init(struct adapter *padapter)
  17 {
  18         if (is_primary_adapter(padapter)) {     /* if (padapter->isprimary) */
  19                 padapter->hal_data_sz = sizeof(struct hal_com_data);
  20                 padapter->HalData = vzalloc(padapter->hal_data_sz);
  21                 if (!padapter->HalData) {
  22                         DBG_8192C("cannot alloc memory for HAL DATA\n");
  23                         return _FAIL;
  24                 }
  25         }
  26         return _SUCCESS;
  27 }
  28
  29 void rtw_hal_data_deinit(struct adapter *padapter)
  30 {
  31         if (is_primary_adapter(padapter)) {     /* if (padapter->isprimary) */
  32                 if (padapter->HalData) {
  33                         vfree(padapter->HalData);
  34                         padapter->HalData = NULL;
  35                         padapter->hal_data_sz = 0;
  36                 }
  37         }
  38 }
  39
  40
  41 void dump_chip_info(HAL_VERSION ChipVersion)
  42 {
  43         int cnt = 0;
  44         u8 buf[128];
  45
  46         cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8723B_");
  47         cnt += sprintf((buf+cnt), "%s_", IS_NORMAL_CHIP(ChipVersion) ? "Normal_Chip" : "Test_Chip");
  48         if (IS_CHIP_VENDOR_TSMC(ChipVersion))
  49                 cnt += sprintf((buf+cnt), "%s_", "TSMC");
  50         else if (IS_CHIP_VENDOR_UMC(ChipVersion))
  51                 cnt += sprintf((buf+cnt), "%s_", "UMC");
  52         else if (IS_CHIP_VENDOR_SMIC(ChipVersion))
  53                 cnt += sprintf((buf+cnt), "%s_", "SMIC");
  54
  55         if (IS_A_CUT(ChipVersion))
  56                 cnt += sprintf((buf+cnt), "A_CUT_");
  57         else if (IS_B_CUT(ChipVersion))
  58                 cnt += sprintf((buf+cnt), "B_CUT_");
  59         else if (IS_C_CUT(ChipVersion))
  60                 cnt += sprintf((buf+cnt), "C_CUT_");
  61         else if (IS_D_CUT(ChipVersion))
  62                 cnt += sprintf((buf+cnt), "D_CUT_");
  63         else if (IS_E_CUT(ChipVersion))
  64                 cnt += sprintf((buf+cnt), "E_CUT_");
  65         else if (IS_I_CUT(ChipVersion))
  66                 cnt += sprintf((buf+cnt), "I_CUT_");
  67         else if (IS_J_CUT(ChipVersion))
  68                 cnt += sprintf((buf+cnt), "J_CUT_");
  69         else if (IS_K_CUT(ChipVersion))
  70                 cnt += sprintf((buf+cnt), "K_CUT_");
  71         else
  72                 cnt += sprintf((buf+cnt), "UNKNOWN_CUT(%d)_", ChipVersion.CUTVersion);
  73
  74         if (IS_1T1R(ChipVersion))
  75                 cnt += sprintf((buf+cnt), "1T1R_");
  76         else if (IS_1T2R(ChipVersion))
  77                 cnt += sprintf((buf+cnt), "1T2R_");
  78         else if (IS_2T2R(ChipVersion))
  79                 cnt += sprintf((buf+cnt), "2T2R_");
  80         else
  81                 cnt += sprintf((buf+cnt), "UNKNOWN_RFTYPE(%d)_", ChipVersion.RFType);
  82
  83         cnt += sprintf((buf+cnt), "RomVer(%d)\n", ChipVersion.ROMVer);
  84
  85         DBG_871X("%s", buf);
  86 }
  87
  88
  89 #define EEPROM_CHANNEL_PLAN_BY_HW_MASK  0x80
  90
  91 /*
  92  * Description:
  93  *Use hardware(efuse), driver parameter(registry) and default channel plan
  94  *to decide which one should be used.
  95  *
  96  * Parameters:
  97  *padapter                      pointer of adapter
  98  *hw_channel_plan               channel plan from HW (efuse/eeprom)
  99  *                                      BIT[7] software configure mode; 0:Enable, 1:disable
 100  *                                      BIT[6:0] Channel Plan
 101  *sw_channel_plan               channel plan from SW (registry/module param)
 102  *def_channel_plan      channel plan used when HW/SW both invalid
 103  *AutoLoadFail          efuse autoload fail or not
 104  *
 105  * Return:
 106  *Final channel plan decision
 107  *
 108  */
 109 u8 hal_com_config_channel_plan(
 110         struct adapter *padapter,
 111         u8 hw_channel_plan,
 112         u8 sw_channel_plan,
 113         u8 def_channel_plan,
 114         bool AutoLoadFail
 115 )
 116 {
 117         struct hal_com_data *pHalData;
 118         u8 chnlPlan;
 119
 120         pHalData = GET_HAL_DATA(padapter);
 121         pHalData->bDisableSWChannelPlan = false;
 122         chnlPlan = def_channel_plan;
 123
 124         if (0xFF == hw_channel_plan)
 125                 AutoLoadFail = true;
 126
 127         if (!AutoLoadFail) {
 128                 u8 hw_chnlPlan;
 129
 130                 hw_chnlPlan = hw_channel_plan & (~EEPROM_CHANNEL_PLAN_BY_HW_MASK);
 131                 if (rtw_is_channel_plan_valid(hw_chnlPlan)) {
 132 #ifndef CONFIG_SW_CHANNEL_PLAN
 133                         if (hw_channel_plan & EEPROM_CHANNEL_PLAN_BY_HW_MASK)
 134                                 pHalData->bDisableSWChannelPlan = true;
 135 #endif /*  !CONFIG_SW_CHANNEL_PLAN */
 136
 137                         chnlPlan = hw_chnlPlan;
 138                 }
 139         }
 140
 141         if (
 142                 (false == pHalData->bDisableSWChannelPlan) &&
 143                 rtw_is_channel_plan_valid(sw_channel_plan)
 144         )
 145                 chnlPlan = sw_channel_plan;
 146
 147         return chnlPlan;
 148 }
 149
 150 bool HAL_IsLegalChannel(struct adapter *Adapter, u32 Channel)
 151 {
 152         bool bLegalChannel = true;
 153
 154         if ((Channel <= 14) && (Channel >= 1)) {
 155                 if (IsSupported24G(Adapter->registrypriv.wireless_mode) == false) {
 156                         bLegalChannel = false;
 157                         DBG_871X("(Channel <= 14) && (Channel >= 1) but wireless_mode do not support 2.4G\n");
 158                 }
 159         } else {
 160                 bLegalChannel = false;
 161                 DBG_871X("Channel is Invalid !!!\n");
 162         }
 163
 164         return bLegalChannel;
 165 }
 166
 167 u8 MRateToHwRate(u8 rate)
 168 {
 169         u8 ret = DESC_RATE1M;
 170
 171         switch (rate) {
 172         case MGN_1M:
 173                 ret = DESC_RATE1M;
 174                 break;
 175         case MGN_2M:
 176                 ret = DESC_RATE2M;
 177                 break;
 178         case MGN_5_5M:
 179                 ret = DESC_RATE5_5M;
 180                 break;
 181         case MGN_11M:
 182                 ret = DESC_RATE11M;
 183                 break;
 184         case MGN_6M:
 185                 ret = DESC_RATE6M;
 186                 break;
 187         case MGN_9M:
 188                 ret = DESC_RATE9M;
 189                 break;
 190         case MGN_12M:
 191                 ret = DESC_RATE12M;
 192                 break;
 193         case MGN_18M:
 194                 ret = DESC_RATE18M;
 195                 break;
 196         case MGN_24M:
 197                 ret = DESC_RATE24M;
 198                 break;
 199         case MGN_36M:
 200                 ret = DESC_RATE36M;
 201                 break;
 202         case MGN_48M:
 203                 ret = DESC_RATE48M;
 204                 break;
 205         case MGN_54M:
 206                 ret = DESC_RATE54M;
 207                 break;
 208         case MGN_MCS0:
 209                 ret = DESC_RATEMCS0;
 210                 break;
 211         case MGN_MCS1:
 212                 ret = DESC_RATEMCS1;
 213                 break;
 214         case MGN_MCS2:
 215                 ret = DESC_RATEMCS2;
 216                 break;
 217         case MGN_MCS3:
 218                 ret = DESC_RATEMCS3;
 219                 break;
 220         case MGN_MCS4:
 221                 ret = DESC_RATEMCS4;
 222                 break;
 223         case MGN_MCS5:
 224                 ret = DESC_RATEMCS5;
 225                 break;
 226         case MGN_MCS6:
 227                 ret = DESC_RATEMCS6;
 228                 break;
 229         case MGN_MCS7:
 230                 ret = DESC_RATEMCS7;
 231                 break;
 232         case MGN_MCS8:
 233                 ret = DESC_RATEMCS8;
 234                 break;
 235         case MGN_MCS9:
 236                 ret = DESC_RATEMCS9;
 237                 break;
 238         case MGN_MCS10:
 239                 ret = DESC_RATEMCS10;
 240                 break;
 241         case MGN_MCS11:
 242                 ret = DESC_RATEMCS11;
 243                 break;
 244         case MGN_MCS12:
 245                 ret = DESC_RATEMCS12;
 246                 break;
 247         case MGN_MCS13:
 248                 ret = DESC_RATEMCS13;
 249                 break;
 250         case MGN_MCS14:
 251                 ret = DESC_RATEMCS14;
 252                 break;
 253         case MGN_MCS15:
 254                 ret = DESC_RATEMCS15;
 255                 break;
 256         case MGN_MCS16:
 257                 ret = DESC_RATEMCS16;
 258                 break;
 259         case MGN_MCS17:
 260                 ret = DESC_RATEMCS17;
 261                 break;
 262         case MGN_MCS18:
 263                 ret = DESC_RATEMCS18;
 264                 break;
 265         case MGN_MCS19:
 266                 ret = DESC_RATEMCS19;
 267                 break;
 268         case MGN_MCS20:
 269                 ret = DESC_RATEMCS20;
 270                 break;
 271         case MGN_MCS21:
 272                 ret = DESC_RATEMCS21;
 273                 break;
 274         case MGN_MCS22:
 275                 ret = DESC_RATEMCS22;
 276                 break;
 277         case MGN_MCS23:
 278                 ret = DESC_RATEMCS23;
 279                 break;
 280         case MGN_MCS24:
 281                 ret = DESC_RATEMCS24;
 282                 break;
 283         case MGN_MCS25:
 284                 ret = DESC_RATEMCS25;
 285                 break;
 286         case MGN_MCS26:
 287                 ret = DESC_RATEMCS26;
 288                 break;
 289         case MGN_MCS27:
 290                 ret = DESC_RATEMCS27;
 291                 break;
 292         case MGN_MCS28:
 293                 ret = DESC_RATEMCS28;
 294                 break;
 295         case MGN_MCS29:
 296                 ret = DESC_RATEMCS29;
 297                 break;
 298         case MGN_MCS30:
 299                 ret = DESC_RATEMCS30;
 300                 break;
 301         case MGN_MCS31:
 302                 ret = DESC_RATEMCS31;
 303                 break;
 304         case MGN_VHT1SS_MCS0:
 305                 ret = DESC_RATEVHTSS1MCS0;
 306                 break;
 307         case MGN_VHT1SS_MCS1:
 308                 ret = DESC_RATEVHTSS1MCS1;
 309                 break;
 310         case MGN_VHT1SS_MCS2:
 311                 ret = DESC_RATEVHTSS1MCS2;
 312                 break;
 313         case MGN_VHT1SS_MCS3:
 314                 ret = DESC_RATEVHTSS1MCS3;
 315                 break;
 316         case MGN_VHT1SS_MCS4:
 317                 ret = DESC_RATEVHTSS1MCS4;
 318                 break;
 319         case MGN_VHT1SS_MCS5:
 320                 ret = DESC_RATEVHTSS1MCS5;
 321                 break;
 322         case MGN_VHT1SS_MCS6:
 323                 ret = DESC_RATEVHTSS1MCS6;
 324                 break;
 325         case MGN_VHT1SS_MCS7:
 326                 ret = DESC_RATEVHTSS1MCS7;
 327                 break;
 328         case MGN_VHT1SS_MCS8:
 329                 ret = DESC_RATEVHTSS1MCS8;
 330                 break;
 331         case MGN_VHT1SS_MCS9:
 332                 ret = DESC_RATEVHTSS1MCS9;
 333                 break;
 334         case MGN_VHT2SS_MCS0:
 335                 ret = DESC_RATEVHTSS2MCS0;
 336                 break;
 337         case MGN_VHT2SS_MCS1:
 338                 ret = DESC_RATEVHTSS2MCS1;
 339                 break;
 340         case MGN_VHT2SS_MCS2:
 341                 ret = DESC_RATEVHTSS2MCS2;
 342                 break;
 343         case MGN_VHT2SS_MCS3:
 344                 ret = DESC_RATEVHTSS2MCS3;
 345                 break;
 346         case MGN_VHT2SS_MCS4:
 347                 ret = DESC_RATEVHTSS2MCS4;
 348                 break;
 349         case MGN_VHT2SS_MCS5:
 350                 ret = DESC_RATEVHTSS2MCS5;
 351                 break;
 352         case MGN_VHT2SS_MCS6:
 353                 ret = DESC_RATEVHTSS2MCS6;
 354                 break;
 355         case MGN_VHT2SS_MCS7:
 356                 ret = DESC_RATEVHTSS2MCS7;
 357                 break;
 358         case MGN_VHT2SS_MCS8:
 359                 ret = DESC_RATEVHTSS2MCS8;
 360                 break;
 361         case MGN_VHT2SS_MCS9:
 362                 ret = DESC_RATEVHTSS2MCS9;
 363                 break;
 364         case MGN_VHT3SS_MCS0:
 365                 ret = DESC_RATEVHTSS3MCS0;
 366                 break;
 367         case MGN_VHT3SS_MCS1:
 368                 ret = DESC_RATEVHTSS3MCS1;
 369                 break;
 370         case MGN_VHT3SS_MCS2:
 371                 ret = DESC_RATEVHTSS3MCS2;
 372                 break;
 373         case MGN_VHT3SS_MCS3:
 374                 ret = DESC_RATEVHTSS3MCS3;
 375                 break;
 376         case MGN_VHT3SS_MCS4:
 377                 ret = DESC_RATEVHTSS3MCS4;
 378                 break;
 379         case MGN_VHT3SS_MCS5:
 380                 ret = DESC_RATEVHTSS3MCS5;
 381                 break;
 382         case MGN_VHT3SS_MCS6:
 383                 ret = DESC_RATEVHTSS3MCS6;
 384                 break;
 385         case MGN_VHT3SS_MCS7:
 386                 ret = DESC_RATEVHTSS3MCS7;
 387                 break;
 388         case MGN_VHT3SS_MCS8:
 389                 ret = DESC_RATEVHTSS3MCS8;
 390                 break;
 391         case MGN_VHT3SS_MCS9:
 392                 ret = DESC_RATEVHTSS3MCS9;
 393                 break;
 394         case MGN_VHT4SS_MCS0:
 395                 ret = DESC_RATEVHTSS4MCS0;
 396                 break;
 397         case MGN_VHT4SS_MCS1:
 398                 ret = DESC_RATEVHTSS4MCS1;
 399                 break;
 400         case MGN_VHT4SS_MCS2:
 401                 ret = DESC_RATEVHTSS4MCS2;
 402                 break;
 403         case MGN_VHT4SS_MCS3:
 404                 ret = DESC_RATEVHTSS4MCS3;
 405                 break;
 406         case MGN_VHT4SS_MCS4:
 407                 ret = DESC_RATEVHTSS4MCS4;
 408                 break;
 409         case MGN_VHT4SS_MCS5:
 410                 ret = DESC_RATEVHTSS4MCS5;
 411                 break;
 412         case MGN_VHT4SS_MCS6:
 413                 ret = DESC_RATEVHTSS4MCS6;
 414                 break;
 415         case MGN_VHT4SS_MCS7:
 416                 ret = DESC_RATEVHTSS4MCS7;
 417                 break;
 418         case MGN_VHT4SS_MCS8:
 419                 ret = DESC_RATEVHTSS4MCS8;
 420                 break;
 421         case MGN_VHT4SS_MCS9:
 422                 ret = DESC_RATEVHTSS4MCS9;
 423                 break;
 424         default:
 425                 break;
 426         }
 427
 428         return ret;
 429 }
 430
 431 u8 HwRateToMRate(u8 rate)
 432 {
 433         u8 ret_rate = MGN_1M;
 434
 435         switch (rate) {
 436         case DESC_RATE1M:
 437                 ret_rate = MGN_1M;
 438                 break;
 439         case DESC_RATE2M:
 440                 ret_rate = MGN_2M;
 441                 break;
 442         case DESC_RATE5_5M:
 443                 ret_rate = MGN_5_5M;
 444                 break;
 445         case DESC_RATE11M:
 446                 ret_rate = MGN_11M;
 447                 break;
 448         case DESC_RATE6M:
 449                 ret_rate = MGN_6M;
 450                 break;
 451         case DESC_RATE9M:
 452                 ret_rate = MGN_9M;
 453                 break;
 454         case DESC_RATE12M:
 455                 ret_rate = MGN_12M;
 456                 break;
 457         case DESC_RATE18M:
 458                 ret_rate = MGN_18M;
 459                 break;
 460         case DESC_RATE24M:
 461                 ret_rate = MGN_24M;
 462                 break;
 463         case DESC_RATE36M:
 464                 ret_rate = MGN_36M;
 465                 break;
 466         case DESC_RATE48M:
 467                 ret_rate = MGN_48M;
 468                 break;
 469         case DESC_RATE54M:
 470                 ret_rate = MGN_54M;
 471                 break;
 472         case DESC_RATEMCS0:
 473                 ret_rate = MGN_MCS0;
 474                 break;
 475         case DESC_RATEMCS1:
 476                 ret_rate = MGN_MCS1;
 477                 break;
 478         case DESC_RATEMCS2:
 479                 ret_rate = MGN_MCS2;
 480                 break;
 481         case DESC_RATEMCS3:
 482                 ret_rate = MGN_MCS3;
 483                 break;
 484         case DESC_RATEMCS4:
 485                 ret_rate = MGN_MCS4;
 486                 break;
 487         case DESC_RATEMCS5:
 488                 ret_rate = MGN_MCS5;
 489                 break;
 490         case DESC_RATEMCS6:
 491                 ret_rate = MGN_MCS6;
 492                 break;
 493         case DESC_RATEMCS7:
 494                 ret_rate = MGN_MCS7;
 495                 break;
 496         case DESC_RATEMCS8:
 497                 ret_rate = MGN_MCS8;
 498                 break;
 499         case DESC_RATEMCS9:
 500                 ret_rate = MGN_MCS9;
 501                 break;
 502         case DESC_RATEMCS10:
 503                 ret_rate = MGN_MCS10;
 504                 break;
 505         case DESC_RATEMCS11:
 506                 ret_rate = MGN_MCS11;
 507                 break;
 508         case DESC_RATEMCS12:
 509                 ret_rate = MGN_MCS12;
 510                 break;
 511         case DESC_RATEMCS13:
 512                 ret_rate = MGN_MCS13;
 513                 break;
 514         case DESC_RATEMCS14:
 515                 ret_rate = MGN_MCS14;
 516                 break;
 517         case DESC_RATEMCS15:
 518                 ret_rate = MGN_MCS15;
 519                 break;
 520         case DESC_RATEMCS16:
 521                 ret_rate = MGN_MCS16;
 522                 break;
 523         case DESC_RATEMCS17:
 524                 ret_rate = MGN_MCS17;
 525                 break;
 526         case DESC_RATEMCS18:
 527                 ret_rate = MGN_MCS18;
 528                 break;
 529         case DESC_RATEMCS19:
 530                 ret_rate = MGN_MCS19;
 531                 break;
 532         case DESC_RATEMCS20:
 533                 ret_rate = MGN_MCS20;
 534                 break;
 535         case DESC_RATEMCS21:
 536                 ret_rate = MGN_MCS21;
 537                 break;
 538         case DESC_RATEMCS22:
 539                 ret_rate = MGN_MCS22;
 540                 break;
 541         case DESC_RATEMCS23:
 542                 ret_rate = MGN_MCS23;
 543                 break;
 544         case DESC_RATEMCS24:
 545                 ret_rate = MGN_MCS24;
 546                 break;
 547         case DESC_RATEMCS25:
 548                 ret_rate = MGN_MCS25;
 549                 break;
 550         case DESC_RATEMCS26:
 551                 ret_rate = MGN_MCS26;
 552                 break;
 553         case DESC_RATEMCS27:
 554                 ret_rate = MGN_MCS27;
 555                 break;
 556         case DESC_RATEMCS28:
 557                 ret_rate = MGN_MCS28;
 558                 break;
 559         case DESC_RATEMCS29:
 560                 ret_rate = MGN_MCS29;
 561                 break;
 562         case DESC_RATEMCS30:
 563                 ret_rate = MGN_MCS30;
 564                 break;
 565         case DESC_RATEMCS31:
 566                 ret_rate = MGN_MCS31;
 567                 break;
 568         case DESC_RATEVHTSS1MCS0:
 569                 ret_rate = MGN_VHT1SS_MCS0;
 570                 break;
 571         case DESC_RATEVHTSS1MCS1:
 572                 ret_rate = MGN_VHT1SS_MCS1;
 573                 break;
 574         case DESC_RATEVHTSS1MCS2:
 575                 ret_rate = MGN_VHT1SS_MCS2;
 576                 break;
 577         case DESC_RATEVHTSS1MCS3:
 578                 ret_rate = MGN_VHT1SS_MCS3;
 579                 break;
 580         case DESC_RATEVHTSS1MCS4:
 581                 ret_rate = MGN_VHT1SS_MCS4;
 582                 break;
 583         case DESC_RATEVHTSS1MCS5:
 584                 ret_rate = MGN_VHT1SS_MCS5;
 585                 break;
 586         case DESC_RATEVHTSS1MCS6:
 587                 ret_rate = MGN_VHT1SS_MCS6;
 588                 break;
 589         case DESC_RATEVHTSS1MCS7:
 590                 ret_rate = MGN_VHT1SS_MCS7;
 591                 break;
 592         case DESC_RATEVHTSS1MCS8:
 593                 ret_rate = MGN_VHT1SS_MCS8;
 594                 break;
 595         case DESC_RATEVHTSS1MCS9:
 596                 ret_rate = MGN_VHT1SS_MCS9;
 597                 break;
 598         case DESC_RATEVHTSS2MCS0:
 599                 ret_rate = MGN_VHT2SS_MCS0;
 600                 break;
 601         case DESC_RATEVHTSS2MCS1:
 602                 ret_rate = MGN_VHT2SS_MCS1;
 603                 break;
 604         case DESC_RATEVHTSS2MCS2:
 605                 ret_rate = MGN_VHT2SS_MCS2;
 606                 break;
 607         case DESC_RATEVHTSS2MCS3:
 608                 ret_rate = MGN_VHT2SS_MCS3;
 609                 break;
 610         case DESC_RATEVHTSS2MCS4:
 611                 ret_rate = MGN_VHT2SS_MCS4;
 612                 break;
 613         case DESC_RATEVHTSS2MCS5:
 614                 ret_rate = MGN_VHT2SS_MCS5;
 615                 break;
 616         case DESC_RATEVHTSS2MCS6:
 617                 ret_rate = MGN_VHT2SS_MCS6;
 618                 break;
 619         case DESC_RATEVHTSS2MCS7:
 620                 ret_rate = MGN_VHT2SS_MCS7;
 621                 break;
 622         case DESC_RATEVHTSS2MCS8:
 623                 ret_rate = MGN_VHT2SS_MCS8;
 624                 break;
 625         case DESC_RATEVHTSS2MCS9:
 626                 ret_rate = MGN_VHT2SS_MCS9;
 627                 break;
 628         case DESC_RATEVHTSS3MCS0:
 629                 ret_rate = MGN_VHT3SS_MCS0;
 630                 break;
 631         case DESC_RATEVHTSS3MCS1:
 632                 ret_rate = MGN_VHT3SS_MCS1;
 633                 break;
 634         case DESC_RATEVHTSS3MCS2:
 635                 ret_rate = MGN_VHT3SS_MCS2;
 636                 break;
 637         case DESC_RATEVHTSS3MCS3:
 638                 ret_rate = MGN_VHT3SS_MCS3;
 639                 break;
 640         case DESC_RATEVHTSS3MCS4:
 641                 ret_rate = MGN_VHT3SS_MCS4;
 642                 break;
 643         case DESC_RATEVHTSS3MCS5:
 644                 ret_rate = MGN_VHT3SS_MCS5;
 645                 break;
 646         case DESC_RATEVHTSS3MCS6:
 647                 ret_rate = MGN_VHT3SS_MCS6;
 648                 break;
 649         case DESC_RATEVHTSS3MCS7:
 650                 ret_rate = MGN_VHT3SS_MCS7;
 651                 break;
 652         case DESC_RATEVHTSS3MCS8:
 653                 ret_rate = MGN_VHT3SS_MCS8;
 654                 break;
 655         case DESC_RATEVHTSS3MCS9:
 656                 ret_rate = MGN_VHT3SS_MCS9;
 657                 break;
 658         case DESC_RATEVHTSS4MCS0:
 659                 ret_rate = MGN_VHT4SS_MCS0;
 660                 break;
 661         case DESC_RATEVHTSS4MCS1:
 662                 ret_rate = MGN_VHT4SS_MCS1;
 663                 break;
 664         case DESC_RATEVHTSS4MCS2:
 665                 ret_rate = MGN_VHT4SS_MCS2;
 666                 break;
 667         case DESC_RATEVHTSS4MCS3:
 668                 ret_rate = MGN_VHT4SS_MCS3;
 669                 break;
 670         case DESC_RATEVHTSS4MCS4:
 671                 ret_rate = MGN_VHT4SS_MCS4;
 672                 break;
 673         case DESC_RATEVHTSS4MCS5:
 674                 ret_rate = MGN_VHT4SS_MCS5;
 675                 break;
 676         case DESC_RATEVHTSS4MCS6:
 677                 ret_rate = MGN_VHT4SS_MCS6;
 678                 break;
 679         case DESC_RATEVHTSS4MCS7:
 680                 ret_rate = MGN_VHT4SS_MCS7;
 681                 break;
 682         case DESC_RATEVHTSS4MCS8:
 683                 ret_rate = MGN_VHT4SS_MCS8;
 684                 break;
 685         case DESC_RATEVHTSS4MCS9:
 686                 ret_rate = MGN_VHT4SS_MCS9;
 687                 break;
 688
 689         default:
 690                 DBG_871X("HwRateToMRate(): Non supported Rate [%x]!!!\n", rate);
 691                 break;
 692         }
 693
 694         return ret_rate;
 695 }
 696
 697 void HalSetBrateCfg(struct adapter *Adapter, u8 *mBratesOS, u16 *pBrateCfg)
 698 {
 699         u8 i, is_brate, brate;
 700
 701         for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
 702
 703                 is_brate = mBratesOS[i] & IEEE80211_BASIC_RATE_MASK;
 704                 brate = mBratesOS[i] & 0x7f;
 705
 706                 if (is_brate) {
 707                         switch (brate) {
 708                         case IEEE80211_CCK_RATE_1MB:
 709                                 *pBrateCfg |= RATE_1M;
 710                                 break;
 711                         case IEEE80211_CCK_RATE_2MB:
 712                                 *pBrateCfg |= RATE_2M;
 713                                 break;
 714                         case IEEE80211_CCK_RATE_5MB:
 715                                 *pBrateCfg |= RATE_5_5M;
 716                                 break;
 717                         case IEEE80211_CCK_RATE_11MB:
 718                                 *pBrateCfg |= RATE_11M;
 719                                 break;
 720                         case IEEE80211_OFDM_RATE_6MB:
 721                                 *pBrateCfg |= RATE_6M;
 722                                 break;
 723                         case IEEE80211_OFDM_RATE_9MB:
 724                                 *pBrateCfg |= RATE_9M;
 725                                 break;
 726                         case IEEE80211_OFDM_RATE_12MB:
 727                                 *pBrateCfg |= RATE_12M;
 728                                 break;
 729                         case IEEE80211_OFDM_RATE_18MB:
 730                                 *pBrateCfg |= RATE_18M;
 731                                 break;
 732                         case IEEE80211_OFDM_RATE_24MB:
 733                                 *pBrateCfg |= RATE_24M;
 734                                 break;
 735                         case IEEE80211_OFDM_RATE_36MB:
 736                                 *pBrateCfg |= RATE_36M;
 737                                 break;
 738                         case IEEE80211_OFDM_RATE_48MB:
 739                                 *pBrateCfg |= RATE_48M;
 740                                 break;
 741                         case IEEE80211_OFDM_RATE_54MB:
 742                                 *pBrateCfg |= RATE_54M;
 743                                 break;
 744                         }
 745                 }
 746         }
 747 }
 748
 749 static void _OneOutPipeMapping(struct adapter *padapter)
 750 {
 751         struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
 752
 753         pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
 754         pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
 755         pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];/* BE */
 756         pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
 757
 758         pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
 759         pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
 760         pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
 761         pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
 762 }
 763
 764 static void _TwoOutPipeMapping(struct adapter *padapter, bool bWIFICfg)
 765 {
 766         struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
 767
 768         if (bWIFICfg) { /* WMM */
 769
 770                 /*      BK,     BE,     VI,     VO,     BCN,    CMD, MGT, HIGH, HCCA */
 771                 /*   0,         1,      0,      1,      0,      0,      0,      0,              0       }; */
 772                 /* 0:ep_0 num, 1:ep_1 num */
 773
 774                 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];/* VO */
 775                 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
 776                 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
 777                 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
 778
 779                 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
 780                 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
 781                 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
 782                 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
 783
 784         } else { /* typical setting */
 785
 786
 787                 /* BK,  BE,     VI,     VO,     BCN,    CMD, MGT, HIGH, HCCA */
 788                 /*   1,         1,      0,      0,      0,      0,      0,      0,              0       }; */
 789                 /* 0:ep_0 num, 1:ep_1 num */
 790
 791                 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
 792                 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
 793                 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
 794                 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
 795
 796                 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
 797                 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
 798                 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
 799                 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
 800
 801         }
 802
 803 }
 804
 805 static void _ThreeOutPipeMapping(struct adapter *padapter, bool bWIFICfg)
 806 {
 807         struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
 808
 809         if (bWIFICfg) { /* for WMM */
 810
 811                 /*      BK,     BE,     VI,     VO,     BCN,    CMD, MGT, HIGH, HCCA */
 812                 /*   1,         2,      1,      0,      0,      0,      0,      0,              0       }; */
 813                 /* 0:H, 1:N, 2:L */
 814
 815                 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
 816                 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
 817                 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
 818                 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
 819
 820                 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
 821                 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
 822                 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
 823                 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
 824
 825         } else { /* typical setting */
 826
 827
 828                 /*      BK,     BE,     VI,     VO,     BCN,    CMD, MGT, HIGH, HCCA */
 829                 /*   2,         2,      1,      0,      0,      0,      0,      0,              0       }; */
 830                 /* 0:H, 1:N, 2:L */
 831
 832                 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
 833                 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
 834                 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
 835                 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];/* BK */
 836
 837                 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
 838                 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
 839                 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
 840                 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
 841         }
 842
 843 }
 844
 845 bool Hal_MappingOutPipe(struct adapter *padapter, u8 NumOutPipe)
 846 {
 847         struct registry_priv *pregistrypriv = &padapter->registrypriv;
 848
 849         bool bWIFICfg = (pregistrypriv->wifi_spec) ? true : false;
 850
 851         bool result = true;
 852
 853         switch (NumOutPipe) {
 854         case 2:
 855                 _TwoOutPipeMapping(padapter, bWIFICfg);
 856                 break;
 857         case 3:
 858         case 4:
 859                 _ThreeOutPipeMapping(padapter, bWIFICfg);
 860                 break;
 861         case 1:
 862                 _OneOutPipeMapping(padapter);
 863                 break;
 864         default:
 865                 result = false;
 866                 break;
 867         }
 868
 869         return result;
 870
 871 }
 872
 873 void hal_init_macaddr(struct adapter *adapter)
 874 {
 875         rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter->eeprompriv.mac_addr);
 876 }
 877
 878 void rtw_init_hal_com_default_value(struct adapter *Adapter)
 879 {
 880         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 881
 882         pHalData->AntDetection = 1;
 883 }
 884
 885 /*
 886 * C2H event format:
 887 * Field  TRIGGER                CONTENT    CMD_SEQ      CMD_LEN          CMD_ID
 888 * BITS   [127:120]      [119:16]      [15:8]              [7:4]            [3:0]
 889 */
 890
 891 void c2h_evt_clear(struct adapter *adapter)
 892 {
 893         rtw_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
 894 }
 895
 896 /*
 897 * C2H event format:
 898 * Field    TRIGGER    CMD_LEN    CONTENT    CMD_SEQ    CMD_ID
 899 * BITS    [127:120]   [119:112]    [111:16]          [15:8]         [7:0]
 900 */
 901 s32 c2h_evt_read_88xx(struct adapter *adapter, u8 *buf)
 902 {
 903         s32 ret = _FAIL;
 904         struct c2h_evt_hdr_88xx *c2h_evt;
 905         int i;
 906         u8 trigger;
 907
 908         if (!buf)
 909                 goto exit;
 910
 911         trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR);
 912
 913         if (trigger == C2H_EVT_HOST_CLOSE)
 914                 goto exit; /* Not ready */
 915         else if (trigger != C2H_EVT_FW_CLOSE)
 916                 goto clear_evt; /* Not a valid value */
 917
 918         c2h_evt = (struct c2h_evt_hdr_88xx *)buf;
 919
 920         memset(c2h_evt, 0, 16);
 921
 922         c2h_evt->id = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL);
 923         c2h_evt->seq = rtw_read8(adapter, REG_C2HEVT_CMD_SEQ_88XX);
 924         c2h_evt->plen = rtw_read8(adapter, REG_C2HEVT_CMD_LEN_88XX);
 925
 926         RT_PRINT_DATA(
 927                 _module_hal_init_c_,
 928                 _drv_info_,
 929                 "c2h_evt_read(): ",
 930                 &c2h_evt,
 931                 sizeof(c2h_evt)
 932         );
 933
 934         DBG_871X(
 935                 "%s id:%u, len:%u, seq:%u, trigger:0x%02x\n",
 936                 __func__,
 937                 c2h_evt->id,
 938                 c2h_evt->plen,
 939                 c2h_evt->seq,
 940                 trigger
 941         );
 942
 943         /* Read the content */
 944         for (i = 0; i < c2h_evt->plen; i++)
 945                 c2h_evt->payload[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i);
 946
 947         RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): Command Content:\n",
 948                 c2h_evt->payload, c2h_evt->plen);
 949
 950         ret = _SUCCESS;
 951
 952 clear_evt:
 953         /*
 954         * Clear event to notify FW we have read the command.
 955         * If this field isn't clear, the FW won't update the next command message.
 956         */
 957         c2h_evt_clear(adapter);
 958 exit:
 959         return ret;
 960 }
 961
 962 u8 rtw_get_mgntframe_raid(struct adapter *adapter, unsigned char network_type)
 963 {
 964         return (network_type & WIRELESS_11B) ? RATEID_IDX_B : RATEID_IDX_G;
 965 }
 966
 967 void rtw_hal_update_sta_rate_mask(struct adapter *padapter, struct sta_info *psta)
 968 {
 969         u8 i, rf_type, limit;
 970         u32 tx_ra_bitmap;
 971
 972         if (!psta)
 973                 return;
 974
 975         tx_ra_bitmap = 0;
 976
 977         /* b/g mode ra_bitmap */
 978         for (i = 0; i < sizeof(psta->bssrateset); i++) {
 979                 if (psta->bssrateset[i])
 980                         tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i]&0x7f);
 981         }
 982
 983         /* n mode ra_bitmap */
 984         if (psta->htpriv.ht_option) {
 985                 rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
 986                 if (rf_type == RF_2T2R)
 987                         limit = 16; /*  2R */
 988                 else
 989                         limit = 8; /*   1R */
 990
 991                 for (i = 0; i < limit; i++) {
 992                         if (psta->htpriv.ht_cap.supp_mcs_set[i/8] & BIT(i%8))
 993                                 tx_ra_bitmap |= BIT(i+12);
 994                 }
 995         }
 996
 997         psta->ra_mask = tx_ra_bitmap;
 998         psta->init_rate = get_highest_rate_idx(tx_ra_bitmap)&0x3f;
 999 }
1000
1001 void hw_var_port_switch(struct adapter *adapter)
1002 {
1003 }
1004
1005 void SetHwReg(struct adapter *adapter, u8 variable, u8 *val)
1006 {
1007         struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
1008         DM_ODM_T *odm = &(hal_data->odmpriv);
1009
1010         switch (variable) {
1011         case HW_VAR_PORT_SWITCH:
1012                 hw_var_port_switch(adapter);
1013                 break;
1014         case HW_VAR_INIT_RTS_RATE:
1015                 rtw_warn_on(1);
1016                 break;
1017         case HW_VAR_SEC_CFG:
1018         {
1019                 u16 reg_scr;
1020
1021                 reg_scr = rtw_read16(adapter, REG_SECCFG);
1022                 rtw_write16(adapter, REG_SECCFG, reg_scr|SCR_CHK_KEYID|SCR_RxDecEnable|SCR_TxEncEnable);
1023         }
1024                 break;
1025         case HW_VAR_SEC_DK_CFG:
1026         {
1027                 struct security_priv *sec = &adapter->securitypriv;
1028                 u8 reg_scr = rtw_read8(adapter, REG_SECCFG);
1029
1030                 if (val) { /* Enable default key related setting */
1031                         reg_scr |= SCR_TXBCUSEDK;
1032                         if (sec->dot11AuthAlgrthm != dot11AuthAlgrthm_8021X)
1033                                 reg_scr |= (SCR_RxUseDK|SCR_TxUseDK);
1034                 } else /* Disable default key related setting */
1035                         reg_scr &= ~(SCR_RXBCUSEDK|SCR_TXBCUSEDK|SCR_RxUseDK|SCR_TxUseDK);
1036
1037                 rtw_write8(adapter, REG_SECCFG, reg_scr);
1038         }
1039                 break;
1040         case HW_VAR_DM_FLAG:
1041                 odm->SupportAbility = *((u32 *)val);
1042                 break;
1043         case HW_VAR_DM_FUNC_OP:
1044                 if (*((u8 *)val) == true) {
1045                         /* save dm flag */
1046                         odm->BK_SupportAbility = odm->SupportAbility;
1047                 } else {
1048                         /* restore dm flag */
1049                         odm->SupportAbility = odm->BK_SupportAbility;
1050                 }
1051                 break;
1052         case HW_VAR_DM_FUNC_SET:
1053                 if (*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE) {
1054                         struct dm_priv *dm = &hal_data->dmpriv;
1055                         dm->DMFlag = dm->InitDMFlag;
1056                         odm->SupportAbility = dm->InitODMFlag;
1057                 } else {
1058                         odm->SupportAbility |= *((u32 *)val);
1059                 }
1060                 break;
1061         case HW_VAR_DM_FUNC_CLR:
1062                 /*
1063                 * input is already a mask to clear function
1064                 * don't invert it again! George, Lucas@20130513
1065                 */
1066                 odm->SupportAbility &= *((u32 *)val);
1067                 break;
1068         case HW_VAR_AMPDU_MIN_SPACE:
1069                 /* TODO - Is something needed here? */
1070                 break;
1071         case HW_VAR_WIRELESS_MODE:
1072                 /* TODO - Is something needed here? */
1073                 break;
1074         default:
1075                 DBG_871X_LEVEL(
1076                         _drv_always_,
1077                         FUNC_ADPT_FMT" variable(%d) not defined!\n",
1078                         FUNC_ADPT_ARG(adapter),
1079                         variable
1080                 );
1081                 break;
1082         }
1083 }
1084
1085 void GetHwReg(struct adapter *adapter, u8 variable, u8 *val)
1086 {
1087         struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
1088         DM_ODM_T *odm = &(hal_data->odmpriv);
1089
1090         switch (variable) {
1091         case HW_VAR_BASIC_RATE:
1092                 *((u16 *)val) = hal_data->BasicRateSet;
1093                 break;
1094         case HW_VAR_DM_FLAG:
1095                 *((u32 *)val) = odm->SupportAbility;
1096                 break;
1097         case HW_VAR_RF_TYPE:
1098                 *((u8 *)val) = hal_data->rf_type;
1099                 break;
1100         default:
1101                 DBG_871X_LEVEL(
1102                         _drv_always_,
1103                         FUNC_ADPT_FMT" variable(%d) not defined!\n",
1104                         FUNC_ADPT_ARG(adapter),
1105                         variable
1106                 );
1107                 break;
1108         }
1109 }
1110
1111
1112
1113
1114 u8 SetHalDefVar(
1115         struct adapter *adapter, enum HAL_DEF_VARIABLE variable, void *value
1116 )
1117 {
1118         struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
1119         DM_ODM_T *odm = &(hal_data->odmpriv);
1120         u8 bResult = _SUCCESS;
1121
1122         switch (variable) {
1123         case HW_DEF_FA_CNT_DUMP:
1124                 /* ODM_COMP_COMMON */
1125                 if (*((u8 *)value))
1126                         odm->DebugComponents |= (ODM_COMP_DIG | ODM_COMP_FA_CNT);
1127                 else
1128                         odm->DebugComponents &= ~(ODM_COMP_DIG | ODM_COMP_FA_CNT);
1129                 break;
1130         case HAL_DEF_DBG_RX_INFO_DUMP:
1131                 DBG_871X("============ Rx Info dump ===================\n");
1132                 DBG_871X("bLinked = %d, RSSI_Min = %d(%%)\n",
1133                         odm->bLinked, odm->RSSI_Min);
1134
1135                 if (odm->bLinked) {
1136                         DBG_871X("RxRate = %s, RSSI_A = %d(%%), RSSI_B = %d(%%)\n",
1137                                 HDATA_RATE(odm->RxRate), odm->RSSI_A, odm->RSSI_B);
1138
1139                         #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
1140                         rtw_dump_raw_rssi_info(adapter);
1141                         #endif
1142                 }
1143                 break;
1144         case HW_DEF_ODM_DBG_FLAG:
1145                 ODM_CmnInfoUpdate(odm, ODM_CMNINFO_DBG_COMP, *((u64 *)value));
1146                 break;
1147         case HW_DEF_ODM_DBG_LEVEL:
1148                 ODM_CmnInfoUpdate(odm, ODM_CMNINFO_DBG_LEVEL, *((u32 *)value));
1149                 break;
1150         case HAL_DEF_DBG_DM_FUNC:
1151         {
1152                 u8 dm_func = *((u8 *)value);
1153                 struct dm_priv *dm = &hal_data->dmpriv;
1154
1155                 if (dm_func == 0) { /* disable all dynamic func */
1156                         odm->SupportAbility = DYNAMIC_FUNC_DISABLE;
1157                         DBG_8192C("==> Disable all dynamic function...\n");
1158                 } else if (dm_func == 1) {/* disable DIG */
1159                         odm->SupportAbility  &= (~DYNAMIC_BB_DIG);
1160                         DBG_8192C("==> Disable DIG...\n");
1161                 } else if (dm_func == 2) {/* disable High power */
1162                         odm->SupportAbility  &= (~DYNAMIC_BB_DYNAMIC_TXPWR);
1163                 } else if (dm_func == 3) {/* disable tx power tracking */
1164                         odm->SupportAbility  &= (~DYNAMIC_RF_CALIBRATION);
1165                         DBG_8192C("==> Disable tx power tracking...\n");
1166                 } else if (dm_func == 4) {/* disable BT coexistence */
1167                         dm->DMFlag &= (~DYNAMIC_FUNC_BT);
1168                 } else if (dm_func == 5) {/* disable antenna diversity */
1169                         odm->SupportAbility  &= (~DYNAMIC_BB_ANT_DIV);
1170                 } else if (dm_func == 6) {/* turn on all dynamic func */
1171                         if (!(odm->SupportAbility  & DYNAMIC_BB_DIG)) {
1172                                 DIG_T   *pDigTable = &odm->DM_DigTable;
1173                                 pDigTable->CurIGValue = rtw_read8(adapter, 0xc50);
1174                         }
1175                         dm->DMFlag |= DYNAMIC_FUNC_BT;
1176                         odm->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE;
1177                         DBG_8192C("==> Turn on all dynamic function...\n");
1178                 }
1179         }
1180                 break;
1181         case HAL_DEF_DBG_DUMP_RXPKT:
1182                 hal_data->bDumpRxPkt = *((u8 *)value);
1183                 break;
1184         case HAL_DEF_DBG_DUMP_TXPKT:
1185                 hal_data->bDumpTxPkt = *((u8 *)value);
1186                 break;
1187         case HAL_DEF_ANT_DETECT:
1188                 hal_data->AntDetection = *((u8 *)value);
1189                 break;
1190         default:
1191                 DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __func__, variable);
1192                 bResult = _FAIL;
1193                 break;
1194         }
1195
1196         return bResult;
1197 }
1198
1199 u8 GetHalDefVar(
1200         struct adapter *adapter, enum HAL_DEF_VARIABLE variable, void *value
1201 )
1202 {
1203         struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
1204         DM_ODM_T *odm = &(hal_data->odmpriv);
1205         u8 bResult = _SUCCESS;
1206
1207         switch (variable) {
1208         case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
1209                 {
1210                         struct mlme_priv *pmlmepriv;
1211                         struct sta_priv *pstapriv;
1212                         struct sta_info *psta;
1213
1214                         pmlmepriv = &adapter->mlmepriv;
1215                         pstapriv = &adapter->stapriv;
1216                         psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
1217                         if (psta)
1218                                 *((int *)value) = psta->rssi_stat.UndecoratedSmoothedPWDB;
1219                 }
1220                 break;
1221         case HW_DEF_ODM_DBG_FLAG:
1222                 *((u64 *)value) = odm->DebugComponents;
1223                 break;
1224         case HW_DEF_ODM_DBG_LEVEL:
1225                 *((u32 *)value) = odm->DebugLevel;
1226                 break;
1227         case HAL_DEF_DBG_DM_FUNC:
1228                 *((u32 *)value) = hal_data->odmpriv.SupportAbility;
1229                 break;
1230         case HAL_DEF_DBG_DUMP_RXPKT:
1231                 *((u8 *)value) = hal_data->bDumpRxPkt;
1232                 break;
1233         case HAL_DEF_DBG_DUMP_TXPKT:
1234                 *((u8 *)value) = hal_data->bDumpTxPkt;
1235                 break;
1236         case HAL_DEF_ANT_DETECT:
1237                 *((u8 *)value) = hal_data->AntDetection;
1238                 break;
1239         case HAL_DEF_MACID_SLEEP:
1240                 *(u8 *)value = false;
1241                 break;
1242         case HAL_DEF_TX_PAGE_SIZE:
1243                 *((u32 *)value) = PAGE_SIZE_128;
1244                 break;
1245         default:
1246                 DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __func__, variable);
1247                 bResult = _FAIL;
1248                 break;
1249         }
1250
1251         return bResult;
1252 }
1253
1254 void GetHalODMVar(
1255         struct adapter *Adapter,
1256         enum HAL_ODM_VARIABLE eVariable,
1257         void *pValue1,
1258         void *pValue2
1259 )
1260 {
1261         switch (eVariable) {
1262 #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
1263         case HAL_ODM_NOISE_MONITOR:
1264                 {
1265                         struct hal_com_data     *pHalData = GET_HAL_DATA(Adapter);
1266                         u8 chan = *(u8 *)pValue1;
1267                         *(s16 *)pValue2 = pHalData->noise[chan];
1268                         #ifdef DBG_NOISE_MONITOR
1269                         DBG_8192C("### Noise monitor chan(%d)-noise:%d (dBm) ###\n",
1270                                 chan, pHalData->noise[chan]);
1271                         #endif
1272
1273                 }
1274                 break;
1275 #endif/* ifdef CONFIG_BACKGROUND_NOISE_MONITOR */
1276         default:
1277                 break;
1278         }
1279 }
1280
1281 void SetHalODMVar(
1282         struct adapter *Adapter,
1283         enum HAL_ODM_VARIABLE eVariable,
1284         void *pValue1,
1285         bool bSet
1286 )
1287 {
1288         struct hal_com_data     *pHalData = GET_HAL_DATA(Adapter);
1289         PDM_ODM_T podmpriv = &pHalData->odmpriv;
1290         /* _irqL irqL; */
1291         switch (eVariable) {
1292         case HAL_ODM_STA_INFO:
1293                 {
1294                         struct sta_info *psta = pValue1;
1295                         if (bSet) {
1296                                 DBG_8192C("### Set STA_(%d) info ###\n", psta->mac_id);
1297                                 ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, psta);
1298                         } else {
1299                                 DBG_8192C("### Clean STA_(%d) info ###\n", psta->mac_id);
1300                                 /* spin_lock_bh(&pHalData->odm_stainfo_lock); */
1301                                 ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, NULL);
1302
1303                                 /* spin_unlock_bh(&pHalData->odm_stainfo_lock); */
1304                     }
1305                 }
1306                 break;
1307         case HAL_ODM_P2P_STATE:
1308                         ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
1309                 break;
1310         case HAL_ODM_WIFI_DISPLAY_STATE:
1311                         ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
1312                 break;
1313         #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
1314         case HAL_ODM_NOISE_MONITOR:
1315                 {
1316                         struct noise_info *pinfo = pValue1;
1317
1318                         #ifdef DBG_NOISE_MONITOR
1319                         DBG_8192C("### Noise monitor chan(%d)-bPauseDIG:%d, IGIValue:0x%02x, max_time:%d (ms) ###\n",
1320                                 pinfo->chan, pinfo->bPauseDIG, pinfo->IGIValue, pinfo->max_time);
1321                         #endif
1322
1323                         pHalData->noise[pinfo->chan] = ODM_InbandNoise_Monitor(podmpriv, pinfo->bPauseDIG, pinfo->IGIValue, pinfo->max_time);
1324                         DBG_871X("chan_%d, noise = %d (dBm)\n", pinfo->chan, pHalData->noise[pinfo->chan]);
1325                         #ifdef DBG_NOISE_MONITOR
1326                         DBG_871X("noise_a = %d, noise_b = %d  noise_all:%d\n",
1327                                 podmpriv->noise_level.noise[ODM_RF_PATH_A],
1328                                 podmpriv->noise_level.noise[ODM_RF_PATH_B],
1329                                 podmpriv->noise_level.noise_all);
1330                         #endif
1331                 }
1332                 break;
1333         #endif/* ifdef CONFIG_BACKGROUND_NOISE_MONITOR */
1334
1335         default:
1336                 break;
1337         }
1338 }
1339
1340
1341 bool eqNByte(u8 *str1, u8 *str2, u32 num)
1342 {
1343         if (num == 0)
1344                 return false;
1345         while (num > 0) {
1346                 num--;
1347                 if (str1[num] != str2[num])
1348                         return false;
1349         }
1350         return true;
1351 }
1352
1353 /*  */
1354 /*      Description: */
1355 /*              Return true if chTmp is represent for hex digit and */
1356 /*              false otherwise. */
1357 /*  */
1358 /*  */
1359 bool IsHexDigit(char chTmp)
1360 {
1361         if (
1362                 (chTmp >= '0' && chTmp <= '9') ||
1363                 (chTmp >= 'a' && chTmp <= 'f') ||
1364                 (chTmp >= 'A' && chTmp <= 'F')
1365         )
1366                 return true;
1367         else
1368                 return false;
1369 }
1370
1371
1372 /*  */
1373 /*      Description: */
1374 /*              Translate a character to hex digit. */
1375 /*  */
1376 u32 MapCharToHexDigit(char chTmp)
1377 {
1378         if (chTmp >= '0' && chTmp <= '9')
1379                 return chTmp - '0';
1380         else if (chTmp >= 'a' && chTmp <= 'f')
1381                 return 10 + (chTmp - 'a');
1382         else if (chTmp >= 'A' && chTmp <= 'F')
1383                 return 10 + (chTmp - 'A');
1384         else
1385                 return 0;
1386 }
1387
1388
1389
1390 /*      Description: */
1391 /*              Parse hex number from the string pucStr. */
1392 bool GetHexValueFromString(char *szStr, u32 *pu4bVal, u32 *pu4bMove)
1393 {
1394         char *szScan = szStr;
1395
1396         /*  Check input parameter. */
1397         if (!szStr || !pu4bVal || !pu4bMove) {
1398                 DBG_871X("GetHexValueFromString(): Invalid input arguments! szStr: %p, pu4bVal: %p, pu4bMove: %p\n",
1399                          szStr, pu4bVal, pu4bMove);
1400                 return false;
1401         }
1402
1403         /*  Initialize output. */
1404         *pu4bMove = 0;
1405         *pu4bVal = 0;
1406
1407         /*  Skip leading space. */
1408         while (*szScan != '\0' && (*szScan == ' ' || *szScan == '\t')) {
1409                 szScan++;
1410                 (*pu4bMove)++;
1411         }
1412
1413         /*  Skip leading '0x' or '0X'. */
1414         if (*szScan == '0' && (*(szScan+1) == 'x' || *(szScan+1) == 'X')) {
1415                 szScan += 2;
1416                 (*pu4bMove) += 2;
1417         }
1418
1419         /*  Check if szScan is now pointer to a character for hex digit, */
1420         /*  if not, it means this is not a valid hex number. */
1421         if (!IsHexDigit(*szScan))
1422                 return false;
1423
1424         /*  Parse each digit. */
1425         do {
1426                 (*pu4bVal) <<= 4;
1427                 *pu4bVal += MapCharToHexDigit(*szScan);
1428
1429                 szScan++;
1430                 (*pu4bMove)++;
1431         } while (IsHexDigit(*szScan));
1432
1433         return true;
1434 }
1435
1436 bool GetFractionValueFromString(
1437         char *szStr, u8 *pInteger, u8 *pFraction, u32 *pu4bMove
1438 )
1439 {
1440         char *szScan = szStr;
1441
1442         /*  Initialize output. */
1443         *pu4bMove = 0;
1444         *pInteger = 0;
1445         *pFraction = 0;
1446
1447         /*  Skip leading space. */
1448         while (*szScan != '\0' &&       (*szScan == ' ' || *szScan == '\t')) {
1449                 ++szScan;
1450                 ++(*pu4bMove);
1451         }
1452
1453         /*  Parse each digit. */
1454         do {
1455                 (*pInteger) *= 10;
1456                 *pInteger += (*szScan - '0');
1457
1458                 ++szScan;
1459                 ++(*pu4bMove);
1460
1461                 if (*szScan == '.') {
1462                         ++szScan;
1463                         ++(*pu4bMove);
1464
1465                         if (*szScan < '0' || *szScan > '9')
1466                                 return false;
1467                         else {
1468                                 *pFraction = *szScan - '0';
1469                                 ++szScan;
1470                                 ++(*pu4bMove);
1471                                 return true;
1472                         }
1473                 }
1474         } while (*szScan >= '0' && *szScan <= '9');
1475
1476         return true;
1477 }
1478
1479 /*  */
1480 /*      Description: */
1481 /*              Return true if szStr is comment out with leading "//". */
1482 /*  */
1483 bool IsCommentString(char *szStr)
1484 {
1485         if (*szStr == '/' && *(szStr+1) == '/')
1486                 return true;
1487         else
1488                 return false;
1489 }
1490
1491 bool GetU1ByteIntegerFromStringInDecimal(char *Str, u8 *pInt)
1492 {
1493         u16 i = 0;
1494         *pInt = 0;
1495
1496         while (Str[i] != '\0') {
1497                 if (Str[i] >= '0' && Str[i] <= '9') {
1498                         *pInt *= 10;
1499                         *pInt += (Str[i] - '0');
1500                 } else
1501                         return false;
1502
1503                 ++i;
1504         }
1505
1506         return true;
1507 }
1508
1509 /*  <20121004, Kordan> For example,
1510  *  ParseQualifiedString(inString, 0, outString, '[', ']') gets "Kordan" from
1511  *  a string "Hello [Kordan]".
1512  *  If RightQualifier does not exist, it will hang in the while loop
1513  */
1514 bool ParseQualifiedString(
1515         char *In, u32 *Start, char *Out, char LeftQualifier, char RightQualifier
1516 )
1517 {
1518         u32 i = 0, j = 0;
1519         char c = In[(*Start)++];
1520
1521         if (c != LeftQualifier)
1522                 return false;
1523
1524         i = (*Start);
1525         while ((c = In[(*Start)++]) != RightQualifier)
1526                 ; /*  find ']' */
1527         j = (*Start) - 2;
1528         strncpy((char *)Out, (const char *)(In+i), j-i+1);
1529
1530         return true;
1531 }
1532
1533 bool isAllSpaceOrTab(u8 *data, u8 size)
1534 {
1535         u8 cnt = 0, NumOfSpaceAndTab = 0;
1536
1537         while (size > cnt) {
1538                 if (data[cnt] == ' ' || data[cnt] == '\t' || data[cnt] == '\0')
1539                         ++NumOfSpaceAndTab;
1540
1541                 ++cnt;
1542         }
1543
1544         return size == NumOfSpaceAndTab;
1545 }
1546
1547
1548 void rtw_hal_check_rxfifo_full(struct adapter *adapter)
1549 {
1550         struct dvobj_priv *psdpriv = adapter->dvobj;
1551         struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
1552         int save_cnt = false;
1553
1554         /* switch counter to RX fifo */
1555         /* printk("8723b or 8192e , MAC_667 set 0xf0\n"); */
1556         rtw_write8(adapter, REG_RXERR_RPT+3, rtw_read8(adapter, REG_RXERR_RPT+3)|0xf0);
1557         save_cnt = true;
1558         /* todo: other chips */
1559
1560         if (save_cnt) {
1561                 /* rtw_write8(adapter, REG_RXERR_RPT+3, rtw_read8(adapter, REG_RXERR_RPT+3)|0xa0); */
1562                 pdbgpriv->dbg_rx_fifo_last_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow;
1563                 pdbgpriv->dbg_rx_fifo_curr_overflow = rtw_read16(adapter, REG_RXERR_RPT);
1564                 pdbgpriv->dbg_rx_fifo_diff_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow-pdbgpriv->dbg_rx_fifo_last_overflow;
1565         }
1566 }
1567
1568 void linked_info_dump(struct adapter *padapter, u8 benable)
1569 {
1570         struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
1571
1572         if (padapter->bLinkInfoDump == benable)
1573                 return;
1574
1575         DBG_871X("%s %s\n", __func__, (benable) ? "enable" : "disable");
1576
1577         if (benable) {
1578                 pwrctrlpriv->org_power_mgnt = pwrctrlpriv->power_mgnt;/* keep org value */
1579                 rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
1580
1581                 pwrctrlpriv->ips_org_mode = pwrctrlpriv->ips_mode;/* keep org value */
1582                 rtw_pm_set_ips(padapter, IPS_NONE);
1583         } else {
1584                 rtw_pm_set_ips(padapter, pwrctrlpriv->ips_org_mode);
1585
1586                 rtw_pm_set_lps(padapter, pwrctrlpriv->ips_org_mode);
1587         }
1588         padapter->bLinkInfoDump = benable;
1589 }
1590
1591 #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
1592 void rtw_get_raw_rssi_info(void *sel, struct adapter *padapter)
1593 {
1594         u8 isCCKrate, rf_path;
1595         struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1596         struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
1597
1598         DBG_871X_SEL_NL(
1599                 sel,
1600                 "RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n",
1601                 HDATA_RATE(psample_pkt_rssi->data_rate),
1602                 psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all
1603         );
1604
1605         isCCKrate = psample_pkt_rssi->data_rate <= DESC_RATE11M;
1606
1607         if (isCCKrate)
1608                 psample_pkt_rssi->mimo_signal_strength[0] = psample_pkt_rssi->pwdball;
1609
1610         for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
1611                 DBG_871X_SEL_NL(
1612                         sel,
1613                         "RF_PATH_%d =>signal_strength:%d(%%), signal_quality:%d(%%)\n",
1614                         rf_path, psample_pkt_rssi->mimo_signal_strength[rf_path],
1615                         psample_pkt_rssi->mimo_signal_quality[rf_path]
1616                 );
1617
1618                 if (!isCCKrate) {
1619                         DBG_871X_SEL_NL(
1620                                 sel,
1621                                 "\trx_ofdm_pwr:%d(dBm), rx_ofdm_snr:%d(dB)\n",
1622                                 psample_pkt_rssi->ofdm_pwr[rf_path],
1623                                 psample_pkt_rssi->ofdm_snr[rf_path]
1624                         );
1625                 }
1626         }
1627 }
1628
1629 void rtw_dump_raw_rssi_info(struct adapter *padapter)
1630 {
1631         u8 isCCKrate, rf_path;
1632         struct hal_com_data *pHalData =  GET_HAL_DATA(padapter);
1633         struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
1634         DBG_871X("============ RAW Rx Info dump ===================\n");
1635         DBG_871X("RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n",
1636                         HDATA_RATE(psample_pkt_rssi->data_rate), psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all);
1637
1638         isCCKrate = psample_pkt_rssi->data_rate <= DESC_RATE11M;
1639
1640         if (isCCKrate)
1641                 psample_pkt_rssi->mimo_signal_strength[0] = psample_pkt_rssi->pwdball;
1642
1643         for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
1644                 DBG_871X("RF_PATH_%d =>signal_strength:%d(%%), signal_quality:%d(%%)"
1645                         , rf_path, psample_pkt_rssi->mimo_signal_strength[rf_path], psample_pkt_rssi->mimo_signal_quality[rf_path]);
1646
1647                 if (!isCCKrate) {
1648                         printk(", rx_ofdm_pwr:%d(dBm), rx_ofdm_snr:%d(dB)\n",
1649                         psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]);
1650                 } else {
1651                         printk("\n");
1652                 }
1653         }
1654 }
1655
1656 void rtw_store_phy_info(struct adapter *padapter, union recv_frame *prframe)
1657 {
1658         u8 isCCKrate, rf_path;
1659         struct hal_com_data *pHalData =  GET_HAL_DATA(padapter);
1660         struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
1661
1662         struct odm_phy_info *pPhyInfo  = (PODM_PHY_INFO_T)(&pattrib->phy_info);
1663         struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
1664
1665         psample_pkt_rssi->data_rate = pattrib->data_rate;
1666         isCCKrate = pattrib->data_rate <= DESC_RATE11M;
1667
1668         psample_pkt_rssi->pwdball = pPhyInfo->rx_pwd_ba11;
1669         psample_pkt_rssi->pwr_all = pPhyInfo->recv_signal_power;
1670
1671         for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
1672                 psample_pkt_rssi->mimo_signal_strength[rf_path] = pPhyInfo->rx_mimo_signal_strength[rf_path];
1673                 psample_pkt_rssi->mimo_signal_quality[rf_path] = pPhyInfo->rx_mimo_signal_quality[rf_path];
1674                 if (!isCCKrate) {
1675                         psample_pkt_rssi->ofdm_pwr[rf_path] = pPhyInfo->RxPwr[rf_path];
1676                         psample_pkt_rssi->ofdm_snr[rf_path] = pPhyInfo->RxSNR[rf_path];
1677                 }
1678         }
1679 }
1680 #endif
1681
1682 static u32 Array_kfreemap[] = {
1683         0xf8, 0xe,
1684         0xf6, 0xc,
1685         0xf4, 0xa,
1686         0xf2, 0x8,
1687         0xf0, 0x6,
1688         0xf3, 0x4,
1689         0xf5, 0x2,
1690         0xf7, 0x0,
1691         0xf9, 0x0,
1692         0xfc, 0x0,
1693 };
1694
1695 void rtw_bb_rf_gain_offset(struct adapter *padapter)
1696 {
1697         u8 value = padapter->eeprompriv.EEPROMRFGainOffset;
1698         u32 res, i = 0;
1699         u32 *Array = Array_kfreemap;
1700         u32 v1 = 0, v2 = 0, target = 0;
1701         /* DBG_871X("+%s value: 0x%02x+\n", __func__, value); */
1702
1703         if (value & BIT4) {
1704                 DBG_871X("Offset RF Gain.\n");
1705                 DBG_871X("Offset RF Gain.  padapter->eeprompriv.EEPROMRFGainVal = 0x%x\n", padapter->eeprompriv.EEPROMRFGainVal);
1706                 if (padapter->eeprompriv.EEPROMRFGainVal != 0xff) {
1707                         res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
1708                         res &= 0xfff87fff;
1709                         DBG_871X("Offset RF Gain. before reg 0x7f = 0x%08x\n", res);
1710                         /* res &= 0xfff87fff; */
1711                         for (i = 0; i < ARRAY_SIZE(Array_kfreemap); i += 2) {
1712                                 v1 = Array[i];
1713                                 v2 = Array[i+1];
1714                                 if (v1 == padapter->eeprompriv.EEPROMRFGainVal) {
1715                                         DBG_871X("Offset RF Gain. got v1 = 0x%x , v2 = 0x%x\n", v1, v2);
1716                                         target = v2;
1717                                         break;
1718                                 }
1719                         }
1720                         DBG_871X("padapter->eeprompriv.EEPROMRFGainVal = 0x%x , Gain offset Target Value = 0x%x\n", padapter->eeprompriv.EEPROMRFGainVal, target);
1721                         PHY_SetRFReg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18|BIT17|BIT16|BIT15, target);
1722
1723                         /* res |= (padapter->eeprompriv.EEPROMRFGainVal & 0x0f)<< 15; */
1724                         /* rtw_hal_write_rfreg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, RF_GAIN_OFFSET_MASK, res); */
1725                         res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
1726                         DBG_871X("Offset RF Gain. After reg 0x7f = 0x%08x\n", res);
1727                 } else
1728                         DBG_871X("Offset RF Gain.  padapter->eeprompriv.EEPROMRFGainVal = 0x%x  != 0xff, didn't run Kfree\n", padapter->eeprompriv.EEPROMRFGainVal);
1729         } else
1730                 DBG_871X("Using the default RF gain.\n");
1731 }