drivers/staging/rtl8712/rtl8712_edcasetting_bitdef.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
   5  *
   6  * Modifications for inclusion into the Linux staging tree are
   7  * Copyright(c) 2010 Larry Finger. All rights reserved.
   8  *
   9  * Contact information:
  10  * WLAN FAE <wlanfae@realtek.com>
  11  * Larry Finger <Larry.Finger@lwfinger.net>
  12  *
  13  ******************************************************************************/
  14 #ifndef __RTL8712_EDCASETTING_BITDEF_H__
  15 #define __RTL8712_EDCASETTING_BITDEF_H__
  16
  17 /*EDCAPARAM*/
  18 #define _TXOPLIMIT_MSK          0xFFFF0000
  19 #define _TXOPLIMIT_SHT          16
  20 #define _ECWIN_MSK              0x0000FF00
  21 #define _ECWIN_SHT              8
  22 #define _AIFS_MSK               0x000000FF
  23 #define _AIFS_SHT               0
  24
  25 /*BCNTCFG*/
  26 #define _BCNECW_MSK             0xFF00
  27 #define _BCNECW_SHT             8
  28 #define _BCNIFS_MSK             0x00FF
  29 #define _BCNIFS_SHT             0
  30
  31 /*CWRR*/
  32 #define _CWRR_MSK               0x03FF
  33
  34 /*ACMAVG*/
  35 #define _AVG_TIME_UP            BIT(3)
  36 #define _AVGPERIOD_MSK          0x03
  37
  38 /*ACMHWCTRL*/
  39 #define _VOQ_ACM_STATUS         BIT(6)
  40 #define _VIQ_ACM_STATUS         BIT(5)
  41 #define _BEQ_ACM_STATUS         BIT(4)
  42 #define _VOQ_ACM_EN             BIT(3)
  43 #define _VIQ_ACM_EN             BIT(2)
  44 #define _BEQ_ACM_EN             BIT(1)
  45 #define _ACMHWEN                BIT(0)
  46
  47 /*VO_ADMTIME*/
  48 #define _VO_ACM_RUT             BIT(18)
  49 #define _VO_ADMTIME_MSK         0x0003FFF
  50
  51 /*VI_ADMTIME*/
  52 #define _VI_ACM_RUT             BIT(18)
  53 #define _VI_ADMTIME_MSK         0x0003FFF
  54
  55 /*BE_ADMTIME*/
  56 #define _BE_ACM_RUT             BIT(18)
  57 #define _BE_ADMTIME_MSK         0x0003FFF
  58
  59 /*Retry limit reg*/
  60 #define _SRL_MSK                0xFF00
  61 #define _SRL_SHT                8
  62 #define _LRL_MSK                0x00FF
  63 #define _LRL_SHT                0
  64
  65 #endif /* __RTL8712_EDCASETTING_BITDEF_H__*/