1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _R819XU_PHYREG_H
3 #define _R819XU_PHYREG_H
5 #define RF_DATA 0x1d4 /* FW will write RF data in the register.*/
8 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */
9 #define rFPGA0_TxGainStage 0x80c
10 #define rFPGA0_XA_HSSIParameter1 0x820
11 #define rFPGA0_XA_HSSIParameter2 0x824
12 #define rFPGA0_XB_HSSIParameter1 0x828
13 #define rFPGA0_XB_HSSIParameter2 0x82c
14 #define rFPGA0_XC_HSSIParameter1 0x830
15 #define rFPGA0_XC_HSSIParameter2 0x834
16 #define rFPGA0_XD_HSSIParameter1 0x838
17 #define rFPGA0_XD_HSSIParameter2 0x83c
18 #define rFPGA0_XA_LSSIParameter 0x840
19 #define rFPGA0_XB_LSSIParameter 0x844
20 #define rFPGA0_XC_LSSIParameter 0x848
21 #define rFPGA0_XD_LSSIParameter 0x84c
22 #define rFPGA0_XAB_SwitchControl 0x858
23 #define rFPGA0_XCD_SwitchControl 0x85c
24 #define rFPGA0_XA_RFInterfaceOE 0x860
25 #define rFPGA0_XB_RFInterfaceOE 0x864
26 #define rFPGA0_XC_RFInterfaceOE 0x868
27 #define rFPGA0_XD_RFInterfaceOE 0x86c
28 #define rFPGA0_XAB_RFInterfaceSW 0x870
29 #define rFPGA0_XCD_RFInterfaceSW 0x874
30 #define rFPGA0_XAB_RFParameter 0x878
31 #define rFPGA0_XCD_RFParameter 0x87c
32 #define rFPGA0_AnalogParameter1 0x880
33 #define rFPGA0_AnalogParameter4 0x88c
34 #define rFPGA0_XA_LSSIReadBack 0x8a0
35 #define rFPGA0_XB_LSSIReadBack 0x8a4
36 #define rFPGA0_XC_LSSIReadBack 0x8a8
37 #define rFPGA0_XD_LSSIReadBack 0x8ac
38 #define rFPGA0_XAB_RFInterfaceRB 0x8e0
39 #define rFPGA0_XCD_RFInterfaceRB 0x8e4
42 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */
45 #define rCCK0_System 0xa00
46 #define rCCK0_AFESetting 0xa04
47 #define rCCK0_CCA 0xa08
48 #define rCCK0_TxFilter1 0xa20
49 #define rCCK0_TxFilter2 0xa24
50 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */
53 #define rOFDM0_TRxPathEnable 0xc04
54 #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */
55 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imbalance matrix */
56 #define rOFDM0_XBRxAFE 0xc18
57 #define rOFDM0_XBRxIQImbalance 0xc1c
58 #define rOFDM0_XCRxAFE 0xc20
59 #define rOFDM0_XCRxIQImbalance 0xc24
60 #define rOFDM0_XDRxAFE 0xc28
61 #define rOFDM0_XDRxIQImbalance 0xc2c
62 #define rOFDM0_RxDetector1 0xc30 /* PD,BW & SBD */
63 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync.*/
64 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync.*/
65 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
66 #define rOFDM0_XAAGCCore1 0xc50
67 #define rOFDM0_XAAGCCore2 0xc54
68 #define rOFDM0_XBAGCCore1 0xc58
69 #define rOFDM0_XBAGCCore2 0xc5c
70 #define rOFDM0_XCAGCCore1 0xc60
71 #define rOFDM0_XCAGCCore2 0xc64
72 #define rOFDM0_XDAGCCore1 0xc68
73 #define rOFDM0_XDAGCCore2 0xc6c
74 #define rOFDM0_XATxIQImbalance 0xc80
75 #define rOFDM0_XATxAFE 0xc84
76 #define rOFDM0_XBTxIQImbalance 0xc88
77 #define rOFDM0_XBTxAFE 0xc8c
78 #define rOFDM0_XCTxIQImbalance 0xc90
79 #define rOFDM0_XCTxAFE 0xc94
80 #define rOFDM0_XDTxIQImbalance 0xc98
81 #define rOFDM0_XDTxAFE 0xc9c
84 #define rOFDM1_LSTF 0xd00
85 #define rOFDM1_TRxPathEnable 0xd04
88 #define rTxAGC_Rate18_06 0xe00
89 #define rTxAGC_Rate54_24 0xe04
90 #define rTxAGC_CCK_Mcs32 0xe08
91 #define rTxAGC_Mcs03_Mcs00 0xe10
92 #define rTxAGC_Mcs07_Mcs04 0xe14
93 #define rTxAGC_Mcs11_Mcs08 0xe18
94 #define rTxAGC_Mcs15_Mcs12 0xe1c
99 #define rZebra1_Channel 0x7
102 #define rGlobalCtrl 0
108 #define bCCKEn 0x1000000
109 #define bOFDMEn 0x2000000
110 #define bXBTxAGC 0xf00
111 #define bXCTxAGC 0xf000
112 #define b3WireDataLength 0x800
113 #define b3WireAddressLength 0x400
114 #define bRFSI_RFENV 0x10
115 #define bLSSIReadAddress 0x3f000000 /* LSSI "Read" Address */
116 #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */
117 #define bLSSIReadBackData 0xfff
118 #define bXtalCap 0x0f000000
121 #define bCCKSideBand 0x10
124 #define bTxAGCRateCCK 0x7f00
129 #define bZebra1_ChannelNum 0xf80
132 /* for PutRegsetting & GetRegSetting BitMask */
133 #define bMaskByte0 0xff
134 #define bMaskByte1 0xff00
135 #define bMaskByte2 0xff0000
136 #define bMaskHWord 0xffff0000
137 #define bMaskLWord 0x0000ffff
138 #define bMaskDWord 0xffffffff
140 /* for PutRFRegsetting & GetRFRegSetting BitMask */
141 #define bMask12Bits 0xfff
143 #endif /* __INC_HAL8190PCIPHYREG_H */