1 // SPDX-License-Identifier: GPL-2.0
4 #include "r819xU_phy.h"
5 #include "r819xU_phyreg.h"
6 #include "r8190_rtl8256.h"
8 #include "r819xU_firmware_img.h"
10 #include "ieee80211/dot11d.h"
11 #include <linux/bitops.h>
13 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
31 #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
33 /******************************************************************************
34 * function: This function checks different RF type to execute legal judgement.
35 * If RF Path is illegal, we will return false.
36 * input: net_device *dev
39 * return: 0(illegal, false), 1(legal, true)
40 *****************************************************************************/
41 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 e_rfpath)
44 struct r8192_priv *priv = ieee80211_priv(dev);
46 if (priv->rf_type == RF_2T4R) {
48 } else if (priv->rf_type == RF_1T2R) {
49 if (e_rfpath == RF90_PATH_A || e_rfpath == RF90_PATH_B)
51 else if (e_rfpath == RF90_PATH_C || e_rfpath == RF90_PATH_D)
57 /******************************************************************************
58 * function: This function sets specific bits to BB register
59 * input: net_device *dev
60 * u32 reg_addr //target addr to be modified
61 * u32 bitmask //taget bit pos to be modified
62 * u32 data //value to be write
66 ******************************************************************************/
67 void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask,
73 if (bitmask != bMaskDWord) {
74 read_nic_dword(dev, reg_addr, ®);
75 bitshift = ffs(bitmask) - 1;
77 reg |= data << bitshift;
78 write_nic_dword(dev, reg_addr, reg);
80 write_nic_dword(dev, reg_addr, data);
84 /******************************************************************************
85 * function: This function reads specific bits from BB register
86 * input: net_device *dev
87 * u32 reg_addr //target addr to be readback
88 * u32 bitmask //taget bit pos to be readback
90 * return: u32 data //the readback register value
92 ******************************************************************************/
93 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask)
97 read_nic_dword(dev, reg_addr, ®);
98 bitshift = ffs(bitmask) - 1;
100 return (reg & bitmask) >> bitshift;
103 static u32 phy_FwRFSerialRead(struct net_device *dev,
104 enum rf90_radio_path_e e_rfpath,
107 static void phy_FwRFSerialWrite(struct net_device *dev,
108 enum rf90_radio_path_e e_rfpath,
112 /******************************************************************************
113 * function: This function reads register from RF chip
114 * input: net_device *dev
115 * rf90_radio_path_e e_rfpath //radio path of A/B/C/D
116 * u32 offset //target address to be read
118 * return: u32 readback value
119 * notice: There are three types of serial operations:
120 * (1) Software serial write.
121 * (2)Hardware LSSI-Low Speed Serial Interface.
122 * (3)Hardware HSSI-High speed serial write.
123 * Driver here need to implement (1) and (2)
124 * ---need more spec for this information.
125 ******************************************************************************/
126 static u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
127 enum rf90_radio_path_e e_rfpath, u32 offset)
129 struct r8192_priv *priv = ieee80211_priv(dev);
132 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[e_rfpath];
134 rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
135 /* Make sure RF register offset is correct */
138 /* Switch page for 8256 RF IC */
139 if (priv->rf_chip == RF_8256) {
141 priv->RfReg0Value[e_rfpath] |= 0x140;
142 /* Switch to Reg_Mode2 for Reg 31-45 */
143 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
145 priv->RfReg0Value[e_rfpath]<<16);
147 new_offset = offset - 30;
148 } else if (offset >= 16) {
149 priv->RfReg0Value[e_rfpath] |= 0x100;
150 priv->RfReg0Value[e_rfpath] &= (~0x40);
151 /* Switch to Reg_Mode1 for Reg16-30 */
152 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
154 priv->RfReg0Value[e_rfpath]<<16);
156 new_offset = offset - 15;
161 RT_TRACE((COMP_PHY|COMP_ERR),
162 "check RF type here, need to be 8256\n");
165 /* Put desired read addr to LSSI control Register */
166 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
168 /* Issue a posedge trigger */
169 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
170 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
173 /* TODO: we should not delay such a long time. Ask for help from SD3 */
174 usleep_range(1000, 1000);
176 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack,
180 /* Switch back to Reg_Mode0 */
181 if (priv->rf_chip == RF_8256) {
182 priv->RfReg0Value[e_rfpath] &= 0xebf;
184 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
185 priv->RfReg0Value[e_rfpath] << 16);
191 /******************************************************************************
192 * function: This function writes data to RF register
193 * input: net_device *dev
194 * rf90_radio_path_e e_rfpath //radio path of A/B/C/D
195 * u32 offset //target address to be written
196 * u32 data //the new register data to be written
199 * notice: For RF8256 only.
200 * ===========================================================================
201 * Reg Mode RegCTL[1] RegCTL[0] Note
202 * (Reg00[12]) (Reg00[10])
203 * ===========================================================================
204 * Reg_Mode0 0 x Reg 0 ~ 15(0x0 ~ 0xf)
205 * ---------------------------------------------------------------------------
206 * Reg_Mode1 1 0 Reg 16 ~ 30(0x1 ~ 0xf)
207 * ---------------------------------------------------------------------------
208 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
209 * ---------------------------------------------------------------------------
210 *****************************************************************************/
211 static void rtl8192_phy_RFSerialWrite(struct net_device *dev,
212 enum rf90_radio_path_e e_rfpath,
216 struct r8192_priv *priv = ieee80211_priv(dev);
217 u32 DataAndAddr = 0, new_offset = 0;
218 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[e_rfpath];
221 if (priv->rf_chip == RF_8256) {
224 priv->RfReg0Value[e_rfpath] |= 0x140;
225 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
227 priv->RfReg0Value[e_rfpath] << 16);
228 new_offset = offset - 30;
229 } else if (offset >= 16) {
230 priv->RfReg0Value[e_rfpath] |= 0x100;
231 priv->RfReg0Value[e_rfpath] &= (~0x40);
232 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
234 priv->RfReg0Value[e_rfpath]<<16);
235 new_offset = offset - 15;
240 RT_TRACE((COMP_PHY|COMP_ERR),
241 "check RF type here, need to be 8256\n");
245 /* Put write addr in [5:0] and write data in [31:16] */
246 DataAndAddr = (data<<16) | (new_offset&0x3f);
248 /* Write operation */
249 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
253 priv->RfReg0Value[e_rfpath] = data;
255 /* Switch back to Reg_Mode0 */
256 if (priv->rf_chip == RF_8256) {
258 priv->RfReg0Value[e_rfpath] &= 0xebf;
259 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
261 priv->RfReg0Value[e_rfpath] << 16);
266 /******************************************************************************
267 * function: This function set specific bits to RF register
268 * input: net_device dev
269 * rf90_radio_path_e e_rfpath //radio path of A/B/C/D
270 * u32 reg_addr //target addr to be modified
271 * u32 bitmask //taget bit pos to be modified
272 * u32 data //value to be written
276 *****************************************************************************/
277 void rtl8192_phy_SetRFReg(struct net_device *dev,
278 enum rf90_radio_path_e e_rfpath,
279 u32 reg_addr, u32 bitmask, u32 data)
281 struct r8192_priv *priv = ieee80211_priv(dev);
284 if (!rtl8192_phy_CheckIsLegalRFPath(dev, e_rfpath))
287 if (priv->Rf_Mode == RF_OP_By_FW) {
288 if (bitmask != bMask12Bits) {
289 /* RF data is 12 bits only */
290 reg = phy_FwRFSerialRead(dev, e_rfpath, reg_addr);
291 bitshift = ffs(bitmask) - 1;
293 reg |= data << bitshift;
295 phy_FwRFSerialWrite(dev, e_rfpath, reg_addr, reg);
297 phy_FwRFSerialWrite(dev, e_rfpath, reg_addr, data);
303 if (bitmask != bMask12Bits) {
304 /* RF data is 12 bits only */
305 reg = rtl8192_phy_RFSerialRead(dev, e_rfpath, reg_addr);
306 bitshift = ffs(bitmask) - 1;
308 reg |= data << bitshift;
310 rtl8192_phy_RFSerialWrite(dev, e_rfpath, reg_addr, reg);
312 rtl8192_phy_RFSerialWrite(dev, e_rfpath, reg_addr, data);
317 /******************************************************************************
318 * function: This function reads specific bits from RF register
319 * input: net_device *dev
320 * u32 reg_addr //target addr to be readback
321 * u32 bitmask //taget bit pos to be readback
323 * return: u32 data //the readback register value
325 *****************************************************************************/
326 u32 rtl8192_phy_QueryRFReg(struct net_device *dev,
327 enum rf90_radio_path_e e_rfpath,
328 u32 reg_addr, u32 bitmask)
331 struct r8192_priv *priv = ieee80211_priv(dev);
334 if (!rtl8192_phy_CheckIsLegalRFPath(dev, e_rfpath))
336 if (priv->Rf_Mode == RF_OP_By_FW) {
337 reg = phy_FwRFSerialRead(dev, e_rfpath, reg_addr);
340 reg = rtl8192_phy_RFSerialRead(dev, e_rfpath, reg_addr);
342 bitshift = ffs(bitmask) - 1;
343 reg = (reg & bitmask) >> bitshift;
348 /******************************************************************************
349 * function: We support firmware to execute RF-R/W.
350 * input: net_device *dev
351 * rf90_radio_path_e e_rfpath
356 ****************************************************************************/
357 static u32 phy_FwRFSerialRead(struct net_device *dev,
358 enum rf90_radio_path_e e_rfpath,
366 /* Firmware RF Write control.
367 * We can not execute the scheme in the initial step.
368 * Otherwise, RF-R/W will waste much time.
369 * This is only for site survey.
371 /* 1. Read operation need not insert data. bit 0-11 */
372 /* 2. Write RF register address. bit 12-19 */
373 data |= ((offset&0xFF)<<12);
374 /* 3. Write RF path. bit 20-21 */
375 data |= ((e_rfpath&0x3)<<20);
376 /* 4. Set RF read indicator. bit 22=0 */
377 /* 5. Trigger Fw to operate the command. bit 31 */
379 /* 6. We can not execute read operation if bit 31 is 1. */
380 read_nic_dword(dev, QPNR, &tmp);
381 while (tmp & 0x80000000) {
382 /* If FW can not finish RF-R/W for more than ?? times.
387 read_nic_dword(dev, QPNR, &tmp);
392 /* 7. Execute read operation. */
393 write_nic_dword(dev, QPNR, data);
394 /* 8. Check if firmware send back RF content. */
395 read_nic_dword(dev, QPNR, &tmp);
396 while (tmp & 0x80000000) {
397 /* If FW can not finish RF-R/W for more than ?? times.
402 read_nic_dword(dev, QPNR, &tmp);
407 read_nic_dword(dev, RF_DATA, ®);
412 /******************************************************************************
413 * function: We support firmware to execute RF-R/W.
414 * input: net_device *dev
415 * rf90_radio_path_e e_rfpath
421 ****************************************************************************/
422 static void phy_FwRFSerialWrite(struct net_device *dev,
423 enum rf90_radio_path_e e_rfpath,
424 u32 offset, u32 data)
429 /* Firmware RF Write control.
430 * We can not execute the scheme in the initial step.
431 * Otherwise, RF-R/W will waste much time.
432 * This is only for site survey.
435 /* 1. Set driver write bit and 12 bit data. bit 0-11 */
436 /* 2. Write RF register address. bit 12-19 */
437 data |= ((offset&0xFF)<<12);
438 /* 3. Write RF path. bit 20-21 */
439 data |= ((e_rfpath&0x3)<<20);
440 /* 4. Set RF write indicator. bit 22=1 */
442 /* 5. Trigger Fw to operate the command. bit 31=1 */
445 /* 6. Write operation. We can not write if bit 31 is 1. */
446 read_nic_dword(dev, QPNR, &tmp);
447 while (tmp & 0x80000000) {
448 /* If FW can not finish RF-R/W for more than ?? times.
453 read_nic_dword(dev, QPNR, &tmp);
458 /* 7. No matter check bit. We always force the write.
459 * Because FW will not accept the command.
461 write_nic_dword(dev, QPNR, data);
462 /* According to test, we must delay 20us to wait firmware
463 * to finish RF write operation.
465 /* We support delay in firmware side now. */
468 /******************************************************************************
469 * function: This function reads BB parameters from header file we generate,
470 * and do register read/write
471 * input: net_device *dev
474 * notice: BB parameters may change all the time, so please make
475 * sure it has been synced with the newest.
476 *****************************************************************************/
477 void rtl8192_phy_configmac(struct net_device *dev)
479 u32 dwArrayLen = 0, i;
480 u32 *pdwArray = NULL;
481 struct r8192_priv *priv = ieee80211_priv(dev);
483 if (priv->btxpowerdata_readfromEEPORM) {
484 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
485 dwArrayLen = MACPHY_Array_PGLength;
486 pdwArray = Rtl8192UsbMACPHY_Array_PG;
489 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n");
490 dwArrayLen = MACPHY_ArrayLength;
491 pdwArray = rtl819XMACPHY_Array;
493 for (i = 0; i < dwArrayLen; i = i+3) {
494 if (pdwArray[i] == 0x318)
495 pdwArray[i+2] = 0x00000800;
498 "Rtl8190MACPHY_Array[0]=%x Rtl8190MACPHY_Array[1]=%x Rtl8190MACPHY_Array[2]=%x\n",
499 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
500 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1],
505 /******************************************************************************
506 * function: This function does dirty work
507 * input: net_device *dev
511 * notice: BB parameters may change all the time, so please make
512 * sure it has been synced with the newest.
513 *****************************************************************************/
514 static void rtl8192_phyConfigBB(struct net_device *dev,
515 enum baseband_config_type ConfigType)
519 if (ConfigType == BASEBAND_CONFIG_PHY_REG) {
520 for (i = 0; i < PHY_REG_1T2RArrayLength; i += 2) {
521 rtl8192_setBBreg(dev, Rtl8192UsbPHY_REG_1T2RArray[i],
523 Rtl8192UsbPHY_REG_1T2RArray[i+1]);
525 "i: %x, Rtl819xUsbPHY_REGArray[0]=%x Rtl819xUsbPHY_REGArray[1]=%x\n",
526 i, Rtl8192UsbPHY_REG_1T2RArray[i],
527 Rtl8192UsbPHY_REG_1T2RArray[i+1]);
529 } else if (ConfigType == BASEBAND_CONFIG_AGC_TAB) {
530 for (i = 0; i < AGCTAB_ArrayLength; i += 2) {
531 rtl8192_setBBreg(dev, Rtl8192UsbAGCTAB_Array[i],
532 bMaskDWord, Rtl8192UsbAGCTAB_Array[i+1]);
534 "i: %x, Rtl8192UsbAGCTAB_Array[0]=%x Rtl8192UsbAGCTAB_Array[1]=%x\n",
535 i, Rtl8192UsbAGCTAB_Array[i],
536 Rtl8192UsbAGCTAB_Array[i+1]);
541 /******************************************************************************
542 * function: This function initializes Register definition offset for
544 * input: net_device *dev
547 * notice: Initialization value here is constant and it should never
549 *****************************************************************************/
550 static void rtl8192_InitBBRFRegDef(struct net_device *dev)
552 struct r8192_priv *priv = ieee80211_priv(dev);
554 /* RF Interface Software Control */
555 /* 16 LSBs if read 32-bit from 0x870 */
556 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
557 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
558 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
559 /* 16 LSBs if read 32-bit from 0x874 */
560 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
561 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
562 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
564 /* RF Interface Readback Value */
565 /* 16 LSBs if read 32-bit from 0x8E0 */
566 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
567 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
568 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
569 /* 16 LSBs if read 32-bit from 0x8E4 */
570 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
571 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
572 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
574 /* RF Interface Output (and Enable) */
575 /* 16 LSBs if read 32-bit from 0x860 */
576 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
577 /* 16 LSBs if read 32-bit from 0x864 */
578 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
579 /* 16 LSBs if read 32-bit from 0x868 */
580 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
581 /* 16 LSBs if read 32-bit from 0x86C */
582 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
584 /* RF Interface (Output and) Enable */
585 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
586 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
587 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
588 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
589 /* 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) */
590 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
591 /* 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) */
592 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
594 /* Addr of LSSI. Write RF register by driver */
595 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
596 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
597 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
598 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
602 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
603 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
604 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
605 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
607 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
608 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
609 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
610 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
611 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
613 /* Tranceiver A~D HSSI Parameter-1 */
614 /* wire control parameter1 */
615 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
616 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
617 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
618 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
620 /* Tranceiver A~D HSSI Parameter-2 */
621 /* wire control parameter2 */
622 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
623 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
624 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
625 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
627 /* RF Switch Control */
628 /* TR/Ant switch control */
629 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
630 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
631 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
632 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
635 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
636 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
637 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
638 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
641 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
642 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
643 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
644 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
646 /* RX AFE control 1 */
647 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
648 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
649 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
650 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
652 /* RX AFE control 1 */
653 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
654 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
655 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
656 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
658 /* Tx AFE control 1 */
659 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
660 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
661 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
662 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
664 /* Tx AFE control 2 */
665 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
666 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
667 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
668 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
670 /* Tranceiver LSSI Readback */
671 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
672 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
673 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
674 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
677 /******************************************************************************
678 * function: This function is to write register and then readback to make
679 * sure whether BB and RF is OK
680 * input: net_device *dev
681 * hw90_block_e CheckBlock
682 * rf90_radio_path_e e_rfpath //only used when checkblock is
685 * return: return whether BB and RF is ok (0:OK, 1:Fail)
686 * notice: This function may be removed in the ASIC
687 ******************************************************************************/
688 u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, enum hw90_block_e CheckBlock,
689 enum rf90_radio_path_e e_rfpath)
692 u32 i, CheckTimes = 4, reg = 0;
694 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
696 /* Initialize register address offset to be checked */
697 WriteAddr[HW90_BLOCK_MAC] = 0x100;
698 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
699 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
700 WriteAddr[HW90_BLOCK_RF] = 0x3;
701 RT_TRACE(COMP_PHY, "%s(), CheckBlock: %d\n", __func__, CheckBlock);
702 for (i = 0; i < CheckTimes; i++) {
704 /* Write data to register and readback */
705 switch (CheckBlock) {
708 "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
711 case HW90_BLOCK_PHY0:
712 case HW90_BLOCK_PHY1:
713 write_nic_dword(dev, WriteAddr[CheckBlock],
715 read_nic_dword(dev, WriteAddr[CheckBlock], ®);
719 WriteData[i] &= 0xfff;
720 rtl8192_phy_SetRFReg(dev, e_rfpath,
721 WriteAddr[HW90_BLOCK_RF],
722 bMask12Bits, WriteData[i]);
723 /* TODO: we should not delay for such a long time.
726 usleep_range(1000, 1000);
727 reg = rtl8192_phy_QueryRFReg(dev, e_rfpath,
728 WriteAddr[HW90_BLOCK_RF],
730 usleep_range(1000, 1000);
739 /* Check whether readback data is correct */
740 if (reg != WriteData[i]) {
741 RT_TRACE((COMP_PHY|COMP_ERR),
742 "error reg: %x, WriteData: %x\n",
752 /******************************************************************************
753 * function: This function initializes BB&RF
754 * input: net_device *dev
757 * notice: Initialization value may change all the time, so please make
758 * sure it has been synced with the newest.
759 ******************************************************************************/
760 static void rtl8192_BB_Config_ParaFile(struct net_device *dev)
762 struct r8192_priv *priv = ieee80211_priv(dev);
763 u8 reg_u8 = 0, eCheckItem = 0, status = 0;
766 /**************************************
767 * <1> Initialize BaseBand
768 *************************************/
770 /* --set BB Global Reset-- */
771 read_nic_byte(dev, BB_GLOBAL_RESET, ®_u8);
772 write_nic_byte(dev, BB_GLOBAL_RESET, (reg_u8|BB_GLOBAL_RESET_BIT));
774 /* ---set BB reset Active--- */
775 read_nic_dword(dev, CPU_GEN, ®_u32);
776 write_nic_dword(dev, CPU_GEN, (reg_u32&(~CPU_GEN_BB_RST)));
778 /* ----Ckeck FPGAPHY0 and PHY1 board is OK---- */
779 /* TODO: this function should be removed on ASIC */
780 for (eCheckItem = (enum hw90_block_e)HW90_BLOCK_PHY0;
781 eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
782 /* don't care RF path */
783 status = rtl8192_phy_checkBBAndRF(dev, (enum hw90_block_e)eCheckItem,
784 (enum rf90_radio_path_e)0);
786 RT_TRACE((COMP_ERR | COMP_PHY),
787 "phy_rf8256_config(): Check PHY%d Fail!!\n",
792 /* ---- Set CCK and OFDM Block "OFF"---- */
793 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
794 /* ----BB Register Initilazation---- */
795 /* ==m==>Set PHY REG From Header<==m== */
796 rtl8192_phyConfigBB(dev, BASEBAND_CONFIG_PHY_REG);
798 /* ----Set BB reset de-Active---- */
799 read_nic_dword(dev, CPU_GEN, ®_u32);
800 write_nic_dword(dev, CPU_GEN, (reg_u32|CPU_GEN_BB_RST));
802 /* ----BB AGC table Initialization---- */
803 /* ==m==>Set PHY REG From Header<==m== */
804 rtl8192_phyConfigBB(dev, BASEBAND_CONFIG_AGC_TAB);
806 /* ----Enable XSTAL ---- */
807 write_nic_byte_E(dev, 0x5e, 0x00);
808 if (priv->card_8192_version == VERSION_819XU_A) {
809 /* Antenna gain offset from B/C/D to A */
810 reg_u32 = priv->AntennaTxPwDiff[1]<<4 |
811 priv->AntennaTxPwDiff[0];
812 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC),
816 reg_u32 = priv->CrystalCap & 0xf;
817 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap,
821 /* Check if the CCK HighPower is turned ON.
822 * This is used to calculate PWDB.
824 priv->bCckHighPower = (u8)rtl8192_QueryBBReg(dev,
825 rFPGA0_XA_HSSIParameter2,
829 /******************************************************************************
830 * function: This function initializes BB&RF
831 * input: net_device *dev
834 * notice: Initialization value may change all the time, so please make
835 * sure it has been synced with the newest.
836 *****************************************************************************/
837 void rtl8192_BBConfig(struct net_device *dev)
839 rtl8192_InitBBRFRegDef(dev);
840 /* config BB&RF. As hardCode based initialization has not been well
841 * implemented, so use file first.
842 * FIXME: should implement it for hardcode?
844 rtl8192_BB_Config_ParaFile(dev);
848 /******************************************************************************
849 * function: This function obtains the initialization value of Tx power Level
851 * input: net_device *dev
854 *****************************************************************************/
855 void rtl8192_phy_getTxPower(struct net_device *dev)
857 struct r8192_priv *priv = ieee80211_priv(dev);
860 read_nic_dword(dev, rTxAGC_Rate18_06,
861 &priv->MCSTxPowerLevelOriginalOffset[0]);
862 read_nic_dword(dev, rTxAGC_Rate54_24,
863 &priv->MCSTxPowerLevelOriginalOffset[1]);
864 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00,
865 &priv->MCSTxPowerLevelOriginalOffset[2]);
866 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04,
867 &priv->MCSTxPowerLevelOriginalOffset[3]);
868 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08,
869 &priv->MCSTxPowerLevelOriginalOffset[4]);
870 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12,
871 &priv->MCSTxPowerLevelOriginalOffset[5]);
873 /* Read rx initial gain */
874 read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]);
875 read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]);
876 read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]);
877 read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]);
879 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
880 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
881 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
884 read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync);
885 read_nic_byte(dev, rOFDM0_RxDetector2, &tmp);
886 priv->framesyncC34 = tmp;
887 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
888 rOFDM0_RxDetector3, priv->framesync);
890 /* Read SIFS (save the value read fome MACPHY_REG.txt) */
891 read_nic_word(dev, SIFS, &priv->SifsTime);
894 /******************************************************************************
895 * function: This function sets the initialization value of Tx power Level
897 * input: net_device *dev
901 ******************************************************************************/
902 void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
904 struct r8192_priv *priv = ieee80211_priv(dev);
905 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
906 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
908 switch (priv->rf_chip) {
910 /* need further implement */
911 phy_set_rf8256_cck_tx_power(dev, powerlevel);
912 phy_set_rf8256_ofdm_tx_power(dev, powerlevelOFDM24G);
915 RT_TRACE((COMP_PHY|COMP_ERR),
916 "error RF chipID(8225 or 8258) in function %s()\n",
922 /******************************************************************************
923 * function: This function checks Rf chip to do RF config
924 * input: net_device *dev
926 * return: only 8256 is supported
927 ******************************************************************************/
928 void rtl8192_phy_RFConfig(struct net_device *dev)
930 struct r8192_priv *priv = ieee80211_priv(dev);
932 switch (priv->rf_chip) {
934 phy_rf8256_config(dev);
937 RT_TRACE(COMP_ERR, "error chip id\n");
942 /******************************************************************************
943 * function: This function updates Initial gain
944 * input: net_device *dev
946 * return: As Windows has not implemented this, wait for complement
947 ******************************************************************************/
948 void rtl8192_phy_updateInitGain(struct net_device *dev)
952 /******************************************************************************
953 * function: This function read RF parameters from general head file,
955 * input: net_device *dev
956 * rf90_radio_path_e e_rfpath
958 * return: return code show if RF configuration is successful(0:pass, 1:fail)
959 * notice: Delay may be required for RF configuration
960 *****************************************************************************/
961 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
962 enum rf90_radio_path_e e_rfpath)
969 for (i = 0; i < RadioA_ArrayLength; i = i+2) {
971 if (Rtl8192UsbRadioA_Array[i] == 0xfe) {
975 rtl8192_phy_SetRFReg(dev, e_rfpath,
976 Rtl8192UsbRadioA_Array[i],
978 Rtl8192UsbRadioA_Array[i+1]);
984 for (i = 0; i < RadioB_ArrayLength; i = i+2) {
986 if (Rtl8192UsbRadioB_Array[i] == 0xfe) {
990 rtl8192_phy_SetRFReg(dev, e_rfpath,
991 Rtl8192UsbRadioB_Array[i],
993 Rtl8192UsbRadioB_Array[i+1]);
999 for (i = 0; i < RadioC_ArrayLength; i = i+2) {
1001 if (Rtl8192UsbRadioC_Array[i] == 0xfe) {
1005 rtl8192_phy_SetRFReg(dev, e_rfpath,
1006 Rtl8192UsbRadioC_Array[i],
1008 Rtl8192UsbRadioC_Array[i+1]);
1014 for (i = 0; i < RadioD_ArrayLength; i = i+2) {
1016 if (Rtl8192UsbRadioD_Array[i] == 0xfe) {
1020 rtl8192_phy_SetRFReg(dev, e_rfpath,
1021 Rtl8192UsbRadioD_Array[i],
1023 Rtl8192UsbRadioD_Array[i+1]);
1036 /******************************************************************************
1037 * function: This function sets Tx Power of the channel
1038 * input: net_device *dev
1043 ******************************************************************************/
1044 static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
1046 struct r8192_priv *priv = ieee80211_priv(dev);
1047 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
1048 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1050 switch (priv->rf_chip) {
1055 phy_set_rf8256_cck_tx_power(dev, powerlevel);
1056 phy_set_rf8256_ofdm_tx_power(dev, powerlevelOFDM24G);
1062 RT_TRACE(COMP_ERR, "unknown rf chip ID in %s()\n", __func__);
1067 /******************************************************************************
1068 * function: This function sets RF state on or off
1069 * input: net_device *dev
1070 * RT_RF_POWER_STATE eRFPowerState //Power State to set
1074 *****************************************************************************/
1075 bool rtl8192_SetRFPowerState(struct net_device *dev,
1076 RT_RF_POWER_STATE eRFPowerState)
1078 bool bResult = true;
1079 struct r8192_priv *priv = ieee80211_priv(dev);
1081 if (eRFPowerState == priv->ieee80211->eRFPowerState)
1084 if (priv->SetRFPowerStateInProgress)
1087 priv->SetRFPowerStateInProgress = true;
1089 switch (priv->rf_chip) {
1091 switch (eRFPowerState) {
1094 /* enable RF-Chip A/B - 0x860[4] */
1095 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4),
1097 /* analog to digital on - 0x88c[9:8] */
1098 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300,
1100 /* digital to analog on - 0x880[4:3] */
1101 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1103 /* rx antenna on - 0xc04[1:0] */
1104 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);
1105 /* rx antenna on - 0xd04[1:0] */
1106 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);
1107 /* analog to digital part2 on - 0x880[6:5] */
1108 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1119 /* disable RF-Chip A/B - 0x860[4] */
1120 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4),
1122 /* analog to digital off, for power save */
1123 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00,
1124 0x0); /* 0x88c[11:8] */
1125 /* digital to analog off, for power save - 0x880[4:3] */
1126 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1128 /* rx antenna off - 0xc04[3:0] */
1129 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1130 /* rx antenna off - 0xd04[3:0] */
1131 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1132 /* analog to digital part2 off, for power save */
1133 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1134 0x0); /* 0x880[6:5] */
1140 RT_TRACE(COMP_ERR, "%s(): unknown state to set: 0x%X\n",
1141 __func__, eRFPowerState);
1146 RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip);
1149 priv->SetRFPowerStateInProgress = false;
1154 /******************************************************************************
1155 * function: This function sets command table variable (struct sw_chnl_cmd).
1156 * input: sw_chnl_cmd *CmdTable //table to be set
1157 * u32 CmdTableIdx //variable index in table to be set
1158 * u32 CmdTableSz //table size
1159 * switch_chan_cmd_id CmdID //command ID to set
1164 * return: true if finished, false otherwise
1166 ******************************************************************************/
1167 static u8 rtl8192_phy_SetSwChnlCmdArray(struct sw_chnl_cmd *CmdTable, u32 CmdTableIdx,
1168 u32 CmdTableSz, enum switch_chan_cmd_id CmdID,
1169 u32 Para1, u32 Para2, u32 msDelay)
1171 struct sw_chnl_cmd *pCmd;
1173 if (CmdTable == NULL) {
1174 RT_TRACE(COMP_ERR, "%s(): CmdTable cannot be NULL\n", __func__);
1177 if (CmdTableIdx >= CmdTableSz) {
1178 RT_TRACE(COMP_ERR, "%s(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1179 __func__, CmdTableIdx, CmdTableSz);
1183 pCmd = CmdTable + CmdTableIdx;
1184 pCmd->cmd_id = CmdID;
1185 pCmd->para_1 = Para1;
1186 pCmd->para_2 = Para2;
1187 pCmd->ms_delay = msDelay;
1192 /******************************************************************************
1193 * function: This function sets channel step by step
1194 * input: net_device *dev
1196 * u8 *stage //3 stages
1198 * u32 *delay //whether need to delay
1199 * output: store new stage, step and delay for next step
1200 * (combine with function above)
1201 * return: true if finished, false otherwise
1202 * notice: Wait for simpler function to replace it
1203 *****************************************************************************/
1204 static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel,
1205 u8 *stage, u8 *step, u32 *delay)
1207 struct r8192_priv *priv = ieee80211_priv(dev);
1208 struct sw_chnl_cmd PreCommonCmd[MAX_PRECMD_CNT];
1209 u32 PreCommonCmdCnt;
1210 struct sw_chnl_cmd PostCommonCmd[MAX_POSTCMD_CNT];
1211 u32 PostCommonCmdCnt;
1212 struct sw_chnl_cmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
1214 struct sw_chnl_cmd *CurrentCmd = NULL;
1217 RT_TRACE(COMP_CH, "%s() stage: %d, step: %d, channel: %d\n",
1218 __func__, *stage, *step, channel);
1219 if (!is_legal_channel(priv->ieee80211, channel)) {
1220 RT_TRACE(COMP_ERR, "set to illegal channel: %d\n", channel);
1221 /* return true to tell upper caller function this channel
1222 * setting is finished! Or it will in while loop.
1226 /* FIXME: need to check whether channel is legal or not here */
1229 /* <1> Fill up pre common command. */
1230 PreCommonCmdCnt = 0;
1231 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1232 MAX_PRECMD_CNT, CMD_ID_SET_TX_PWR_LEVEL,
1234 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1235 MAX_PRECMD_CNT, CMD_ID_END, 0, 0, 0);
1237 /* <2> Fill up post common command. */
1238 PostCommonCmdCnt = 0;
1240 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++,
1241 MAX_POSTCMD_CNT, CMD_ID_END, 0, 0, 0);
1243 /* <3> Fill up RF dependent command. */
1245 switch (priv->rf_chip) {
1247 if (!(channel >= 1 && channel <= 14)) {
1249 "illegal channel for Zebra 8225: %d\n",
1253 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1254 MAX_RFDEPENDCMD_CNT,
1255 CMD_ID_RF_WRITE_REG,
1257 RF_CHANNEL_TABLE_ZEBRA[channel],
1259 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1260 MAX_RFDEPENDCMD_CNT,
1261 CMD_ID_END, 0, 0, 0);
1265 /* TEST!! This is not the table for 8256!! */
1266 if (!(channel >= 1 && channel <= 14)) {
1268 "illegal channel for Zebra 8256: %d\n",
1272 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1273 MAX_RFDEPENDCMD_CNT,
1274 CMD_ID_RF_WRITE_REG,
1275 rZebra1_Channel, channel, 10);
1276 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1277 MAX_RFDEPENDCMD_CNT,
1278 CMD_ID_END, 0, 0, 0);
1285 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1293 CurrentCmd = &PreCommonCmd[*step];
1296 CurrentCmd = &RfDependCmd[*step];
1299 CurrentCmd = &PostCommonCmd[*step];
1303 if (CurrentCmd->cmd_id == CMD_ID_END) {
1304 if ((*stage) == 2) {
1305 (*delay) = CurrentCmd->ms_delay;
1313 switch (CurrentCmd->cmd_id) {
1314 case CMD_ID_SET_TX_PWR_LEVEL:
1315 if (priv->card_8192_version == VERSION_819XU_A)
1316 /* consider it later! */
1317 rtl8192_SetTxPowerLevel(dev, channel);
1319 case CMD_ID_WRITE_PORT_ULONG:
1320 write_nic_dword(dev, CurrentCmd->para_1,
1321 CurrentCmd->para_2);
1323 case CMD_ID_WRITE_PORT_USHORT:
1324 write_nic_word(dev, CurrentCmd->para_1,
1325 (u16)CurrentCmd->para_2);
1327 case CMD_ID_WRITE_PORT_UCHAR:
1328 write_nic_byte(dev, CurrentCmd->para_1,
1329 (u8)CurrentCmd->para_2);
1331 case CMD_ID_RF_WRITE_REG:
1332 for (e_rfpath = 0; e_rfpath < RF90_PATH_MAX; e_rfpath++) {
1333 rtl8192_phy_SetRFReg(dev,
1334 (enum rf90_radio_path_e)e_rfpath,
1337 CurrentCmd->para_2);
1347 (*delay) = CurrentCmd->ms_delay;
1352 /******************************************************************************
1353 * function: This function does actually set channel work
1354 * input: net_device *dev
1358 * notice: We should not call this function directly
1359 *****************************************************************************/
1360 static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
1362 struct r8192_priv *priv = ieee80211_priv(dev);
1365 while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage,
1366 &priv->SwChnlStep, &delay)) {
1372 /******************************************************************************
1373 * function: Callback routine of the work item for switch channel.
1374 * input: net_device *dev
1378 *****************************************************************************/
1379 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1382 struct r8192_priv *priv = ieee80211_priv(dev);
1384 RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n",
1388 rtl8192_phy_FinishSwChnlNow(dev, priv->chan);
1390 RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n");
1393 /******************************************************************************
1394 * function: This function scheduled actual work item to set channel
1395 * input: net_device *dev
1396 * u8 channel //channel to set
1398 * return: return code show if workitem is scheduled (1:pass, 0:fail)
1399 * notice: Delay may be required for RF configuration
1400 ******************************************************************************/
1401 u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
1403 struct r8192_priv *priv = ieee80211_priv(dev);
1405 RT_TRACE(COMP_CH, "%s(), SwChnlInProgress: %d\n", __func__,
1406 priv->SwChnlInProgress);
1409 if (priv->SwChnlInProgress)
1412 /* -------------------------------------------- */
1413 switch (priv->ieee80211->mode) {
1414 case WIRELESS_MODE_A:
1415 case WIRELESS_MODE_N_5G:
1416 if (channel <= 14) {
1417 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14\n");
1421 case WIRELESS_MODE_B:
1423 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14\n");
1427 case WIRELESS_MODE_G:
1428 case WIRELESS_MODE_N_24G:
1430 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14\n");
1435 /* -------------------------------------------- */
1437 priv->SwChnlInProgress = true;
1441 priv->chan = channel;
1443 priv->SwChnlStage = 0;
1444 priv->SwChnlStep = 0;
1446 rtl8192_SwChnl_WorkItem(dev);
1448 priv->SwChnlInProgress = false;
1452 /******************************************************************************
1453 * function: Callback routine of the work item for set bandwidth mode.
1454 * input: net_device *dev
1457 * notice: I doubt whether SetBWModeInProgress flag is necessary as we can
1458 * test whether current work in the queue or not.//do I?
1459 *****************************************************************************/
1460 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1463 struct r8192_priv *priv = ieee80211_priv(dev);
1466 RT_TRACE(COMP_SWBW, "%s() Switch to %s bandwidth\n", __func__,
1467 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
1470 if (priv->rf_chip == RF_PSEUDO_11N) {
1471 priv->SetBWModeInProgress = false;
1475 /* <1> Set MAC register */
1476 read_nic_byte(dev, BW_OPMODE, ®BwOpMode);
1478 switch (priv->CurrentChannelBW) {
1479 case HT_CHANNEL_WIDTH_20:
1480 regBwOpMode |= BW_OPMODE_20MHZ;
1481 /* We have not verify whether this register works */
1482 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1485 case HT_CHANNEL_WIDTH_20_40:
1486 regBwOpMode &= ~BW_OPMODE_20MHZ;
1487 /* We have not verify whether this register works */
1488 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1493 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1494 priv->CurrentChannelBW);
1498 /* <2> Set PHY related register */
1499 switch (priv->CurrentChannelBW) {
1500 case HT_CHANNEL_WIDTH_20:
1501 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1502 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1503 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1506 /* Correct the tx power for CCK rate in 20M. */
1507 priv->cck_present_attenuation =
1508 priv->cck_present_attenuation_20Mdefault +
1509 priv->cck_present_attenuation_difference;
1511 if (priv->cck_present_attenuation > 22)
1512 priv->cck_present_attenuation = 22;
1513 if (priv->cck_present_attenuation < 0)
1514 priv->cck_present_attenuation = 0;
1516 "20M, pHalData->CCKPresentAttentuation = %d\n",
1517 priv->cck_present_attenuation);
1519 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1520 priv->bcck_in_ch14 = true;
1521 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1522 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1523 priv->bcck_in_ch14 = false;
1524 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1526 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1530 case HT_CHANNEL_WIDTH_20_40:
1531 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1532 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1533 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
1534 priv->nCur40MhzPrimeSC >> 1);
1535 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1536 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
1537 priv->nCur40MhzPrimeSC);
1538 priv->cck_present_attenuation =
1539 priv->cck_present_attenuation_40Mdefault +
1540 priv->cck_present_attenuation_difference;
1542 if (priv->cck_present_attenuation > 22)
1543 priv->cck_present_attenuation = 22;
1544 if (priv->cck_present_attenuation < 0)
1545 priv->cck_present_attenuation = 0;
1548 "40M, pHalData->CCKPresentAttentuation = %d\n",
1549 priv->cck_present_attenuation);
1550 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1551 priv->bcck_in_ch14 = true;
1552 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1553 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1554 priv->bcck_in_ch14 = false;
1555 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1557 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1563 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1564 priv->CurrentChannelBW);
1568 /* Skip over setting of J-mode in BB register here.
1569 * Default value is "None J mode".
1572 /* <3> Set RF related register */
1573 switch (priv->rf_chip) {
1578 phy_set_rf8256_bandwidth(dev, priv->CurrentChannelBW);
1588 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1591 priv->SetBWModeInProgress = false;
1593 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d\n",
1594 atomic_read(&priv->ieee80211->atm_swbw));
1597 /******************************************************************************
1598 * function: This function schedules bandwidth switch work.
1599 * input: struct net_deviceq *dev
1600 * HT_CHANNEL_WIDTH bandwidth //20M or 40M
1601 * HT_EXTCHNL_OFFSET offset //Upper, Lower, or Don't care
1604 * notice: I doubt whether SetBWModeInProgress flag is necessary as we can
1605 * test whether current work in the queue or not.//do I?
1606 *****************************************************************************/
1607 void rtl8192_SetBWMode(struct net_device *dev,
1608 enum ht_channel_width bandwidth,
1609 enum ht_extension_chan_offset offset)
1611 struct r8192_priv *priv = ieee80211_priv(dev);
1613 if (priv->SetBWModeInProgress)
1615 priv->SetBWModeInProgress = true;
1617 priv->CurrentChannelBW = bandwidth;
1619 if (offset == HT_EXTCHNL_OFFSET_LOWER)
1620 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1621 else if (offset == HT_EXTCHNL_OFFSET_UPPER)
1622 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1624 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1626 rtl8192_SetBWModeWorkItem(dev);
1630 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
1632 struct r8192_priv *priv = ieee80211_priv(dev);
1634 priv->InitialGainOperateType = Operation;
1637 queue_delayed_work(priv->priv_wq, &priv->initialgain_operate_wq, 0);
1640 void InitialGainOperateWorkItemCallBack(struct work_struct *work)
1642 struct delayed_work *dwork = to_delayed_work(work);
1643 struct r8192_priv *priv = container_of(dwork, struct r8192_priv,
1644 initialgain_operate_wq);
1645 struct net_device *dev = priv->ieee80211->dev;
1646 #define SCAN_RX_INITIAL_GAIN 0x17
1647 #define POWER_DETECTION_TH 0x08
1652 Operation = priv->InitialGainOperateType;
1654 switch (Operation) {
1656 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
1657 initial_gain = SCAN_RX_INITIAL_GAIN;
1658 bitmask = bMaskByte0;
1659 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1661 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1662 priv->initgain_backup.xaagccore1 =
1663 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bitmask);
1664 priv->initgain_backup.xbagccore1 =
1665 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bitmask);
1666 priv->initgain_backup.xcagccore1 =
1667 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bitmask);
1668 priv->initgain_backup.xdagccore1 =
1669 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bitmask);
1670 bitmask = bMaskByte2;
1671 priv->initgain_backup.cca =
1672 (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bitmask);
1674 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",
1675 priv->initgain_backup.xaagccore1);
1676 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",
1677 priv->initgain_backup.xbagccore1);
1678 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",
1679 priv->initgain_backup.xcagccore1);
1680 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",
1681 priv->initgain_backup.xdagccore1);
1682 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",
1683 priv->initgain_backup.cca);
1685 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n",
1687 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1688 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1689 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1690 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1691 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n",
1692 POWER_DETECTION_TH);
1693 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1696 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
1697 bitmask = 0x7f; /* Bit0 ~ Bit6 */
1698 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1700 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1702 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bitmask,
1703 (u32)priv->initgain_backup.xaagccore1);
1704 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bitmask,
1705 (u32)priv->initgain_backup.xbagccore1);
1706 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bitmask,
1707 (u32)priv->initgain_backup.xcagccore1);
1708 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bitmask,
1709 (u32)priv->initgain_backup.xdagccore1);
1710 bitmask = bMaskByte2;
1711 rtl8192_setBBreg(dev, rCCK0_CCA, bitmask,
1712 (u32)priv->initgain_backup.cca);
1714 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",
1715 priv->initgain_backup.xaagccore1);
1716 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",
1717 priv->initgain_backup.xbagccore1);
1718 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",
1719 priv->initgain_backup.xcagccore1);
1720 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",
1721 priv->initgain_backup.xdagccore1);
1722 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",
1723 priv->initgain_backup.cca);
1725 rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel);
1727 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1729 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
1732 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");