drivers/staging/rtl8192u/r8192U_dm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*++
   3 Copyright-c Realtek Semiconductor Corp. All rights reserved.
   4
   5 Module Name:
   6         r8192U_dm.c
   7
   8 Abstract:
   9         HW dynamic mechanism.
  10
  11 Major Change History:
  12         When            Who                             What
  13         ----------      --------------- -------------------------------
  14         2008-05-14      amy                     create version 0 porting from windows code.
  15
  16 --*/
  17 #include "r8192U.h"
  18 #include "r8192U_dm.h"
  19 #include "r8192U_hw.h"
  20 #include "r819xU_phy.h"
  21 #include "r819xU_phyreg.h"
  22 #include "r8190_rtl8256.h"
  23 #include "r819xU_cmdpkt.h"
  24 /*---------------------------Define Local Constant---------------------------*/
  25 /* Indicate different AP vendor for IOT issue. */
  26 static u32 edca_setting_DL[HT_IOT_PEER_MAX] = {
  27         0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0x00a44f, 0x5ea44f
  28 };
  29 static u32 edca_setting_UL[HT_IOT_PEER_MAX] = {
  30         0x5e4322, 0x00a44f, 0x5e4322, 0x604322, 0x5ea44f, 0x5ea44f
  31 };
  32
  33 #define RTK_UL_EDCA 0xa44f
  34 #define RTK_DL_EDCA 0x5e4322
  35 /*---------------------------Define Local Constant---------------------------*/
  36
  37
  38 /*------------------------Define global variable-----------------------------*/
  39 /* Debug variable ? */
  40 struct dig dm_digtable;
  41 /* Store current software write register content for MAC PHY. */
  42 u8              dm_shadow[16][256] = { {0} };
  43 /* For Dynamic Rx Path Selection by Signal Strength */
  44 static struct dynamic_rx_path_sel DM_RxPathSelTable;
  45
  46 extern  void dm_check_fsync(struct net_device *dev);
  47
  48 /* DM --> Rate Adaptive */
  49 static  void    dm_check_rate_adaptive(struct net_device *dev);
  50
  51 /* DM --> Bandwidth switch */
  52 static  void    dm_init_bandwidth_autoswitch(struct net_device *dev);
  53 static  void    dm_bandwidth_autoswitch(struct net_device *dev);
  54
  55 /* DM --> TX power control */
  56 /*static        void    dm_initialize_txpower_tracking(struct net_device *dev);*/
  57
  58 static  void    dm_check_txpower_tracking(struct net_device *dev);
  59
  60 /*static        void    dm_txpower_reset_recovery(struct net_device *dev);*/
  61
  62 /* DM --> Dynamic Init Gain by RSSI */
  63 static  void    dm_dig_init(struct net_device *dev);
  64 static  void    dm_ctrl_initgain_byrssi(struct net_device *dev);
  65 static  void    dm_ctrl_initgain_byrssi_highpwr(struct net_device *dev);
  66 static  void    dm_ctrl_initgain_byrssi_by_driverrssi(struct net_device *dev);
  67 static  void    dm_ctrl_initgain_byrssi_by_fwfalse_alarm(struct net_device *dev);
  68 static  void    dm_initial_gain(struct net_device *dev);
  69 static  void    dm_pd_th(struct net_device *dev);
  70 static  void    dm_cs_ratio(struct net_device *dev);
  71
  72 static  void dm_init_ctstoself(struct net_device *dev);
  73 /* DM --> EDCA turbo mode control */
  74 static  void    dm_check_edca_turbo(struct net_device *dev);
  75
  76 /*static        void    dm_gpio_change_rf(struct net_device *dev);*/
  77 /* DM --> Check PBC */
  78 static  void dm_check_pbc_gpio(struct net_device *dev);
  79
  80 /* DM --> Check current RX RF path state */
  81 static  void    dm_check_rx_path_selection(struct net_device *dev);
  82 static  void dm_init_rxpath_selection(struct net_device *dev);
  83 static  void dm_rxpath_sel_byrssi(struct net_device *dev);
  84
  85 /* DM --> Fsync for broadcom ap */
  86 static void dm_init_fsync(struct net_device *dev);
  87 static void dm_deInit_fsync(struct net_device *dev);
  88
  89 /* Added by vivi, 20080522 */
  90 static  void    dm_check_txrateandretrycount(struct net_device *dev);
  91
  92 /*---------------------Define local function prototype-----------------------*/
  93
  94 /*---------------------Define of Tx Power Control For Near/Far Range --------*/   /*Add by Jacken 2008/02/18 */
  95 static  void    dm_init_dynamic_txpower(struct net_device *dev);
  96 static  void    dm_dynamic_txpower(struct net_device *dev);
  97
  98 /* DM --> For rate adaptive and DIG, we must send RSSI to firmware */
  99 static  void dm_send_rssi_tofw(struct net_device *dev);
 100 static  void    dm_ctstoself(struct net_device *dev);
 101 /*---------------------------Define function prototype------------------------*/
 102 /*
 103  * ================================================================================
 104  *      HW Dynamic mechanism interface.
 105  * ================================================================================
 106  *
 107  *
 108  *      Description:
 109  *              Prepare SW resource for HW dynamic mechanism.
 110  *
 111  *      Assumption:
 112  *              This function is only invoked at driver initialization once.
 113  */
 114 void init_hal_dm(struct net_device *dev)
 115 {
 116         struct r8192_priv *priv = ieee80211_priv(dev);
 117
 118         /* Undecorated Smoothed Signal Strength, it can utilized to dynamic mechanism. */
 119         priv->undecorated_smoothed_pwdb = -1;
 120
 121         /* Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code. */
 122         dm_init_dynamic_txpower(dev);
 123         init_rate_adaptive(dev);
 124         /*dm_initialize_txpower_tracking(dev);*/
 125         dm_dig_init(dev);
 126         dm_init_edca_turbo(dev);
 127         dm_init_bandwidth_autoswitch(dev);
 128         dm_init_fsync(dev);
 129         dm_init_rxpath_selection(dev);
 130         dm_init_ctstoself(dev);
 131
 132 }       /* InitHalDm */
 133
 134 void deinit_hal_dm(struct net_device *dev)
 135 {
 136         dm_deInit_fsync(dev);
 137 }
 138
 139 #ifdef USB_RX_AGGREGATION_SUPPORT
 140 void dm_CheckRxAggregation(struct net_device *dev)
 141 {
 142         struct r8192_priv *priv = ieee80211_priv(dev);
 143         PRT_HIGH_THROUGHPUT     pHTInfo = priv->ieee80211->pHTInfo;
 144         static unsigned long    lastTxOkCnt;
 145         static unsigned long    lastRxOkCnt;
 146         unsigned long           curTxOkCnt = 0;
 147         unsigned long           curRxOkCnt = 0;
 148
 149 /*
 150         if (pHalData->bForcedUsbRxAggr) {
 151                 if (pHalData->ForcedUsbRxAggrInfo == 0) {
 152                         if (pHalData->bCurrentRxAggrEnable) {
 153                                 Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, FALSE);
 154                         }
 155                 } else {
 156                         if (!pHalData->bCurrentRxAggrEnable || (pHalData->ForcedUsbRxAggrInfo != pHalData->LastUsbRxAggrInfoSetting)) {
 157                                 Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, TRUE);
 158                         }
 159                 }
 160                 return;
 161         }
 162
 163 */
 164         curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
 165         curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
 166
 167         if ((curTxOkCnt + curRxOkCnt) < 15000000)
 168                 return;
 169
 170         if (curTxOkCnt > 4*curRxOkCnt) {
 171                 if (priv->bCurrentRxAggrEnable) {
 172                         write_nic_dword(dev, 0x1a8, 0);
 173                         priv->bCurrentRxAggrEnable = false;
 174                 }
 175         } else {
 176                 if (!priv->bCurrentRxAggrEnable && !pHTInfo->bCurrentRT2RTAggregation) {
 177                         u32 ulValue;
 178
 179                         ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) |
 180                                 (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout);
 181                         /*
 182                          * If usb rx firmware aggregation is enabled,
 183                          * when anyone of three threshold conditions above is reached,
 184                          * firmware will send aggregated packet to driver.
 185                          */
 186                         write_nic_dword(dev, 0x1a8, ulValue);
 187                         priv->bCurrentRxAggrEnable = true;
 188                 }
 189         }
 190
 191         lastTxOkCnt = priv->stats.txbytesunicast;
 192         lastRxOkCnt = priv->stats.rxbytesunicast;
 193 }       /* dm_CheckEdcaTurbo */
 194 #endif
 195
 196 void hal_dm_watchdog(struct net_device *dev)
 197 {
 198         /*struct r8192_priv *priv = ieee80211_priv(dev);*/
 199
 200         /*static u8     previous_bssid[6] ={0};*/
 201
 202         /*Add by amy 2008/05/15 ,porting from windows code.*/
 203         dm_check_rate_adaptive(dev);
 204         dm_dynamic_txpower(dev);
 205         dm_check_txrateandretrycount(dev);
 206         dm_check_txpower_tracking(dev);
 207         dm_ctrl_initgain_byrssi(dev);
 208         dm_check_edca_turbo(dev);
 209         dm_bandwidth_autoswitch(dev);
 210         dm_check_rx_path_selection(dev);
 211         dm_check_fsync(dev);
 212
 213         /* Add by amy 2008-05-15 porting from windows code. */
 214         dm_check_pbc_gpio(dev);
 215         dm_send_rssi_tofw(dev);
 216         dm_ctstoself(dev);
 217 #ifdef USB_RX_AGGREGATION_SUPPORT
 218         dm_CheckRxAggregation(dev);
 219 #endif
 220 }       /* HalDmWatchDog */
 221
 222 /*
 223  * Decide Rate Adaptive Set according to distance (signal strength)
 224  *      01/11/2008      MHC             Modify input arguments and RATR table level.
 225  *      01/16/2008      MHC             RF_Type is assigned in ReadAdapterInfo(). We must call
 226  *                                              the function after making sure RF_Type.
 227  */
 228 void init_rate_adaptive(struct net_device *dev)
 229 {
 230         struct r8192_priv *priv = ieee80211_priv(dev);
 231         prate_adaptive  pra = (prate_adaptive)&priv->rate_adaptive;
 232
 233         pra->ratr_state = DM_RATR_STA_MAX;
 234         pra->high2low_rssi_thresh_for_ra = RATE_ADAPTIVE_TH_HIGH;
 235         pra->low2high_rssi_thresh_for_ra20M = RATE_ADAPTIVE_TH_LOW_20M + 5;
 236         pra->low2high_rssi_thresh_for_ra40M = RATE_ADAPTIVE_TH_LOW_40M + 5;
 237
 238         pra->high_rssi_thresh_for_ra = RATE_ADAPTIVE_TH_HIGH + 5;
 239         pra->low_rssi_thresh_for_ra20M = RATE_ADAPTIVE_TH_LOW_20M;
 240         pra->low_rssi_thresh_for_ra40M = RATE_ADAPTIVE_TH_LOW_40M;
 241
 242         if (priv->CustomerID == RT_CID_819x_Netcore)
 243                 pra->ping_rssi_enable = 1;
 244         else
 245                 pra->ping_rssi_enable = 0;
 246         pra->ping_rssi_thresh_for_ra = 15;
 247
 248         if (priv->rf_type == RF_2T4R) {
 249                 /*
 250                  * 07/10/08 MH Modify for RA smooth scheme.
 251                  * 2008/01/11 MH Modify 2T RATR table for different RSSI. 080515 porting by amy from windows code.
 252                  */
 253                 pra->upper_rssi_threshold_ratr          =       0x8f0f0000;
 254                 pra->middle_rssi_threshold_ratr         =       0x8f0ff000;
 255                 pra->low_rssi_threshold_ratr            =       0x8f0ff001;
 256                 pra->low_rssi_threshold_ratr_40M        =       0x8f0ff005;
 257                 pra->low_rssi_threshold_ratr_20M        =       0x8f0ff001;
 258                 pra->ping_rssi_ratr     =       0x0000000d;/* cosa add for test */
 259         } else if (priv->rf_type == RF_1T2R) {
 260                 pra->upper_rssi_threshold_ratr          =       0x000f0000;
 261                 pra->middle_rssi_threshold_ratr         =       0x000ff000;
 262                 pra->low_rssi_threshold_ratr            =       0x000ff001;
 263                 pra->low_rssi_threshold_ratr_40M        =       0x000ff005;
 264                 pra->low_rssi_threshold_ratr_20M        =       0x000ff001;
 265                 pra->ping_rssi_ratr     =       0x0000000d;/* cosa add for test */
 266         }
 267
 268 }       /* InitRateAdaptive */
 269
 270 /*-----------------------------------------------------------------------------
 271  * Function:    dm_check_rate_adaptive()
 272  *
 273  * Overview:
 274  *
 275  * Input:               NONE
 276  *
 277  * Output:              NONE
 278  *
 279  * Return:              NONE
 280  *
 281  * Revised History:
 282  *      When            Who             Remark
 283  *      05/26/08        amy     Create version 0 porting from windows code.
 284  *
 285  *---------------------------------------------------------------------------*/
 286 static void dm_check_rate_adaptive(struct net_device *dev)
 287 {
 288         struct r8192_priv *priv = ieee80211_priv(dev);
 289         PRT_HIGH_THROUGHPUT     pHTInfo = priv->ieee80211->pHTInfo;
 290         prate_adaptive                  pra = (prate_adaptive)&priv->rate_adaptive;
 291         u32                                             currentRATR, targetRATR = 0;
 292         u32                                             LowRSSIThreshForRA = 0, HighRSSIThreshForRA = 0;
 293         bool                                            bshort_gi_enabled = false;
 294         static u8                                       ping_rssi_state;
 295
 296         if (!priv->up) {
 297                 RT_TRACE(COMP_RATE, "<---- dm_check_rate_adaptive(): driver is going to unload\n");
 298                 return;
 299         }
 300
 301         if (pra->rate_adaptive_disabled) /* this variable is set by ioctl. */
 302                 return;
 303
 304         /* TODO: Only 11n mode is implemented currently, */
 305         if (!(priv->ieee80211->mode == WIRELESS_MODE_N_24G ||
 306               priv->ieee80211->mode == WIRELESS_MODE_N_5G))
 307                 return;
 308
 309         if (priv->ieee80211->state == IEEE80211_LINKED) {
 310                 /*RT_TRACE(COMP_RATE, "dm_CheckRateAdaptive(): \t");*/
 311
 312                 /* Check whether Short GI is enabled */
 313                 bshort_gi_enabled = (pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI40MHz) ||
 314                         (!pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI20MHz);
 315
 316                 pra->upper_rssi_threshold_ratr =
 317                                 (pra->upper_rssi_threshold_ratr & (~BIT(31))) |
 318                                 ((bshort_gi_enabled) ? BIT(31) : 0);
 319
 320                 pra->middle_rssi_threshold_ratr =
 321                                 (pra->middle_rssi_threshold_ratr & (~BIT(31))) |
 322                                 ((bshort_gi_enabled) ? BIT(31) : 0);
 323
 324                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
 325                         pra->low_rssi_threshold_ratr =
 326                               (pra->low_rssi_threshold_ratr_40M & (~BIT(31))) |
 327                               ((bshort_gi_enabled) ? BIT(31) : 0);
 328                 } else {
 329                         pra->low_rssi_threshold_ratr =
 330                         (pra->low_rssi_threshold_ratr_20M & (~BIT(31))) |
 331                         ((bshort_gi_enabled) ? BIT(31) : 0);
 332                 }
 333                 /* cosa add for test */
 334                 pra->ping_rssi_ratr =
 335                                 (pra->ping_rssi_ratr & (~BIT(31))) |
 336                                 ((bshort_gi_enabled) ? BIT(31) : 0);
 337
 338                 /* 2007/10/08 MH We support RA smooth scheme now. When it is the first
 339                    time to link with AP. We will not change upper/lower threshold. If
 340                    STA stay in high or low level, we must change two different threshold
 341                    to prevent jumping frequently. */
 342                 if (pra->ratr_state == DM_RATR_STA_HIGH) {
 343                         HighRSSIThreshForRA     = pra->high2low_rssi_thresh_for_ra;
 344                         LowRSSIThreshForRA      = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ?
 345                                         (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
 346                 } else if (pra->ratr_state == DM_RATR_STA_LOW) {
 347                         HighRSSIThreshForRA     = pra->high_rssi_thresh_for_ra;
 348                         LowRSSIThreshForRA      = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ?
 349                                         (pra->low2high_rssi_thresh_for_ra40M):(pra->low2high_rssi_thresh_for_ra20M);
 350                 } else {
 351                         HighRSSIThreshForRA     = pra->high_rssi_thresh_for_ra;
 352                         LowRSSIThreshForRA      = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ?
 353                                         (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
 354                 }
 355
 356                 /*DbgPrint("[DM] THresh H/L=%d/%d\n\r", RATR.HighRSSIThreshForRA, RATR.LowRSSIThreshForRA);*/
 357                 if (priv->undecorated_smoothed_pwdb >= (long)HighRSSIThreshForRA) {
 358                         /*DbgPrint("[DM] RSSI=%d STA=HIGH\n\r", pHalData->UndecoratedSmoothedPWDB);*/
 359                         pra->ratr_state = DM_RATR_STA_HIGH;
 360                         targetRATR = pra->upper_rssi_threshold_ratr;
 361                 } else if (priv->undecorated_smoothed_pwdb >= (long)LowRSSIThreshForRA) {
 362                         /*DbgPrint("[DM] RSSI=%d STA=Middle\n\r", pHalData->UndecoratedSmoothedPWDB);*/
 363                         pra->ratr_state = DM_RATR_STA_MIDDLE;
 364                         targetRATR = pra->middle_rssi_threshold_ratr;
 365                 } else {
 366                         /*DbgPrint("[DM] RSSI=%d STA=LOW\n\r", pHalData->UndecoratedSmoothedPWDB);*/
 367                         pra->ratr_state = DM_RATR_STA_LOW;
 368                         targetRATR = pra->low_rssi_threshold_ratr;
 369                 }
 370
 371                 /* cosa add for test */
 372                 if (pra->ping_rssi_enable) {
 373                         /*pHalData->UndecoratedSmoothedPWDB = 19;*/
 374                         if (priv->undecorated_smoothed_pwdb < (long)(pra->ping_rssi_thresh_for_ra+5)) {
 375                                 if ((priv->undecorated_smoothed_pwdb < (long)pra->ping_rssi_thresh_for_ra) ||
 376                                         ping_rssi_state) {
 377                                         /*DbgPrint("TestRSSI = %d, set RATR to 0x%x\n", pHalData->UndecoratedSmoothedPWDB, pRA->TestRSSIRATR);*/
 378                                         pra->ratr_state = DM_RATR_STA_LOW;
 379                                         targetRATR = pra->ping_rssi_ratr;
 380                                         ping_rssi_state = 1;
 381                                 }
 382                                 /*else
 383                                         DbgPrint("TestRSSI is between the range.\n");*/
 384                         } else {
 385                                 /*DbgPrint("TestRSSI Recover to 0x%x\n", targetRATR);*/
 386                                 ping_rssi_state = 0;
 387                         }
 388                 }
 389
 390                 /*
 391                  * 2008.04.01
 392                  * For RTL819X, if pairwisekey = wep/tkip, we support only MCS0~7.
 393                  */
 394                 if (priv->ieee80211->GetHalfNmodeSupportByAPsHandler(dev))
 395                         targetRATR &= 0xf00fffff;
 396
 397                 /* Check whether updating of RATR0 is required */
 398                 read_nic_dword(dev, RATR0, &currentRATR);
 399                 if (targetRATR !=  currentRATR) {
 400                         u32 ratr_value;
 401
 402                         ratr_value = targetRATR;
 403                         RT_TRACE(COMP_RATE, "currentRATR = %x, targetRATR = %x\n", currentRATR, targetRATR);
 404                         if (priv->rf_type == RF_1T2R)
 405                                 ratr_value &= ~(RATE_ALL_OFDM_2SS);
 406                         write_nic_dword(dev, RATR0, ratr_value);
 407                         write_nic_byte(dev, UFWP, 1);
 408
 409                         pra->last_ratr = targetRATR;
 410                 }
 411
 412         } else {
 413                 pra->ratr_state = DM_RATR_STA_MAX;
 414         }
 415
 416 }       /* dm_CheckRateAdaptive */
 417
 418 static void dm_init_bandwidth_autoswitch(struct net_device *dev)
 419 {
 420         struct r8192_priv *priv = ieee80211_priv(dev);
 421
 422         priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz = BW_AUTO_SWITCH_LOW_HIGH;
 423         priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz = BW_AUTO_SWITCH_HIGH_LOW;
 424         priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false;
 425         priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable = false;
 426
 427 }       /* dm_init_bandwidth_autoswitch */
 428
 429 static void dm_bandwidth_autoswitch(struct net_device *dev)
 430 {
 431         struct r8192_priv *priv = ieee80211_priv(dev);
 432
 433         if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 || !priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable)
 434                 return;
 435         if (!priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz) { /* If send packets in 40 Mhz in 20/40 */
 436                 if (priv->undecorated_smoothed_pwdb <= priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz)
 437                         priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = true;
 438         } else { /* in force send packets in 20 Mhz in 20/40 */
 439                 if (priv->undecorated_smoothed_pwdb >= priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz)
 440                         priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false;
 441         }
 442 }       /* dm_BandwidthAutoSwitch */
 443
 444 /* OFDM default at 0db, index=6. */
 445 static u32 OFDMSwingTable[OFDM_Table_Length] = {
 446         0x7f8001fe,     /* 0, +6db */
 447         0x71c001c7,     /* 1, +5db */
 448         0x65400195,     /* 2, +4db */
 449         0x5a400169,     /* 3, +3db */
 450         0x50800142,     /* 4, +2db */
 451         0x47c0011f,     /* 5, +1db */
 452         0x40000100,     /* 6, +0db ===> default, upper for higher temperature, lower for low temperature */
 453         0x390000e4,     /* 7, -1db */
 454         0x32c000cb,     /* 8, -2db */
 455         0x2d4000b5,     /* 9, -3db */
 456         0x288000a2,     /* 10, -4db */
 457         0x24000090,     /* 11, -5db */
 458         0x20000080,     /* 12, -6db */
 459         0x1c800072,     /* 13, -7db */
 460         0x19800066,     /* 14, -8db */
 461         0x26c0005b,     /* 15, -9db */
 462         0x24400051,     /* 16, -10db */
 463         0x12000048,     /* 17, -11db */
 464         0x10000040      /* 18, -12db */
 465 };
 466
 467 static u8       CCKSwingTable_Ch1_Ch13[CCK_Table_length][8] = {
 468         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},       /* 0, +0db ===> CCK40M default */
 469         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},       /* 1, -1db */
 470         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},       /* 2, -2db */
 471         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},       /* 3, -3db */
 472         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},       /* 4, -4db */
 473         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},       /* 5, -5db */
 474         {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},       /* 6, -6db ===> CCK20M default */
 475         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},       /* 7, -7db */
 476         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},       /* 8, -8db */
 477         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},       /* 9, -9db */
 478         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},       /* 10, -10db */
 479         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}        /* 11, -11db */
 480 };
 481
 482 static u8       CCKSwingTable_Ch14[CCK_Table_length][8] = {
 483         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},       /* 0, +0db  ===> CCK40M default */
 484         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},       /* 1, -1db */
 485         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},       /* 2, -2db */
 486         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},       /* 3, -3db */
 487         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},       /* 4, -4db */
 488         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},       /* 5, -5db */
 489         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},       /* 6, -6db  ===> CCK20M default */
 490         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},       /* 7, -7db */
 491         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},       /* 8, -8db */
 492         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},       /* 9, -9db */
 493         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},       /* 10, -10db */
 494         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}        /* 11, -11db */
 495 };
 496
 497 static void dm_TXPowerTrackingCallback_TSSI(struct net_device *dev)
 498 {
 499         struct r8192_priv *priv = ieee80211_priv(dev);
 500         bool                                            viviflag = false;
 501         struct tx_config_cmd                            tx_cmd;
 502         u8                                              powerlevelOFDM24G;
 503         int                                             i = 0, j = 0, k = 0;
 504         u8                                              RF_Type, tmp_report[5] = {0, 0, 0, 0, 0};
 505         u32                                             Value;
 506         u8                                              Pwr_Flag;
 507         u16                                             Avg_TSSI_Meas, TSSI_13dBm, Avg_TSSI_Meas_from_driver = 0;
 508         /*RT_STATUS                             rtStatus = RT_STATUS_SUCCESS;*/
 509         bool rtStatus = true;
 510         u32                                             delta = 0;
 511
 512         write_nic_byte(dev, 0x1ba, 0);
 513
 514         priv->ieee80211->bdynamic_txpower_enable = false;
 515
 516         powerlevelOFDM24G = (u8)(priv->Pwr_Track>>24);
 517         RF_Type = priv->rf_type;
 518         Value = (RF_Type<<8) | powerlevelOFDM24G;
 519
 520         RT_TRACE(COMP_POWER_TRACKING, "powerlevelOFDM24G = %x\n", powerlevelOFDM24G);
 521
 522         for (j = 0; j <= 30; j++) { /* fill tx_cmd */
 523                 tx_cmd.cmd_op = TXCMD_SET_TX_PWR_TRACKING;
 524                 tx_cmd.cmd_length = sizeof(tx_cmd.cmd_op);
 525                 tx_cmd.cmd_value = Value;
 526                 rtStatus = SendTxCommandPacket(dev, &tx_cmd, sizeof(struct tx_config_cmd));
 527                 if (rtStatus == RT_STATUS_FAILURE)
 528                         RT_TRACE(COMP_POWER_TRACKING, "Set configuration with tx cmd queue fail!\n");
 529                 usleep_range(1000, 2000);
 530                 /*DbgPrint("hi, vivi, strange\n");*/
 531                 for (i = 0; i <= 30; i++) {
 532                         read_nic_byte(dev, 0x1ba, &Pwr_Flag);
 533
 534                         if (Pwr_Flag == 0) {
 535                                 usleep_range(1000, 2000);
 536                                 continue;
 537                         }
 538                         read_nic_word(dev, 0x13c, &Avg_TSSI_Meas);
 539                         if (Avg_TSSI_Meas == 0) {
 540                                 write_nic_byte(dev, 0x1ba, 0);
 541                                 break;
 542                         }
 543
 544                         for (k = 0; k < 5; k++) {
 545                                 if (k != 4)
 546                                         read_nic_byte(dev, 0x134+k, &tmp_report[k]);
 547                                 else
 548                                         read_nic_byte(dev, 0x13e, &tmp_report[k]);
 549                                 RT_TRACE(COMP_POWER_TRACKING, "TSSI_report_value = %d\n", tmp_report[k]);
 550                         }
 551
 552                         /* check if the report value is right */
 553                         for (k = 0; k < 5; k++) {
 554                                 if (tmp_report[k] <= 20) {
 555                                         viviflag = true;
 556                                         break;
 557                                 }
 558                         }
 559                         if (viviflag) {
 560                                 write_nic_byte(dev, 0x1ba, 0);
 561                                 viviflag = false;
 562                                 RT_TRACE(COMP_POWER_TRACKING, "we filtered the data\n");
 563                                 for (k = 0; k < 5; k++)
 564                                         tmp_report[k] = 0;
 565                                 break;
 566                         }
 567
 568                         for (k = 0; k < 5; k++)
 569                                 Avg_TSSI_Meas_from_driver += tmp_report[k];
 570
 571                         Avg_TSSI_Meas_from_driver = Avg_TSSI_Meas_from_driver*100/5;
 572                         RT_TRACE(COMP_POWER_TRACKING, "Avg_TSSI_Meas_from_driver = %d\n", Avg_TSSI_Meas_from_driver);
 573                         TSSI_13dBm = priv->TSSI_13dBm;
 574                         RT_TRACE(COMP_POWER_TRACKING, "TSSI_13dBm = %d\n", TSSI_13dBm);
 575
 576                         /*if (abs(Avg_TSSI_Meas_from_driver - TSSI_13dBm) <= E_FOR_TX_POWER_TRACK)*/
 577                         /* For MacOS-compatible */
 578                         if (Avg_TSSI_Meas_from_driver > TSSI_13dBm)
 579                                 delta = Avg_TSSI_Meas_from_driver - TSSI_13dBm;
 580                         else
 581                                 delta = TSSI_13dBm - Avg_TSSI_Meas_from_driver;
 582
 583                         if (delta <= E_FOR_TX_POWER_TRACK) {
 584                                 priv->ieee80211->bdynamic_txpower_enable = true;
 585                                 write_nic_byte(dev, 0x1ba, 0);
 586                                 RT_TRACE(COMP_POWER_TRACKING, "tx power track is done\n");
 587                                 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
 588                                 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
 589                                 RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attenuation_difference = %d\n", priv->cck_present_attenuation_difference);
 590                                 RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attenuation = %d\n", priv->cck_present_attenuation);
 591                                 return;
 592                         }
 593                         if (Avg_TSSI_Meas_from_driver < TSSI_13dBm - E_FOR_TX_POWER_TRACK) {
 594                                 if (priv->rfa_txpowertrackingindex > 0) {
 595                                         priv->rfa_txpowertrackingindex--;
 596                                         if (priv->rfa_txpowertrackingindex_real > 4) {
 597                                                 priv->rfa_txpowertrackingindex_real--;
 598                                                 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
 599                                         }
 600                                 }
 601                         } else {
 602                                 if (priv->rfa_txpowertrackingindex < 36) {
 603                                         priv->rfa_txpowertrackingindex++;
 604                                         priv->rfa_txpowertrackingindex_real++;
 605                                         rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
 606
 607                                 }
 608                         }
 609                         priv->cck_present_attenuation_difference
 610                                 = priv->rfa_txpowertrackingindex - priv->rfa_txpowertracking_default;
 611
 612                         if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
 613                                 priv->cck_present_attenuation
 614                                         = priv->cck_present_attenuation_20Mdefault + priv->cck_present_attenuation_difference;
 615                         else
 616                                 priv->cck_present_attenuation
 617                                         = priv->cck_present_attenuation_40Mdefault + priv->cck_present_attenuation_difference;
 618
 619                         if (priv->cck_present_attenuation > -1 && priv->cck_present_attenuation < 23) {
 620                                 if (priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) {
 621                                         priv->bcck_in_ch14 = true;
 622                                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
 623                                 } else if (priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) {
 624                                         priv->bcck_in_ch14 = false;
 625                                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
 626                                 } else
 627                                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
 628                         }
 629                         RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
 630                         RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
 631                         RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attenuation_difference = %d\n", priv->cck_present_attenuation_difference);
 632                         RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attenuation = %d\n", priv->cck_present_attenuation);
 633
 634                         if (priv->cck_present_attenuation_difference <= -12 || priv->cck_present_attenuation_difference >= 24) {
 635                                 priv->ieee80211->bdynamic_txpower_enable = true;
 636                                 write_nic_byte(dev, 0x1ba, 0);
 637                                 RT_TRACE(COMP_POWER_TRACKING, "tx power track--->limited\n");
 638                                 return;
 639                         }
 640
 641                         write_nic_byte(dev, 0x1ba, 0);
 642                         Avg_TSSI_Meas_from_driver = 0;
 643                         for (k = 0; k < 5; k++)
 644                                 tmp_report[k] = 0;
 645                         break;
 646                 }
 647         }
 648         priv->ieee80211->bdynamic_txpower_enable = true;
 649         write_nic_byte(dev, 0x1ba, 0);
 650 }
 651
 652 static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device *dev)
 653 {
 654 #define ThermalMeterVal 9
 655         struct r8192_priv *priv = ieee80211_priv(dev);
 656         u32 tmpRegA, TempCCk;
 657         u8 tmpOFDMindex, tmpCCKindex, tmpCCK20Mindex, tmpCCK40Mindex, tmpval;
 658         int i = 0, CCKSwingNeedUpdate = 0;
 659
 660         if (!priv->btxpower_trackingInit) {
 661                 /* Query OFDM default setting */
 662                 tmpRegA = rtl8192_QueryBBReg(dev, rOFDM0_XATxIQImbalance, bMaskDWord);
 663                 for (i = 0; i < OFDM_Table_Length; i++) { /* find the index */
 664                         if (tmpRegA == OFDMSwingTable[i]) {
 665                                 priv->OFDM_index = (u8)i;
 666                                 RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, OFDM_index=0x%x\n",
 667                                         rOFDM0_XATxIQImbalance, tmpRegA, priv->OFDM_index);
 668                         }
 669                 }
 670
 671                 /* Query CCK default setting From 0xa22 */
 672                 TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2);
 673                 for (i = 0; i < CCK_Table_length; i++) {
 674                         if (TempCCk == (u32)CCKSwingTable_Ch1_Ch13[i][0]) {
 675                                 priv->CCK_index = (u8) i;
 676                                 RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, CCK_index=0x%x\n",
 677                                         rCCK0_TxFilter1, TempCCk, priv->CCK_index);
 678                                 break;
 679                         }
 680                 }
 681                 priv->btxpower_trackingInit = true;
 682                 /*pHalData->TXPowercount = 0;*/
 683                 return;
 684         }
 685
 686         /*
 687          * ==========================
 688          * this is only for test, should be masked
 689          * ==========================
 690          */
 691
 692         /* read and filter out unreasonable value */
 693         tmpRegA = rtl8192_phy_QueryRFReg(dev, RF90_PATH_A, 0x12, 0x078);        /* 0x12: RF Reg[10:7] */
 694         RT_TRACE(COMP_POWER_TRACKING, "Readback ThermalMeterA = %d\n", tmpRegA);
 695         if (tmpRegA < 3 || tmpRegA > 13)
 696                 return;
 697         if (tmpRegA >= 12)      /* if over 12, TP will be bad when high temperature */
 698                 tmpRegA = 12;
 699         RT_TRACE(COMP_POWER_TRACKING, "Valid ThermalMeterA = %d\n", tmpRegA);
 700         priv->ThermalMeter[0] = ThermalMeterVal;        /* We use fixed value by Bryant's suggestion */
 701         priv->ThermalMeter[1] = ThermalMeterVal;        /* We use fixed value by Bryant's suggestion */
 702
 703         /* Get current RF-A temperature index */
 704         if (priv->ThermalMeter[0] >= (u8)tmpRegA) {     /* lower temperature */
 705                 tmpOFDMindex = tmpCCK20Mindex = 6+(priv->ThermalMeter[0]-(u8)tmpRegA);
 706                 tmpCCK40Mindex = tmpCCK20Mindex - 6;
 707                 if (tmpOFDMindex >= OFDM_Table_Length)
 708                         tmpOFDMindex = OFDM_Table_Length-1;
 709                 if (tmpCCK20Mindex >= CCK_Table_length)
 710                         tmpCCK20Mindex = CCK_Table_length-1;
 711                 if (tmpCCK40Mindex >= CCK_Table_length)
 712                         tmpCCK40Mindex = CCK_Table_length-1;
 713         } else {
 714                 tmpval = (u8)tmpRegA - priv->ThermalMeter[0];
 715
 716                 if (tmpval >= 6) {
 717                         /* higher temperature */
 718                         tmpOFDMindex = 0;
 719                         tmpCCK20Mindex = 0;
 720                 } else {
 721                         /* max to +6dB */
 722                         tmpOFDMindex = 6 - tmpval;
 723                         tmpCCK20Mindex = 6 - tmpval;
 724                 }
 725                 tmpCCK40Mindex = 0;
 726         }
 727         /*DbgPrint("%ddb, tmpOFDMindex = %d, tmpCCK20Mindex = %d, tmpCCK40Mindex = %d",
 728                 ((u1Byte)tmpRegA - pHalData->ThermalMeter[0]),
 729                 tmpOFDMindex, tmpCCK20Mindex, tmpCCK40Mindex);*/
 730         if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)      /* 40M */
 731                 tmpCCKindex = tmpCCK40Mindex;
 732         else
 733                 tmpCCKindex = tmpCCK20Mindex;
 734
 735         if (priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) {
 736                 priv->bcck_in_ch14 = true;
 737                 CCKSwingNeedUpdate = 1;
 738         } else if (priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) {
 739                 priv->bcck_in_ch14 = false;
 740                 CCKSwingNeedUpdate = 1;
 741         }
 742
 743         if (priv->CCK_index != tmpCCKindex) {
 744                 priv->CCK_index = tmpCCKindex;
 745                 CCKSwingNeedUpdate = 1;
 746         }
 747
 748         if (CCKSwingNeedUpdate) {
 749                 /*DbgPrint("Update CCK Swing, CCK_index = %d\n", pHalData->CCK_index);*/
 750                 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
 751         }
 752         if (priv->OFDM_index != tmpOFDMindex) {
 753                 priv->OFDM_index = tmpOFDMindex;
 754                 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[priv->OFDM_index]);
 755                 RT_TRACE(COMP_POWER_TRACKING, "Update OFDMSwing[%d] = 0x%x\n",
 756                         priv->OFDM_index, OFDMSwingTable[priv->OFDM_index]);
 757         }
 758         priv->txpower_count = 0;
 759 }
 760
 761 void dm_txpower_trackingcallback(struct work_struct *work)
 762 {
 763         struct delayed_work *dwork = to_delayed_work(work);
 764         struct r8192_priv *priv = container_of(dwork, struct r8192_priv, txpower_tracking_wq);
 765         struct net_device *dev = priv->ieee80211->dev;
 766
 767         if (priv->bDcut)
 768                 dm_TXPowerTrackingCallback_TSSI(dev);
 769         else
 770                 dm_TXPowerTrackingCallback_ThermalMeter(dev);
 771 }
 772
 773 static void dm_InitializeTXPowerTracking_TSSI(struct net_device *dev)
 774 {
 775         struct r8192_priv *priv = ieee80211_priv(dev);
 776
 777         /* Initial the Tx BB index and mapping value */
 778         priv->txbbgain_table[0].txbb_iq_amplifygain =                   12;
 779         priv->txbbgain_table[0].txbbgain_value = 0x7f8001fe;
 780         priv->txbbgain_table[1].txbb_iq_amplifygain =                   11;
 781         priv->txbbgain_table[1].txbbgain_value = 0x788001e2;
 782         priv->txbbgain_table[2].txbb_iq_amplifygain =                   10;
 783         priv->txbbgain_table[2].txbbgain_value = 0x71c001c7;
 784         priv->txbbgain_table[3].txbb_iq_amplifygain =                   9;
 785         priv->txbbgain_table[3].txbbgain_value = 0x6b8001ae;
 786         priv->txbbgain_table[4].txbb_iq_amplifygain =                  8;
 787         priv->txbbgain_table[4].txbbgain_value = 0x65400195;
 788         priv->txbbgain_table[5].txbb_iq_amplifygain =                  7;
 789         priv->txbbgain_table[5].txbbgain_value = 0x5fc0017f;
 790         priv->txbbgain_table[6].txbb_iq_amplifygain =                  6;
 791         priv->txbbgain_table[6].txbbgain_value = 0x5a400169;
 792         priv->txbbgain_table[7].txbb_iq_amplifygain =                  5;
 793         priv->txbbgain_table[7].txbbgain_value = 0x55400155;
 794         priv->txbbgain_table[8].txbb_iq_amplifygain =                  4;
 795         priv->txbbgain_table[8].txbbgain_value = 0x50800142;
 796         priv->txbbgain_table[9].txbb_iq_amplifygain =                  3;
 797         priv->txbbgain_table[9].txbbgain_value = 0x4c000130;
 798         priv->txbbgain_table[10].txbb_iq_amplifygain =                 2;
 799         priv->txbbgain_table[10].txbbgain_value = 0x47c0011f;
 800         priv->txbbgain_table[11].txbb_iq_amplifygain =                 1;
 801         priv->txbbgain_table[11].txbbgain_value = 0x43c0010f;
 802         priv->txbbgain_table[12].txbb_iq_amplifygain =                 0;
 803         priv->txbbgain_table[12].txbbgain_value = 0x40000100;
 804         priv->txbbgain_table[13].txbb_iq_amplifygain =                 -1;
 805         priv->txbbgain_table[13].txbbgain_value = 0x3c8000f2;
 806         priv->txbbgain_table[14].txbb_iq_amplifygain =               -2;
 807         priv->txbbgain_table[14].txbbgain_value = 0x390000e4;
 808         priv->txbbgain_table[15].txbb_iq_amplifygain =               -3;
 809         priv->txbbgain_table[15].txbbgain_value = 0x35c000d7;
 810         priv->txbbgain_table[16].txbb_iq_amplifygain =               -4;
 811         priv->txbbgain_table[16].txbbgain_value = 0x32c000cb;
 812         priv->txbbgain_table[17].txbb_iq_amplifygain =               -5;
 813         priv->txbbgain_table[17].txbbgain_value = 0x300000c0;
 814         priv->txbbgain_table[18].txbb_iq_amplifygain =                      -6;
 815         priv->txbbgain_table[18].txbbgain_value = 0x2d4000b5;
 816         priv->txbbgain_table[19].txbb_iq_amplifygain =               -7;
 817         priv->txbbgain_table[19].txbbgain_value = 0x2ac000ab;
 818         priv->txbbgain_table[20].txbb_iq_amplifygain =               -8;
 819         priv->txbbgain_table[20].txbbgain_value = 0x288000a2;
 820         priv->txbbgain_table[21].txbb_iq_amplifygain =               -9;
 821         priv->txbbgain_table[21].txbbgain_value = 0x26000098;
 822         priv->txbbgain_table[22].txbb_iq_amplifygain =               -10;
 823         priv->txbbgain_table[22].txbbgain_value = 0x24000090;
 824         priv->txbbgain_table[23].txbb_iq_amplifygain =               -11;
 825         priv->txbbgain_table[23].txbbgain_value = 0x22000088;
 826         priv->txbbgain_table[24].txbb_iq_amplifygain =               -12;
 827         priv->txbbgain_table[24].txbbgain_value = 0x20000080;
 828         priv->txbbgain_table[25].txbb_iq_amplifygain =               -13;
 829         priv->txbbgain_table[25].txbbgain_value = 0x1a00006c;
 830         priv->txbbgain_table[26].txbb_iq_amplifygain =               -14;
 831         priv->txbbgain_table[26].txbbgain_value = 0x1c800072;
 832         priv->txbbgain_table[27].txbb_iq_amplifygain =               -15;
 833         priv->txbbgain_table[27].txbbgain_value = 0x18000060;
 834         priv->txbbgain_table[28].txbb_iq_amplifygain =               -16;
 835         priv->txbbgain_table[28].txbbgain_value = 0x19800066;
 836         priv->txbbgain_table[29].txbb_iq_amplifygain =               -17;
 837         priv->txbbgain_table[29].txbbgain_value = 0x15800056;
 838         priv->txbbgain_table[30].txbb_iq_amplifygain =               -18;
 839         priv->txbbgain_table[30].txbbgain_value = 0x26c0005b;
 840         priv->txbbgain_table[31].txbb_iq_amplifygain =               -19;
 841         priv->txbbgain_table[31].txbbgain_value = 0x14400051;
 842         priv->txbbgain_table[32].txbb_iq_amplifygain =               -20;
 843         priv->txbbgain_table[32].txbbgain_value = 0x24400051;
 844         priv->txbbgain_table[33].txbb_iq_amplifygain =               -21;
 845         priv->txbbgain_table[33].txbbgain_value = 0x1300004c;
 846         priv->txbbgain_table[34].txbb_iq_amplifygain =               -22;
 847         priv->txbbgain_table[34].txbbgain_value = 0x12000048;
 848         priv->txbbgain_table[35].txbb_iq_amplifygain =               -23;
 849         priv->txbbgain_table[35].txbbgain_value = 0x11000044;
 850         priv->txbbgain_table[36].txbb_iq_amplifygain =               -24;
 851         priv->txbbgain_table[36].txbbgain_value = 0x10000040;
 852
 853         /*
 854          * ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
 855          * This Table is for CH1~CH13
 856          */
 857         priv->cck_txbbgain_table[0].ccktxbb_valuearray[0] = 0x36;
 858         priv->cck_txbbgain_table[0].ccktxbb_valuearray[1] = 0x35;
 859         priv->cck_txbbgain_table[0].ccktxbb_valuearray[2] = 0x2e;
 860         priv->cck_txbbgain_table[0].ccktxbb_valuearray[3] = 0x25;
 861         priv->cck_txbbgain_table[0].ccktxbb_valuearray[4] = 0x1c;
 862         priv->cck_txbbgain_table[0].ccktxbb_valuearray[5] = 0x12;
 863         priv->cck_txbbgain_table[0].ccktxbb_valuearray[6] = 0x09;
 864         priv->cck_txbbgain_table[0].ccktxbb_valuearray[7] = 0x04;
 865
 866         priv->cck_txbbgain_table[1].ccktxbb_valuearray[0] = 0x33;
 867         priv->cck_txbbgain_table[1].ccktxbb_valuearray[1] = 0x32;
 868         priv->cck_txbbgain_table[1].ccktxbb_valuearray[2] = 0x2b;
 869         priv->cck_txbbgain_table[1].ccktxbb_valuearray[3] = 0x23;
 870         priv->cck_txbbgain_table[1].ccktxbb_valuearray[4] = 0x1a;
 871         priv->cck_txbbgain_table[1].ccktxbb_valuearray[5] = 0x11;
 872         priv->cck_txbbgain_table[1].ccktxbb_valuearray[6] = 0x08;
 873         priv->cck_txbbgain_table[1].ccktxbb_valuearray[7] = 0x04;
 874
 875         priv->cck_txbbgain_table[2].ccktxbb_valuearray[0] = 0x30;
 876         priv->cck_txbbgain_table[2].ccktxbb_valuearray[1] = 0x2f;
 877         priv->cck_txbbgain_table[2].ccktxbb_valuearray[2] = 0x29;
 878         priv->cck_txbbgain_table[2].ccktxbb_valuearray[3] = 0x21;
 879         priv->cck_txbbgain_table[2].ccktxbb_valuearray[4] = 0x19;
 880         priv->cck_txbbgain_table[2].ccktxbb_valuearray[5] = 0x10;
 881         priv->cck_txbbgain_table[2].ccktxbb_valuearray[6] = 0x08;
 882         priv->cck_txbbgain_table[2].ccktxbb_valuearray[7] = 0x03;
 883
 884         priv->cck_txbbgain_table[3].ccktxbb_valuearray[0] = 0x2d;
 885         priv->cck_txbbgain_table[3].ccktxbb_valuearray[1] = 0x2d;
 886         priv->cck_txbbgain_table[3].ccktxbb_valuearray[2] = 0x27;
 887         priv->cck_txbbgain_table[3].ccktxbb_valuearray[3] = 0x1f;
 888         priv->cck_txbbgain_table[3].ccktxbb_valuearray[4] = 0x18;
 889         priv->cck_txbbgain_table[3].ccktxbb_valuearray[5] = 0x0f;
 890         priv->cck_txbbgain_table[3].ccktxbb_valuearray[6] = 0x08;
 891         priv->cck_txbbgain_table[3].ccktxbb_valuearray[7] = 0x03;
 892
 893         priv->cck_txbbgain_table[4].ccktxbb_valuearray[0] = 0x2b;
 894         priv->cck_txbbgain_table[4].ccktxbb_valuearray[1] = 0x2a;
 895         priv->cck_txbbgain_table[4].ccktxbb_valuearray[2] = 0x25;
 896         priv->cck_txbbgain_table[4].ccktxbb_valuearray[3] = 0x1e;
 897         priv->cck_txbbgain_table[4].ccktxbb_valuearray[4] = 0x16;
 898         priv->cck_txbbgain_table[4].ccktxbb_valuearray[5] = 0x0e;
 899         priv->cck_txbbgain_table[4].ccktxbb_valuearray[6] = 0x07;
 900         priv->cck_txbbgain_table[4].ccktxbb_valuearray[7] = 0x03;
 901
 902         priv->cck_txbbgain_table[5].ccktxbb_valuearray[0] = 0x28;
 903         priv->cck_txbbgain_table[5].ccktxbb_valuearray[1] = 0x28;
 904         priv->cck_txbbgain_table[5].ccktxbb_valuearray[2] = 0x22;
 905         priv->cck_txbbgain_table[5].ccktxbb_valuearray[3] = 0x1c;
 906         priv->cck_txbbgain_table[5].ccktxbb_valuearray[4] = 0x15;
 907         priv->cck_txbbgain_table[5].ccktxbb_valuearray[5] = 0x0d;
 908         priv->cck_txbbgain_table[5].ccktxbb_valuearray[6] = 0x07;
 909         priv->cck_txbbgain_table[5].ccktxbb_valuearray[7] = 0x03;
 910
 911         priv->cck_txbbgain_table[6].ccktxbb_valuearray[0] = 0x26;
 912         priv->cck_txbbgain_table[6].ccktxbb_valuearray[1] = 0x25;
 913         priv->cck_txbbgain_table[6].ccktxbb_valuearray[2] = 0x21;
 914         priv->cck_txbbgain_table[6].ccktxbb_valuearray[3] = 0x1b;
 915         priv->cck_txbbgain_table[6].ccktxbb_valuearray[4] = 0x14;
 916         priv->cck_txbbgain_table[6].ccktxbb_valuearray[5] = 0x0d;
 917         priv->cck_txbbgain_table[6].ccktxbb_valuearray[6] = 0x06;
 918         priv->cck_txbbgain_table[6].ccktxbb_valuearray[7] = 0x03;
 919
 920         priv->cck_txbbgain_table[7].ccktxbb_valuearray[0] = 0x24;
 921         priv->cck_txbbgain_table[7].ccktxbb_valuearray[1] = 0x23;
 922         priv->cck_txbbgain_table[7].ccktxbb_valuearray[2] = 0x1f;
 923         priv->cck_txbbgain_table[7].ccktxbb_valuearray[3] = 0x19;
 924         priv->cck_txbbgain_table[7].ccktxbb_valuearray[4] = 0x13;
 925         priv->cck_txbbgain_table[7].ccktxbb_valuearray[5] = 0x0c;
 926         priv->cck_txbbgain_table[7].ccktxbb_valuearray[6] = 0x06;
 927         priv->cck_txbbgain_table[7].ccktxbb_valuearray[7] = 0x03;
 928
 929         priv->cck_txbbgain_table[8].ccktxbb_valuearray[0] = 0x22;
 930         priv->cck_txbbgain_table[8].ccktxbb_valuearray[1] = 0x21;
 931         priv->cck_txbbgain_table[8].ccktxbb_valuearray[2] = 0x1d;
 932         priv->cck_txbbgain_table[8].ccktxbb_valuearray[3] = 0x18;
 933         priv->cck_txbbgain_table[8].ccktxbb_valuearray[4] = 0x11;
 934         priv->cck_txbbgain_table[8].ccktxbb_valuearray[5] = 0x0b;
 935         priv->cck_txbbgain_table[8].ccktxbb_valuearray[6] = 0x06;
 936         priv->cck_txbbgain_table[8].ccktxbb_valuearray[7] = 0x02;
 937
 938         priv->cck_txbbgain_table[9].ccktxbb_valuearray[0] = 0x20;
 939         priv->cck_txbbgain_table[9].ccktxbb_valuearray[1] = 0x20;
 940         priv->cck_txbbgain_table[9].ccktxbb_valuearray[2] = 0x1b;
 941         priv->cck_txbbgain_table[9].ccktxbb_valuearray[3] = 0x16;
 942         priv->cck_txbbgain_table[9].ccktxbb_valuearray[4] = 0x11;
 943         priv->cck_txbbgain_table[9].ccktxbb_valuearray[5] = 0x08;
 944         priv->cck_txbbgain_table[9].ccktxbb_valuearray[6] = 0x05;
 945         priv->cck_txbbgain_table[9].ccktxbb_valuearray[7] = 0x02;
 946
 947         priv->cck_txbbgain_table[10].ccktxbb_valuearray[0] = 0x1f;
 948         priv->cck_txbbgain_table[10].ccktxbb_valuearray[1] = 0x1e;
 949         priv->cck_txbbgain_table[10].ccktxbb_valuearray[2] = 0x1a;
 950         priv->cck_txbbgain_table[10].ccktxbb_valuearray[3] = 0x15;
 951         priv->cck_txbbgain_table[10].ccktxbb_valuearray[4] = 0x10;
 952         priv->cck_txbbgain_table[10].ccktxbb_valuearray[5] = 0x0a;
 953         priv->cck_txbbgain_table[10].ccktxbb_valuearray[6] = 0x05;
 954         priv->cck_txbbgain_table[10].ccktxbb_valuearray[7] = 0x02;
 955
 956         priv->cck_txbbgain_table[11].ccktxbb_valuearray[0] = 0x1d;
 957         priv->cck_txbbgain_table[11].ccktxbb_valuearray[1] = 0x1c;
 958         priv->cck_txbbgain_table[11].ccktxbb_valuearray[2] = 0x18;
 959         priv->cck_txbbgain_table[11].ccktxbb_valuearray[3] = 0x14;
 960         priv->cck_txbbgain_table[11].ccktxbb_valuearray[4] = 0x0f;
 961         priv->cck_txbbgain_table[11].ccktxbb_valuearray[5] = 0x0a;
 962         priv->cck_txbbgain_table[11].ccktxbb_valuearray[6] = 0x05;
 963         priv->cck_txbbgain_table[11].ccktxbb_valuearray[7] = 0x02;
 964
 965         priv->cck_txbbgain_table[12].ccktxbb_valuearray[0] = 0x1b;
 966         priv->cck_txbbgain_table[12].ccktxbb_valuearray[1] = 0x1a;
 967         priv->cck_txbbgain_table[12].ccktxbb_valuearray[2] = 0x17;
 968         priv->cck_txbbgain_table[12].ccktxbb_valuearray[3] = 0x13;
 969         priv->cck_txbbgain_table[12].ccktxbb_valuearray[4] = 0x0e;
 970         priv->cck_txbbgain_table[12].ccktxbb_valuearray[5] = 0x09;
 971         priv->cck_txbbgain_table[12].ccktxbb_valuearray[6] = 0x04;
 972         priv->cck_txbbgain_table[12].ccktxbb_valuearray[7] = 0x02;
 973
 974         priv->cck_txbbgain_table[13].ccktxbb_valuearray[0] = 0x1a;
 975         priv->cck_txbbgain_table[13].ccktxbb_valuearray[1] = 0x19;
 976         priv->cck_txbbgain_table[13].ccktxbb_valuearray[2] = 0x16;
 977         priv->cck_txbbgain_table[13].ccktxbb_valuearray[3] = 0x12;
 978         priv->cck_txbbgain_table[13].ccktxbb_valuearray[4] = 0x0d;
 979         priv->cck_txbbgain_table[13].ccktxbb_valuearray[5] = 0x09;
 980         priv->cck_txbbgain_table[13].ccktxbb_valuearray[6] = 0x04;
 981         priv->cck_txbbgain_table[13].ccktxbb_valuearray[7] = 0x02;
 982
 983         priv->cck_txbbgain_table[14].ccktxbb_valuearray[0] = 0x18;
 984         priv->cck_txbbgain_table[14].ccktxbb_valuearray[1] = 0x17;
 985         priv->cck_txbbgain_table[14].ccktxbb_valuearray[2] = 0x15;
 986         priv->cck_txbbgain_table[14].ccktxbb_valuearray[3] = 0x11;
 987         priv->cck_txbbgain_table[14].ccktxbb_valuearray[4] = 0x0c;
 988         priv->cck_txbbgain_table[14].ccktxbb_valuearray[5] = 0x08;
 989         priv->cck_txbbgain_table[14].ccktxbb_valuearray[6] = 0x04;
 990         priv->cck_txbbgain_table[14].ccktxbb_valuearray[7] = 0x02;
 991
 992         priv->cck_txbbgain_table[15].ccktxbb_valuearray[0] = 0x17;
 993         priv->cck_txbbgain_table[15].ccktxbb_valuearray[1] = 0x16;
 994         priv->cck_txbbgain_table[15].ccktxbb_valuearray[2] = 0x13;
 995         priv->cck_txbbgain_table[15].ccktxbb_valuearray[3] = 0x10;
 996         priv->cck_txbbgain_table[15].ccktxbb_valuearray[4] = 0x0c;
 997         priv->cck_txbbgain_table[15].ccktxbb_valuearray[5] = 0x08;
 998         priv->cck_txbbgain_table[15].ccktxbb_valuearray[6] = 0x04;
 999         priv->cck_txbbgain_table[15].ccktxbb_valuearray[7] = 0x02;
1000
1001         priv->cck_txbbgain_table[16].ccktxbb_valuearray[0] = 0x16;
1002         priv->cck_txbbgain_table[16].ccktxbb_valuearray[1] = 0x15;
1003         priv->cck_txbbgain_table[16].ccktxbb_valuearray[2] = 0x12;
1004         priv->cck_txbbgain_table[16].ccktxbb_valuearray[3] = 0x0f;
1005         priv->cck_txbbgain_table[16].ccktxbb_valuearray[4] = 0x0b;
1006         priv->cck_txbbgain_table[16].ccktxbb_valuearray[5] = 0x07;
1007         priv->cck_txbbgain_table[16].ccktxbb_valuearray[6] = 0x04;
1008         priv->cck_txbbgain_table[16].ccktxbb_valuearray[7] = 0x01;
1009
1010         priv->cck_txbbgain_table[17].ccktxbb_valuearray[0] = 0x14;
1011         priv->cck_txbbgain_table[17].ccktxbb_valuearray[1] = 0x14;
1012         priv->cck_txbbgain_table[17].ccktxbb_valuearray[2] = 0x11;
1013         priv->cck_txbbgain_table[17].ccktxbb_valuearray[3] = 0x0e;
1014         priv->cck_txbbgain_table[17].ccktxbb_valuearray[4] = 0x0b;
1015         priv->cck_txbbgain_table[17].ccktxbb_valuearray[5] = 0x07;
1016         priv->cck_txbbgain_table[17].ccktxbb_valuearray[6] = 0x03;
1017         priv->cck_txbbgain_table[17].ccktxbb_valuearray[7] = 0x02;
1018
1019         priv->cck_txbbgain_table[18].ccktxbb_valuearray[0] = 0x13;
1020         priv->cck_txbbgain_table[18].ccktxbb_valuearray[1] = 0x13;
1021         priv->cck_txbbgain_table[18].ccktxbb_valuearray[2] = 0x10;
1022         priv->cck_txbbgain_table[18].ccktxbb_valuearray[3] = 0x0d;
1023         priv->cck_txbbgain_table[18].ccktxbb_valuearray[4] = 0x0a;
1024         priv->cck_txbbgain_table[18].ccktxbb_valuearray[5] = 0x06;
1025         priv->cck_txbbgain_table[18].ccktxbb_valuearray[6] = 0x03;
1026         priv->cck_txbbgain_table[18].ccktxbb_valuearray[7] = 0x01;
1027
1028         priv->cck_txbbgain_table[19].ccktxbb_valuearray[0] = 0x12;
1029         priv->cck_txbbgain_table[19].ccktxbb_valuearray[1] = 0x12;
1030         priv->cck_txbbgain_table[19].ccktxbb_valuearray[2] = 0x0f;
1031         priv->cck_txbbgain_table[19].ccktxbb_valuearray[3] = 0x0c;
1032         priv->cck_txbbgain_table[19].ccktxbb_valuearray[4] = 0x09;
1033         priv->cck_txbbgain_table[19].ccktxbb_valuearray[5] = 0x06;
1034         priv->cck_txbbgain_table[19].ccktxbb_valuearray[6] = 0x03;
1035         priv->cck_txbbgain_table[19].ccktxbb_valuearray[7] = 0x01;
1036
1037         priv->cck_txbbgain_table[20].ccktxbb_valuearray[0] = 0x11;
1038         priv->cck_txbbgain_table[20].ccktxbb_valuearray[1] = 0x11;
1039         priv->cck_txbbgain_table[20].ccktxbb_valuearray[2] = 0x0f;
1040         priv->cck_txbbgain_table[20].ccktxbb_valuearray[3] = 0x0c;
1041         priv->cck_txbbgain_table[20].ccktxbb_valuearray[4] = 0x09;
1042         priv->cck_txbbgain_table[20].ccktxbb_valuearray[5] = 0x06;
1043         priv->cck_txbbgain_table[20].ccktxbb_valuearray[6] = 0x03;
1044         priv->cck_txbbgain_table[20].ccktxbb_valuearray[7] = 0x01;
1045
1046         priv->cck_txbbgain_table[21].ccktxbb_valuearray[0] = 0x10;
1047         priv->cck_txbbgain_table[21].ccktxbb_valuearray[1] = 0x10;
1048         priv->cck_txbbgain_table[21].ccktxbb_valuearray[2] = 0x0e;
1049         priv->cck_txbbgain_table[21].ccktxbb_valuearray[3] = 0x0b;
1050         priv->cck_txbbgain_table[21].ccktxbb_valuearray[4] = 0x08;
1051         priv->cck_txbbgain_table[21].ccktxbb_valuearray[5] = 0x05;
1052         priv->cck_txbbgain_table[21].ccktxbb_valuearray[6] = 0x03;
1053         priv->cck_txbbgain_table[21].ccktxbb_valuearray[7] = 0x01;
1054
1055         priv->cck_txbbgain_table[22].ccktxbb_valuearray[0] = 0x0f;
1056         priv->cck_txbbgain_table[22].ccktxbb_valuearray[1] = 0x0f;
1057         priv->cck_txbbgain_table[22].ccktxbb_valuearray[2] = 0x0d;
1058         priv->cck_txbbgain_table[22].ccktxbb_valuearray[3] = 0x0b;
1059         priv->cck_txbbgain_table[22].ccktxbb_valuearray[4] = 0x08;
1060         priv->cck_txbbgain_table[22].ccktxbb_valuearray[5] = 0x05;
1061         priv->cck_txbbgain_table[22].ccktxbb_valuearray[6] = 0x03;
1062         priv->cck_txbbgain_table[22].ccktxbb_valuearray[7] = 0x01;
1063
1064         /*
1065          * ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
1066          * This Table is for CH14
1067          */
1068         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[0] = 0x36;
1069         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[1] = 0x35;
1070         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[2] = 0x2e;
1071         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[3] = 0x1b;
1072         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[4] = 0x00;
1073         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[5] = 0x00;
1074         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[6] = 0x00;
1075         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[7] = 0x00;
1076
1077         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[0] = 0x33;
1078         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[1] = 0x32;
1079         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[2] = 0x2b;
1080         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[3] = 0x19;
1081         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[4] = 0x00;
1082         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[5] = 0x00;
1083         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[6] = 0x00;
1084         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[7] = 0x00;
1085
1086         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[0] = 0x30;
1087         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[1] = 0x2f;
1088         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[2] = 0x29;
1089         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[3] = 0x18;
1090         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[4] = 0x00;
1091         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[5] = 0x00;
1092         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[6] = 0x00;
1093         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[7] = 0x00;
1094
1095         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[0] = 0x2d;
1096         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[1] = 0x2d;
1097         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[2] = 0x27;
1098         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[3] = 0x17;
1099         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[4] = 0x00;
1100         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[5] = 0x00;
1101         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[6] = 0x00;
1102         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[7] = 0x00;
1103
1104         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[0] = 0x2b;
1105         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[1] = 0x2a;
1106         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[2] = 0x25;
1107         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[3] = 0x15;
1108         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[4] = 0x00;
1109         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[5] = 0x00;
1110         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[6] = 0x00;
1111         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[7] = 0x00;
1112
1113         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[0] = 0x28;
1114         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[1] = 0x28;
1115         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[2] = 0x22;
1116         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[3] = 0x14;
1117         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[4] = 0x00;
1118         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[5] = 0x00;
1119         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[6] = 0x00;
1120         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[7] = 0x00;
1121
1122         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[0] = 0x26;
1123         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[1] = 0x25;
1124         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[2] = 0x21;
1125         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[3] = 0x13;
1126         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[4] = 0x00;
1127         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[5] = 0x00;
1128         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[6] = 0x00;
1129         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[7] = 0x00;
1130
1131         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[0] = 0x24;
1132         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[1] = 0x23;
1133         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[2] = 0x1f;
1134         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[3] = 0x12;
1135         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[4] = 0x00;
1136         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[5] = 0x00;
1137         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[6] = 0x00;
1138         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[7] = 0x00;
1139
1140         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[0] = 0x22;
1141         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[1] = 0x21;
1142         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[2] = 0x1d;
1143         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[3] = 0x11;
1144         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[4] = 0x00;
1145         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[5] = 0x00;
1146         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[6] = 0x00;
1147         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[7] = 0x00;
1148
1149         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[0] = 0x20;
1150         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[1] = 0x20;
1151         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[2] = 0x1b;
1152         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[3] = 0x10;
1153         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[4] = 0x00;
1154         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[5] = 0x00;
1155         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[6] = 0x00;
1156         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[7] = 0x00;
1157
1158         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[0] = 0x1f;
1159         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[1] = 0x1e;
1160         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[2] = 0x1a;
1161         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[3] = 0x0f;
1162         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[4] = 0x00;
1163         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[5] = 0x00;
1164         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[6] = 0x00;
1165         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[7] = 0x00;
1166
1167         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[0] = 0x1d;
1168         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[1] = 0x1c;
1169         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[2] = 0x18;
1170         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[3] = 0x0e;
1171         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[4] = 0x00;
1172         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[5] = 0x00;
1173         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[6] = 0x00;
1174         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[7] = 0x00;
1175
1176         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[0] = 0x1b;
1177         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[1] = 0x1a;
1178         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[2] = 0x17;
1179         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[3] = 0x0e;
1180         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[4] = 0x00;
1181         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[5] = 0x00;
1182         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[6] = 0x00;
1183         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[7] = 0x00;
1184
1185         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[0] = 0x1a;
1186         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[1] = 0x19;
1187         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[2] = 0x16;
1188         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[3] = 0x0d;
1189         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[4] = 0x00;
1190         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[5] = 0x00;
1191         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[6] = 0x00;
1192         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[7] = 0x00;
1193
1194         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[0] = 0x18;
1195         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[1] = 0x17;
1196         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[2] = 0x15;
1197         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[3] = 0x0c;
1198         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[4] = 0x00;
1199         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[5] = 0x00;
1200         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[6] = 0x00;
1201         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[7] = 0x00;
1202
1203         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[0] = 0x17;
1204         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[1] = 0x16;
1205         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[2] = 0x13;
1206         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[3] = 0x0b;
1207         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[4] = 0x00;
1208         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[5] = 0x00;
1209         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[6] = 0x00;
1210         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[7] = 0x00;
1211
1212         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[0] = 0x16;
1213         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[1] = 0x15;
1214         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[2] = 0x12;
1215         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[3] = 0x0b;
1216         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[4] = 0x00;
1217         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[5] = 0x00;
1218         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[6] = 0x00;
1219         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[7] = 0x00;
1220
1221         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[0] = 0x14;
1222         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[1] = 0x14;
1223         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[2] = 0x11;
1224         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[3] = 0x0a;
1225         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[4] = 0x00;
1226         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[5] = 0x00;
1227         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[6] = 0x00;
1228         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[7] = 0x00;
1229
1230         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[0] = 0x13;
1231         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[1] = 0x13;
1232         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[2] = 0x10;
1233         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[3] = 0x0a;
1234         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[4] = 0x00;
1235         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[5] = 0x00;
1236         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[6] = 0x00;
1237         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[7] = 0x00;
1238
1239         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[0] = 0x12;
1240         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[1] = 0x12;
1241         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[2] = 0x0f;
1242         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[3] = 0x09;
1243         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[4] = 0x00;
1244         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[5] = 0x00;
1245         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[6] = 0x00;
1246         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[7] = 0x00;
1247
1248         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[0] = 0x11;
1249         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[1] = 0x11;
1250         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[2] = 0x0f;
1251         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[3] = 0x09;
1252         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[4] = 0x00;
1253         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[5] = 0x00;
1254         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[6] = 0x00;
1255         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[7] = 0x00;
1256
1257         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[0] = 0x10;
1258         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[1] = 0x10;
1259         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[2] = 0x0e;
1260         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[3] = 0x08;
1261         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[4] = 0x00;
1262         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[5] = 0x00;
1263         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[6] = 0x00;
1264         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[7] = 0x00;
1265
1266         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[0] = 0x0f;
1267         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[1] = 0x0f;
1268         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[2] = 0x0d;
1269         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[3] = 0x08;
1270         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[4] = 0x00;
1271         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[5] = 0x00;
1272         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[6] = 0x00;
1273         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[7] = 0x00;
1274
1275         priv->btxpower_tracking = true;
1276         priv->txpower_count       = 0;
1277         priv->btxpower_trackingInit = false;
1278
1279 }
1280
1281 static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device *dev)
1282 {
1283         struct r8192_priv *priv = ieee80211_priv(dev);
1284
1285         /*
1286          * Tx Power tracking by Thermal Meter requires Firmware R/W 3-wire. This mechanism
1287          * can be enabled only when Firmware R/W 3-wire is enabled. Otherwise, frequent r/w
1288          * 3-wire by driver causes RF to go into a wrong state.
1289          */
1290         if (priv->ieee80211->FwRWRF)
1291                 priv->btxpower_tracking = true;
1292         else
1293                 priv->btxpower_tracking = false;
1294         priv->txpower_count       = 0;
1295         priv->btxpower_trackingInit = false;
1296 }
1297
1298 void dm_initialize_txpower_tracking(struct net_device *dev)
1299 {
1300         struct r8192_priv *priv = ieee80211_priv(dev);
1301
1302         if (priv->bDcut)
1303                 dm_InitializeTXPowerTracking_TSSI(dev);
1304         else
1305                 dm_InitializeTXPowerTracking_ThermalMeter(dev);
1306 } /* dm_InitializeTXPowerTracking */
1307
1308 static void dm_CheckTXPowerTracking_TSSI(struct net_device *dev)
1309 {
1310         struct r8192_priv *priv = ieee80211_priv(dev);
1311         static u32 tx_power_track_counter;
1312
1313         if (!priv->btxpower_tracking)
1314                 return;
1315         if ((tx_power_track_counter % 30 == 0) && (tx_power_track_counter != 0))
1316                 queue_delayed_work(priv->priv_wq, &priv->txpower_tracking_wq, 0);
1317         tx_power_track_counter++;
1318 }
1319
1320 static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev)
1321 {
1322         struct r8192_priv *priv = ieee80211_priv(dev);
1323         static u8       TM_Trigger;
1324         /*DbgPrint("dm_CheckTXPowerTracking()\n");*/
1325         if (!priv->btxpower_tracking)
1326                 return;
1327         if (priv->txpower_count  <= 2) {
1328                 priv->txpower_count++;
1329                 return;
1330         }
1331
1332         if (!TM_Trigger) {
1333                 /*
1334                  * Attention!! You have to write all 12bits of data to RF, or it may cause RF to crash
1335                  * actually write reg0x02 bit1=0, then bit1=1.
1336                  * DbgPrint("Trigger ThermalMeter, write RF reg0x2 = 0x4d to 0x4f\n");
1337                  */
1338                 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1339                 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1340                 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1341                 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1342                 TM_Trigger = 1;
1343                 return;
1344         }
1345         /*DbgPrint("Schedule TxPowerTrackingWorkItem\n");*/
1346                 queue_delayed_work(priv->priv_wq, &priv->txpower_tracking_wq, 0);
1347         TM_Trigger = 0;
1348 }
1349
1350 static void dm_check_txpower_tracking(struct net_device *dev)
1351 {
1352         struct r8192_priv *priv = ieee80211_priv(dev);
1353         /*static u32 tx_power_track_counter = 0;*/
1354
1355 #ifdef RTL8190P
1356         dm_CheckTXPowerTracking_TSSI(dev);
1357 #else
1358         if (priv->bDcut)
1359                 dm_CheckTXPowerTracking_TSSI(dev);
1360         else
1361                 dm_CheckTXPowerTracking_ThermalMeter(dev);
1362 #endif
1363
1364 }       /* dm_CheckTXPowerTracking */
1365
1366 static void dm_CCKTxPowerAdjust_TSSI(struct net_device *dev, bool  bInCH14)
1367 {
1368         u32 TempVal;
1369         struct r8192_priv *priv = ieee80211_priv(dev);
1370
1371         /* Write 0xa22 0xa23 */
1372         TempVal = 0;
1373         if (!bInCH14) {
1374                 /* Write 0xa22 0xa23 */
1375                 TempVal =       priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[0] +
1376                                         (priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[1]<<8);
1377
1378                 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1379                 /* Write 0xa24 ~ 0xa27 */
1380                 TempVal =       priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[2] +
1381                                         (priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[3]<<8) +
1382                                         (priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[4]<<16)+
1383                                         (priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[5]<<24);
1384                 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1385                 /* Write 0xa28  0xa29 */
1386                 TempVal =       priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[6] +
1387                                         (priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[7]<<8);
1388
1389                 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1390         } else {
1391                 TempVal =       priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[0] +
1392                                         (priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[1]<<8);
1393
1394                 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1395                 /* Write 0xa24 ~ 0xa27 */
1396                 TempVal =       priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[2] +
1397                                         (priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[3]<<8) +
1398                                         (priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[4]<<16)+
1399                                         (priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[5]<<24);
1400                 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1401                 /* Write 0xa28  0xa29 */
1402                 TempVal =       priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[6] +
1403                                         (priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[7]<<8);
1404
1405                 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1406         }
1407 }
1408
1409 static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool  bInCH14)
1410 {
1411         u32 TempVal;
1412         struct r8192_priv *priv = ieee80211_priv(dev);
1413
1414         TempVal = 0;
1415         if (!bInCH14) {
1416                 /* Write 0xa22 0xa23 */
1417                 TempVal =       CCKSwingTable_Ch1_Ch13[priv->CCK_index][0] +
1418                                         (CCKSwingTable_Ch1_Ch13[priv->CCK_index][1]<<8);
1419                 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1420                 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1421                         rCCK0_TxFilter1, TempVal);
1422                 /* Write 0xa24 ~ 0xa27 */
1423                 TempVal =       CCKSwingTable_Ch1_Ch13[priv->CCK_index][2] +
1424                                         (CCKSwingTable_Ch1_Ch13[priv->CCK_index][3]<<8) +
1425                                         (CCKSwingTable_Ch1_Ch13[priv->CCK_index][4]<<16)+
1426                                         (CCKSwingTable_Ch1_Ch13[priv->CCK_index][5]<<24);
1427                 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1428                 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1429                         rCCK0_TxFilter2, TempVal);
1430                 /* Write 0xa28  0xa29 */
1431                 TempVal =       CCKSwingTable_Ch1_Ch13[priv->CCK_index][6] +
1432                                         (CCKSwingTable_Ch1_Ch13[priv->CCK_index][7]<<8);
1433
1434                 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1435                 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1436                         rCCK0_DebugPort, TempVal);
1437         } else {
1438                 /*priv->CCKTxPowerAdjustCntNotCh14++;   cosa add for debug.*/
1439                 /* Write 0xa22 0xa23 */
1440                 TempVal =       CCKSwingTable_Ch14[priv->CCK_index][0] +
1441                                         (CCKSwingTable_Ch14[priv->CCK_index][1]<<8);
1442
1443                 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1444                 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1445                          rCCK0_TxFilter1, TempVal);
1446                 /* Write 0xa24 ~ 0xa27 */
1447                 TempVal =       CCKSwingTable_Ch14[priv->CCK_index][2] +
1448                                         (CCKSwingTable_Ch14[priv->CCK_index][3]<<8) +
1449                                         (CCKSwingTable_Ch14[priv->CCK_index][4]<<16)+
1450                                         (CCKSwingTable_Ch14[priv->CCK_index][5]<<24);
1451                 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1452                 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1453                          rCCK0_TxFilter2, TempVal);
1454                 /* Write 0xa28  0xa29 */
1455                 TempVal =       CCKSwingTable_Ch14[priv->CCK_index][6] +
1456                                         (CCKSwingTable_Ch14[priv->CCK_index][7]<<8);
1457
1458                 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1459                 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1460                          rCCK0_DebugPort, TempVal);
1461         }
1462 }
1463
1464 void dm_cck_txpower_adjust(struct net_device *dev, bool binch14)
1465 {       /*  dm_CCKTxPowerAdjust */
1466         struct r8192_priv *priv = ieee80211_priv(dev);
1467
1468         if (priv->bDcut)
1469                 dm_CCKTxPowerAdjust_TSSI(dev, binch14);
1470         else
1471                 dm_CCKTxPowerAdjust_ThermalMeter(dev, binch14);
1472 }
1473
1474 #ifndef RTL8192U
1475 static void dm_txpower_reset_recovery(
1476         struct net_device *dev
1477 )
1478 {
1479         struct r8192_priv *priv = ieee80211_priv(dev);
1480
1481         RT_TRACE(COMP_POWER_TRACKING, "Start Reset Recovery ==>\n");
1482         rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1483         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc80 is %08x\n", priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1484         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFA_txPowerTrackingIndex is %x\n", priv->rfa_txpowertrackingindex);
1485         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF A I/Q Amplify Gain is %ld\n", priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbb_iq_amplifygain);
1486         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: CCK Attenuation is %d dB\n", priv->cck_present_attenuation);
1487         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1488
1489         rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
1490         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc90 is %08x\n", priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
1491         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFC_txPowerTrackingIndex is %x\n", priv->rfc_txpowertrackingindex);
1492         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF C I/Q Amplify Gain is %ld\n", priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbb_iq_amplifygain);
1493
1494 }       /* dm_TXPowerResetRecovery */
1495
1496 void dm_restore_dynamic_mechanism_state(struct net_device *dev)
1497 {
1498         struct r8192_priv *priv = ieee80211_priv(dev);
1499         u32     reg_ratr = priv->rate_adaptive.last_ratr;
1500
1501         if (!priv->up) {
1502                 RT_TRACE(COMP_RATE, "<---- dm_restore_dynamic_mechanism_state(): driver is going to unload\n");
1503                 return;
1504         }
1505
1506         /* Restore previous state for rate adaptive */
1507         if (priv->rate_adaptive.rate_adaptive_disabled)
1508                 return;
1509         /* TODO: Only 11n mode is implemented currently, */
1510         if (!(priv->ieee80211->mode == WIRELESS_MODE_N_24G ||
1511               priv->ieee80211->mode == WIRELESS_MODE_N_5G))
1512                 return;
1513
1514         {
1515                         /* 2007/11/15 MH Copy from 8190PCI. */
1516                         u32 ratr_value;
1517
1518                         ratr_value = reg_ratr;
1519                         if (priv->rf_type == RF_1T2R) { /* 1T2R, Spatial Stream 2 should be disabled */
1520                                 ratr_value &= ~(RATE_ALL_OFDM_2SS);
1521                                 /*DbgPrint("HW_VAR_TATR_0 from 0x%x ==> 0x%x\n", ((pu4Byte)(val))[0], ratr_value);*/
1522                         }
1523                         /*DbgPrint("set HW_VAR_TATR_0 = 0x%x\n", ratr_value);*/
1524                         /*cosa PlatformEFIOWrite4Byte(Adapter, RATR0, ((pu4Byte)(val))[0]);*/
1525                         write_nic_dword(dev, RATR0, ratr_value);
1526                         write_nic_byte(dev, UFWP, 1);
1527         }
1528         /* Restore TX Power Tracking Index */
1529         if (priv->btxpower_trackingInit && priv->btxpower_tracking)
1530                 dm_txpower_reset_recovery(dev);
1531
1532         /* Restore BB Initial Gain */
1533         dm_bb_initialgain_restore(dev);
1534
1535 }       /* DM_RestoreDynamicMechanismState */
1536
1537 static void dm_bb_initialgain_restore(struct net_device *dev)
1538 {
1539         struct r8192_priv *priv = ieee80211_priv(dev);
1540         u32 bit_mask = 0x7f; /* Bit0~ Bit6 */
1541
1542         if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1543                 return;
1544
1545         /* Disable Initial Gain */
1546         /*PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);*/
1547         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   /* Only clear byte 1 and rewrite. */
1548         rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1);
1549         rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1);
1550         rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bit_mask, (u32)priv->initgain_backup.xcagccore1);
1551         rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1);
1552         bit_mask  = bMaskByte2;
1553         rtl8192_setBBreg(dev, rCCK0_CCA, bit_mask, (u32)priv->initgain_backup.cca);
1554
1555         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc50 is %x\n", priv->initgain_backup.xaagccore1);
1556         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc58 is %x\n", priv->initgain_backup.xbagccore1);
1557         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc60 is %x\n", priv->initgain_backup.xcagccore1);
1558         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc68 is %x\n", priv->initgain_backup.xdagccore1);
1559         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x\n", priv->initgain_backup.cca);
1560         /* Enable Initial Gain */
1561         /*PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x100);*/
1562         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);   /* Only clear byte 1 and rewrite. */
1563
1564 }       /* dm_BBInitialGainRestore */
1565
1566 void dm_backup_dynamic_mechanism_state(struct net_device *dev)
1567 {
1568         struct r8192_priv *priv = ieee80211_priv(dev);
1569
1570         /* Fsync to avoid reset */
1571         priv->bswitch_fsync  = false;
1572         priv->bfsync_processing = false;
1573         /* Backup BB InitialGain */
1574         dm_bb_initialgain_backup(dev);
1575
1576 }       /* DM_BackupDynamicMechanismState */
1577
1578 static void dm_bb_initialgain_backup(struct net_device *dev)
1579 {
1580         struct r8192_priv *priv = ieee80211_priv(dev);
1581         u32 bit_mask = bMaskByte0; /* Bit0~ Bit6 */
1582
1583         if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1584                 return;
1585
1586         /*PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);*/
1587         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   /* Only clear byte 1 and rewrite. */
1588         priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask);
1589         priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask);
1590         priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bit_mask);
1591         priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bit_mask);
1592         bit_mask  = bMaskByte2;
1593         priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bit_mask);
1594
1595         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc50 is %x\n", priv->initgain_backup.xaagccore1);
1596         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc58 is %x\n", priv->initgain_backup.xbagccore1);
1597         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc60 is %x\n", priv->initgain_backup.xcagccore1);
1598         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc68 is %x\n", priv->initgain_backup.xdagccore1);
1599         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xa0a is %x\n", priv->initgain_backup.cca);
1600
1601 }   /* dm_BBInitialGainBakcup */
1602
1603 #endif
1604 /*-----------------------------------------------------------------------------
1605  * Function:    dm_dig_init()
1606  *
1607  * Overview:    Set DIG scheme init value.
1608  *
1609  * Input:               NONE
1610  *
1611  * Output:              NONE
1612  *
1613  * Return:              NONE
1614  *
1615  * Revised History:
1616  *      When            Who             Remark
1617  *      05/15/2008      amy             Create Version 0 porting from windows code.
1618  *
1619  *---------------------------------------------------------------------------*/
1620 static void dm_dig_init(struct net_device *dev)
1621 {
1622         struct r8192_priv *priv = ieee80211_priv(dev);
1623         /* 2007/10/05 MH Disable DIG scheme now. Not tested. */
1624         dm_digtable.dig_enable_flag     = true;
1625         dm_digtable.dig_algorithm = DIG_ALGO_BY_RSSI;
1626         dm_digtable.dig_algorithm_switch = 0;
1627
1628         /* 2007/10/04 MH Define init gain threshold. */
1629         dm_digtable.dig_state           = DM_STA_DIG_MAX;
1630         dm_digtable.dig_highpwr_state   = DM_STA_DIG_MAX;
1631
1632         dm_digtable.rssi_low_thresh     = DM_DIG_THRESH_LOW;
1633         dm_digtable.rssi_high_thresh    = DM_DIG_THRESH_HIGH;
1634
1635         dm_digtable.rssi_high_power_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW;
1636         dm_digtable.rssi_high_power_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH;
1637
1638         dm_digtable.rssi_val = 50;      /* for new dig debug rssi value */
1639         dm_digtable.backoff_val = DM_DIG_BACKOFF;
1640         if (priv->CustomerID == RT_CID_819x_Netcore)
1641                 dm_digtable.rx_gain_range_min = DM_DIG_MIN_NETCORE;
1642         else
1643                 dm_digtable.rx_gain_range_min = DM_DIG_MIN;
1644
1645 }       /* dm_dig_init */
1646
1647 /*-----------------------------------------------------------------------------
1648  * Function:    dm_ctrl_initgain_byrssi()
1649  *
1650  * Overview:    Driver must monitor RSSI and notify firmware to change initial
1651  *                              gain according to different threshold. BB team provide the
1652  *                              suggested solution.
1653  *
1654  * Input:                       struct net_device *dev
1655  *
1656  * Output:              NONE
1657  *
1658  * Return:              NONE
1659  *
1660  * Revised History:
1661  *      When            Who             Remark
1662  *      05/27/2008      amy             Create Version 0 porting from windows code.
1663  *---------------------------------------------------------------------------*/
1664 static void dm_ctrl_initgain_byrssi(struct net_device *dev)
1665 {
1666         if (!dm_digtable.dig_enable_flag)
1667                 return;
1668
1669         if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1670                 dm_ctrl_initgain_byrssi_by_fwfalse_alarm(dev);
1671         else if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1672                 dm_ctrl_initgain_byrssi_by_driverrssi(dev);
1673         /* ; */
1674         else
1675                 return;
1676 }
1677
1678 static void dm_ctrl_initgain_byrssi_by_driverrssi(
1679         struct net_device *dev)
1680 {
1681         struct r8192_priv *priv = ieee80211_priv(dev);
1682         u8 i;
1683         static u8       fw_dig;
1684
1685         if (!dm_digtable.dig_enable_flag)
1686                 return;
1687
1688         /*DbgPrint("Dig by Sw Rssi\n");*/
1689         if (dm_digtable.dig_algorithm_switch)   /* if switched algorithm, we have to disable FW Dig. */
1690                 fw_dig = 0;
1691
1692         if (fw_dig <= 3) { /* execute several times to make sure the FW Dig is disabled */
1693                 /* FW DIG Off */
1694                 for (i = 0; i < 3; i++)
1695                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   /* Only clear byte 1 and rewrite. */
1696                 fw_dig++;
1697                 dm_digtable.dig_state = DM_STA_DIG_OFF; /* fw dig off. */
1698         }
1699
1700         if (priv->ieee80211->state == IEEE80211_LINKED)
1701                 dm_digtable.cur_connect_state = DIG_CONNECT;
1702         else
1703                 dm_digtable.cur_connect_state = DIG_DISCONNECT;
1704
1705         /*DbgPrint("DM_DigTable.PreConnectState = %d, DM_DigTable.CurConnectState = %d\n",
1706                 DM_DigTable.PreConnectState, DM_DigTable.CurConnectState);*/
1707
1708         dm_digtable.rssi_val = priv->undecorated_smoothed_pwdb;
1709         /*DbgPrint("DM_DigTable.Rssi_val = %d\n", DM_DigTable.Rssi_val);*/
1710         dm_initial_gain(dev);
1711         dm_pd_th(dev);
1712         dm_cs_ratio(dev);
1713         if (dm_digtable.dig_algorithm_switch)
1714                 dm_digtable.dig_algorithm_switch = 0;
1715         dm_digtable.pre_connect_state = dm_digtable.cur_connect_state;
1716
1717 }       /* dm_CtrlInitGainByRssi */
1718
1719 static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
1720         struct net_device *dev)
1721 {
1722         struct r8192_priv *priv = ieee80211_priv(dev);
1723         static u32 reset_cnt;
1724         u8 i;
1725
1726         if (!dm_digtable.dig_enable_flag)
1727                 return;
1728
1729         if (dm_digtable.dig_algorithm_switch) {
1730                 dm_digtable.dig_state = DM_STA_DIG_MAX;
1731                 /* Fw DIG On. */
1732                 for (i = 0; i < 3; i++)
1733                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);   /* Only clear byte 1 and rewrite.*/
1734                 dm_digtable.dig_algorithm_switch = 0;
1735         }
1736
1737         if (priv->ieee80211->state != IEEE80211_LINKED)
1738                 return;
1739
1740         /* For smooth, we can not change DIG state. */
1741         if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_low_thresh) &&
1742             (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_thresh))
1743                 return;
1744
1745         /*DbgPrint("Dig by Fw False Alarm\n");*/
1746         /*if (DM_DigTable.Dig_State == DM_STA_DIG_OFF)*/
1747         /*DbgPrint("DIG Check\n\r RSSI=%d LOW=%d HIGH=%d STATE=%d",
1748         pHalData->UndecoratedSmoothedPWDB, DM_DigTable.RssiLowThresh,
1749         DM_DigTable.RssiHighThresh, DM_DigTable.Dig_State);*/
1750         /* 1. When RSSI decrease, We have to judge if it is smaller than a threshold
1751                   and then execute the step below. */
1752         if (priv->undecorated_smoothed_pwdb <= dm_digtable.rssi_low_thresh) {
1753                 /* 2008/02/05 MH When we execute silent reset, the DIG PHY parameters
1754                    will be reset to init value. We must prevent the condition. */
1755                 if (dm_digtable.dig_state == DM_STA_DIG_OFF &&
1756                     (priv->reset_count == reset_cnt)) {
1757                         return;
1758                 }
1759                 reset_cnt = priv->reset_count;
1760
1761                 /* If DIG is off, DIG high power state must reset. */
1762                 dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX;
1763                 dm_digtable.dig_state = DM_STA_DIG_OFF;
1764
1765                 /*  1.1 DIG Off. */
1766                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   /*  Only clear byte 1 and rewrite. */
1767
1768                 /*  1.2 Set initial gain. */
1769                 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17);
1770                 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17);
1771                 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x17);
1772                 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x17);
1773
1774                 /*  1.3 Lower PD_TH for OFDM. */
1775                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
1776                         /*
1777                          * 2008/01/11 MH 40MHZ 90/92 register are not the same.
1778                          * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1779                          */
1780                         write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
1781                         /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1782                                 write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40);
1783                         else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
1784                         else
1785                                 PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40);
1786                         */
1787                 } else
1788                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1789
1790                 /* 1.4 Lower CS ratio for CCK. */
1791                 write_nic_byte(dev, 0xa0a, 0x08);
1792
1793                 /* 1.5 Higher EDCCA. */
1794                 /*PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x325);*/
1795                 return;
1796
1797         }
1798
1799         /* 2. When RSSI increase, We have to judge if it is larger than a threshold
1800                   and then execute the step below.  */
1801         if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) {
1802                 u8 reset_flag = 0;
1803
1804                 if (dm_digtable.dig_state == DM_STA_DIG_ON &&
1805                     (priv->reset_count == reset_cnt)) {
1806                         dm_ctrl_initgain_byrssi_highpwr(dev);
1807                         return;
1808                 }
1809                 if (priv->reset_count != reset_cnt)
1810                         reset_flag = 1;
1811
1812                 reset_cnt = priv->reset_count;
1813
1814                 dm_digtable.dig_state = DM_STA_DIG_ON;
1815                 /*DbgPrint("DIG ON\n\r");*/
1816
1817                 /*
1818                  * 2.1 Set initial gain.
1819                  * 2008/02/26 MH SD3-Jerry suggest to prevent dirty environment.
1820                  */
1821                 if (reset_flag == 1) {
1822                         write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c);
1823                         write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c);
1824                         write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x2c);
1825                         write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x2c);
1826                 } else {
1827                         write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20);
1828                         write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20);
1829                         write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x20);
1830                         write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x20);
1831                 }
1832
1833                 /* 2.2 Higher PD_TH for OFDM. */
1834                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
1835                         /*
1836                          * 2008/01/11 MH 40MHZ 90/92 register are not the same.
1837                          * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1838                          */
1839                         write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
1840                         /*
1841                         else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1842                                 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1843                         else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
1844                         else
1845                                 PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42);
1846                         */
1847                 } else
1848                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
1849
1850                 /* 2.3 Higher CS ratio for CCK. */
1851                 write_nic_byte(dev, 0xa0a, 0xcd);
1852
1853                 /*
1854                  * 2.4 Lower EDCCA.
1855                  * 2008/01/11 MH 90/92 series are the same.
1856                  */
1857                 /*PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x346);*/
1858
1859                 /* 2.5 DIG On. */
1860                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);   /*  Only clear byte 1 and rewrite. */
1861
1862         }
1863
1864         dm_ctrl_initgain_byrssi_highpwr(dev);
1865
1866 }       /* dm_CtrlInitGainByRssi */
1867
1868 /*-----------------------------------------------------------------------------
1869  * Function:    dm_ctrl_initgain_byrssi_highpwr()
1870  *
1871  * Overview:
1872  *
1873  * Input:               NONE
1874  *
1875  * Output:              NONE
1876  *
1877  * Return:              NONE
1878  *
1879  * Revised History:
1880  *      When            Who             Remark
1881  *      05/28/2008      amy             Create Version 0 porting from windows code.
1882  *
1883  *---------------------------------------------------------------------------*/
1884 static void dm_ctrl_initgain_byrssi_highpwr(
1885         struct net_device *dev)
1886 {
1887         struct r8192_priv *priv = ieee80211_priv(dev);
1888         static u32 reset_cnt_highpwr;
1889
1890         /*  For smooth, we can not change high power DIG state in the range. */
1891         if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_high_power_lowthresh) &&
1892                 (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_highthresh))
1893                 return;
1894
1895         /*
1896          * 3. When RSSI >75% or <70%, it is a high power issue. We have to judge if
1897          *    it is larger than a threshold and then execute the step below.
1898          *
1899          * 2008/02/05 MH SD3-Jerry Modify PD_TH for high power issue.
1900          */
1901         if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_power_highthresh) {
1902                 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_ON &&
1903                     (priv->reset_count == reset_cnt_highpwr))
1904                         return;
1905                 dm_digtable.dig_highpwr_state = DM_STA_DIG_ON;
1906
1907                 /* 3.1 Higher PD_TH for OFDM for high power state. */
1908                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
1909                         write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
1910
1911                         /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1912                                 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
1913                         */
1914
1915                 } else
1916                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
1917         } else {
1918                 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_OFF &&
1919                     (priv->reset_count == reset_cnt_highpwr))
1920                         return;
1921                 dm_digtable.dig_highpwr_state = DM_STA_DIG_OFF;
1922
1923                 if (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_lowthresh &&
1924                          priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) {
1925                         /*  3.2 Recover PD_TH for OFDM for normal power region. */
1926                         if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
1927                                 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
1928                                 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1929                                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1930                                 */
1931
1932                         } else
1933                                 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
1934                 }
1935         }
1936
1937         reset_cnt_highpwr = priv->reset_count;
1938
1939 }       /* dm_CtrlInitGainByRssiHighPwr */
1940
1941 static void dm_initial_gain(
1942         struct net_device *dev)
1943 {
1944         struct r8192_priv *priv = ieee80211_priv(dev);
1945         u8                                      initial_gain = 0;
1946         static u8                               initialized, force_write;
1947         static u32                      reset_cnt;
1948         u8                              tmp;
1949
1950         if (dm_digtable.dig_algorithm_switch) {
1951                 initialized = 0;
1952                 reset_cnt = 0;
1953         }
1954
1955         if (dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) {
1956                 if (dm_digtable.cur_connect_state == DIG_CONNECT) {
1957                         if ((dm_digtable.rssi_val + 10 - dm_digtable.backoff_val) > DM_DIG_MAX)
1958                                 dm_digtable.cur_ig_value = DM_DIG_MAX;
1959                         else if ((dm_digtable.rssi_val+10-dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min)
1960                                 dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_min;
1961                         else
1962                                 dm_digtable.cur_ig_value = dm_digtable.rssi_val+10-dm_digtable.backoff_val;
1963                 } else {        /* current state is disconnected */
1964                         if (dm_digtable.cur_ig_value == 0)
1965                                 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
1966                         else
1967                                 dm_digtable.cur_ig_value = dm_digtable.pre_ig_value;
1968                 }
1969         } else { /*  disconnected -> connected or connected -> disconnected */
1970                 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
1971                 dm_digtable.pre_ig_value = 0;
1972         }
1973         /*DbgPrint("DM_DigTable.CurIGValue = 0x%x, DM_DigTable.PreIGValue = 0x%x\n", DM_DigTable.CurIGValue, DM_DigTable.PreIGValue);*/
1974
1975         /* if silent reset happened, we should rewrite the values back */
1976         if (priv->reset_count != reset_cnt) {
1977                 force_write = 1;
1978                 reset_cnt = priv->reset_count;
1979         }
1980
1981         read_nic_byte(dev, rOFDM0_XAAGCCore1, &tmp);
1982         if (dm_digtable.pre_ig_value != tmp)
1983                 force_write = 1;
1984
1985         {
1986                 if ((dm_digtable.pre_ig_value != dm_digtable.cur_ig_value)
1987                         || !initialized || force_write) {
1988                         initial_gain = (u8)dm_digtable.cur_ig_value;
1989                         /*DbgPrint("Write initial gain = 0x%x\n", initial_gain);*/
1990                         /*  Set initial gain. */
1991                         write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1992                         write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1993                         write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1994                         write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1995                         dm_digtable.pre_ig_value = dm_digtable.cur_ig_value;
1996                         initialized = 1;
1997                         force_write = 0;
1998                 }
1999         }
2000 }
2001
2002 static void dm_pd_th(
2003         struct net_device *dev)
2004 {
2005         struct r8192_priv *priv = ieee80211_priv(dev);
2006         static u8                               initialized, force_write;
2007         static u32                      reset_cnt;
2008
2009         if (dm_digtable.dig_algorithm_switch) {
2010                 initialized = 0;
2011                 reset_cnt = 0;
2012         }
2013
2014         if (dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) {
2015                 if (dm_digtable.cur_connect_state == DIG_CONNECT) {
2016                         if (dm_digtable.rssi_val >= dm_digtable.rssi_high_power_highthresh)
2017                                 dm_digtable.curpd_thstate = DIG_PD_AT_HIGH_POWER;
2018                         else if (dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh)
2019                                 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2020                         else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) &&
2021                                         (dm_digtable.rssi_val < dm_digtable.rssi_high_power_lowthresh))
2022                                 dm_digtable.curpd_thstate = DIG_PD_AT_NORMAL_POWER;
2023                         else
2024                                 dm_digtable.curpd_thstate = dm_digtable.prepd_thstate;
2025                 } else {
2026                         dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2027                 }
2028         } else { /* disconnected -> connected or connected -> disconnected */
2029                 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2030         }
2031
2032         /*  if silent reset happened, we should rewrite the values back */
2033         if (priv->reset_count != reset_cnt) {
2034                 force_write = 1;
2035                 reset_cnt = priv->reset_count;
2036         }
2037
2038         {
2039                 if ((dm_digtable.prepd_thstate != dm_digtable.curpd_thstate) ||
2040                     (initialized <= 3) || force_write) {
2041                         /*DbgPrint("Write PD_TH state = %d\n", DM_DigTable.CurPD_THState);*/
2042                         if (dm_digtable.curpd_thstate == DIG_PD_AT_LOW_POWER) {
2043                                 /*  Lower PD_TH for OFDM. */
2044                                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
2045                                         /*
2046                                          * 2008/01/11 MH 40MHZ 90/92 register are not the same.
2047                                          * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2048                                          */
2049                                         write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
2050                                         /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2051                                                 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
2052                                         */
2053                                 } else
2054                                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2055                         } else if (dm_digtable.curpd_thstate == DIG_PD_AT_NORMAL_POWER) {
2056                                 /* Higher PD_TH for OFDM. */
2057                                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
2058                                         /*
2059                                          * 2008/01/11 MH 40MHZ 90/92 register are not the same.
2060                                          * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2061                                          */
2062                                         write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
2063                                         /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2064                                                 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2065                                         */
2066                                 } else
2067                                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
2068                         } else if (dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER) {
2069                                 /* Higher PD_TH for OFDM for high power state. */
2070                                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
2071                                         write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
2072                                         /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2073                                                 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2074                                         */
2075                                 } else
2076                                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
2077                         }
2078                         dm_digtable.prepd_thstate = dm_digtable.curpd_thstate;
2079                         if (initialized <= 3)
2080                                 initialized++;
2081                         force_write = 0;
2082                 }
2083         }
2084 }
2085
2086 static  void dm_cs_ratio(
2087         struct net_device *dev)
2088 {
2089         struct r8192_priv *priv = ieee80211_priv(dev);
2090         static u8                               initialized, force_write;
2091         static u32                      reset_cnt;
2092
2093         if (dm_digtable.dig_algorithm_switch) {
2094                 initialized = 0;
2095                 reset_cnt = 0;
2096         }
2097
2098         if (dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) {
2099                 if (dm_digtable.cur_connect_state == DIG_CONNECT) {
2100                         if (dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh)
2101                                 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2102                         else if (dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh)
2103                                 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_HIGHER;
2104                         else
2105                                 dm_digtable.curcs_ratio_state = dm_digtable.precs_ratio_state;
2106                 } else {
2107                         dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2108                 }
2109         } else  /* disconnected -> connected or connected -> disconnected */
2110                 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2111
2112         /* if silent reset happened, we should rewrite the values back */
2113         if (priv->reset_count != reset_cnt) {
2114                 force_write = 1;
2115                 reset_cnt = priv->reset_count;
2116         }
2117
2118         {
2119                 if ((dm_digtable.precs_ratio_state != dm_digtable.curcs_ratio_state) ||
2120                     !initialized || force_write) {
2121                         /*DbgPrint("Write CS_ratio state = %d\n", DM_DigTable.CurCS_ratioState);*/
2122                         if (dm_digtable.curcs_ratio_state == DIG_CS_RATIO_LOWER) {
2123                                 /*  Lower CS ratio for CCK. */
2124                                 write_nic_byte(dev, 0xa0a, 0x08);
2125                         } else if (dm_digtable.curcs_ratio_state == DIG_CS_RATIO_HIGHER) {
2126                                 /*  Higher CS ratio for CCK. */
2127                                 write_nic_byte(dev, 0xa0a, 0xcd);
2128                         }
2129                         dm_digtable.precs_ratio_state = dm_digtable.curcs_ratio_state;
2130                         initialized = 1;
2131                         force_write = 0;
2132                 }
2133         }
2134 }
2135
2136 void dm_init_edca_turbo(struct net_device *dev)
2137 {
2138         struct r8192_priv *priv = ieee80211_priv(dev);
2139
2140         priv->bcurrent_turbo_EDCA = false;
2141         priv->ieee80211->bis_any_nonbepkts = false;
2142         priv->bis_cur_rdlstate = false;
2143 }       /* dm_init_edca_turbo */
2144
2145 static void dm_check_edca_turbo(
2146         struct net_device *dev)
2147 {
2148         struct r8192_priv *priv = ieee80211_priv(dev);
2149         PRT_HIGH_THROUGHPUT     pHTInfo = priv->ieee80211->pHTInfo;
2150         /*PSTA_QOS                      pStaQos = pMgntInfo->pStaQos;*/
2151
2152         /* Keep past Tx/Rx packet count for RT-to-RT EDCA turbo. */
2153         static unsigned long                    lastTxOkCnt;
2154         static unsigned long                    lastRxOkCnt;
2155         unsigned long                           curTxOkCnt = 0;
2156         unsigned long                           curRxOkCnt = 0;
2157
2158         /*
2159          * Do not be Turbo if it's under WiFi config and Qos Enabled, because the EDCA parameters
2160          * should follow the settings from QAP. By Bruce, 2007-12-07.
2161          */
2162         if (priv->ieee80211->state != IEEE80211_LINKED)
2163                 goto dm_CheckEdcaTurbo_EXIT;
2164         /* We do not turn on EDCA turbo mode for some AP that has IOT issue */
2165         if (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO)
2166                 goto dm_CheckEdcaTurbo_EXIT;
2167
2168         /*printk("========>%s():bis_any_nonbepkts is %d\n", __func__, priv->bis_any_nonbepkts);*/
2169         /* Check the status for current condition. */
2170         if (!priv->ieee80211->bis_any_nonbepkts) {
2171                 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
2172                 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
2173                 /* For RT-AP, we needs to turn it on when Rx>Tx */
2174                 if (curRxOkCnt > 4*curTxOkCnt) {
2175                         /*printk("%s():curRxOkCnt > 4*curTxOkCnt\n");*/
2176                         if (!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) {
2177                                 write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]);
2178                                 priv->bis_cur_rdlstate = true;
2179                         }
2180                 } else {
2181                         /*printk("%s():curRxOkCnt < 4*curTxOkCnt\n");*/
2182                         if (priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) {
2183                                 write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]);
2184                                 priv->bis_cur_rdlstate = false;
2185                         }
2186
2187                 }
2188
2189                 priv->bcurrent_turbo_EDCA = true;
2190         } else {
2191                 /*
2192                  * Turn Off EDCA turbo here.
2193                  * Restore original EDCA according to the declaration of AP.
2194                  */
2195                 if (priv->bcurrent_turbo_EDCA) {
2196                         u8      u1bAIFS;
2197                         u32     u4bAcParam, op_limit, cw_max, cw_min;
2198
2199                         struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters;
2200                         u8 mode = priv->ieee80211->mode;
2201
2202                         /*  For Each time updating EDCA parameter, reset EDCA turbo mode status. */
2203                         dm_init_edca_turbo(dev);
2204
2205                         u1bAIFS = qos_parameters->aifs[0] * ((mode & (IEEE_G | IEEE_N_24G)) ? 9 : 20) + aSifsTime;
2206
2207                         op_limit = (u32)le16_to_cpu(qos_parameters->tx_op_limit[0]);
2208                         cw_max   = (u32)le16_to_cpu(qos_parameters->cw_max[0]);
2209                         cw_min   = (u32)le16_to_cpu(qos_parameters->cw_min[0]);
2210
2211                         op_limit <<= AC_PARAM_TXOP_LIMIT_OFFSET;
2212                         cw_max   <<= AC_PARAM_ECW_MAX_OFFSET;
2213                         cw_min   <<= AC_PARAM_ECW_MIN_OFFSET;
2214                         u1bAIFS  <<= AC_PARAM_AIFS_OFFSET;
2215
2216                         u4bAcParam = op_limit | cw_max | cw_min | u1bAIFS;
2217                         cpu_to_le32s(&u4bAcParam);
2218
2219                         write_nic_dword(dev, EDCAPARA_BE, u4bAcParam);
2220
2221
2222                         /*
2223                          * Check ACM bit.
2224                          * If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
2225                          */
2226                         {
2227                                 /*  TODO:  Modified this part and try to set acm control in only 1 IO processing!! */
2228
2229                                 struct aci_aifsn *pAciAifsn = (struct aci_aifsn *)&(qos_parameters->aifs[0]);
2230                                 u8              AcmCtrl;
2231
2232                                 read_nic_byte(dev, AcmHwCtrl, &AcmCtrl);
2233
2234                                 if (pAciAifsn->acm) { /*  acm bit is 1. */
2235                                         AcmCtrl |= AcmHw_BeqEn;
2236                                 } else {        /* ACM bit is 0. */
2237                                         AcmCtrl &= (~AcmHw_BeqEn);
2238                                 }
2239
2240                                 RT_TRACE(COMP_QOS, "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
2241                                 write_nic_byte(dev, AcmHwCtrl, AcmCtrl);
2242                         }
2243                         priv->bcurrent_turbo_EDCA = false;
2244                 }
2245         }
2246
2247 dm_CheckEdcaTurbo_EXIT:
2248         /* Set variables for next time. */
2249         priv->ieee80211->bis_any_nonbepkts = false;
2250         lastTxOkCnt = priv->stats.txbytesunicast;
2251         lastRxOkCnt = priv->stats.rxbytesunicast;
2252 }       /* dm_CheckEdcaTurbo */
2253
2254 static void dm_init_ctstoself(struct net_device *dev)
2255 {
2256         struct r8192_priv *priv = ieee80211_priv(dev);
2257
2258         priv->ieee80211->bCTSToSelfEnable = true;
2259         priv->ieee80211->CTSToSelfTH = CTS_TO_SELF_TH_VAL;
2260 }
2261
2262 static void dm_ctstoself(struct net_device *dev)
2263 {
2264         struct r8192_priv *priv = ieee80211_priv(dev);
2265         PRT_HIGH_THROUGHPUT     pHTInfo = priv->ieee80211->pHTInfo;
2266         static unsigned long                            lastTxOkCnt;
2267         static unsigned long                            lastRxOkCnt;
2268         unsigned long                                           curTxOkCnt = 0;
2269         unsigned long                                           curRxOkCnt = 0;
2270
2271         if (priv->ieee80211->bCTSToSelfEnable != true) {
2272                 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
2273                 return;
2274         }
2275         /*
2276         1. Uplink
2277         2. Linksys350/Linksys300N
2278         3. <50 disable, >55 enable
2279         */
2280
2281         if (pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM) {
2282                 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
2283                 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
2284                 if (curRxOkCnt > 4*curTxOkCnt) { /* downlink, disable CTS to self */
2285                         pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
2286                         /*DbgPrint("dm_CTSToSelf() ==> CTS to self disabled -- downlink\n");*/
2287                 } else { /* uplink */
2288                         pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF;
2289                 }
2290
2291                 lastTxOkCnt = priv->stats.txbytesunicast;
2292                 lastRxOkCnt = priv->stats.rxbytesunicast;
2293         }
2294 }
2295
2296 /*-----------------------------------------------------------------------------
2297  * Function:    dm_check_pbc_gpio()
2298  *
2299  * Overview:    Check if PBC button is pressed.
2300  *
2301  * Input:               NONE
2302  *
2303  * Output:              NONE
2304  *
2305  * Return:              NONE
2306  *
2307  * Revised History:
2308  *      When            Who             Remark
2309  *      05/28/2008      amy     Create Version 0 porting from windows code.
2310  *
2311  *---------------------------------------------------------------------------*/
2312 static  void    dm_check_pbc_gpio(struct net_device *dev)
2313 {
2314         struct r8192_priv *priv = ieee80211_priv(dev);
2315         u8 tmp1byte;
2316
2317         read_nic_byte(dev, GPI, &tmp1byte);
2318         if (tmp1byte == 0xff)
2319                 return;
2320
2321         if (tmp1byte & BIT(6) || tmp1byte & BIT(0)) {
2322                 /*
2323                  * Here we only set bPbcPressed to TRUE
2324                  * After trigger PBC, the variable will be set to FALSE
2325                  */
2326                 RT_TRACE(COMP_IO, "CheckPbcGPIO - PBC is pressed\n");
2327                 priv->bpbc_pressed = true;
2328         }
2329
2330 }
2331
2332 /*-----------------------------------------------------------------------------
2333  * Function:    DM_RFPathCheckWorkItemCallBack()
2334  *
2335  * Overview:    Check if Current RF RX path is enabled
2336  *
2337  * Input:               NONE
2338  *
2339  * Output:              NONE
2340  *
2341  * Return:              NONE
2342  *
2343  * Revised History:
2344  *      When            Who             Remark
2345  *      01/30/2008      MHC             Create Version 0.
2346  *
2347  *---------------------------------------------------------------------------*/
2348 void dm_rf_pathcheck_workitemcallback(struct work_struct *work)
2349 {
2350         struct delayed_work *dwork = to_delayed_work(work);
2351         struct r8192_priv *priv = container_of(dwork, struct r8192_priv, rfpath_check_wq);
2352         struct net_device *dev = priv->ieee80211->dev;
2353         /*bool bactually_set = false;*/
2354         u8 rfpath = 0, i;
2355
2356         /* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will
2357            always be the same. We only read 0xc04 now. */
2358         read_nic_byte(dev, 0xc04, &rfpath);
2359
2360         /* Check Bit 0-3, it means if RF A-D is enabled. */
2361         for (i = 0; i < RF90_PATH_MAX; i++) {
2362                 if (rfpath & (0x01<<i))
2363                         priv->brfpath_rxenable[i] = true;
2364                 else
2365                         priv->brfpath_rxenable[i] = false;
2366         }
2367
2368         dm_rxpath_sel_byrssi(dev);
2369 }       /* DM_RFPathCheckWorkItemCallBack */
2370
2371 static void dm_init_rxpath_selection(struct net_device *dev)
2372 {
2373         u8 i;
2374         struct r8192_priv *priv = ieee80211_priv(dev);
2375
2376         if (priv->CustomerID == RT_CID_819x_Netcore)
2377                 DM_RxPathSelTable.cck_method = CCK_RX_VERSION_2;
2378         else
2379                 DM_RxPathSelTable.cck_method = CCK_RX_VERSION_1;
2380         DM_RxPathSelTable.disabled_rf = 0;
2381         for (i = 0; i < 4; i++) {
2382                 DM_RxPathSelTable.rf_rssi[i] = 50;
2383                 DM_RxPathSelTable.cck_pwdb_sta[i] = -64;
2384                 DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
2385         }
2386 }
2387
2388 static void dm_rxpath_sel_byrssi(struct net_device *dev)
2389 {
2390         struct r8192_priv *priv = ieee80211_priv(dev);
2391         u8                              i, max_rssi_index = 0, min_rssi_index = 0, sec_rssi_index = 0, rf_num = 0;
2392         u8                              tmp_max_rssi = 0, tmp_min_rssi = 0, tmp_sec_rssi = 0;
2393         u8                              cck_default_Rx = 0x2;  /* RF-C */
2394         u8                              cck_optional_Rx = 0x3; /* RF-D */
2395         long                            tmp_cck_max_pwdb = 0, tmp_cck_min_pwdb = 0, tmp_cck_sec_pwdb = 0;
2396         u8                              cck_rx_ver2_max_index = 0, cck_rx_ver2_min_index = 0, cck_rx_ver2_sec_index = 0;
2397         u8                              cur_rf_rssi;
2398         long                            cur_cck_pwdb;
2399         static u8                       disabled_rf_cnt, cck_Rx_Path_initialized;
2400         u8                              update_cck_rx_path;
2401
2402         if (priv->rf_type != RF_2T4R)
2403                 return;
2404
2405         if (!cck_Rx_Path_initialized) {
2406                 read_nic_byte(dev, 0xa07, &DM_RxPathSelTable.cck_rx_path);
2407                 DM_RxPathSelTable.cck_rx_path &= 0xf;
2408                 cck_Rx_Path_initialized = 1;
2409         }
2410
2411         read_nic_byte(dev, 0xc04, &DM_RxPathSelTable.disabled_rf);
2412         DM_RxPathSelTable.disabled_rf = ~DM_RxPathSelTable.disabled_rf & 0xf;
2413
2414         if (priv->ieee80211->mode == WIRELESS_MODE_B) {
2415                 DM_RxPathSelTable.cck_method = CCK_RX_VERSION_2;        /* pure B mode, fixed cck version2 */
2416                 /*DbgPrint("Pure B mode, use cck rx version2\n");*/
2417         }
2418
2419         /* decide max/sec/min rssi index */
2420         for (i = 0; i < RF90_PATH_MAX; i++) {
2421                 DM_RxPathSelTable.rf_rssi[i] = priv->stats.rx_rssi_percentage[i];
2422
2423                 if (priv->brfpath_rxenable[i]) {
2424                         rf_num++;
2425                         cur_rf_rssi = DM_RxPathSelTable.rf_rssi[i];
2426
2427                         if (rf_num == 1) { /* find first enabled rf path and the rssi values */
2428                                 /* initialize, set all rssi index to the same one */
2429                                 max_rssi_index = min_rssi_index = sec_rssi_index = i;
2430                                 tmp_max_rssi = tmp_min_rssi = tmp_sec_rssi = cur_rf_rssi;
2431                         } else if (rf_num == 2) { /* we pick up the max index first, and let sec and min to be the same one */
2432                                 if (cur_rf_rssi >= tmp_max_rssi) {
2433                                         tmp_max_rssi = cur_rf_rssi;
2434                                         max_rssi_index = i;
2435                                 } else {
2436                                         tmp_sec_rssi = tmp_min_rssi = cur_rf_rssi;
2437                                         sec_rssi_index = min_rssi_index = i;
2438                                 }
2439                         } else {
2440                                 if (cur_rf_rssi > tmp_max_rssi) {
2441                                         tmp_sec_rssi = tmp_max_rssi;
2442                                         sec_rssi_index = max_rssi_index;
2443                                         tmp_max_rssi = cur_rf_rssi;
2444                                         max_rssi_index = i;
2445                                 } else if (cur_rf_rssi == tmp_max_rssi) {       /* let sec and min point to the different index */
2446                                         tmp_sec_rssi = cur_rf_rssi;
2447                                         sec_rssi_index = i;
2448                                 } else if ((cur_rf_rssi < tmp_max_rssi) && (cur_rf_rssi > tmp_sec_rssi)) {
2449                                         tmp_sec_rssi = cur_rf_rssi;
2450                                         sec_rssi_index = i;
2451                                 } else if (cur_rf_rssi == tmp_sec_rssi) {
2452                                         if (tmp_sec_rssi == tmp_min_rssi) {
2453                                                 /* let sec and min point to the different index */
2454                                                 tmp_sec_rssi = cur_rf_rssi;
2455                                                 sec_rssi_index = i;
2456                                         } else {
2457                                                 /* This case we don't need to set any index */
2458                                         }
2459                                 } else if ((cur_rf_rssi < tmp_sec_rssi) && (cur_rf_rssi > tmp_min_rssi)) {
2460                                         /* This case we don't need to set any index */
2461                                 } else if (cur_rf_rssi == tmp_min_rssi) {
2462                                         if (tmp_sec_rssi == tmp_min_rssi) {
2463                                                 /* let sec and min point to the different index */
2464                                                 tmp_min_rssi = cur_rf_rssi;
2465                                                 min_rssi_index = i;
2466                                         } else {
2467                                                 /* This case we don't need to set any index */
2468                                         }
2469                                 } else if (cur_rf_rssi < tmp_min_rssi) {
2470                                         tmp_min_rssi = cur_rf_rssi;
2471                                         min_rssi_index = i;
2472                                 }
2473                         }
2474                 }
2475         }
2476
2477         rf_num = 0;
2478         /* decide max/sec/min cck pwdb index */
2479         if (DM_RxPathSelTable.cck_method == CCK_RX_VERSION_2) {
2480                 for (i = 0; i < RF90_PATH_MAX; i++) {
2481                         if (priv->brfpath_rxenable[i]) {
2482                                 rf_num++;
2483                                 cur_cck_pwdb =  DM_RxPathSelTable.cck_pwdb_sta[i];
2484
2485                                 if (rf_num == 1) {      /* find first enabled rf path and the rssi values */
2486                                         /* initialize, set all rssi index to the same one */
2487                                         cck_rx_ver2_max_index = cck_rx_ver2_min_index = cck_rx_ver2_sec_index = i;
2488                                         tmp_cck_max_pwdb = tmp_cck_min_pwdb = tmp_cck_sec_pwdb = cur_cck_pwdb;
2489                                 } else if (rf_num == 2) {       /* we pick up the max index first, and let sec and min to be the same one */
2490                                         if (cur_cck_pwdb >= tmp_cck_max_pwdb) {
2491                                                 tmp_cck_max_pwdb = cur_cck_pwdb;
2492                                                 cck_rx_ver2_max_index = i;
2493                                         } else {
2494                                                 tmp_cck_sec_pwdb = tmp_cck_min_pwdb = cur_cck_pwdb;
2495                                                 cck_rx_ver2_sec_index = cck_rx_ver2_min_index = i;
2496                                         }
2497                                 } else {
2498                                         if (cur_cck_pwdb > tmp_cck_max_pwdb) {
2499                                                 tmp_cck_sec_pwdb = tmp_cck_max_pwdb;
2500                                                 cck_rx_ver2_sec_index = cck_rx_ver2_max_index;
2501                                                 tmp_cck_max_pwdb = cur_cck_pwdb;
2502                                                 cck_rx_ver2_max_index = i;
2503                                         } else if (cur_cck_pwdb == tmp_cck_max_pwdb) {
2504                                                 /* let sec and min point to the different index */
2505                                                 tmp_cck_sec_pwdb = cur_cck_pwdb;
2506                                                 cck_rx_ver2_sec_index = i;
2507                                         } else if ((cur_cck_pwdb < tmp_cck_max_pwdb) && (cur_cck_pwdb > tmp_cck_sec_pwdb)) {
2508                                                 tmp_cck_sec_pwdb = cur_cck_pwdb;
2509                                                 cck_rx_ver2_sec_index = i;
2510                                         } else if (cur_cck_pwdb == tmp_cck_sec_pwdb && tmp_cck_sec_pwdb == tmp_cck_min_pwdb) {
2511                                                 /* let sec and min point to the different index */
2512                                                 tmp_cck_sec_pwdb = cur_cck_pwdb;
2513                                                 cck_rx_ver2_sec_index = i;
2514                                                 /* otherwise we don't need to set any index */
2515                                         } else if ((cur_cck_pwdb < tmp_cck_sec_pwdb) && (cur_cck_pwdb > tmp_cck_min_pwdb)) {
2516                                                 /*  This case we don't need to set any index */
2517                                         } else if (cur_cck_pwdb == tmp_cck_min_pwdb && tmp_cck_sec_pwdb == tmp_cck_min_pwdb) {
2518                                                 /*  let sec and min point to the different index */
2519                                                 tmp_cck_min_pwdb = cur_cck_pwdb;
2520                                                 cck_rx_ver2_min_index = i;
2521                                                 /* otherwise we don't need to set any index */
2522                                         } else if (cur_cck_pwdb < tmp_cck_min_pwdb) {
2523                                                 tmp_cck_min_pwdb = cur_cck_pwdb;
2524                                                 cck_rx_ver2_min_index = i;
2525                                         }
2526                                 }
2527
2528                         }
2529                 }
2530         }
2531
2532         /*
2533          * Set CCK Rx path
2534          * reg0xA07[3:2]=cck default rx path, reg0xa07[1:0]=cck optional rx path.
2535          */
2536         update_cck_rx_path = 0;
2537         if (DM_RxPathSelTable.cck_method == CCK_RX_VERSION_2) {
2538                 cck_default_Rx = cck_rx_ver2_max_index;
2539                 cck_optional_Rx = cck_rx_ver2_sec_index;
2540                 if (tmp_cck_max_pwdb != -64)
2541                         update_cck_rx_path = 1;
2542         }
2543
2544         if (tmp_min_rssi < RX_PATH_SELECTION_SS_TH_LOW && disabled_rf_cnt < 2) {
2545                 if ((tmp_max_rssi - tmp_min_rssi) >= RX_PATH_SELECTION_DIFF_TH) {
2546                         /* record the enabled rssi threshold */
2547                         DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] = tmp_max_rssi+5;
2548                         /* disable the BB Rx path, OFDM */
2549                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<min_rssi_index, 0x0);  /* 0xc04[3:0] */
2550                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<min_rssi_index, 0x0);  /* 0xd04[3:0] */
2551                         disabled_rf_cnt++;
2552                 }
2553                 if (DM_RxPathSelTable.cck_method == CCK_RX_VERSION_1) {
2554                         cck_default_Rx = max_rssi_index;
2555                         cck_optional_Rx = sec_rssi_index;
2556                         if (tmp_max_rssi)
2557                                 update_cck_rx_path = 1;
2558                 }
2559         }
2560
2561         if (update_cck_rx_path) {
2562                 DM_RxPathSelTable.cck_rx_path = (cck_default_Rx<<2)|(cck_optional_Rx);
2563                 rtl8192_setBBreg(dev, rCCK0_AFESetting, 0x0f000000, DM_RxPathSelTable.cck_rx_path);
2564         }
2565
2566         if (DM_RxPathSelTable.disabled_rf) {
2567                 for (i = 0; i < 4; i++) {
2568                         if ((DM_RxPathSelTable.disabled_rf >> i) & 0x1) {       /* disabled rf */
2569                                 if (tmp_max_rssi >= DM_RxPathSelTable.rf_enable_rssi_th[i]) {
2570                                         /* enable the BB Rx path */
2571                                         /*DbgPrint("RF-%d is enabled.\n", 0x1<<i);*/
2572                                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<i, 0x1);       /* 0xc04[3:0] */
2573                                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<i, 0x1);       /* 0xd04[3:0] */
2574                                         DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
2575                                         disabled_rf_cnt--;
2576                                 }
2577                         }
2578                 }
2579         }
2580 }
2581
2582 /*-----------------------------------------------------------------------------
2583  * Function:    dm_check_rx_path_selection()
2584  *
2585  * Overview:    Call a workitem to check current RXRF path and Rx Path selection by RSSI.
2586  *
2587  * Input:               NONE
2588  *
2589  * Output:              NONE
2590  *
2591  * Return:              NONE
2592  *
2593  * Revised History:
2594  *      When            Who             Remark
2595  *      05/28/2008      amy             Create Version 0 porting from windows code.
2596  *
2597  *---------------------------------------------------------------------------*/
2598 static void dm_check_rx_path_selection(struct net_device *dev)
2599 {
2600         struct r8192_priv *priv = ieee80211_priv(dev);
2601
2602         queue_delayed_work(priv->priv_wq, &priv->rfpath_check_wq, 0);
2603 }       /* dm_CheckRxRFPath */
2604
2605 static void dm_init_fsync(struct net_device *dev)
2606 {
2607         struct r8192_priv *priv = ieee80211_priv(dev);
2608
2609         priv->ieee80211->fsync_time_interval = 500;
2610         priv->ieee80211->fsync_rate_bitmap = 0x0f000800;
2611         priv->ieee80211->fsync_rssi_threshold = 30;
2612         priv->ieee80211->bfsync_enable = false;
2613         priv->ieee80211->fsync_multiple_timeinterval = 3;
2614         priv->ieee80211->fsync_firstdiff_ratethreshold = 100;
2615         priv->ieee80211->fsync_seconddiff_ratethreshold = 200;
2616         priv->ieee80211->fsync_state = Default_Fsync;
2617         priv->framesyncMonitor = 1;     /* current default 0xc38 monitor on */
2618         timer_setup(&priv->fsync_timer, dm_fsync_timer_callback, 0);
2619 }
2620
2621 static void dm_deInit_fsync(struct net_device *dev)
2622 {
2623         struct r8192_priv *priv = ieee80211_priv(dev);
2624
2625         del_timer_sync(&priv->fsync_timer);
2626 }
2627
2628 void dm_fsync_timer_callback(struct timer_list *t)
2629 {
2630         struct r8192_priv *priv = from_timer(priv, t, fsync_timer);
2631         struct net_device *dev = priv->ieee80211->dev;
2632         u32 rate_index, rate_count = 0, rate_count_diff = 0;
2633         bool            bSwitchFromCountDiff = false;
2634         bool            bDoubleTimeInterval = false;
2635
2636         if (priv->ieee80211->state == IEEE80211_LINKED &&
2637             priv->ieee80211->bfsync_enable &&
2638                 (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC)) {
2639                 /* Count rate 54, MCS [7], [12, 13, 14, 15] */
2640                 u32 rate_bitmap;
2641
2642                 for (rate_index = 0; rate_index <= 27; rate_index++) {
2643                         rate_bitmap  = 1 << rate_index;
2644                         if (priv->ieee80211->fsync_rate_bitmap &  rate_bitmap)
2645                                 rate_count += priv->stats.received_rate_histogram[1][rate_index];
2646                 }
2647
2648                 if (rate_count < priv->rate_record)
2649                         rate_count_diff = 0xffffffff - rate_count + priv->rate_record;
2650                 else
2651                         rate_count_diff = rate_count - priv->rate_record;
2652                 if (rate_count_diff < priv->rateCountDiffRecord) {
2653                         u32 DiffNum = priv->rateCountDiffRecord - rate_count_diff;
2654                         /* Continue count */
2655                         if (DiffNum >= priv->ieee80211->fsync_seconddiff_ratethreshold)
2656                                 priv->ContinueDiffCount++;
2657                         else
2658                                 priv->ContinueDiffCount = 0;
2659
2660                         /* Continue count over */
2661                         if (priv->ContinueDiffCount >= 2) {
2662                                 bSwitchFromCountDiff = true;
2663                                 priv->ContinueDiffCount = 0;
2664                         }
2665                 } else {
2666                         /* Stop the continued count */
2667                         priv->ContinueDiffCount = 0;
2668                 }
2669
2670                 /* If Count diff <= FsyncRateCountThreshold */
2671                 if (rate_count_diff <= priv->ieee80211->fsync_firstdiff_ratethreshold) {
2672                         bSwitchFromCountDiff = true;
2673                         priv->ContinueDiffCount = 0;
2674                 }
2675                 priv->rate_record = rate_count;
2676                 priv->rateCountDiffRecord = rate_count_diff;
2677                 RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff, priv->bswitch_fsync);
2678                 /* if we never receive those mcs rate and rssi > 30 % then switch fsyn */
2679                 if (priv->undecorated_smoothed_pwdb > priv->ieee80211->fsync_rssi_threshold && bSwitchFromCountDiff) {
2680                         bDoubleTimeInterval = true;
2681                         priv->bswitch_fsync = !priv->bswitch_fsync;
2682                         if (priv->bswitch_fsync) {
2683                                 write_nic_byte(dev, 0xC36, 0x1c);
2684                                 write_nic_byte(dev, 0xC3e, 0x90);
2685                         } else {
2686                                 write_nic_byte(dev, 0xC36, 0x5c);
2687                                 write_nic_byte(dev, 0xC3e, 0x96);
2688                         }
2689                 } else if (priv->undecorated_smoothed_pwdb <= priv->ieee80211->fsync_rssi_threshold) {
2690                         if (priv->bswitch_fsync) {
2691                                 priv->bswitch_fsync  = false;
2692                                 write_nic_byte(dev, 0xC36, 0x5c);
2693                                 write_nic_byte(dev, 0xC3e, 0x96);
2694                         }
2695                 }
2696                 if (bDoubleTimeInterval) {
2697                         if (timer_pending(&priv->fsync_timer))
2698                                 del_timer_sync(&priv->fsync_timer);
2699                         priv->fsync_timer.expires = jiffies +
2700                                 msecs_to_jiffies(priv->ieee80211->fsync_time_interval*priv->ieee80211->fsync_multiple_timeinterval);
2701                         add_timer(&priv->fsync_timer);
2702                 } else {
2703                         if (timer_pending(&priv->fsync_timer))
2704                                 del_timer_sync(&priv->fsync_timer);
2705                         priv->fsync_timer.expires = jiffies +
2706                                 msecs_to_jiffies(priv->ieee80211->fsync_time_interval);
2707                         add_timer(&priv->fsync_timer);
2708                 }
2709         } else {
2710                 /* Let Register return to default value; */
2711                 if (priv->bswitch_fsync) {
2712                         priv->bswitch_fsync  = false;
2713                         write_nic_byte(dev, 0xC36, 0x5c);
2714                         write_nic_byte(dev, 0xC3e, 0x96);
2715                 }
2716                 priv->ContinueDiffCount = 0;
2717                 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
2718         }
2719         RT_TRACE(COMP_HALDM, "ContinueDiffCount %d\n", priv->ContinueDiffCount);
2720         RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff, priv->bswitch_fsync);
2721 }
2722
2723 static void dm_StartHWFsync(struct net_device *dev)
2724 {
2725         RT_TRACE(COMP_HALDM, "%s\n", __func__);
2726         write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cf);
2727         write_nic_byte(dev, 0xc3b, 0x41);
2728 }
2729
2730 static void dm_EndSWFsync(struct net_device *dev)
2731 {
2732         struct r8192_priv *priv = ieee80211_priv(dev);
2733
2734         RT_TRACE(COMP_HALDM, "%s\n", __func__);
2735         del_timer_sync(&(priv->fsync_timer));
2736
2737         /* Let Register return to default value; */
2738         if (priv->bswitch_fsync) {
2739                 priv->bswitch_fsync  = false;
2740
2741                 write_nic_byte(dev, 0xC36, 0x5c);
2742
2743                 write_nic_byte(dev, 0xC3e, 0x96);
2744         }
2745
2746         priv->ContinueDiffCount = 0;
2747         write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
2748
2749 }
2750
2751 static void dm_StartSWFsync(struct net_device *dev)
2752 {
2753         struct r8192_priv *priv = ieee80211_priv(dev);
2754         u32                     rateIndex;
2755         u32                     rateBitmap;
2756
2757         RT_TRACE(COMP_HALDM, "%s\n", __func__);
2758         /* Initial rate record to zero, start to record. */
2759         priv->rate_record = 0;
2760         /* Initialize continue diff count to zero, start to record. */
2761         priv->ContinueDiffCount = 0;
2762         priv->rateCountDiffRecord = 0;
2763         priv->bswitch_fsync  = false;
2764
2765         if (priv->ieee80211->mode == WIRELESS_MODE_N_24G) {
2766                 priv->ieee80211->fsync_firstdiff_ratethreshold = 600;
2767                 priv->ieee80211->fsync_seconddiff_ratethreshold = 0xffff;
2768         } else {
2769                 priv->ieee80211->fsync_firstdiff_ratethreshold = 200;
2770                 priv->ieee80211->fsync_seconddiff_ratethreshold = 200;
2771         }
2772         for (rateIndex = 0; rateIndex <= 27; rateIndex++) {
2773                 rateBitmap = 1 << rateIndex;
2774                 if (priv->ieee80211->fsync_rate_bitmap &  rateBitmap)
2775                         priv->rate_record += priv->stats.received_rate_histogram[1][rateIndex];
2776         }
2777         if (timer_pending(&priv->fsync_timer))
2778                 del_timer_sync(&priv->fsync_timer);
2779         priv->fsync_timer.expires = jiffies +
2780                         msecs_to_jiffies(priv->ieee80211->fsync_time_interval);
2781         add_timer(&priv->fsync_timer);
2782
2783         write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cd);
2784
2785 }
2786
2787 static void dm_EndHWFsync(struct net_device *dev)
2788 {
2789         RT_TRACE(COMP_HALDM, "%s\n", __func__);
2790         write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
2791         write_nic_byte(dev, 0xc3b, 0x49);
2792
2793 }
2794
2795 void dm_check_fsync(struct net_device *dev)
2796 {
2797 #define RegC38_Default                          0
2798 #define RegC38_NonFsync_Other_AP                1
2799 #define RegC38_Fsync_AP_BCM                     2
2800         struct r8192_priv *priv = ieee80211_priv(dev);
2801         /*u32                   framesyncC34;*/
2802         static u8               reg_c38_State = RegC38_Default;
2803         static u32      reset_cnt;
2804
2805         RT_TRACE(COMP_HALDM, "RSSI %d TimeInterval %d MultipleTimeInterval %d\n", priv->ieee80211->fsync_rssi_threshold, priv->ieee80211->fsync_time_interval, priv->ieee80211->fsync_multiple_timeinterval);
2806         RT_TRACE(COMP_HALDM, "RateBitmap 0x%x FirstDiffRateThreshold %d SecondDiffRateThreshold %d\n", priv->ieee80211->fsync_rate_bitmap, priv->ieee80211->fsync_firstdiff_ratethreshold, priv->ieee80211->fsync_seconddiff_ratethreshold);
2807
2808         if (priv->ieee80211->state == IEEE80211_LINKED &&
2809                 (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC)) {
2810                 if (priv->ieee80211->bfsync_enable == 0) {
2811                         switch (priv->ieee80211->fsync_state) {
2812                         case Default_Fsync:
2813                                 dm_StartHWFsync(dev);
2814                                 priv->ieee80211->fsync_state = HW_Fsync;
2815                                 break;
2816                         case SW_Fsync:
2817                                 dm_EndSWFsync(dev);
2818                                 dm_StartHWFsync(dev);
2819                                 priv->ieee80211->fsync_state = HW_Fsync;
2820                                 break;
2821                         case HW_Fsync:
2822                         default:
2823                                 break;
2824                         }
2825                 } else {
2826                         switch (priv->ieee80211->fsync_state) {
2827                         case Default_Fsync:
2828                                 dm_StartSWFsync(dev);
2829                                 priv->ieee80211->fsync_state = SW_Fsync;
2830                                 break;
2831                         case HW_Fsync:
2832                                 dm_EndHWFsync(dev);
2833                                 dm_StartSWFsync(dev);
2834                                 priv->ieee80211->fsync_state = SW_Fsync;
2835                                 break;
2836                         case SW_Fsync:
2837                         default:
2838                                 break;
2839                         }
2840                 }
2841                 if (priv->framesyncMonitor) {
2842                         if (reg_c38_State != RegC38_Fsync_AP_BCM) {
2843                                 /* For broadcom AP we write different default value */
2844                                 write_nic_byte(dev, rOFDM0_RxDetector3, 0x95);
2845
2846                                 reg_c38_State = RegC38_Fsync_AP_BCM;
2847                         }
2848                 }
2849         } else {
2850                 switch (priv->ieee80211->fsync_state) {
2851                 case HW_Fsync:
2852                         dm_EndHWFsync(dev);
2853                         priv->ieee80211->fsync_state = Default_Fsync;
2854                         break;
2855                 case SW_Fsync:
2856                         dm_EndSWFsync(dev);
2857                         priv->ieee80211->fsync_state = Default_Fsync;
2858                         break;
2859                 case Default_Fsync:
2860                 default:
2861                         break;
2862                 }
2863
2864                 if (priv->framesyncMonitor) {
2865                         if (priv->ieee80211->state == IEEE80211_LINKED) {
2866                                 if (priv->undecorated_smoothed_pwdb <= REG_C38_TH) {
2867                                         if (reg_c38_State != RegC38_NonFsync_Other_AP) {
2868                                                 write_nic_byte(dev, rOFDM0_RxDetector3, 0x90);
2869
2870                                                 reg_c38_State = RegC38_NonFsync_Other_AP;
2871                                         }
2872                                 } else if (priv->undecorated_smoothed_pwdb >= (REG_C38_TH + 5)) {
2873                                         if (reg_c38_State) {
2874                                                 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
2875                                                 reg_c38_State = RegC38_Default;
2876                                                 /*DbgPrint("Fsync is idle, rssi>=40, write 0xc38 = 0x%x\n", pHalData->framesync);*/
2877                                         }
2878                                 }
2879                         } else {
2880                                 if (reg_c38_State) {
2881                                         write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
2882                                         reg_c38_State = RegC38_Default;
2883                                         /*DbgPrint("Fsync is idle, not connected, write 0xc38 = 0x%x\n", pHalData->framesync);*/
2884                                 }
2885                         }
2886                 }
2887         }
2888         if (priv->framesyncMonitor) {
2889                 if (priv->reset_count != reset_cnt) { /* After silent reset, the reg_c38_State will be returned to default value */
2890                         write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
2891                         reg_c38_State = RegC38_Default;
2892                         reset_cnt = priv->reset_count;
2893                         /*DbgPrint("reg_c38_State = 0 for silent reset.\n");*/
2894                 }
2895         } else {
2896                 if (reg_c38_State) {
2897                         write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
2898                         reg_c38_State = RegC38_Default;
2899                         /*DbgPrint("framesync no monitor, write 0xc38 = 0x%x\n", pHalData->framesync);*/
2900                 }
2901         }
2902 }
2903
2904 /*-----------------------------------------------------------------------------
2905  * Function:    dm_shadow_init()
2906  *
2907  * Overview:    Store all NIC MAC/BB register content.
2908  *
2909  * Input:               NONE
2910  *
2911  * Output:              NONE
2912  *
2913  * Return:              NONE
2914  *
2915  * Revised History:
2916  *      When            Who             Remark
2917  *      05/29/2008      amy             Create Version 0 porting from windows code.
2918  *
2919  *---------------------------------------------------------------------------*/
2920 void dm_shadow_init(struct net_device *dev)
2921 {
2922         u8      page;
2923         u16     offset;
2924
2925         for (page = 0; page < 5; page++)
2926                 for (offset = 0; offset < 256; offset++) {
2927                         read_nic_byte(dev, offset + page * 256, &dm_shadow[page][offset]);
2928                         /*DbgPrint("P-%d/O-%02x=%02x\r\n", page, offset, DM_Shadow[page][offset]);*/
2929                 }
2930
2931         for (page = 8; page < 11; page++)
2932                 for (offset = 0; offset < 256; offset++)
2933                         read_nic_byte(dev, offset + page * 256, &dm_shadow[page][offset]);
2934
2935         for (page = 12; page < 15; page++)
2936                 for (offset = 0; offset < 256; offset++)
2937                         read_nic_byte(dev, offset + page * 256, &dm_shadow[page][offset]);
2938
2939 }   /* dm_shadow_init */
2940
2941 /*---------------------------Define function prototype------------------------*/
2942 /*-----------------------------------------------------------------------------
2943  * Function:    DM_DynamicTxPower()
2944  *
2945  * Overview:    Detect Signal strength to control TX Registry
2946                         Tx Power Control For Near/Far Range
2947  *
2948  * Input:               NONE
2949  *
2950  * Output:              NONE
2951  *
2952  * Return:              NONE
2953  *
2954  * Revised History:
2955  *      When            Who             Remark
2956  *      03/06/2008      Jacken  Create Version 0.
2957  *
2958  *---------------------------------------------------------------------------*/
2959 static void dm_init_dynamic_txpower(struct net_device *dev)
2960 {
2961         struct r8192_priv *priv = ieee80211_priv(dev);
2962
2963         /* Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code. */
2964         priv->ieee80211->bdynamic_txpower_enable = true;    /* Default to enable Tx Power Control */
2965         priv->bLastDTPFlag_High = false;
2966         priv->bLastDTPFlag_Low = false;
2967         priv->bDynamicTxHighPower = false;
2968         priv->bDynamicTxLowPower = false;
2969 }
2970
2971 static void dm_dynamic_txpower(struct net_device *dev)
2972 {
2973         struct r8192_priv *priv = ieee80211_priv(dev);
2974         unsigned int txhipower_threshold = 0;
2975         unsigned int txlowpower_threshold = 0;
2976
2977         if (priv->ieee80211->bdynamic_txpower_enable != true) {
2978                 priv->bDynamicTxHighPower = false;
2979                 priv->bDynamicTxLowPower = false;
2980                 return;
2981         }
2982         /*printk("priv->ieee80211->current_network.unknown_cap_exist is %d , priv->ieee80211->current_network.broadcom_cap_exist is %d\n", priv->ieee80211->current_network.unknown_cap_exist, priv->ieee80211->current_network.broadcom_cap_exist);*/
2983         if ((priv->ieee80211->current_network.atheros_cap_exist) && (priv->ieee80211->mode == IEEE_G)) {
2984                 txhipower_threshold = TX_POWER_ATHEROAP_THRESH_HIGH;
2985                 txlowpower_threshold = TX_POWER_ATHEROAP_THRESH_LOW;
2986         } else {
2987                 txhipower_threshold = TX_POWER_NEAR_FIELD_THRESH_HIGH;
2988                 txlowpower_threshold = TX_POWER_NEAR_FIELD_THRESH_LOW;
2989         }
2990
2991         /*printk("=======>%s(): txhipower_threshold is %d, txlowpower_threshold is %d\n", __func__, txhipower_threshold, txlowpower_threshold);*/
2992         RT_TRACE(COMP_TXAGC, "priv->undecorated_smoothed_pwdb = %ld\n", priv->undecorated_smoothed_pwdb);
2993
2994         if (priv->ieee80211->state == IEEE80211_LINKED) {
2995                 if (priv->undecorated_smoothed_pwdb >= txhipower_threshold) {
2996                         priv->bDynamicTxHighPower = true;
2997                         priv->bDynamicTxLowPower = false;
2998                 } else {
2999                         /* high power state check */
3000                         if (priv->undecorated_smoothed_pwdb < txlowpower_threshold && priv->bDynamicTxHighPower)
3001                                 priv->bDynamicTxHighPower = false;
3002
3003                         /* low power state check */
3004                         if (priv->undecorated_smoothed_pwdb < 35)
3005                                 priv->bDynamicTxLowPower = true;
3006                         else if (priv->undecorated_smoothed_pwdb >= 40)
3007                                 priv->bDynamicTxLowPower = false;
3008                 }
3009         } else {
3010                 /*pHalData->bTXPowerCtrlforNearFarRange = !pHalData->bTXPowerCtrlforNearFarRange;*/
3011                 priv->bDynamicTxHighPower = false;
3012                 priv->bDynamicTxLowPower = false;
3013         }
3014
3015         if ((priv->bDynamicTxHighPower != priv->bLastDTPFlag_High) ||
3016                 (priv->bDynamicTxLowPower != priv->bLastDTPFlag_Low)) {
3017                 RT_TRACE(COMP_TXAGC, "SetTxPowerLevel8190()  channel = %d\n", priv->ieee80211->current_network.channel);
3018
3019 #if  defined(RTL8190P) || defined(RTL8192E)
3020                 SetTxPowerLevel8190(Adapter, pHalData->CurrentChannel);
3021 #endif
3022
3023                 rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel);
3024                 /*pHalData->bStartTxCtrlByTPCNFR = FALSE;    Clear th flag of Set TX Power from Sitesurvey*/
3025         }
3026         priv->bLastDTPFlag_High = priv->bDynamicTxHighPower;
3027         priv->bLastDTPFlag_Low = priv->bDynamicTxLowPower;
3028
3029 }       /* dm_dynamic_txpower */
3030
3031 /* added by vivi, for read tx rate and retrycount */
3032 static void dm_check_txrateandretrycount(struct net_device *dev)
3033 {
3034         struct r8192_priv *priv = ieee80211_priv(dev);
3035         struct ieee80211_device *ieee = priv->ieee80211;
3036         /* for 11n tx rate */
3037         /*priv->stats.CurrentShowTxate = read_nic_byte(dev, CURRENT_TX_RATE_REG);*/
3038         read_nic_byte(dev, CURRENT_TX_RATE_REG, &ieee->softmac_stats.CurrentShowTxate);
3039         /*printk("=============>tx_rate_reg:%x\n", ieee->softmac_stats.CurrentShowTxate);*/
3040         /* for initial tx rate */
3041         /*priv->stats.last_packet_rate = read_nic_byte(dev, INITIAL_TX_RATE_REG);*/
3042         read_nic_byte(dev, INITIAL_TX_RATE_REG, &ieee->softmac_stats.last_packet_rate);
3043         /* for tx tx retry count */
3044         /*priv->stats.txretrycount = read_nic_dword(dev, TX_RETRY_COUNT_REG);*/
3045         read_nic_dword(dev, TX_RETRY_COUNT_REG, &ieee->softmac_stats.txretrycount);
3046 }
3047
3048 static void dm_send_rssi_tofw(struct net_device *dev)
3049 {
3050         struct r8192_priv *priv = ieee80211_priv(dev);
3051
3052         /*
3053          * If we test chariot, we should stop the TX command ?
3054          * Because 92E will always silent reset when we send tx command. We use register
3055          * 0x1e0(byte) to notify driver.
3056          */
3057         write_nic_byte(dev, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb);
3058 }
3059
3060 /*---------------------------Define function prototype------------------------*/