1 /* SPDX-License-Identifier: GPL-2.0 */
3 * This is part of rtl8187 OpenSource driver.
4 * Copyright (C) Andrea Merello 2004-2005 <andrea.merello@gmail.com>
5 * Released under the terms of GPL (General Public Licence)
7 * Parts of this driver are based on the GPL part of the
8 * official realtek driver
10 * Parts of this driver are based on the rtl8192 driver skeleton
11 * from Patric Schenke & Andres Salomon
13 * Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
15 * We want to thank the Authors of those projects and the Ndiswrapper
22 #include <linux/compiler.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/ioport.h>
26 #include <linux/sched.h>
27 #include <linux/types.h>
28 #include <linux/slab.h>
29 #include <linux/netdevice.h>
30 #include <linux/usb.h>
31 #include <linux/etherdevice.h>
32 #include <linux/delay.h>
33 #include <linux/rtnetlink.h>
34 #include <linux/wireless.h>
35 #include <linux/timer.h>
36 #include <linux/proc_fs.h>
37 #include <linux/if_arp.h>
38 #include <linux/random.h>
40 #include "ieee80211/ieee80211.h"
43 #define RTL819XU_MODULE_NAME "rtl819xU"
45 #define MAX_KEY_LEN 61
46 #define KEY_BUF_SIZE 5
48 #define RX_SMOOTH_FACTOR 20
49 #define DMESG(x, a...)
50 #define DMESGW(x, a...)
51 #define DMESGE(x, a...)
52 extern u32 rt_global_debug_component;
53 #define RT_TRACE(component, x, args...) \
55 if (rt_global_debug_component & (component)) \
56 pr_debug("RTL8192U: " x "\n", ##args); \
59 #define COMP_TRACE BIT(0) /* Function call tracing. */
60 #define COMP_DBG BIT(1)
61 #define COMP_INIT BIT(2) /* Driver initialization/halt/reset. */
63 #define COMP_RECV BIT(3) /* Receive data path. */
64 #define COMP_SEND BIT(4) /* Send data path. */
65 #define COMP_IO BIT(5)
66 /* 802.11 Power Save mode or System/Device Power state. */
67 #define COMP_POWER BIT(6)
68 /* 802.11 link related: join/start BSS, leave BSS. */
69 #define COMP_EPROM BIT(7)
70 #define COMP_SWBW BIT(8) /* Bandwidth switch. */
71 #define COMP_POWER_TRACKING BIT(9) /* 8190 TX Power Tracking */
72 #define COMP_TURBO BIT(10) /* Turbo Mode */
73 #define COMP_QOS BIT(11)
74 #define COMP_RATE BIT(12) /* Rate Adaptive mechanism */
75 #define COMP_RM BIT(13) /* Radio Measurement */
76 #define COMP_DIG BIT(14)
77 #define COMP_PHY BIT(15)
78 #define COMP_CH BIT(16) /* Channel setting debug */
79 #define COMP_TXAGC BIT(17) /* Tx power */
80 #define COMP_HIPWR BIT(18) /* High Power Mechanism */
81 #define COMP_HALDM BIT(19) /* HW Dynamic Mechanism */
82 #define COMP_SEC BIT(20) /* Event handling */
83 #define COMP_LED BIT(21)
84 #define COMP_RF BIT(22)
85 #define COMP_RXDESC BIT(23) /* Rx desc information for SD3 debug */
87 /* 11n or 8190 specific code */
89 #define COMP_FIRMWARE BIT(24) /* Firmware downloading */
90 #define COMP_HT BIT(25) /* 802.11n HT related information */
91 #define COMP_AMSDU BIT(26) /* A-MSDU Debugging */
92 #define COMP_SCAN BIT(27)
93 #define COMP_DOWN BIT(29) /* rm driver module */
94 #define COMP_RESET BIT(30) /* Silent reset */
95 #define COMP_ERR BIT(31) /* Error out, always on */
99 #define RTL8192U_ASSERT(expr) \
102 pr_debug("Assertion failed! %s, %s, %s, line = %d\n", \
103 #expr, __FILE__, __func__, __LINE__); \
107 * Debug out data buf.
108 * If you want to print DATA buffer related BA,
109 * please set ieee80211_debug_level to DATA|BA
111 #define RT_DEBUG_DATA(level, data, datalen) \
113 if ((rt_global_debug_component & (level)) == (level)) { \
115 u8 *pdata = (u8 *)data; \
116 pr_debug("RTL8192U: %s()\n", __func__); \
117 for (i = 0; i < (int)(datalen); i++) { \
118 printk("%2x ", pdata[i]); \
126 #define RTL8192U_ASSERT(expr) do {} while (0)
127 #define RT_DEBUG_DATA(level, data, datalen) do {} while (0)
128 #endif /* RTL8169_DEBUG */
130 /* Queue Select Value in TxDesc */
135 #define QSLT_BEACON 0x10
136 #define QSLT_HIGH 0x11
137 #define QSLT_MGNT 0x12
138 #define QSLT_CMD 0x13
140 #define DESC90_RATE1M 0x00
141 #define DESC90_RATE2M 0x01
142 #define DESC90_RATE5_5M 0x02
143 #define DESC90_RATE11M 0x03
144 #define DESC90_RATE6M 0x04
145 #define DESC90_RATE9M 0x05
146 #define DESC90_RATE12M 0x06
147 #define DESC90_RATE18M 0x07
148 #define DESC90_RATE24M 0x08
149 #define DESC90_RATE36M 0x09
150 #define DESC90_RATE48M 0x0a
151 #define DESC90_RATE54M 0x0b
152 #define DESC90_RATEMCS0 0x00
153 #define DESC90_RATEMCS1 0x01
154 #define DESC90_RATEMCS2 0x02
155 #define DESC90_RATEMCS3 0x03
156 #define DESC90_RATEMCS4 0x04
157 #define DESC90_RATEMCS5 0x05
158 #define DESC90_RATEMCS6 0x06
159 #define DESC90_RATEMCS7 0x07
160 #define DESC90_RATEMCS8 0x08
161 #define DESC90_RATEMCS9 0x09
162 #define DESC90_RATEMCS10 0x0a
163 #define DESC90_RATEMCS11 0x0b
164 #define DESC90_RATEMCS12 0x0c
165 #define DESC90_RATEMCS13 0x0d
166 #define DESC90_RATEMCS14 0x0e
167 #define DESC90_RATEMCS15 0x0f
168 #define DESC90_RATEMCS32 0x20
170 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
172 #define IEEE80211_WATCH_DOG_TIME 2000
173 #define PHY_Beacon_RSSI_SLID_WIN_MAX 10
174 /* For Tx Power Tracking */
175 #define OFDM_Table_Length 19
176 #define CCK_Table_length 12
179 struct tx_desc_819x_usb {
207 u8 ResvForPaddingLen:7;
217 struct tx_desc_cmd_819x_usb {
244 struct tx_fwinfo_819x_usb {
251 u8 Short:1; /* Error out, always on */
252 u8 TxBandwidth:1; /* Used for HT MCS rate only */
253 u8 TxSubCarrier:2; /* Used for legacy OFDM rate only */
255 u8 AllowAggregation:1;
256 /* Interpret RtsRate field as high throughput data rate */
258 u8 RtsShort:1; /* Short PLCP for CCK or short GI for 11n MCS */
259 u8 RtsBandwidth:1; /* Used for HT MCS rate only */
260 u8 RtsSubcarrier:2;/* Used for legacy OFDM rate only */
262 /* Enable firmware to recalculate and assign packet duration */
268 /* 1 indicate Tx info gathered by firmware and returned by Rx Cmd */
269 u32 TxPerPktInfoFeedback:1;
277 struct rtl8192_rx_info {
279 struct net_device *dev;
283 struct rx_desc_819x_usb {
298 struct rx_drvinfo_819x_usb {
321 /* Support till 64 bit bus width OS */
322 #define MAX_DEV_ADDR_SIZE 8
324 #define MAX_FIRMWARE_INFORMATION_SIZE 32
325 #define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE)
326 #define ENCRYPTION_MAX_OVERHEAD 128
327 #define USB_HWDESC_HEADER_LEN sizeof(struct tx_desc_819x_usb)
328 #define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(struct tx_fwinfo_819x_usb))
329 #define MAX_FRAGMENT_COUNT 8
330 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
331 #define MAX_TRANSMIT_BUFFER_SIZE 32000
333 #define MAX_TRANSMIT_BUFFER_SIZE 8000
335 /* Octets for crc32 (FCS, ICV) */
339 RF_OP_By_SW_3wire = 0,
344 /* 8190 Loopback Mode definition */
345 typedef enum _rtl819xUsb_loopback {
346 RTL819xU_NO_LOOPBACK = 0,
347 RTL819xU_MAC_LOOPBACK = 1,
348 RTL819xU_DMA_LOOPBACK = 2,
349 RTL819xU_CCK_LOOPBACK = 3,
350 } rtl819xUsb_loopback_e;
352 /* due to rtl8192 firmware */
353 typedef enum _desc_packet_type_e {
354 DESC_PACKET_TYPE_INIT = 0,
355 DESC_PACKET_TYPE_NORMAL = 1,
356 } desc_packet_type_e;
358 typedef enum _firmware_status {
359 FW_STATUS_0_INIT = 0,
360 FW_STATUS_1_MOVE_BOOT_CODE = 1,
361 FW_STATUS_2_MOVE_MAIN_CODE = 2,
362 FW_STATUS_3_TURNON_CPU = 3,
363 FW_STATUS_4_MOVE_DATA_CODE = 4,
364 FW_STATUS_5_READY = 5,
367 typedef struct _fw_seg_container {
370 } fw_seg_container, *pfw_seg_container;
371 typedef struct _rt_firmware {
372 firmware_status_e firmware_status;
373 u16 cmdpacket_frag_threshold;
374 #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000
375 u8 firmware_buf[RTL8190_MAX_FIRMWARE_CODE_SIZE];
376 u16 firmware_buf_size;
377 } rt_firmware, *prt_firmware;
379 /* Add this to 9100 bytes to receive A-MSDU from RT-AP */
380 #define MAX_RECEIVE_BUFFER_SIZE 9100
382 typedef struct _rt_firmware_info_819xUsb {
384 } rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb;
386 /* Firmware Queue Layout */
387 #define NUM_OF_FIRMWARE_QUEUE 10
388 #define NUM_OF_PAGES_IN_FW 0x100
391 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x000
392 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x000
393 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x0ff
394 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x000
395 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0
396 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
397 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x00
398 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0
399 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x0
400 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x00
403 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x020
404 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x020
405 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x040
406 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x040
407 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0
408 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x4
409 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x20
410 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0
411 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4
412 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x18
416 #define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000
417 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00
418 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08
419 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10
420 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18
421 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10
422 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT 0x08
423 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00
424 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08
427 * =================================================================
428 * =================================================================
431 #define EPROM_93c46 0
432 #define EPROM_93c56 1
434 #define DEFAULT_FRAG_THRESHOLD 2342U
435 #define MIN_FRAG_THRESHOLD 256U
436 #define DEFAULT_BEACONINTERVAL 0x64U
437 #define DEFAULT_BEACON_ESSID "Rtl819xU"
439 #define DEFAULT_SSID ""
440 #define DEFAULT_RETRY_RTS 7
441 #define DEFAULT_RETRY_DATA 7
442 #define PRISM_HDR_SIZE 64
444 #define PHY_RSSI_SLID_WIN_MAX 100
446 typedef enum _WIRELESS_MODE {
447 WIRELESS_MODE_UNKNOWN = 0x00,
448 WIRELESS_MODE_A = 0x01,
449 WIRELESS_MODE_B = 0x02,
450 WIRELESS_MODE_G = 0x04,
451 WIRELESS_MODE_AUTO = 0x08,
452 WIRELESS_MODE_N_24G = 0x10,
453 WIRELESS_MODE_N_5G = 0x20
456 #define RTL_IOCTL_WPA_SUPPLICANT (SIOCIWFIRSTPRIV + 30)
458 typedef struct buffer {
464 typedef struct rtl_reg_debug {
470 unsigned char length;
472 unsigned char buf[0xff];
475 typedef struct _rt_9x_tx_rate_history {
479 } rt_tx_rahis_t, *prt_tx_rahis_t;
480 typedef struct _RT_SMOOTH_DATA_4RF {
481 s8 elements[4][100]; /* array to store values */
482 u32 index; /* index to current array to store */
483 u32 TotalNum; /* num of valid elements */
484 u32 TotalVal[4]; /* sum of valid elements */
485 } RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
487 /* This maybe changed for D-cut larger aggregation size */
488 #define MAX_8192U_RX_SIZE 8192
489 /* Stats seems messed up, clean it ASAP */
490 typedef struct Stats {
493 unsigned long rxframgment;
494 unsigned long rxurberr;
495 unsigned long rxstaterr;
496 /* 0: Total, 1: OK, 2: CRC, 3: ICV */
497 unsigned long received_rate_histogram[4][32];
498 /* 0: Long preamble/GI, 1: Short preamble/GI */
499 unsigned long received_preamble_GI[2][32];
500 /* level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K) */
501 unsigned long rx_AMPDUsize_histogram[5];
502 /* level: (<5), (5~10), (10~20), (20~40), (>40) */
503 unsigned long rx_AMPDUnum_histogram[5];
504 unsigned long numpacket_matchbssid;
505 unsigned long numpacket_toself;
506 unsigned long num_process_phyinfo;
507 unsigned long numqry_phystatus;
508 unsigned long numqry_phystatusCCK;
509 unsigned long numqry_phystatusHT;
510 /* 0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate */
511 unsigned long received_bwtype[5];
512 unsigned long txnperr;
513 unsigned long txnpdrop;
514 unsigned long txresumed;
515 unsigned long txnpokint;
516 unsigned long txoverflow;
517 unsigned long txlpokint;
518 unsigned long txlpdrop;
519 unsigned long txlperr;
520 unsigned long txbeokint;
521 unsigned long txbedrop;
522 unsigned long txbeerr;
523 unsigned long txbkokint;
524 unsigned long txbkdrop;
525 unsigned long txbkerr;
526 unsigned long txviokint;
527 unsigned long txvidrop;
528 unsigned long txvierr;
529 unsigned long txvookint;
530 unsigned long txvodrop;
531 unsigned long txvoerr;
532 unsigned long txbeaconokint;
533 unsigned long txbeacondrop;
534 unsigned long txbeaconerr;
535 unsigned long txmanageokint;
536 unsigned long txmanagedrop;
537 unsigned long txmanageerr;
538 unsigned long txdatapkt;
539 unsigned long txfeedback;
540 unsigned long txfeedbackok;
542 unsigned long txoktotal;
543 unsigned long txokbytestotal;
544 unsigned long txokinperiod;
545 unsigned long txmulticast;
546 unsigned long txbytesmulticast;
547 unsigned long txbroadcast;
548 unsigned long txbytesbroadcast;
549 unsigned long txunicast;
550 unsigned long txbytesunicast;
552 unsigned long rxoktotal;
553 unsigned long rxbytesunicast;
554 unsigned long txfeedbackfail;
555 unsigned long txerrtotal;
556 unsigned long txerrbytestotal;
557 unsigned long txerrmulticast;
558 unsigned long txerrbroadcast;
559 unsigned long txerrunicast;
560 unsigned long txretrycount;
561 unsigned long txfeedbackretry;
563 unsigned long slide_signal_strength[100];
564 unsigned long slide_evm[100];
565 /* For recording sliding window's RSSI value */
566 unsigned long slide_rssi_total;
567 /* For recording sliding window's EVM value */
568 unsigned long slide_evm_total;
569 /* Transformed in dbm. Beautified signal strength for UI, not correct */
570 long signal_strength;
572 long last_signal_strength_inpercent;
573 /* Correct smoothed ss in dbm, only used in driver
574 * to report real power now
576 long recv_signal_power;
577 u8 rx_rssi_percentage[4];
578 u8 rx_evm_percentage[2];
580 rt_tx_rahis_t txrate;
581 /* For beacon RSSI */
582 u32 Slide_Beacon_pwdb[100];
583 u32 Slide_Beacon_Total;
584 RT_SMOOTH_DATA_4RF cck_adc_pwdb;
586 u32 CurrentShowTxate;
589 /* Bandwidth Offset */
590 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
591 #define HAL_PRIME_CHNL_OFFSET_LOWER 1
592 #define HAL_PRIME_CHNL_OFFSET_UPPER 2
594 typedef struct ChnlAccessSetting {
601 } *PCHANNEL_ACCESS_SETTING, CHANNEL_ACCESS_SETTING;
603 typedef struct _BB_REGISTER_DEFINITION {
604 /* set software control: 0x870~0x877 [8 bytes] */
606 /* readback data: 0x8e0~0x8e7 [8 bytes] */
608 /* output data: 0x860~0x86f [16 bytes] */
610 /* output enable: 0x860~0x86f [16 bytes] */
612 /* LSSI data: 0x840~0x84f [16 bytes] */
614 /* BB Band Select: 0x878~0x87f [8 bytes] */
616 /* Tx gain stage: 0x80c~0x80f [4 bytes] */
618 /* wire parameter control1: 0x820~0x823, 0x828~0x82b,
619 * 0x830~0x833, 0x838~0x83b [16 bytes]
622 /* wire parameter control2: 0x824~0x827, 0x82c~0x82f,
623 * 0x834~0x837, 0x83c~0x83f [16 bytes]
626 /* Tx Rx antenna control: 0x858~0x85f [16 bytes] */
628 /* AGC parameter control1: 0xc50~0xc53, 0xc58~0xc5b,
629 * 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
632 /* AGC parameter control2: 0xc54~0xc57, 0xc5c~0xc5f,
633 * 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
636 /* OFDM Rx IQ imbalance matrix: 0xc14~0xc17, 0xc1c~0xc1f,
637 * 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
640 /* Rx IQ DC offset and Rx digital filter, Rx DC notch filter:
641 * 0xc10~0xc13, 0xc18~0xc1b,
642 * 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
645 /* OFDM Tx IQ imbalance matrix: 0xc80~0xc83, 0xc88~0xc8b,
646 * 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
649 /* Tx IQ DC Offset and Tx DFIR type:
650 * 0xc84~0xc87, 0xc8c~0xc8f,
651 * 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
654 /* LSSI RF readback data: 0x8a0~0x8af [16 bytes] */
656 } BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
658 typedef enum _RT_RF_TYPE_819xU {
664 } RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
666 /* 2007/10/08 MH Define RATR state. */
667 enum dynamic_ratr_state {
668 DM_RATR_STA_HIGH = 0,
669 DM_RATR_STA_MIDDLE = 1,
674 typedef struct _rate_adaptive {
675 u8 rate_adaptive_disabled;
676 enum dynamic_ratr_state ratr_state;
679 u32 high_rssi_thresh_for_ra;
680 u32 high2low_rssi_thresh_for_ra;
681 u8 low2high_rssi_thresh_for_ra40M;
682 u32 low_rssi_thresh_for_ra40M;
683 u8 low2high_rssi_thresh_for_ra20M;
684 u32 low_rssi_thresh_for_ra20M;
685 u32 upper_rssi_threshold_ratr;
686 u32 middle_rssi_threshold_ratr;
687 u32 low_rssi_threshold_ratr;
688 u32 low_rssi_threshold_ratr_40M;
689 u32 low_rssi_threshold_ratr_20M;
692 u32 ping_rssi_thresh_for_ra;
695 } rate_adaptive, *prate_adaptive;
697 #define TxBBGainTableLength 37
698 #define CCKTxBBGainTableLength 23
700 typedef struct _txbbgain_struct {
701 long txbb_iq_amplifygain;
703 } txbbgain_struct, *ptxbbgain_struct;
705 typedef struct _ccktxbbgain_struct {
706 /* The value is from a22 to a29, one byte one time is much safer */
707 u8 ccktxbb_valuearray[8];
708 } ccktxbbgain_struct, *pccktxbbgain_struct;
710 typedef struct _init_gain {
717 } init_gain, *pinit_gain;
719 typedef struct _phy_ofdm_rx_status_report_819xusb {
733 } phy_sts_ofdm_819xusb_t;
735 typedef struct _phy_cck_rx_status_report_819xusb {
736 /* For CCK rate descriptor. This is an unsigned 8:1 variable.
737 * LSB bit presend 0.5. And MSB 7 bts presend a signed value.
738 * Range from -64~+63.5.
743 } phy_sts_cck_819xusb_t;
745 struct phy_ofdm_rx_status_rxsc_sgien_exintfflag {
752 typedef enum _RT_CUSTOMER_ID {
754 RT_CID_8187_ALPHA0 = 1,
755 RT_CID_8187_SERCOMM_PS = 2,
756 RT_CID_8187_HW_LED = 3,
757 RT_CID_8187_NETGEAR = 4,
759 RT_CID_819x_CAMEO = 6,
760 RT_CID_819x_RUNTOP = 7,
761 RT_CID_819x_Senao = 8,
763 RT_CID_819x_Netcore = 10,
764 RT_CID_Nettronix = 11,
767 } RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
770 * ==========================================================================
772 * ==========================================================================
775 typedef enum _LED_STRATEGY_8190 {
776 SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
777 SW_LED_MODE1, /* SW control for PCI Express */
778 SW_LED_MODE2, /* SW control for Cameo. */
779 SW_LED_MODE3, /* SW control for RunTop. */
780 SW_LED_MODE4, /* SW control for Netcore. */
781 /* HW control 2 LEDs, LED0 and LED1 (4 different control modes) */
783 } LED_STRATEGY_8190, *PLED_STRATEGY_8190;
785 typedef enum _RESET_TYPE {
786 RESET_TYPE_NORESET = 0x00,
787 RESET_TYPE_NORMAL = 0x01,
788 RESET_TYPE_SILENT = 0x02
791 /* The simple tx command OP code. */
792 typedef enum _tag_TxCmd_Config_Index {
793 TXCMD_TXRA_HISTORY_CTRL = 0xFF900000,
794 TXCMD_RESET_TX_PKT_BUFF = 0xFF900001,
795 TXCMD_RESET_RX_PKT_BUFF = 0xFF900002,
796 TXCMD_SET_TX_DURATION = 0xFF900003,
797 TXCMD_SET_RX_RSSI = 0xFF900004,
798 TXCMD_SET_TX_PWR_TRACKING = 0xFF900005,
803 VERSION_819XU_A, // A-cut
804 VERSION_819XU_B, // B-cut
805 VERSION_819XU_C,// C-cut
808 //added for different RF type
814 typedef struct r8192_priv {
815 struct usb_device *udev;
816 /* For maintain info from eeprom */
820 u8 eeprom_CustomerID;
821 u8 eeprom_ChannelPlan;
822 RT_CUSTOMER_ID CustomerID;
823 LED_STRATEGY_8190 LedStrategy;
824 u8 txqueue_to_outpipemap[9];
826 struct ieee80211_device *ieee80211;
828 /* O: rtl8192, 1: rtl8185 V B/C, 2: rtl8185 V D */
830 /* If TCR reports card V B/C, this discriminates */
831 enum version_819xu card_8192_version;
834 PCI, MINIPCI, CARDBUS, USB
837 short plcp_preamble_mode;
849 /* If 1, allow bad crc frame, reception in monitor mode */
852 struct mutex wx_mutex;
854 enum rt_rf_type rf_type; /* 0: 1T2R, 1: 2T4R */
855 RT_RF_TYPE_819xU rf_chip;
857 short (*rf_set_sens)(struct net_device *dev, short sens);
858 u8 (*rf_set_chan)(struct net_device *dev, u8 ch);
859 void (*rf_close)(struct net_device *dev);
860 void (*rf_init)(struct net_device *dev);
864 struct iw_statistics wstats;
868 struct urb **rx_cmd_urb;
872 #ifdef THOMAS_TASKLET
873 atomic_t irt_counter; /* count for irq_rx_tasklet */
875 #ifdef JACKSON_NEW_RX
876 struct sk_buff **pp_rxskb;
880 struct sk_buff_head rx_queue;
881 struct sk_buff_head skb_queue;
882 struct work_struct qos_activate;
884 atomic_t tx_pending[0x10]; /* UART_PRIORITY + 1 */
886 struct tasklet_struct irq_rx_tasklet;
887 struct urb *rxurb_task;
889 /* Tx Related variables */
893 u8 RegCWinMin; /* For turbo mode CW adaptive */
895 u32 LastRxDescTSFHigh;
896 u32 LastRxDescTSFLow;
898 /* Rx Related variables */
899 u16 EarlyRxThreshold;
909 struct ChnlAccessSetting ChannelAccessSetting;
910 struct work_struct reset_wq;
912 /**********************************************************/
918 bool bCurrentRxAggrEnable;
919 enum rf_op_type Rf_Mode; /* For Firmware RF -R/W switch */
920 prt_firmware pFirmware;
921 rtl819xUsb_loopback_e LoopbackMode;
922 u16 EEPROMTxPowerDiff;
923 u8 EEPROMThermalMeter;
927 u8 EEPROMTxPowerLevelCCK; /* CCK channel 1~14 */
928 u8 EEPROMTxPowerLevelCCK_V1[3];
929 u8 EEPROMTxPowerLevelOFDM24G[3]; /* OFDM 2.4G channel 1~14 */
930 u8 EEPROMTxPowerLevelOFDM5G[24]; /* OFDM 5G */
933 BB_REGISTER_DEFINITION_T PHYRegDef[4]; /* Radio A/B/C/D */
934 /* Read/write are allow for following hardware information variables */
935 u32 MCSTxPowerLevelOriginalOffset[6];
936 u32 CCKTxPowerLevelOriginalOffset;
937 u8 TxPowerLevelCCK[14]; /* CCK channel 1~14 */
938 u8 TxPowerLevelOFDM24G[14]; /* OFDM 2.4G channel 1~14 */
939 u8 TxPowerLevelOFDM5G[14]; /* OFDM 5G */
942 u8 AntennaTxPwDiff[2]; /* Antenna gain offset, 0: B, 1: C, 2: D */
944 u8 ThermalMeter[2]; /* index 0: RFIC0, index 1: RFIC1 */
947 /* Use to calculate PWBD */
949 long undecorated_smoothed_pwdb;
951 /* For set channel */
955 u8 SetBWModeInProgress;
956 enum ht_channel_width CurrentChannelBW;
958 /* 8190 40MHz mode */
959 /* Control channel sub-carrier */
961 /* Test for shorten RF configuration time.
962 * We save RF reg0 in this variable to reduce RF reading.
966 bool brfpath_rxenable[4];
968 bool SetRFPowerStateInProgress;
969 struct timer_list watch_dog_timer;
971 /* For dynamic mechanism */
972 /* Tx Power Control for Near/Far Range */
973 bool bdynamic_txpower;
974 bool bDynamicTxHighPower;
975 bool bDynamicTxLowPower;
976 bool bLastDTPFlag_High;
977 bool bLastDTPFlag_Low;
979 bool bstore_last_dtpflag;
980 /* Define to discriminate on High power State or
981 * on sitesurvey to change Tx gain index
983 bool bstart_txctrl_bydtp;
984 rate_adaptive rate_adaptive;
986 * OPEN/CLOSE TX POWER TRACKING
988 txbbgain_struct txbbgain_table[TxBBGainTableLength];
989 u8 txpower_count; /* For 6 sec do tracking again */
990 bool btxpower_trackingInit;
993 /* CCK TX Power Tracking */
994 ccktxbbgain_struct cck_txbbgain_table[CCKTxBBGainTableLength];
995 ccktxbbgain_struct cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
996 u8 rfa_txpowertrackingindex;
997 u8 rfa_txpowertrackingindex_real;
998 u8 rfa_txpowertracking_default;
999 u8 rfc_txpowertrackingindex;
1000 u8 rfc_txpowertrackingindex_real;
1002 s8 cck_present_attenuation;
1003 u8 cck_present_attenuation_20Mdefault;
1004 u8 cck_present_attenuation_40Mdefault;
1005 s8 cck_present_attenuation_difference;
1006 bool btxpower_tracking;
1008 bool btxpowerdata_readfromEEPORM;
1010 init_gain initgain_backup;
1011 u8 DefaultInitialGain[4];
1012 /* For EDCA Turbo mode */
1013 bool bis_any_nonbepkts;
1014 bool bcurrent_turbo_EDCA;
1015 bool bis_cur_rdlstate;
1016 struct timer_list fsync_timer;
1017 bool bfsync_processing; /* 500ms Fsync timer is active or not */
1019 u32 rateCountDiffRecord;
1020 u32 ContinueDiffCount;
1025 u8 framesyncMonitor;
1027 u8 nrxAMPDU_aggr_num;
1034 u32 txpower_checkcnt;
1035 u32 txpower_tracking_callback_cnt;
1036 u8 thermal_read_val[40];
1037 u8 thermal_readback_index;
1038 u32 ccktxpower_adjustcnt_not_ch14;
1039 u32 ccktxpower_adjustcnt_ch14;
1040 u8 tx_fwinfo_force_subcarriermode;
1041 u8 tx_fwinfo_force_subcarrierval;
1042 /* For silent reset */
1043 RESET_TYPE ResetProgress;
1044 bool bForcedSilentReset;
1045 bool bDisableNormalResetCheck;
1048 int IrpPendingCount;
1049 bool bResetInProgress;
1051 u8 InitialGainOperateType;
1055 /* Define work item */
1057 struct delayed_work update_beacon_wq;
1058 struct delayed_work watch_dog_wq;
1059 struct delayed_work txpower_tracking_wq;
1060 struct delayed_work rfpath_check_wq;
1061 struct delayed_work gpio_change_rf_wq;
1062 struct delayed_work initialgain_operate_wq;
1063 struct workqueue_struct *priv_wq;
1068 BULK_PRIORITY = 0x01,
1091 bool init_firmware(struct net_device *dev);
1092 short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1093 short rtl8192_tx(struct net_device *dev, struct sk_buff *skb);
1095 int read_nic_byte(struct net_device *dev, int x, u8 *data);
1096 int read_nic_byte_E(struct net_device *dev, int x, u8 *data);
1097 int read_nic_dword(struct net_device *dev, int x, u32 *data);
1098 int read_nic_word(struct net_device *dev, int x, u16 *data);
1099 int write_nic_byte(struct net_device *dev, int x, u8 y);
1100 int write_nic_byte_E(struct net_device *dev, int x, u8 y);
1101 int write_nic_word(struct net_device *dev, int x, u16 y);
1102 int write_nic_dword(struct net_device *dev, int x, u32 y);
1103 void force_pci_posting(struct net_device *dev);
1105 void rtl8192_rtx_disable(struct net_device *dev);
1106 void rtl8192_rx_enable(struct net_device *dev);
1108 void rtl8192_update_msr(struct net_device *dev);
1109 int rtl8192_down(struct net_device *dev);
1110 int rtl8192_up(struct net_device *dev);
1111 void rtl8192_commit(struct net_device *dev);
1112 void rtl8192_set_chan(struct net_device *dev, short ch);
1113 void rtl8192_set_rxconf(struct net_device *dev);
1114 void rtl819xusb_beacon_tx(struct net_device *dev, u16 tx_rate);
1116 void EnableHWSecurityConfig8192(struct net_device *dev);
1117 void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent);