1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
5 * Contact Information: wlanfae <wlanfae@realtek.com>
7 #ifndef _RTL819XU_HTTYPE_H_
8 #define _RTL819XU_HTTYPE_H_
10 #define MIMO_PS_STATIC 0
14 enum ht_channel_width {
15 HT_CHANNEL_WIDTH_20 = 0,
16 HT_CHANNEL_WIDTH_20_40 = 1,
19 enum ht_extchnl_offset {
20 HT_EXTCHNL_OFFSET_NO_EXT = 0,
21 HT_EXTCHNL_OFFSET_UPPER = 1,
22 HT_EXTCHNL_OFFSET_NO_DEF = 2,
23 HT_EXTCHNL_OFFSET_LOWER = 3,
43 u8 MaxRxAMPDUFactor:2;
63 u8 RecommemdedTxWidth:1;
66 u8 SrvIntGranularity:3;
78 u8 LSigTxopProtectFull:1;
93 HT_AGG_FORCE_ENABLE = 1,
94 HT_AGG_FORCE_DISABLE = 2,
98 struct rt_hi_throughput {
100 u8 bCurrentHTSupport;
114 enum ht_spec_ver ePeerHTSpecVer;
117 struct ht_capab_ele SelfHTCap;
118 struct ht_info_ele SelfHTInfo;
121 u8 PeerHTInfoBuf[32];
126 u8 bCurrent_AMSDU_Support;
127 u16 nCurrent_AMSDU_MaxSize;
130 u8 bCurrentAMPDUEnable;
132 u8 CurrentAMPDUFactor;
134 u8 CurrentMPDUDensity;
136 enum ht_aggre_mode ForcedAMPDUMode;
137 u8 ForcedAMPDUFactor;
138 u8 ForcedMPDUDensity;
140 enum ht_aggre_mode ForcedAMSDUMode;
141 u16 ForcedAMSDUMaxSize;
150 enum ht_extchnl_offset CurSTAExtChnlOffset;
157 u8 bRegRT2RTAggregation;
159 u8 bCurrentRT2RTAggregation;
160 u8 bCurrentRT2RTLongSlotTime;
161 u8 szRT2RTAggBuffer[10];
163 u8 bRegRxReorderEnable;
164 u8 bCurRxReorderEnable;
166 u8 RxReorderPendingTime;
167 u16 RxReorderDropCounter;
184 u8 bd_ht_cap_buf[32];
186 u8 bd_ht_info_buf[32];
189 enum ht_spec_ver bd_ht_spec_ver;
190 enum ht_channel_width bd_bandwidth;
192 u8 bd_rt2rt_aggregation;
193 u8 bd_rt2rt_long_slot_time;
198 extern u8 MCS_FILTER_ALL[16];
199 extern u8 MCS_FILTER_1SS[16];
201 #define RATE_ADPT_1SS_MASK 0xFF
202 #define RATE_ADPT_2SS_MASK 0xF0
203 #define RATE_ADPT_MCS32_MASK 0x01
213 HT_IOT_PEER_UNKNOWN = 0,
214 HT_IOT_PEER_REALTEK = 1,
215 HT_IOT_PEER_REALTEK_92SE = 2,
216 HT_IOT_PEER_BROADCOM = 3,
217 HT_IOT_PEER_RALINK = 4,
218 HT_IOT_PEER_ATHEROS = 5,
219 HT_IOT_PEER_CISCO = 6,
220 HT_IOT_PEER_MARVELL = 7,
221 HT_IOT_PEER_92U_SOFTAP = 8,
222 HT_IOT_PEER_SELF_SOFTAP = 9,
223 HT_IOT_PEER_AIRGO = 10,
224 HT_IOT_PEER_MAX = 11,
228 HT_IOT_ACT_TX_USE_AMSDU_4K = 0x00000001,
229 HT_IOT_ACT_TX_USE_AMSDU_8K = 0x00000002,
230 HT_IOT_ACT_DISABLE_MCS14 = 0x00000004,
231 HT_IOT_ACT_DISABLE_MCS15 = 0x00000008,
232 HT_IOT_ACT_DISABLE_ALL_2SS = 0x00000010,
233 HT_IOT_ACT_DISABLE_EDCA_TURBO = 0x00000020,
234 HT_IOT_ACT_MGNT_USE_CCK_6M = 0x00000040,
235 HT_IOT_ACT_CDD_FSYNC = 0x00000080,
236 HT_IOT_ACT_PURE_N_MODE = 0x00000100,
237 HT_IOT_ACT_FORCED_CTS2SELF = 0x00000200,
238 HT_IOT_ACT_FORCED_RTS = 0x00000400,
239 HT_IOT_ACT_AMSDU_ENABLE = 0x00000800,
240 HT_IOT_ACT_REJECT_ADDBA_REQ = 0x00001000,
241 HT_IOT_ACT_ALLOW_PEER_AGG_ONE_PKT = 0x00002000,
242 HT_IOT_ACT_EDCA_BIAS_ON_RX = 0x00004000,
244 HT_IOT_ACT_HYBRID_AGGREGATION = 0x00010000,
245 HT_IOT_ACT_DISABLE_SHORT_GI = 0x00020000,
246 HT_IOT_ACT_DISABLE_HIGH_POWER = 0x00040000,
247 HT_IOT_ACT_DISABLE_TX_40_MHZ = 0x00080000,
248 HT_IOT_ACT_TX_NO_AGGREGATION = 0x00100000,
249 HT_IOT_ACT_DISABLE_TX_2SS = 0x00200000,
251 HT_IOT_ACT_MID_HIGHPOWER = 0x00400000,
252 HT_IOT_ACT_NULL_DATA_POWER_SAVING = 0x00800000,
254 HT_IOT_ACT_DISABLE_CCK_RATE = 0x01000000,
255 HT_IOT_ACT_FORCED_ENABLE_BE_TXOP = 0x02000000,
256 HT_IOT_ACT_WA_IOT_Broadcom = 0x04000000,
258 HT_IOT_ACT_DISABLE_RX_40MHZ_SHORT_GI = 0x08000000,
263 HT_IOT_RAFUNC_DISABLE_ALL = 0x00,
264 HT_IOT_RAFUNC_PEER_1R = 0x01,
265 HT_IOT_RAFUNC_TX_AMSDU = 0x02,
268 enum rt_ht_capability {
269 RT_HT_CAP_USE_TURBO_AGGR = 0x01,
270 RT_HT_CAP_USE_LONG_PREAMBLE = 0x02,
271 RT_HT_CAP_USE_AMPDU = 0x04,
272 RT_HT_CAP_USE_WOW = 0x8,
273 RT_HT_CAP_USE_SOFTAP = 0x10,
274 RT_HT_CAP_USE_92SE = 0x20,