drivers/staging/rtl8188eu/include/rtl8188e_hal.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   5  *
   6  ******************************************************************************/
   7 #ifndef __RTL8188E_HAL_H__
   8 #define __RTL8188E_HAL_H__
   9
  10 /* include HAL Related header after HAL Related compiling flags */
  11 #include "rtl8188e_spec.h"
  12 #include "hal8188e_phy_reg.h"
  13 #include "hal8188e_phy_cfg.h"
  14 #include "rtl8188e_dm.h"
  15 #include "rtl8188e_recv.h"
  16 #include "rtl8188e_xmit.h"
  17 #include "rtl8188e_cmd.h"
  18 #include "pwrseq.h"
  19 #include "rtw_efuse.h"
  20 #include "rtw_sreset.h"
  21 #include "odm_precomp.h"
  22
  23 /*  Fw Array */
  24 #define Rtl8188E_FwImageArray           Rtl8188EFwImgArray
  25 #define Rtl8188E_FWImgArrayLength       Rtl8188EFWImgArrayLength
  26
  27 #define RTL8188E_FW_UMC_IMG                     "rtl8188E\\rtl8188efw.bin"
  28 #define RTL8188E_PHY_REG                        "rtl8188E\\PHY_REG_1T.txt"
  29 #define RTL8188E_PHY_RADIO_A                    "rtl8188E\\radio_a_1T.txt"
  30 #define RTL8188E_PHY_RADIO_B                    "rtl8188E\\radio_b_1T.txt"
  31 #define RTL8188E_AGC_TAB                        "rtl8188E\\AGC_TAB_1T.txt"
  32 #define RTL8188E_PHY_MACREG                     "rtl8188E\\MAC_REG.txt"
  33 #define RTL8188E_PHY_REG_PG                     "rtl8188E\\PHY_REG_PG.txt"
  34 #define RTL8188E_PHY_REG_MP                     "rtl8188E\\PHY_REG_MP.txt"
  35
  36 /* RTL8188E Power Configuration CMDs for USB/SDIO interfaces */
  37 #define Rtl8188E_NIC_PWR_ON_FLOW                rtl8188E_power_on_flow
  38 #define Rtl8188E_NIC_RF_OFF_FLOW                rtl8188E_radio_off_flow
  39 #define Rtl8188E_NIC_DISABLE_FLOW               rtl8188E_card_disable_flow
  40 #define Rtl8188E_NIC_ENABLE_FLOW                rtl8188E_card_enable_flow
  41 #define Rtl8188E_NIC_SUSPEND_FLOW               rtl8188E_suspend_flow
  42 #define Rtl8188E_NIC_RESUME_FLOW                rtl8188E_resume_flow
  43 #define Rtl8188E_NIC_PDN_FLOW                   rtl8188E_hwpdn_flow
  44 #define Rtl8188E_NIC_LPS_ENTER_FLOW             rtl8188E_enter_lps_flow
  45 #define Rtl8188E_NIC_LPS_LEAVE_FLOW             rtl8188E_leave_lps_flow
  46
  47 #define DRVINFO_SZ      4 /*  unit is 8bytes */
  48 #define PageNum_128(_Len)       (u32)(((_Len) >> 7) + ((_Len) & 0x7F ? 1 : 0))
  49
  50 /*  download firmware related data structure */
  51 #define FW_8188E_SIZE                   0x4000 /* 16384,16k */
  52 #define FW_8188E_START_ADDRESS          0x1000
  53 #define FW_8188E_END_ADDRESS            0x1FFF /* 0x5FFF */
  54
  55 #define MAX_PAGE_SIZE                   4096    /*  @ page : 4k bytes */
  56
  57 #define IS_FW_HEADER_EXIST(_pFwHdr)                              \
  58         ((le16_to_cpu(_pFwHdr->signature) & 0xFFF0) == 0x92C0 || \
  59         (le16_to_cpu(_pFwHdr->signature) & 0xFFF0) == 0x88C0 ||  \
  60         (le16_to_cpu(_pFwHdr->signature) & 0xFFF0) == 0x2300 ||  \
  61         (le16_to_cpu(_pFwHdr->signature) & 0xFFF0) == 0x88E0)
  62
  63 #define DRIVER_EARLY_INT_TIME           0x05
  64 #define BCN_DMA_ATIME_INT_TIME          0x02
  65
  66 enum usb_rx_agg_mode {
  67         USB_RX_AGG_DISABLE,
  68         USB_RX_AGG_DMA,
  69         USB_RX_AGG_USB,
  70         USB_RX_AGG_MIX
  71 };
  72
  73 #define MAX_RX_DMA_BUFFER_SIZE_88E                              \
  74       0x2400 /* 9k for 88E nornal chip , MaxRxBuff=10k-max(TxReportSize(64*8),
  75               * WOLPattern(16*24))
  76               */
  77
  78 #define MAX_TX_REPORT_BUFFER_SIZE               0x0400 /*  1k */
  79
  80 /*  BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */
  81 #define MAX_TX_QUEUE                    9
  82
  83 #define TX_SELE_HQ                      BIT(0)          /*  High Queue */
  84 #define TX_SELE_LQ                      BIT(1)          /*  Low Queue */
  85 #define TX_SELE_NQ                      BIT(2)          /*  Normal Queue */
  86
  87 /*  Note: We will divide number of page equally for each queue other
  88  *  than public queue!
  89  */
  90 /*  22k = 22528 bytes = 176 pages (@page =  128 bytes) */
  91 /*  must reserved about 7 pages for LPS =>  176-7 = 169 (0xA9) */
  92 /*  2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS
  93  *  null-data
  94  */
  95
  96 #define TX_TOTAL_PAGE_NUMBER_88E                0xA9/*   169 (21632=> 21k) */
  97
  98 #define TX_PAGE_BOUNDARY_88E (TX_TOTAL_PAGE_NUMBER_88E + 1)
  99
 100 /* Note: For Normal Chip Setting ,modify later */
 101 #define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER                 \
 102         TX_TOTAL_PAGE_NUMBER_88E  /* 0xA9 , 0xb0=>176=>22k */
 103 #define WMM_NORMAL_TX_PAGE_BOUNDARY_88E                 \
 104         (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1) /* 0xA9 */
 105
 106 /* Chip specific */
 107 #define CHIP_BONDING_IDENTIFIER(_value) (((_value) >> 22) & 0x3)
 108 #define CHIP_BONDING_92C_1T2R   0x1
 109 #define CHIP_BONDING_88C_USB_MCARD      0x2
 110 #define CHIP_BONDING_88C_USB_HP 0x1
 111 #include "HalVerDef.h"
 112 #include "hal_com.h"
 113
 114 /* Channel Plan */
 115 enum ChannelPlan {
 116         CHPL_FCC        = 0,
 117         CHPL_IC         = 1,
 118         CHPL_ETSI       = 2,
 119         CHPL_SPA        = 3,
 120         CHPL_FRANCE     = 4,
 121         CHPL_MKK        = 5,
 122         CHPL_MKK1       = 6,
 123         CHPL_ISRAEL     = 7,
 124         CHPL_TELEC      = 8,
 125         CHPL_GLOBAL     = 9,
 126         CHPL_WORLD      = 10,
 127 };
 128
 129 struct txpowerinfo24g {
 130         u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
 131         u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
 132         /* If only one tx, only BW20 and OFDM are used. */
 133         s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 134         s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 135         s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 136         s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 137 };
 138
 139 #define EFUSE_REAL_CONTENT_LEN          512
 140 #define EFUSE_MAX_SECTION               16
 141 #define EFUSE_IC_ID_OFFSET              506 /* For some inferior IC purpose*/
 142 #define AVAILABLE_EFUSE_ADDR(addr)      (addr < EFUSE_REAL_CONTENT_LEN)
 143 /*  To prevent out of boundary programming case, */
 144 /*  leave 1byte and program full section */
 145 /*  9bytes + 1byt + 5bytes and pre 1byte. */
 146 /*  For worst case: */
 147 /*  | 1byte|----8bytes----|1byte|--5bytes--| */
 148 /*  |         |            Reserved(14bytes)          | */
 149
 150 /*  PG data exclude header, dummy 6 bytes from CP test and reserved 1byte. */
 151 #define EFUSE_OOB_PROTECT_BYTES                 15
 152
 153 #define         HWSET_MAX_SIZE_88E              512
 154
 155 #define         EFUSE_REAL_CONTENT_LEN_88E      256
 156 #define         EFUSE_MAP_LEN_88E               512
 157 #define EFUSE_MAP_LEN                   EFUSE_MAP_LEN_88E
 158 #define         EFUSE_MAX_SECTION_88E           64
 159 #define         EFUSE_MAX_WORD_UNIT_88E         4
 160 #define         EFUSE_IC_ID_OFFSET_88E          506
 161 #define         AVAILABLE_EFUSE_ADDR_88E(addr)                  \
 162         (addr < EFUSE_REAL_CONTENT_LEN_88E)
 163 /*  To prevent out of boundary programming case, leave 1byte and program
 164  *  full section
 165  */
 166 /*  9bytes + 1byt + 5bytes and pre 1byte. */
 167 /*  For worst case: */
 168 /*  | 2byte|----8bytes----|1byte|--7bytes--| 92D */
 169 /*  PG data exclude header, dummy 7 bytes from CP test and reserved 1byte. */
 170 #define         EFUSE_OOB_PROTECT_BYTES_88E     18
 171 #define         EFUSE_PROTECT_BYTES_BANK_88E    16
 172
 173 /* EFUSE for BT definition */
 174 #define EFUSE_BT_REAL_CONTENT_LEN       1536    /*  512*3 */
 175 #define EFUSE_BT_MAP_LEN                1024    /*  1k bytes */
 176 #define EFUSE_BT_MAX_SECTION            128     /*  1024/8 */
 177
 178 #define EFUSE_PROTECT_BYTES_BANK        16
 179
 180 struct hal_data_8188e {
 181         struct HAL_VERSION      VersionID;
 182         u16     CustomerID;
 183         u16     FirmwareVersion;
 184         u16     FirmwareVersionRev;
 185         u16     FirmwareSubVersion;
 186         u16     FirmwareSignature;
 187         u8      PGMaxGroup;
 188         /* current WIFI_PHY values */
 189         u32     ReceiveConfig;
 190         enum wireless_mode CurrentWirelessMode;
 191         enum ht_channel_width CurrentChannelBW;
 192         u8      CurrentChannel;
 193         u8      nCur40MhzPrimeSC;/*  Control channel sub-carrier */
 194
 195         u16     BasicRateSet;
 196
 197         u8      BoardType;
 198
 199         /*  EEPROM setting. */
 200         u16     EEPROMVID;
 201         u16     EEPROMPID;
 202         u16     EEPROMSVID;
 203         u16     EEPROMSDID;
 204         u8      EEPROMCustomerID;
 205         u8      EEPROMSubCustomerID;
 206         u8      EEPROMVersion;
 207         u8      EEPROMRegulatory;
 208
 209         u8      bTXPowerDataReadFromEEPORM;
 210         u8      EEPROMThermalMeter;
 211         u8      bAPKThermalMeterIgnore;
 212
 213         bool    EepromOrEfuse;
 214         /* 92C:256bytes, 88E:512bytes, we use union set (512bytes) */
 215         u8      EfuseMap[2][HWSET_MAX_SIZE_512];
 216         u8      EfuseUsedPercentage;
 217         struct efuse_hal        EfuseHal;
 218
 219         u8      Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
 220         u8      Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
 221         /* If only one tx, only BW20 and OFDM are used. */
 222         s8      CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 223         s8      OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 224         s8      BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 225         s8      BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 226
 227         u8      TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 228         /*  For HT 40MHZ pwr */
 229         u8      TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 230         /*  For HT 40MHZ pwr */
 231         u8      TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 232         /*  HT 20<->40 Pwr diff */
 233         u8      TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 234         /*  For HT<->legacy pwr diff */
 235         u8      TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 236         /*  For power group */
 237         u8      PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 238         u8      PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 239
 240         u8      LegacyHTTxPowerDiff;/*  Legacy to HT rate power diff */
 241         /*  The current Tx Power Level */
 242         u8      CurrentCckTxPwrIdx;
 243         u8      CurrentOfdm24GTxPwrIdx;
 244         u8      CurrentBW2024GTxPwrIdx;
 245         u8      CurrentBW4024GTxPwrIdx;
 246
 247         /*  Read/write are allow for following hardware information variables */
 248         u8      framesync;
 249         u32     framesyncC34;
 250         u8      framesyncMonitor;
 251         u8      DefaultInitialGain[4];
 252         u8      pwrGroupCnt;
 253         u32     MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
 254         u32     CCKTxPowerLevelOriginalOffset;
 255
 256         u8      CrystalCap;
 257
 258         u32     AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
 259
 260         struct bb_reg_def PHYRegDef[4]; /* Radio A/B/C/D */
 261
 262         u32     RfRegChnlVal[2];
 263
 264         /* RDG enable */
 265         bool     bRDGEnable;
 266
 267         /* for host message to fw */
 268         u8      LastHMEBoxNum;
 269
 270         u8      RegTxPause;
 271         /*  Beacon function related global variable. */
 272         u32     RegBcnCtrlVal;
 273         u8      RegFwHwTxQCtrl;
 274         u8      RegReg542;
 275         u8      RegCR_1;
 276
 277         struct dm_priv  dmpriv;
 278         struct odm_dm_struct odmpriv;
 279         struct sreset_priv srestpriv;
 280
 281         u8      CurAntenna;
 282         u8      AntDivCfg;
 283         u8      TRxAntDivType;
 284
 285         u8      bDumpRxPkt;/* for debug */
 286         u8      bDumpTxPkt;/* for debug */
 287         u8      FwRsvdPageStartOffset; /* Reserve page start offset except
 288                                         *  beacon in TxQ.
 289                                         */
 290
 291         /*  2010/08/09 MH Add CU power down mode. */
 292         bool            pwrdown;
 293
 294         /*  Add for dual MAC  0--Mac0 1--Mac1 */
 295         u32     interfaceIndex;
 296
 297         u8      OutEpQueueSel;
 298         u8      OutEpNumber;
 299
 300         u16     EfuseUsedBytes;
 301
 302         /*  Auto FSM to Turn On, include clock, isolation, power control
 303          *  for MAC only
 304          */
 305         u8      bMacPwrCtrlOn;
 306
 307         u32     UsbBulkOutSize;
 308
 309         /*  Interrupt relatd register information. */
 310         u32     IntArray[3];/* HISR0,HISR1,HSISR */
 311         u32     IntrMask[3];
 312         u8      C2hArray[16];
 313         u8      UsbTxAggMode;
 314         u8      UsbTxAggDescNum;
 315         u16     HwRxPageSize;           /*  Hardware setting */
 316         u32     MaxUsbRxAggBlock;
 317
 318         enum usb_rx_agg_mode UsbRxAggMode;
 319         u8      UsbRxAggBlockCount;     /*  USB Block count. Block size is
 320                                          * 512-byte in high speed and 64-byte
 321                                          * in full speed
 322                                          */
 323         u8      UsbRxAggBlockTimeout;
 324         u8      UsbRxAggPageCount;      /*  8192C DMA page count */
 325         u8      UsbRxAggPageTimeout;
 326 };
 327
 328 void Hal_GetChnlGroup88E(u8 chnl, u8 *group);
 329
 330 /*  rtl8188e_hal_init.c */
 331 void _8051Reset88E(struct adapter *padapter);
 332 void rtl8188e_InitializeFirmwareVars(struct adapter *padapter);
 333
 334 s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy);
 335
 336 /*  EFuse */
 337 void Hal_InitPGData88E(struct adapter *padapter);
 338 void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo);
 339 void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *hwinfo,
 340                             bool AutoLoadFail);
 341
 342 void Hal_EfuseParseEEPROMVer88E(struct adapter *padapter, u8 *hwinfo,
 343                                 bool AutoLoadFail);
 344 void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo,
 345                                  bool AutoLoadFail);
 346 void Hal_EfuseParseCustomerID88E(struct adapter *padapter, u8 *hwinfo,
 347                                  bool AutoLoadFail);
 348 void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter, u8 *PROMContent,
 349                                  bool AutoLoadFail);
 350 void Hal_ReadThermalMeter_88E(struct adapter *dapter, u8 *PROMContent,
 351                               bool AutoloadFail);
 352 void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo,
 353                               bool AutoLoadFail);
 354 void Hal_EfuseParseBoardType88E(struct adapter *pAdapter, u8 *hwinfo,
 355                                 bool AutoLoadFail);
 356 void Hal_ReadPowerSavingMode88E(struct adapter *pAdapter, u8 *hwinfo,
 357                                 bool AutoLoadFail);
 358
 359 /*  register */
 360
 361 void rtl8188e_start_thread(struct adapter *padapter);
 362 void rtl8188e_stop_thread(struct adapter *padapter);
 363
 364 s32 iol_execute(struct adapter *padapter, u8 control);
 365 void iol_mode_enable(struct adapter *padapter, u8 enable);
 366 s32 rtl8188e_iol_efuse_patch(struct adapter *padapter);
 367 void rtw_cancel_all_timer(struct adapter *padapter);
 368
 369 #endif /* __RTL8188E_HAL_H__ */