drivers/staging/rtl8188eu/include/pwrseq.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   5  *
   6  ******************************************************************************/
   7
   8 #ifndef __HAL8188EPWRSEQ_H__
   9 #define __HAL8188EPWRSEQ_H__
  10
  11 #include "pwrseqcmd.h"
  12
  13 /*
  14  *      Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
  15  *      There are 6 HW Power States:
  16  *      0: POFF--Power Off
  17  *      1: PDN--Power Down
  18  *      2: CARDEMU--Card Emulation
  19  *      3: ACT--Active Mode
  20  *      4: LPS--Low Power State
  21  *      5: SUS--Suspend
  22  *
  23  *      The transition from different states are defined below
  24  *      TRANS_CARDEMU_TO_ACT
  25  *      TRANS_ACT_TO_CARDEMU
  26  *      TRANS_CARDEMU_TO_SUS
  27  *      TRANS_SUS_TO_CARDEMU
  28  *      TRANS_CARDEMU_TO_PDN
  29  *      TRANS_ACT_TO_LPS
  30  *      TRANS_LPS_TO_ACT
  31  *
  32  *      TRANS_END
  33  *
  34  *   PWR SEQ Version: rtl8188E_PwrSeq_V09.h
  35  */
  36 #define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS     10
  37 #define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS     10
  38 #define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS     10
  39 #define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS     10
  40 #define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS     10
  41 #define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS     10
  42 #define RTL8188E_TRANS_ACT_TO_LPS_STEPS         15
  43 #define RTL8188E_TRANS_LPS_TO_ACT_STEPS         15
  44 #define RTL8188E_TRANS_END_STEPS                1
  45
  46 #define RTL8188E_TRANS_CARDEMU_TO_ACT                                   \
  47         /* format
  48          * { offset, cut_msk, cmd, msk, value
  49          * },
  50          * comment here
  51          */                                                             \
  52         {0x0006, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
  53         /* wait till 0x04[17] = 1    power ready*/      \
  54         {0x0002, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0) | BIT(1), 0}, \
  55         /* 0x02[1:0] = 0        reset BB*/                              \
  56         {0x0026, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
  57         /*0x24[23] = 2b'01 schmit trigger */                            \
  58         {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), 0}, \
  59         /* 0x04[15] = 0 disable HWPDN (control by DRV)*/                \
  60         {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, \
  61         /*0x04[12:11] = 2b'00 disable WL suspend*/                      \
  62         {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
  63         /*0x04[8] = 1 polling until return 0*/                          \
  64         {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(0), 0}, \
  65         /*wait till 0x04[8] = 0*/                                       \
  66         {0x0023, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \
  67         /*LDO normal mode*/
  68
  69 #define RTL8188E_TRANS_ACT_TO_CARDEMU                                   \
  70         /* format
  71          * { offset, cut_msk, cmd, msk, value
  72          * },
  73          * comments here
  74          */                                                             \
  75         {0x001F, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, \
  76         /*0x1F[7:0] = 0 turn off RF*/                                   \
  77         {0x0023, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
  78         /*LDO Sleep mode*/                                              \
  79         {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
  80         /*0x04[9] = 1 turn off MAC by HW state machine*/                \
  81         {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(1), 0}, \
  82         /*wait till 0x04[9] = 0 polling until return 0 to disable*/
  83
  84 #define RTL8188E_TRANS_CARDEMU_TO_SUS                                   \
  85         /* format
  86          * { offset, cut_msk, cmd, msk,
  87          * value },
  88          * comments here
  89          */                                                             \
  90         {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \
  91         /* 0x04[12:11] = 2b'01enable WL suspend */                      \
  92         {0x0007, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, BIT(7)}, \
  93         /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
  94         {0x0041, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \
  95         /*Clear SIC_EN register 0x40[12] = 1'b0 */                      \
  96         {0xfe10, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
  97         /*Set USB suspend enable local register  0xfe10[4]=1 */
  98
  99 #define RTL8188E_TRANS_SUS_TO_CARDEMU                                   \
 100         /* format
 101          * { offset, cut_msk, cmd, msk,
 102          * value },
 103          * comments here
 104          */                                                             \
 105         {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \
 106         /*0x04[12:11] = 2b'01enable WL suspend*/
 107
 108 #define RTL8188E_TRANS_CARDEMU_TO_CARDDIS                               \
 109         /* format
 110          * { offset, cut_msk, cmd, msk,
 111          * value },
 112          * comments here
 113          */                                                             \
 114         {0x0026, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
 115         /*0x24[23] = 2b'01 schmit trigger */                            \
 116         {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \
 117         /*0x04[12:11] = 2b'01 enable WL suspend*/                       \
 118         {0x0007, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, \
 119         /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
 120         {0x0041, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \
 121         /*Clear SIC_EN register 0x40[12] = 1'b0 */                      \
 122         {0xfe10, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
 123         /*Set USB suspend enable local register  0xfe10[4]=1 */
 124
 125 #define RTL8188E_TRANS_CARDDIS_TO_CARDEMU                               \
 126         /* format
 127          * { offset, cut_msk, cmd, msk,
 128          * value },
 129          * comments here
 130          */                                                             \
 131         {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \
 132         /*0x04[12:11] = 2b'01enable WL suspend*/
 133
 134 #define RTL8188E_TRANS_CARDEMU_TO_PDN                                   \
 135         /* format
 136          * { offset, cut_msk, cmd, msk,
 137          * value },
 138          * comments here
 139          */                                                             \
 140         {0x0006, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), 0}, \
 141         /* 0x04[16] = 0*/                                               \
 142         {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
 143         /* 0x04[15] = 1*/
 144
 145 #define RTL8188E_TRANS_PDN_TO_CARDEMU                                   \
 146         /* format
 147          * { offset, cut_msk, cmd, msk,
 148          * value },
 149          * comments here
 150          */                                                             \
 151         {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), 0}, \
 152         /* 0x04[15] = 0*/
 153
 154 /* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */
 155 #define RTL8188E_TRANS_ACT_TO_LPS                                       \
 156         /* format
 157          * { offset, cut_msk, cmd, msk,
 158          * value },
 159          * comments here
 160          */                                                             \
 161         {0x0522, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
 162         {0x05F8, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \
 163         /*Should be zero if no packet is transmitting*/                 \
 164         {0x05F9, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \
 165         /*Should be zero if no packet is transmitting*/                 \
 166         {0x05FA, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \
 167         /*Should be zero if no packet is transmitting*/                 \
 168         {0x05FB, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \
 169         /*Should be zero if no packet is transmitting*/                 \
 170         {0x0002, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), 0}, \
 171         /*CCK and OFDM are disabled,and clock are gated*/               \
 172         {0x0002, PWR_CUT_ALL_MSK, PWR_CMD_DELAY, 0,     PWRSEQ_DELAY_US}, \
 173         /*Delay 1us*/ \
 174         {0x0100, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x3F}, \
 175         /*Reset MAC TRX*/ \
 176         {0x0101, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), 0}, \
 177         /*check if removed later*/\
 178         {0x0553, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(5), BIT(5)}, \
 179         /*Respond TxOK to scheduler*/
 180
 181 #define RTL8188E_TRANS_LPS_TO_ACT                                       \
 182         /* format
 183          * { offset, cut_msk, cmd, msk,
 184          * value },
 185          * comments here
 186          */                                                             \
 187         {0xFE58, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x84}, \
 188         /*USB RPWM*/    \
 189         {0x0002, PWR_CUT_ALL_MSK, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \
 190         /*Delay*/       \
 191         {0x0008, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \
 192         /* 0x08[4] = 0 switch TSF to 40M */                             \
 193         {0x0109, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(7), 0}, \
 194         /* Polling 0x109[7]=0  TSF in 40M */                            \
 195         {0x0029, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(6) | BIT(7), 0}, \
 196         /* 0x29[7:6] = 2b'00  enable BB clock */                        \
 197         {0x0101, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
 198         /* 0x101[1] = 1 */                                              \
 199         {0x0100, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0xFF}, \
 200         /* 0x100[7:0] = 0xFF enable WMAC TRX */                         \
 201         {0x0002, PWR_CUT_ALL_MSK, \
 202         PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \
 203         /* 0x02[1:0] = 2b'11 enable BB macro */                         \
 204         {0x0522, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, /*.  0x522 = 0*/
 205
 206 #define RTL8188E_TRANS_END                                              \
 207         /* format
 208          * { offset, cut_msk, cmd, msk,
 209          * value },
 210          * comments here
 211          */                                                             \
 212         {0xFFFF, PWR_CUT_ALL_MSK, PWR_CMD_END, 0, 0},
 213
 214 extern struct wl_pwr_cfg rtl8188E_power_on_flow
 215                 [RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];
 216 extern struct wl_pwr_cfg rtl8188E_radio_off_flow
 217                 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_END_STEPS];
 218 extern struct wl_pwr_cfg rtl8188E_card_disable_flow
 219                 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
 220                 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
 221                 RTL8188E_TRANS_END_STEPS];
 222 extern struct wl_pwr_cfg rtl8188E_card_enable_flow
 223                 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
 224                 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
 225                 RTL8188E_TRANS_END_STEPS];
 226 extern struct wl_pwr_cfg rtl8188E_suspend_flow[
 227                 RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
 228                 RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
 229                 RTL8188E_TRANS_END_STEPS];
 230 extern struct wl_pwr_cfg rtl8188E_resume_flow
 231                 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
 232                 RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
 233                 RTL8188E_TRANS_END_STEPS];
 234 extern struct wl_pwr_cfg rtl8188E_hwpdn_flow
 235                 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
 236                 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS];
 237 extern struct wl_pwr_cfg rtl8188E_enter_lps_flow
 238                 [RTL8188E_TRANS_ACT_TO_LPS_STEPS + RTL8188E_TRANS_END_STEPS];
 239 extern struct wl_pwr_cfg rtl8188E_leave_lps_flow
 240                 [RTL8188E_TRANS_LPS_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];
 241
 242 #endif /* __HAL8188EPWRSEQ_H__ */