drivers/staging/rtl8188eu/hal/phy.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   5  *
   6  ******************************************************************************/
   7 #define _RTL8188E_PHYCFG_C_
   8
   9 #include <osdep_service.h>
  10 #include <drv_types.h>
  11 #include <rtl8188e_hal.h>
  12 #include <rf.h>
  13 #include <phy.h>
  14
  15 #define MAX_PRECMD_CNT 16
  16 #define MAX_RFDEPENDCMD_CNT 16
  17 #define MAX_POSTCMD_CNT 16
  18
  19 #define MAX_DOZE_WAITING_TIMES_9x 64
  20
  21 static u32 cal_bit_shift(u32 bitmask)
  22 {
  23         u32 i;
  24
  25         for (i = 0; i <= 31; i++) {
  26                 if (((bitmask >> i) & 0x1) == 1)
  27                         break;
  28         }
  29         return i;
  30 }
  31
  32 u32 phy_query_bb_reg(struct adapter *adapt, u32 regaddr, u32 bitmask)
  33 {
  34         u32 original_value, bit_shift;
  35
  36         original_value = usb_read32(adapt, regaddr);
  37         bit_shift = cal_bit_shift(bitmask);
  38         return (original_value & bitmask) >> bit_shift;
  39 }
  40
  41 void phy_set_bb_reg(struct adapter *adapt, u32 regaddr, u32 bitmask, u32 data)
  42 {
  43         u32 original_value, bit_shift;
  44
  45         if (bitmask != bMaskDWord) { /* if not "double word" write */
  46                 original_value = usb_read32(adapt, regaddr);
  47                 bit_shift = cal_bit_shift(bitmask);
  48                 data = (original_value & (~bitmask)) | (data << bit_shift);
  49         }
  50
  51         usb_write32(adapt, regaddr, data);
  52 }
  53
  54 static u32 rf_serial_read(struct adapter *adapt,
  55                         enum rf_radio_path rfpath, u32 offset)
  56 {
  57         u32 ret = 0;
  58         struct bb_reg_def *phyreg = &adapt->HalData->PHYRegDef[rfpath];
  59         u32 tmplong, tmplong2;
  60         u8 rfpi_enable = 0;
  61
  62         offset &= 0xff;
  63
  64         tmplong = phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter2, bMaskDWord);
  65         if (rfpath == RF_PATH_A)
  66                 tmplong2 = tmplong;
  67         else
  68                 tmplong2 = phy_query_bb_reg(adapt, phyreg->rfHSSIPara2,
  69                                             bMaskDWord);
  70
  71         tmplong2 = (tmplong2 & (~bLSSIReadAddress)) |
  72                    (offset<<23) | bLSSIReadEdge;
  73
  74         phy_set_bb_reg(adapt, rFPGA0_XA_HSSIParameter2, bMaskDWord,
  75                        tmplong&(~bLSSIReadEdge));
  76         udelay(10);
  77
  78         phy_set_bb_reg(adapt, phyreg->rfHSSIPara2, bMaskDWord, tmplong2);
  79         udelay(100);
  80
  81         udelay(10);
  82
  83         if (rfpath == RF_PATH_A)
  84                 rfpi_enable = (u8)phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, BIT(8));
  85         else if (rfpath == RF_PATH_B)
  86                 rfpi_enable = (u8)phy_query_bb_reg(adapt, rFPGA0_XB_HSSIParameter1, BIT(8));
  87
  88         if (rfpi_enable)
  89                 ret = phy_query_bb_reg(adapt, phyreg->rfLSSIReadBackPi,
  90                                        bLSSIReadBackData);
  91         else
  92                 ret = phy_query_bb_reg(adapt, phyreg->rfLSSIReadBack,
  93                                        bLSSIReadBackData);
  94         return ret;
  95 }
  96
  97 static void rf_serial_write(struct adapter *adapt,
  98                             enum rf_radio_path rfpath, u32 offset,
  99                             u32 data)
 100 {
 101         u32 data_and_addr = 0;
 102         struct bb_reg_def *phyreg = &adapt->HalData->PHYRegDef[rfpath];
 103
 104         offset &= 0xff;
 105         data_and_addr = ((offset<<20) | (data&0x000fffff)) & 0x0fffffff;
 106         phy_set_bb_reg(adapt, phyreg->rf3wireOffset, bMaskDWord, data_and_addr);
 107 }
 108
 109 u32 rtw_hal_read_rfreg(struct adapter *adapt, enum rf_radio_path rf_path,
 110                      u32 reg_addr, u32 bit_mask)
 111 {
 112         u32 original_value, bit_shift;
 113
 114         original_value = rf_serial_read(adapt, rf_path, reg_addr);
 115         bit_shift =  cal_bit_shift(bit_mask);
 116         return (original_value & bit_mask) >> bit_shift;
 117 }
 118
 119 void phy_set_rf_reg(struct adapter *adapt, enum rf_radio_path rf_path,
 120                      u32 reg_addr, u32 bit_mask, u32 data)
 121 {
 122         u32 original_value, bit_shift;
 123
 124         /*  RF data is 12 bits only */
 125         if (bit_mask != bRFRegOffsetMask) {
 126                 original_value = rf_serial_read(adapt, rf_path, reg_addr);
 127                 bit_shift =  cal_bit_shift(bit_mask);
 128                 data = (original_value & (~bit_mask)) | (data << bit_shift);
 129         }
 130
 131         rf_serial_write(adapt, rf_path, reg_addr, data);
 132 }
 133
 134 static void get_tx_power_index(struct adapter *adapt, u8 channel, u8 *cck_pwr,
 135                                u8 *ofdm_pwr, u8 *bw20_pwr, u8 *bw40_pwr)
 136 {
 137         struct hal_data_8188e *hal_data = adapt->HalData;
 138         u8 index = (channel - 1);
 139         u8 TxCount = 0, path_nums;
 140
 141         path_nums = 1;
 142
 143         for (TxCount = 0; TxCount < path_nums; TxCount++) {
 144                 if (TxCount == RF_PATH_A) {
 145                         cck_pwr[TxCount] = hal_data->Index24G_CCK_Base[TxCount][index];
 146                         ofdm_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index]+
 147                                             hal_data->OFDM_24G_Diff[TxCount][RF_PATH_A];
 148
 149                         bw20_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index]+
 150                                             hal_data->BW20_24G_Diff[TxCount][RF_PATH_A];
 151                         bw40_pwr[TxCount] = hal_data->Index24G_BW40_Base[TxCount][index];
 152                 } else if (TxCount == RF_PATH_B) {
 153                         cck_pwr[TxCount] = hal_data->Index24G_CCK_Base[TxCount][index];
 154                         ofdm_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index]+
 155                         hal_data->BW20_24G_Diff[RF_PATH_A][index]+
 156                         hal_data->BW20_24G_Diff[TxCount][index];
 157
 158                         bw20_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index]+
 159                         hal_data->BW20_24G_Diff[TxCount][RF_PATH_A]+
 160                         hal_data->BW20_24G_Diff[TxCount][index];
 161                         bw40_pwr[TxCount] = hal_data->Index24G_BW40_Base[TxCount][index];
 162                 }
 163         }
 164 }
 165
 166 static void phy_power_index_check(struct adapter *adapt, u8 channel,
 167                                   u8 *cck_pwr, u8 *ofdm_pwr, u8 *bw20_pwr,
 168                                   u8 *bw40_pwr)
 169 {
 170         struct hal_data_8188e *hal_data = adapt->HalData;
 171
 172         hal_data->CurrentCckTxPwrIdx = cck_pwr[0];
 173         hal_data->CurrentOfdm24GTxPwrIdx = ofdm_pwr[0];
 174         hal_data->CurrentBW2024GTxPwrIdx = bw20_pwr[0];
 175         hal_data->CurrentBW4024GTxPwrIdx = bw40_pwr[0];
 176 }
 177
 178 void phy_set_tx_power_level(struct adapter *adapt, u8 channel)
 179 {
 180         u8 cck_pwr[MAX_TX_COUNT] = {0};
 181         u8 ofdm_pwr[MAX_TX_COUNT] = {0};/*  [0]:RF-A, [1]:RF-B */
 182         u8 bw20_pwr[MAX_TX_COUNT] = {0};
 183         u8 bw40_pwr[MAX_TX_COUNT] = {0};
 184
 185         get_tx_power_index(adapt, channel, &cck_pwr[0], &ofdm_pwr[0],
 186                            &bw20_pwr[0], &bw40_pwr[0]);
 187
 188         phy_power_index_check(adapt, channel, &cck_pwr[0], &ofdm_pwr[0],
 189                               &bw20_pwr[0], &bw40_pwr[0]);
 190
 191         rtl88eu_phy_rf6052_set_cck_txpower(adapt, &cck_pwr[0]);
 192         rtl88eu_phy_rf6052_set_ofdm_txpower(adapt, &ofdm_pwr[0], &bw20_pwr[0],
 193                                           &bw40_pwr[0], channel);
 194 }
 195
 196 static void phy_set_bw_mode_callback(struct adapter *adapt)
 197 {
 198         struct hal_data_8188e *hal_data = adapt->HalData;
 199         u8 reg_bw_opmode;
 200         u8 reg_prsr_rsc;
 201
 202         if (adapt->bDriverStopped)
 203                 return;
 204
 205         /* Set MAC register */
 206
 207         reg_bw_opmode = usb_read8(adapt, REG_BWOPMODE);
 208         reg_prsr_rsc = usb_read8(adapt, REG_RRSR+2);
 209
 210         switch (hal_data->CurrentChannelBW) {
 211         case HT_CHANNEL_WIDTH_20:
 212                 reg_bw_opmode |= BW_OPMODE_20MHZ;
 213                 usb_write8(adapt, REG_BWOPMODE, reg_bw_opmode);
 214                 break;
 215         case HT_CHANNEL_WIDTH_40:
 216                 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
 217                 usb_write8(adapt, REG_BWOPMODE, reg_bw_opmode);
 218                 reg_prsr_rsc = (reg_prsr_rsc&0x90) |
 219                                (hal_data->nCur40MhzPrimeSC<<5);
 220                 usb_write8(adapt, REG_RRSR+2, reg_prsr_rsc);
 221                 break;
 222         default:
 223                 break;
 224         }
 225
 226         /* Set PHY related register */
 227         switch (hal_data->CurrentChannelBW) {
 228         case HT_CHANNEL_WIDTH_20:
 229                 phy_set_bb_reg(adapt, rFPGA0_RFMOD, bRFMOD, 0x0);
 230                 phy_set_bb_reg(adapt, rFPGA1_RFMOD, bRFMOD, 0x0);
 231                 break;
 232         case HT_CHANNEL_WIDTH_40:
 233                 phy_set_bb_reg(adapt, rFPGA0_RFMOD, bRFMOD, 0x1);
 234                 phy_set_bb_reg(adapt, rFPGA1_RFMOD, bRFMOD, 0x1);
 235                 /* Set Control channel to upper or lower.
 236                  * These settings are required only for 40MHz
 237                  */
 238                 phy_set_bb_reg(adapt, rCCK0_System, bCCKSideBand,
 239                     (hal_data->nCur40MhzPrimeSC>>1));
 240                 phy_set_bb_reg(adapt, rOFDM1_LSTF, 0xC00,
 241                                hal_data->nCur40MhzPrimeSC);
 242                 phy_set_bb_reg(adapt, 0x818, (BIT(26) | BIT(27)),
 243                    (hal_data->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
 244                 break;
 245         default:
 246                 break;
 247         }
 248
 249         /* Set RF related register */
 250         rtl88eu_phy_rf6052_set_bandwidth(adapt, hal_data->CurrentChannelBW);
 251 }
 252
 253 void rtw_hal_set_bwmode(struct adapter *adapt, enum ht_channel_width bandwidth,
 254                      unsigned char offset)
 255 {
 256         struct hal_data_8188e *hal_data = adapt->HalData;
 257         enum ht_channel_width tmp_bw = hal_data->CurrentChannelBW;
 258
 259         hal_data->CurrentChannelBW = bandwidth;
 260         hal_data->nCur40MhzPrimeSC = offset;
 261
 262         if ((!adapt->bDriverStopped) && (!adapt->bSurpriseRemoved))
 263                 phy_set_bw_mode_callback(adapt);
 264         else
 265                 hal_data->CurrentChannelBW = tmp_bw;
 266 }
 267
 268 static void phy_sw_chnl_callback(struct adapter *adapt, u8 channel)
 269 {
 270         u32 param1, param2;
 271         struct hal_data_8188e *hal_data = adapt->HalData;
 272
 273         phy_set_tx_power_level(adapt, channel);
 274
 275         param1 = RF_CHNLBW;
 276         param2 = channel;
 277         hal_data->RfRegChnlVal[0] = (hal_data->RfRegChnlVal[0] &
 278                                           0xfffffc00) | param2;
 279         phy_set_rf_reg(adapt, 0, param1,
 280                        bRFRegOffsetMask, hal_data->RfRegChnlVal[0]);
 281 }
 282
 283 void rtw_hal_set_chan(struct adapter *adapt, u8 channel)
 284 {
 285         struct hal_data_8188e *hal_data = adapt->HalData;
 286         u8 tmpchannel = hal_data->CurrentChannel;
 287
 288         if (channel == 0)
 289                 channel = 1;
 290
 291         hal_data->CurrentChannel = channel;
 292
 293         if ((!adapt->bDriverStopped) && (!adapt->bSurpriseRemoved))
 294                 phy_sw_chnl_callback(adapt, channel);
 295         else
 296                 hal_data->CurrentChannel = tmpchannel;
 297 }
 298
 299 #define ODM_TXPWRTRACK_MAX_IDX_88E  6
 300
 301 void rtl88eu_dm_txpower_track_adjust(struct odm_dm_struct *dm_odm, u8 type,
 302                                      u8 *direction, u32 *out_write_val)
 303 {
 304         u8 pwr_value = 0;
 305         /*  Tx power tracking BB swing table. */
 306         if (type == 0) { /* For OFDM adjust */
 307                 ODM_RT_TRACE(dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 308                              ("BbSwingIdxOfdm = %d BbSwingFlagOfdm=%d\n",
 309                              dm_odm->BbSwingIdxOfdm, dm_odm->BbSwingFlagOfdm));
 310
 311                 if (dm_odm->BbSwingIdxOfdm <= dm_odm->BbSwingIdxOfdmBase) {
 312                         *direction = 1;
 313                         pwr_value = dm_odm->BbSwingIdxOfdmBase -
 314                                      dm_odm->BbSwingIdxOfdm;
 315                 } else {
 316                         *direction = 2;
 317                         pwr_value = dm_odm->BbSwingIdxOfdm -
 318                                      dm_odm->BbSwingIdxOfdmBase;
 319                 }
 320
 321         } else if (type == 1) { /* For CCK adjust. */
 322                 ODM_RT_TRACE(dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 323                              ("dm_odm->BbSwingIdxCck = %d dm_odm->BbSwingIdxCckBase = %d\n",
 324                              dm_odm->BbSwingIdxCck, dm_odm->BbSwingIdxCckBase));
 325
 326                 if (dm_odm->BbSwingIdxCck <= dm_odm->BbSwingIdxCckBase) {
 327                         *direction = 1;
 328                         pwr_value = dm_odm->BbSwingIdxCckBase -
 329                                      dm_odm->BbSwingIdxCck;
 330                 } else {
 331                         *direction = 2;
 332                         pwr_value = dm_odm->BbSwingIdxCck -
 333                                      dm_odm->BbSwingIdxCckBase;
 334                 }
 335         }
 336
 337         if (pwr_value >= ODM_TXPWRTRACK_MAX_IDX_88E && *direction == 1)
 338                 pwr_value = ODM_TXPWRTRACK_MAX_IDX_88E;
 339
 340         *out_write_val = pwr_value | (pwr_value<<8) | (pwr_value<<16) |
 341                          (pwr_value<<24);
 342 }
 343
 344 static void dm_txpwr_track_setpwr(struct odm_dm_struct *dm_odm)
 345 {
 346         if (dm_odm->BbSwingFlagOfdm || dm_odm->BbSwingFlagCck) {
 347                 ODM_RT_TRACE(dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 348                              ("dm_txpwr_track_setpwr CH=%d\n", *(dm_odm->pChannel)));
 349                 phy_set_tx_power_level(dm_odm->Adapter, *(dm_odm->pChannel));
 350                 dm_odm->BbSwingFlagOfdm = false;
 351                 dm_odm->BbSwingFlagCck = false;
 352         }
 353 }
 354
 355 void rtl88eu_dm_txpower_tracking_callback_thermalmeter(struct adapter *adapt)
 356 {
 357         struct hal_data_8188e *hal_data = adapt->HalData;
 358         u8 thermal_val = 0, delta, delta_lck, delta_iqk, offset;
 359         u8 thermal_avg_count = 0;
 360         u32 thermal_avg = 0;
 361         s32 ele_d, temp_cck;
 362         s8 ofdm_index[2], cck_index = 0;
 363         s8 ofdm_index_old[2] = {0, 0}, cck_index_old = 0;
 364         u32 i = 0, j = 0;
 365
 366         u8 ofdm_min_index = 6; /* OFDM BB Swing should be less than +3.0dB */
 367         s8 ofdm_index_mapping[2][index_mapping_NUM_88E] = {
 368                 /* 2.4G, decrease power */
 369                 {0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11},
 370                 /* 2.4G, increase power */
 371                 {0, 0, -1, -2, -3, -4, -4, -4, -4, -5, -7, -8, -9, -9, -10},
 372         };
 373         u8 thermal_mapping[2][index_mapping_NUM_88E] = {
 374                 /* 2.4G, decrease power */
 375                 {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 27},
 376                 /* 2.4G, increase power */
 377                 {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 25, 25, 25},
 378         };
 379         struct odm_dm_struct *dm_odm = &hal_data->odmpriv;
 380
 381         dm_txpwr_track_setpwr(dm_odm);
 382
 383         dm_odm->RFCalibrateInfo.TXPowerTrackingCallbackCnt++;
 384
 385         dm_odm->RFCalibrateInfo.RegA24 = 0x090e1317;
 386
 387         thermal_val = (u8)rtw_hal_read_rfreg(adapt, RF_PATH_A,
 388                                            RF_T_METER_88E, 0xfc00);
 389
 390         if (thermal_val) {
 391                 /* Query OFDM path A default setting */
 392                 ele_d = phy_query_bb_reg(adapt, rOFDM0_XATxIQImbalance, bMaskDWord)&bMaskOFDM_D;
 393                 for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) {
 394                         if (ele_d == (OFDMSwingTable[i]&bMaskOFDM_D)) {
 395                                 ofdm_index_old[0] = (u8)i;
 396                                 dm_odm->BbSwingIdxOfdmBase = (u8)i;
 397                                 break;
 398                         }
 399                 }
 400
 401                 /* Query CCK default setting From 0xa24 */
 402                 temp_cck = dm_odm->RFCalibrateInfo.RegA24;
 403
 404                 for (i = 0; i < CCK_TABLE_SIZE; i++) {
 405                         if ((dm_odm->RFCalibrateInfo.bCCKinCH14 &&
 406                                 memcmp(&temp_cck, &CCKSwingTable_Ch14[i][2], 4)) ||
 407                                 memcmp(&temp_cck, &CCKSwingTable_Ch1_Ch13[i][2], 4)) {
 408                                         cck_index_old = (u8)i;
 409                                         dm_odm->BbSwingIdxCckBase = (u8)i;
 410                                         break;
 411                         }
 412                 }
 413
 414                 if (!dm_odm->RFCalibrateInfo.ThermalValue) {
 415                         dm_odm->RFCalibrateInfo.ThermalValue = hal_data->EEPROMThermalMeter;
 416                         dm_odm->RFCalibrateInfo.ThermalValue_LCK = thermal_val;
 417                         dm_odm->RFCalibrateInfo.ThermalValue_IQK = thermal_val;
 418
 419                         dm_odm->RFCalibrateInfo.OFDM_index[0] = ofdm_index_old[0];
 420                         dm_odm->RFCalibrateInfo.CCK_index = cck_index_old;
 421                 }
 422
 423                 /* calculate average thermal meter */
 424                 dm_odm->RFCalibrateInfo.ThermalValue_AVG[dm_odm->RFCalibrateInfo.ThermalValue_AVG_index] = thermal_val;
 425                 dm_odm->RFCalibrateInfo.ThermalValue_AVG_index++;
 426                 if (dm_odm->RFCalibrateInfo.ThermalValue_AVG_index == AVG_THERMAL_NUM_88E)
 427                         dm_odm->RFCalibrateInfo.ThermalValue_AVG_index = 0;
 428
 429                 for (i = 0; i < AVG_THERMAL_NUM_88E; i++) {
 430                         if (dm_odm->RFCalibrateInfo.ThermalValue_AVG[i]) {
 431                                 thermal_avg += dm_odm->RFCalibrateInfo.ThermalValue_AVG[i];
 432                                 thermal_avg_count++;
 433                         }
 434                 }
 435
 436                 if (thermal_avg_count)
 437                         thermal_val = (u8)(thermal_avg / thermal_avg_count);
 438
 439                 if (dm_odm->RFCalibrateInfo.bDoneTxpower &&
 440                         !dm_odm->RFCalibrateInfo.bReloadtxpowerindex) {
 441                         delta = abs(thermal_val - dm_odm->RFCalibrateInfo.ThermalValue);
 442                 } else {
 443                         delta = abs(thermal_val - hal_data->EEPROMThermalMeter);
 444                         if (dm_odm->RFCalibrateInfo.bReloadtxpowerindex) {
 445                                 dm_odm->RFCalibrateInfo.bReloadtxpowerindex = false;
 446                                 dm_odm->RFCalibrateInfo.bDoneTxpower = false;
 447                         }
 448                 }
 449
 450                 delta_lck = abs(dm_odm->RFCalibrateInfo.ThermalValue_LCK - thermal_val);
 451                 delta_iqk = abs(dm_odm->RFCalibrateInfo.ThermalValue_IQK - thermal_val);
 452
 453                 /* Delta temperature is equal to or larger than 20 centigrade.*/
 454                 if ((delta_lck >= 8)) {
 455                         dm_odm->RFCalibrateInfo.ThermalValue_LCK = thermal_val;
 456                         rtl88eu_phy_lc_calibrate(adapt);
 457                 }
 458
 459                 if (delta > 0 && dm_odm->RFCalibrateInfo.TxPowerTrackControl) {
 460                         delta = abs(hal_data->EEPROMThermalMeter - thermal_val);
 461
 462                         /* calculate new OFDM / CCK offset */
 463                         if (thermal_val > hal_data->EEPROMThermalMeter)
 464                                 j = 1;
 465                         else
 466                                 j = 0;
 467                         for (offset = 0; offset < index_mapping_NUM_88E; offset++) {
 468                                 if (delta < thermal_mapping[j][offset]) {
 469                                         if (offset != 0)
 470                                                 offset--;
 471                                         break;
 472                                 }
 473                         }
 474                         if (offset >= index_mapping_NUM_88E)
 475                                 offset = index_mapping_NUM_88E-1;
 476
 477                         /* Updating ofdm_index values with new OFDM / CCK offset */
 478                         ofdm_index[0] = dm_odm->RFCalibrateInfo.OFDM_index[0] + ofdm_index_mapping[j][offset];
 479                         if (ofdm_index[0] > OFDM_TABLE_SIZE_92D-1)
 480                                 ofdm_index[0] = OFDM_TABLE_SIZE_92D-1;
 481                         else if (ofdm_index[0] < ofdm_min_index)
 482                                 ofdm_index[0] = ofdm_min_index;
 483
 484                         cck_index = dm_odm->RFCalibrateInfo.CCK_index + ofdm_index_mapping[j][offset];
 485                         if (cck_index > CCK_TABLE_SIZE-1)
 486                                 cck_index = CCK_TABLE_SIZE-1;
 487                         else if (cck_index < 0)
 488                                 cck_index = 0;
 489
 490                         /* 2 temporarily remove bNOPG */
 491                         /* Config by SwingTable */
 492                         if (dm_odm->RFCalibrateInfo.TxPowerTrackControl) {
 493                                 dm_odm->RFCalibrateInfo.bDoneTxpower = true;
 494
 495                                 /*  Revse TX power table. */
 496                                 dm_odm->BbSwingIdxOfdm = (u8)ofdm_index[0];
 497                                 dm_odm->BbSwingIdxCck = (u8)cck_index;
 498
 499                                 if (dm_odm->BbSwingIdxOfdmCurrent != dm_odm->BbSwingIdxOfdm) {
 500                                         dm_odm->BbSwingIdxOfdmCurrent = dm_odm->BbSwingIdxOfdm;
 501                                         dm_odm->BbSwingFlagOfdm = true;
 502                                 }
 503
 504                                 if (dm_odm->BbSwingIdxCckCurrent != dm_odm->BbSwingIdxCck) {
 505                                         dm_odm->BbSwingIdxCckCurrent = dm_odm->BbSwingIdxCck;
 506                                         dm_odm->BbSwingFlagCck = true;
 507                                 }
 508                         }
 509                 }
 510
 511                 /* Delta temperature is equal to or larger than 20 centigrade.*/
 512                 if (delta_iqk >= 8) {
 513                         dm_odm->RFCalibrateInfo.ThermalValue_IQK = thermal_val;
 514                         rtl88eu_phy_iq_calibrate(adapt, false);
 515                 }
 516                 /* update thermal meter value */
 517                 if (dm_odm->RFCalibrateInfo.TxPowerTrackControl)
 518                         dm_odm->RFCalibrateInfo.ThermalValue = thermal_val;
 519         }
 520         dm_odm->RFCalibrateInfo.TXPowercount = 0;
 521 }
 522
 523 #define MAX_TOLERANCE 5
 524
 525 static u8 phy_path_a_iqk(struct adapter *adapt, bool config_pathb)
 526 {
 527         u32 reg_eac, reg_e94, reg_e9c;
 528         u8 result = 0x00;
 529
 530         /* 1 Tx IQK */
 531         /* path-A IQK setting */
 532         phy_set_bb_reg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);
 533         phy_set_bb_reg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);
 534         phy_set_bb_reg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x8214032a);
 535         phy_set_bb_reg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160000);
 536
 537         /* LO calibration setting */
 538         phy_set_bb_reg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
 539
 540         /* One shot, path A LOK & IQK */
 541         phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
 542         phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
 543
 544         mdelay(IQK_DELAY_TIME_88E);
 545
 546         reg_eac = phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord);
 547         reg_e94 = phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A, bMaskDWord);
 548         reg_e9c = phy_query_bb_reg(adapt, rTx_Power_After_IQK_A, bMaskDWord);
 549
 550         if (!(reg_eac & BIT(28)) &&
 551             (((reg_e94 & 0x03FF0000)>>16) != 0x142) &&
 552             (((reg_e9c & 0x03FF0000)>>16) != 0x42))
 553                 result |= 0x01;
 554         return result;
 555 }
 556
 557 static u8 phy_path_a_rx_iqk(struct adapter *adapt, bool configPathB)
 558 {
 559         u32 reg_eac, reg_e94, reg_e9c, reg_ea4, u4tmp;
 560         u8 result = 0x00;
 561         struct odm_dm_struct *dm_odm = &adapt->HalData->odmpriv;
 562
 563         /* 1 Get TXIMR setting */
 564         /* modify RXIQK mode table */
 565         phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000);
 566         phy_set_rf_reg(adapt, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0);
 567         phy_set_rf_reg(adapt, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
 568         phy_set_rf_reg(adapt, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f);
 569         phy_set_rf_reg(adapt, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B);
 570
 571         /* PA,PAD off */
 572         phy_set_rf_reg(adapt, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980);
 573         phy_set_rf_reg(adapt, RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000);
 574
 575         phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);
 576
 577         /* IQK setting */
 578         phy_set_bb_reg(adapt, rTx_IQK, bMaskDWord, 0x01007c00);
 579         phy_set_bb_reg(adapt, rRx_IQK, bMaskDWord, 0x81004800);
 580
 581         /* path-A IQK setting */
 582         phy_set_bb_reg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);
 583         phy_set_bb_reg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);
 584         phy_set_bb_reg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f);
 585         phy_set_bb_reg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160000);
 586
 587         /* LO calibration setting */
 588         phy_set_bb_reg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
 589
 590         /* One shot, path A LOK & IQK */
 591         phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
 592         phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
 593
 594         /* delay x ms */
 595         mdelay(IQK_DELAY_TIME_88E);
 596
 597         /* Check failed */
 598         reg_eac = phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord);
 599         reg_e94 = phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A, bMaskDWord);
 600         reg_e9c = phy_query_bb_reg(adapt, rTx_Power_After_IQK_A, bMaskDWord);
 601
 602         if (!(reg_eac & BIT(28)) &&
 603             (((reg_e94 & 0x03FF0000)>>16) != 0x142) &&
 604             (((reg_e9c & 0x03FF0000)>>16) != 0x42))
 605                 result |= 0x01;
 606         else                                    /* if Tx not OK, ignore Rx */
 607                 return result;
 608
 609         u4tmp = 0x80007C00 | (reg_e94&0x3FF0000)  | ((reg_e9c&0x3FF0000) >> 16);
 610         phy_set_bb_reg(adapt, rTx_IQK, bMaskDWord, u4tmp);
 611
 612         /* 1 RX IQK */
 613         /* modify RXIQK mode table */
 614         ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
 615                      ("Path-A Rx IQK modify RXIQK mode table 2!\n"));
 616         phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000);
 617         phy_set_rf_reg(adapt, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0);
 618         phy_set_rf_reg(adapt, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
 619         phy_set_rf_reg(adapt, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f);
 620         phy_set_rf_reg(adapt, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa);
 621         phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);
 622
 623         /* IQK setting */
 624         phy_set_bb_reg(adapt, rRx_IQK, bMaskDWord, 0x01004800);
 625
 626         /* path-A IQK setting */
 627         phy_set_bb_reg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
 628         phy_set_bb_reg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
 629         phy_set_bb_reg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x82160c05);
 630         phy_set_bb_reg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160c1f);
 631
 632         /* LO calibration setting */
 633         phy_set_bb_reg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
 634
 635         phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
 636         phy_set_bb_reg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
 637
 638         mdelay(IQK_DELAY_TIME_88E);
 639
 640         /*  Check failed */
 641         reg_eac = phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord);
 642         reg_e94 = phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A, bMaskDWord);
 643         reg_e9c = phy_query_bb_reg(adapt, rTx_Power_After_IQK_A, bMaskDWord);
 644         reg_ea4 = phy_query_bb_reg(adapt, rRx_Power_Before_IQK_A_2, bMaskDWord);
 645
 646         /* reload RF 0xdf */
 647         phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000);
 648         phy_set_rf_reg(adapt, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180);
 649
 650         if (!(reg_eac & BIT(27)) && /* if Tx is OK, check whether Rx is OK */
 651             (((reg_ea4 & 0x03FF0000)>>16) != 0x132) &&
 652             (((reg_eac & 0x03FF0000)>>16) != 0x36))
 653                 result |= 0x02;
 654         else
 655                 ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
 656                              ("Path A Rx IQK fail!!\n"));
 657
 658         return result;
 659 }
 660
 661 static u8 phy_path_b_iqk(struct adapter *adapt)
 662 {
 663         u32 regeac, regeb4, regebc, regec4, regecc;
 664         u8 result = 0x00;
 665         struct odm_dm_struct *dm_odm = &adapt->HalData->odmpriv;
 666
 667         /* One shot, path B LOK & IQK */
 668         phy_set_bb_reg(adapt, rIQK_AGC_Cont, bMaskDWord, 0x00000002);
 669         phy_set_bb_reg(adapt, rIQK_AGC_Cont, bMaskDWord, 0x00000000);
 670
 671         mdelay(IQK_DELAY_TIME_88E);
 672
 673         regeac = phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord);
 674         regeb4 = phy_query_bb_reg(adapt, rTx_Power_Before_IQK_B, bMaskDWord);
 675         regebc = phy_query_bb_reg(adapt, rTx_Power_After_IQK_B, bMaskDWord);
 676         regec4 = phy_query_bb_reg(adapt, rRx_Power_Before_IQK_B_2, bMaskDWord);
 677         regecc = phy_query_bb_reg(adapt, rRx_Power_After_IQK_B_2, bMaskDWord);
 678
 679         if (!(regeac & BIT(31)) &&
 680             (((regeb4 & 0x03FF0000)>>16) != 0x142) &&
 681             (((regebc & 0x03FF0000)>>16) != 0x42))
 682                 result |= 0x01;
 683         else
 684                 return result;
 685
 686         if (!(regeac & BIT(30)) &&
 687             (((regec4 & 0x03FF0000)>>16) != 0x132) &&
 688             (((regecc & 0x03FF0000)>>16) != 0x36))
 689                 result |= 0x02;
 690         else
 691                 ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION,
 692                              ODM_DBG_LOUD,  ("Path B Rx IQK fail!!\n"));
 693         return result;
 694 }
 695
 696 static void patha_fill_iqk(struct adapter *adapt, bool iqkok, s32 result[][8],
 697                            u8 final_candidate, bool txonly)
 698 {
 699         u32 oldval_0, x, tx0_a, reg;
 700         s32 y, tx0_c;
 701
 702         if (final_candidate == 0xFF) {
 703                 return;
 704         } else if (iqkok) {
 705                 oldval_0 = (phy_query_bb_reg(adapt, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
 706
 707                 x = result[final_candidate][0];
 708                 if ((x & 0x00000200) != 0)
 709                         x = x | 0xFFFFFC00;
 710
 711                 tx0_a = (x * oldval_0) >> 8;
 712                 phy_set_bb_reg(adapt, rOFDM0_XATxIQImbalance, 0x3FF, tx0_a);
 713                 phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(31),
 714                                ((x * oldval_0>>7) & 0x1));
 715
 716                 y = result[final_candidate][1];
 717                 if ((y & 0x00000200) != 0)
 718                         y = y | 0xFFFFFC00;
 719
 720                 tx0_c = (y * oldval_0) >> 8;
 721                 phy_set_bb_reg(adapt, rOFDM0_XCTxAFE, 0xF0000000,
 722                                ((tx0_c&0x3C0)>>6));
 723                 phy_set_bb_reg(adapt, rOFDM0_XATxIQImbalance, 0x003F0000,
 724                                (tx0_c&0x3F));
 725                 phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(29),
 726                                ((y * oldval_0>>7) & 0x1));
 727
 728                 if (txonly)
 729                         return;
 730
 731                 reg = result[final_candidate][2];
 732                 phy_set_bb_reg(adapt, rOFDM0_XARxIQImbalance, 0x3FF, reg);
 733
 734                 reg = result[final_candidate][3] & 0x3F;
 735                 phy_set_bb_reg(adapt, rOFDM0_XARxIQImbalance, 0xFC00, reg);
 736
 737                 reg = (result[final_candidate][3] >> 6) & 0xF;
 738                 phy_set_bb_reg(adapt, rOFDM0_RxIQExtAnta, 0xF0000000, reg);
 739         }
 740 }
 741
 742 static void pathb_fill_iqk(struct adapter *adapt, bool iqkok, s32 result[][8],
 743                            u8 final_candidate, bool txonly)
 744 {
 745         u32 oldval_1, x, tx1_a, reg;
 746         s32 y, tx1_c;
 747
 748         if (final_candidate == 0xFF) {
 749                 return;
 750         } else if (iqkok) {
 751                 oldval_1 = (phy_query_bb_reg(adapt, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
 752
 753                 x = result[final_candidate][4];
 754                 if ((x & 0x00000200) != 0)
 755                         x = x | 0xFFFFFC00;
 756                 tx1_a = (x * oldval_1) >> 8;
 757                 phy_set_bb_reg(adapt, rOFDM0_XBTxIQImbalance, 0x3FF, tx1_a);
 758
 759                 phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(27),
 760                                ((x * oldval_1>>7) & 0x1));
 761
 762                 y = result[final_candidate][5];
 763                 if ((y & 0x00000200) != 0)
 764                         y = y | 0xFFFFFC00;
 765
 766                 tx1_c = (y * oldval_1) >> 8;
 767
 768                 phy_set_bb_reg(adapt, rOFDM0_XDTxAFE, 0xF0000000,
 769                                ((tx1_c&0x3C0)>>6));
 770                 phy_set_bb_reg(adapt, rOFDM0_XBTxIQImbalance, 0x003F0000,
 771                                (tx1_c&0x3F));
 772                 phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(25),
 773                                ((y * oldval_1>>7) & 0x1));
 774
 775                 if (txonly)
 776                         return;
 777
 778                 reg = result[final_candidate][6];
 779                 phy_set_bb_reg(adapt, rOFDM0_XBRxIQImbalance, 0x3FF, reg);
 780
 781                 reg = result[final_candidate][7] & 0x3F;
 782                 phy_set_bb_reg(adapt, rOFDM0_XBRxIQImbalance, 0xFC00, reg);
 783
 784                 reg = (result[final_candidate][7] >> 6) & 0xF;
 785                 phy_set_bb_reg(adapt, rOFDM0_AGCRSSITable, 0x0000F000, reg);
 786         }
 787 }
 788
 789 static void save_adda_registers(struct adapter *adapt, u32 *addareg,
 790                                 u32 *backup, u32 register_num)
 791 {
 792         u32 i;
 793
 794         for (i = 0; i < register_num; i++)
 795                 backup[i] = phy_query_bb_reg(adapt, addareg[i], bMaskDWord);
 796 }
 797
 798 static void save_mac_registers(struct adapter *adapt, u32 *mac_reg,
 799                                u32 *backup)
 800 {
 801         u32 i;
 802
 803         for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
 804                 backup[i] = usb_read8(adapt, mac_reg[i]);
 805
 806         backup[i] = usb_read32(adapt, mac_reg[i]);
 807 }
 808
 809 static void reload_adda_reg(struct adapter *adapt, u32 *adda_reg,
 810                             u32 *backup, u32 regiester_num)
 811 {
 812         u32 i;
 813
 814         for (i = 0; i < regiester_num; i++)
 815                 phy_set_bb_reg(adapt, adda_reg[i], bMaskDWord, backup[i]);
 816 }
 817
 818 static void reload_mac_registers(struct adapter *adapt,
 819                                  u32 *mac_reg, u32 *backup)
 820 {
 821         u32 i;
 822
 823         for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
 824                 usb_write8(adapt, mac_reg[i], (u8)backup[i]);
 825
 826         usb_write32(adapt, mac_reg[i], backup[i]);
 827 }
 828
 829 static void path_adda_on(struct adapter *adapt, u32 *adda_reg,
 830                          bool is_path_a_on, bool is2t)
 831 {
 832         u32 path_on;
 833         u32 i;
 834
 835         if (!is2t) {
 836                 path_on = 0x0bdb25a0;
 837                 phy_set_bb_reg(adapt, adda_reg[0], bMaskDWord, 0x0b1b25a0);
 838         } else {
 839                 path_on = is_path_a_on ? 0x04db25a4 : 0x0b1b25a4;
 840                 phy_set_bb_reg(adapt, adda_reg[0], bMaskDWord, path_on);
 841         }
 842
 843         for (i = 1; i < IQK_ADDA_REG_NUM; i++)
 844                 phy_set_bb_reg(adapt, adda_reg[i], bMaskDWord, path_on);
 845 }
 846
 847 static void mac_setting_calibration(struct adapter *adapt, u32 *mac_reg, u32 *backup)
 848 {
 849         u32 i = 0;
 850
 851         usb_write8(adapt, mac_reg[i], 0x3F);
 852
 853         for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
 854                 usb_write8(adapt, mac_reg[i], (u8)(backup[i]&(~BIT(3))));
 855
 856         usb_write8(adapt, mac_reg[i], (u8)(backup[i]&(~BIT(5))));
 857 }
 858
 859 static void path_a_standby(struct adapter *adapt)
 860 {
 861         phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x0);
 862         phy_set_bb_reg(adapt, 0x840, bMaskDWord, 0x00010000);
 863         phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);
 864 }
 865
 866 static void pi_mode_switch(struct adapter *adapt, bool pi_mode)
 867 {
 868         u32 mode;
 869
 870         mode = pi_mode ? 0x01000100 : 0x01000000;
 871         phy_set_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode);
 872         phy_set_bb_reg(adapt, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode);
 873 }
 874
 875 static bool simularity_compare(struct adapter *adapt, s32 resulta[][8],
 876                                u8 c1, u8 c2)
 877 {
 878         u32 i, j, diff, sim_bitmap = 0, bound;
 879         u8 final_candidate[2] = {0xFF, 0xFF};   /* for path A and path B */
 880         bool result = true;
 881         s32 tmp1 = 0, tmp2 = 0;
 882
 883         bound = 4;
 884
 885         for (i = 0; i < bound; i++) {
 886                 if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) {
 887                         if ((resulta[c1][i] & 0x00000200) != 0)
 888                                 tmp1 = resulta[c1][i] | 0xFFFFFC00;
 889                         else
 890                                 tmp1 = resulta[c1][i];
 891
 892                         if ((resulta[c2][i] & 0x00000200) != 0)
 893                                 tmp2 = resulta[c2][i] | 0xFFFFFC00;
 894                         else
 895                                 tmp2 = resulta[c2][i];
 896                 } else {
 897                         tmp1 = resulta[c1][i];
 898                         tmp2 = resulta[c2][i];
 899                 }
 900
 901                 diff = abs(tmp1 - tmp2);
 902
 903                 if (diff > MAX_TOLERANCE) {
 904                         if ((i == 2 || i == 6) && !sim_bitmap) {
 905                                 if (resulta[c1][i] + resulta[c1][i+1] == 0)
 906                                         final_candidate[(i/4)] = c2;
 907                                 else if (resulta[c2][i] + resulta[c2][i+1] == 0)
 908                                         final_candidate[(i/4)] = c1;
 909                                 else
 910                                         sim_bitmap = sim_bitmap | (1<<i);
 911                         } else {
 912                                 sim_bitmap = sim_bitmap | (1<<i);
 913                         }
 914                 }
 915         }
 916
 917         if (sim_bitmap == 0) {
 918                 for (i = 0; i < (bound/4); i++) {
 919                         if (final_candidate[i] != 0xFF) {
 920                                 for (j = i*4; j < (i+1)*4-2; j++)
 921                                         resulta[3][j] = resulta[final_candidate[i]][j];
 922                                 result = false;
 923                         }
 924                 }
 925                 return result;
 926         } else {
 927                 if (!(sim_bitmap & 0x03)) {                /* path A TX OK */
 928                         for (i = 0; i < 2; i++)
 929                                 resulta[3][i] = resulta[c1][i];
 930                 }
 931                 if (!(sim_bitmap & 0x0c)) {                /* path A RX OK */
 932                         for (i = 2; i < 4; i++)
 933                                 resulta[3][i] = resulta[c1][i];
 934                 }
 935
 936                 if (!(sim_bitmap & 0x30)) { /* path B TX OK */
 937                         for (i = 4; i < 6; i++)
 938                                 resulta[3][i] = resulta[c1][i];
 939                 }
 940
 941                 if (!(sim_bitmap & 0xc0)) { /* path B RX OK */
 942                         for (i = 6; i < 8; i++)
 943                                 resulta[3][i] = resulta[c1][i];
 944                 }
 945                 return false;
 946         }
 947 }
 948
 949 static void phy_iq_calibrate(struct adapter *adapt, s32 result[][8],
 950                              u8 t, bool is2t)
 951 {
 952         struct odm_dm_struct *dm_odm = &adapt->HalData->odmpriv;
 953         u32 i;
 954         u8 path_a_ok, path_b_ok;
 955         u32 adda_reg[IQK_ADDA_REG_NUM] = {
 956                                           rFPGA0_XCD_SwitchControl, rBlue_Tooth,
 957                                           rRx_Wait_CCA, rTx_CCK_RFON,
 958                                           rTx_CCK_BBON, rTx_OFDM_RFON,
 959                                           rTx_OFDM_BBON, rTx_To_Rx,
 960                                           rTx_To_Tx, rRx_CCK,
 961                                           rRx_OFDM, rRx_Wait_RIFS,
 962                                           rRx_TO_Rx, rStandby,
 963                                           rSleep, rPMPD_ANAEN};
 964
 965         u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
 966                                             REG_TXPAUSE, REG_BCN_CTRL,
 967                                             REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
 968
 969         /* since 92C & 92D have the different define in IQK_BB_REG */
 970         u32 iqk_bb_reg_92c[IQK_BB_REG_NUM] = {
 971                                               rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar,
 972                                               rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB,
 973                                               rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
 974                                               rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD};
 975
 976         u32 retry_count = 9;
 977
 978         if (*(dm_odm->mp_mode) == 1)
 979                 retry_count = 9;
 980         else
 981                 retry_count = 2;
 982
 983         if (t == 0) {
 984                 /*  Save ADDA parameters, turn Path A ADDA on */
 985                 save_adda_registers(adapt, adda_reg, dm_odm->RFCalibrateInfo.ADDA_backup,
 986                                     IQK_ADDA_REG_NUM);
 987                 save_mac_registers(adapt, iqk_mac_reg,
 988                                    dm_odm->RFCalibrateInfo.IQK_MAC_backup);
 989                 save_adda_registers(adapt, iqk_bb_reg_92c,
 990                                     dm_odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
 991         }
 992
 993         path_adda_on(adapt, adda_reg, true, is2t);
 994         if (t == 0)
 995                 dm_odm->RFCalibrateInfo.bRfPiEnable = (u8)phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter1,
 996                                                                            BIT(8));
 997
 998         if (!dm_odm->RFCalibrateInfo.bRfPiEnable) {
 999                 /*  Switch BB to PI mode to do IQ Calibration. */
1000                 pi_mode_switch(adapt, true);
1001         }
1002
1003         /* BB setting */
1004         phy_set_bb_reg(adapt, rFPGA0_RFMOD, BIT(24), 0x00);
1005         phy_set_bb_reg(adapt, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);
1006         phy_set_bb_reg(adapt, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);
1007         phy_set_bb_reg(adapt, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
1008
1009         phy_set_bb_reg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT(10), 0x01);
1010         phy_set_bb_reg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT(26), 0x01);
1011         phy_set_bb_reg(adapt, rFPGA0_XA_RFInterfaceOE, BIT(10), 0x00);
1012         phy_set_bb_reg(adapt, rFPGA0_XB_RFInterfaceOE, BIT(10), 0x00);
1013
1014         if (is2t) {
1015                 phy_set_bb_reg(adapt, rFPGA0_XA_LSSIParameter, bMaskDWord,
1016                                0x00010000);
1017                 phy_set_bb_reg(adapt, rFPGA0_XB_LSSIParameter, bMaskDWord,
1018                                0x00010000);
1019         }
1020
1021         /* MAC settings */
1022         mac_setting_calibration(adapt, iqk_mac_reg,
1023                                 dm_odm->RFCalibrateInfo.IQK_MAC_backup);
1024
1025         /* Page B init */
1026         /* AP or IQK */
1027         phy_set_bb_reg(adapt, rConfig_AntA, bMaskDWord, 0x0f600000);
1028
1029         if (is2t)
1030                 phy_set_bb_reg(adapt, rConfig_AntB, bMaskDWord, 0x0f600000);
1031
1032         /*  IQ calibration setting */
1033         phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);
1034         phy_set_bb_reg(adapt, rTx_IQK, bMaskDWord, 0x01007c00);
1035         phy_set_bb_reg(adapt, rRx_IQK, bMaskDWord, 0x81004800);
1036
1037         for (i = 0; i < retry_count; i++) {
1038                 path_a_ok = phy_path_a_iqk(adapt, is2t);
1039                 if (path_a_ok == 0x01) {
1040                                 result[t][0] = (phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A,
1041                                                                  bMaskDWord)&0x3FF0000)>>16;
1042                                 result[t][1] = (phy_query_bb_reg(adapt, rTx_Power_After_IQK_A,
1043                                                                  bMaskDWord)&0x3FF0000)>>16;
1044                         break;
1045                 }
1046         }
1047
1048         for (i = 0; i < retry_count; i++) {
1049                 path_a_ok = phy_path_a_rx_iqk(adapt, is2t);
1050                 if (path_a_ok == 0x03) {
1051                                 result[t][2] = (phy_query_bb_reg(adapt, rRx_Power_Before_IQK_A_2,
1052                                                                  bMaskDWord)&0x3FF0000)>>16;
1053                                 result[t][3] = (phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2,
1054                                                                  bMaskDWord)&0x3FF0000)>>16;
1055                         break;
1056                 } else {
1057                         ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
1058                                      ("Path A Rx IQK Fail!!\n"));
1059                 }
1060         }
1061
1062         if (path_a_ok == 0x00) {
1063                 ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
1064                              ("Path A IQK failed!!\n"));
1065         }
1066
1067         if (is2t) {
1068                 path_a_standby(adapt);
1069
1070                 /*  Turn Path B ADDA on */
1071                 path_adda_on(adapt, adda_reg, false, is2t);
1072
1073                 for (i = 0; i < retry_count; i++) {
1074                         path_b_ok = phy_path_b_iqk(adapt);
1075                         if (path_b_ok == 0x03) {
1076                                 result[t][4] = (phy_query_bb_reg(adapt, rTx_Power_Before_IQK_B,
1077                                                                  bMaskDWord)&0x3FF0000)>>16;
1078                                 result[t][5] = (phy_query_bb_reg(adapt, rTx_Power_After_IQK_B,
1079                                                                  bMaskDWord)&0x3FF0000)>>16;
1080                                 result[t][6] = (phy_query_bb_reg(adapt, rRx_Power_Before_IQK_B_2,
1081                                                                  bMaskDWord)&0x3FF0000)>>16;
1082                                 result[t][7] = (phy_query_bb_reg(adapt, rRx_Power_After_IQK_B_2,
1083                                                                  bMaskDWord)&0x3FF0000)>>16;
1084                                 break;
1085                         } else if (i == (retry_count - 1) && path_b_ok == 0x01) {       /* Tx IQK OK */
1086                                 result[t][4] = (phy_query_bb_reg(adapt, rTx_Power_Before_IQK_B,
1087                                                                  bMaskDWord)&0x3FF0000)>>16;
1088                                 result[t][5] = (phy_query_bb_reg(adapt, rTx_Power_After_IQK_B,
1089                                                                  bMaskDWord)&0x3FF0000)>>16;
1090                         }
1091                 }
1092
1093                 if (path_b_ok == 0x00) {
1094                         ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
1095                                      ("Path B IQK failed!!\n"));
1096                 }
1097         }
1098
1099         /* Back to BB mode, load original value */
1100         phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0);
1101
1102         if (t != 0) {
1103                 if (!dm_odm->RFCalibrateInfo.bRfPiEnable) {
1104                         /* Switch back BB to SI mode after
1105                          * finish IQ Calibration.
1106                          */
1107                         pi_mode_switch(adapt, false);
1108                 }
1109
1110                 /*  Reload ADDA power saving parameters */
1111                 reload_adda_reg(adapt, adda_reg, dm_odm->RFCalibrateInfo.ADDA_backup,
1112                                 IQK_ADDA_REG_NUM);
1113
1114                 /*  Reload MAC parameters */
1115                 reload_mac_registers(adapt, iqk_mac_reg,
1116                                      dm_odm->RFCalibrateInfo.IQK_MAC_backup);
1117
1118                 reload_adda_reg(adapt, iqk_bb_reg_92c, dm_odm->RFCalibrateInfo.IQK_BB_backup,
1119                                 IQK_BB_REG_NUM);
1120
1121                 /*  Restore RX initial gain */
1122                 phy_set_bb_reg(adapt, rFPGA0_XA_LSSIParameter,
1123                                bMaskDWord, 0x00032ed3);
1124                 if (is2t)
1125                         phy_set_bb_reg(adapt, rFPGA0_XB_LSSIParameter,
1126                                        bMaskDWord, 0x00032ed3);
1127
1128                 /* load 0xe30 IQC default value */
1129                 phy_set_bb_reg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
1130                 phy_set_bb_reg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
1131         }
1132 }
1133
1134 static void phy_lc_calibrate(struct adapter *adapt, bool is2t)
1135 {
1136         u8 tmpreg;
1137         u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
1138
1139         /* Check continuous TX and Packet TX */
1140         tmpreg = usb_read8(adapt, 0xd03);
1141
1142         if ((tmpreg&0x70) != 0)
1143                 usb_write8(adapt, 0xd03, tmpreg&0x8F);
1144         else
1145                 usb_write8(adapt, REG_TXPAUSE, 0xFF);
1146
1147         if ((tmpreg&0x70) != 0) {
1148                 /* 1. Read original RF mode */
1149                 /* Path-A */
1150                 rf_a_mode = rtw_hal_read_rfreg(adapt, RF_PATH_A, RF_AC,
1151                                              bMask12Bits);
1152
1153                 /* Path-B */
1154                 if (is2t)
1155                         rf_b_mode = rtw_hal_read_rfreg(adapt, RF_PATH_B, RF_AC,
1156                                                      bMask12Bits);
1157
1158                 /* 2. Set RF mode = standby mode */
1159                 /* Path-A */
1160                 phy_set_rf_reg(adapt, RF_PATH_A, RF_AC, bMask12Bits,
1161                                (rf_a_mode&0x8FFFF)|0x10000);
1162
1163                 /* Path-B */
1164                 if (is2t)
1165                         phy_set_rf_reg(adapt, RF_PATH_B, RF_AC, bMask12Bits,
1166                                        (rf_b_mode&0x8FFFF)|0x10000);
1167         }
1168
1169         /* 3. Read RF reg18 */
1170         lc_cal = rtw_hal_read_rfreg(adapt, RF_PATH_A, RF_CHNLBW, bMask12Bits);
1171
1172         /* 4. Set LC calibration begin bit15 */
1173         phy_set_rf_reg(adapt, RF_PATH_A, RF_CHNLBW, bMask12Bits,
1174                        lc_cal|0x08000);
1175
1176         msleep(100);
1177
1178         /* Restore original situation */
1179         if ((tmpreg&0x70) != 0) {
1180                 /* Deal with continuous TX case */
1181                 /* Path-A */
1182                 usb_write8(adapt, 0xd03, tmpreg);
1183                 phy_set_rf_reg(adapt, RF_PATH_A, RF_AC, bMask12Bits, rf_a_mode);
1184
1185                 /* Path-B */
1186                 if (is2t)
1187                         phy_set_rf_reg(adapt, RF_PATH_B, RF_AC, bMask12Bits,
1188                                        rf_b_mode);
1189         } else {
1190                 /* Deal with Packet TX case */
1191                 usb_write8(adapt, REG_TXPAUSE, 0x00);
1192         }
1193 }
1194
1195 void rtl88eu_phy_iq_calibrate(struct adapter *adapt, bool recovery)
1196 {
1197         struct odm_dm_struct *dm_odm = &adapt->HalData->odmpriv;
1198         s32 result[4][8];
1199         u8 i, final;
1200         bool pathaok, pathbok;
1201         s32 reg_e94, reg_e9c, reg_ea4, reg_eb4, reg_ebc, reg_ec4;
1202         bool is12simular, is13simular, is23simular;
1203         bool singletone = false, carrier_sup = false;
1204         u32 iqk_bb_reg_92c[IQK_BB_REG_NUM] = {
1205                 rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance,
1206                 rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable,
1207                 rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance,
1208                 rOFDM0_XCTxAFE, rOFDM0_XDTxAFE,
1209                 rOFDM0_RxIQExtAnta};
1210         bool is2t;
1211
1212         is2t = false;
1213
1214         if (!(dm_odm->SupportAbility & ODM_RF_CALIBRATION))
1215                 return;
1216
1217         if (singletone || carrier_sup)
1218                 return;
1219
1220         if (recovery) {
1221                 ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD,
1222                              ("phy_iq_calibrate: Return due to recovery!\n"));
1223                 reload_adda_reg(adapt, iqk_bb_reg_92c,
1224                                 dm_odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
1225                 return;
1226         }
1227
1228         memset(result, 0, sizeof(result));
1229         for (i = 0; i < 8; i += 2)
1230                 result[3][i] = 0x100;
1231
1232         final = 0xff;
1233         pathaok = false;
1234         pathbok = false;
1235         is12simular = false;
1236         is23simular = false;
1237         is13simular = false;
1238
1239         for (i = 0; i < 3; i++) {
1240                 phy_iq_calibrate(adapt, result, i, is2t);
1241
1242                 if (i == 1) {
1243                         is12simular = simularity_compare(adapt, result, 0, 1);
1244                         if (is12simular) {
1245                                 final = 0;
1246                                 break;
1247                         }
1248                 }
1249
1250                 if (i == 2) {
1251                         is13simular = simularity_compare(adapt, result, 0, 2);
1252                         if (is13simular) {
1253                                 final = 0;
1254                                 break;
1255                         }
1256                         is23simular = simularity_compare(adapt, result, 1, 2);
1257                         if (is23simular)
1258                                 final = 1;
1259                         else
1260                                 final = 3;
1261                 }
1262         }
1263
1264         for (i = 0; i < 4; i++) {
1265                 reg_e94 = result[i][0];
1266                 reg_e9c = result[i][1];
1267                 reg_ea4 = result[i][2];
1268                 reg_eb4 = result[i][4];
1269                 reg_ebc = result[i][5];
1270                 reg_ec4 = result[i][6];
1271         }
1272
1273         if (final != 0xff) {
1274                 reg_e94 = result[final][0];
1275                 reg_e9c = result[final][1];
1276                 reg_ea4 = result[final][2];
1277                 reg_eb4 = result[final][4];
1278                 reg_ebc = result[final][5];
1279                 dm_odm->RFCalibrateInfo.RegE94 = reg_e94;
1280                 dm_odm->RFCalibrateInfo.RegE9C = reg_e9c;
1281                 dm_odm->RFCalibrateInfo.RegEB4 = reg_eb4;
1282                 dm_odm->RFCalibrateInfo.RegEBC = reg_ebc;
1283                 reg_ec4 = result[final][6];
1284                 pathaok = true;
1285                 pathbok = true;
1286         } else {
1287                 ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
1288                              ("IQK: FAIL use default value\n"));
1289                 dm_odm->RFCalibrateInfo.RegE94 = 0x100;
1290                 dm_odm->RFCalibrateInfo.RegEB4 = 0x100;
1291                 dm_odm->RFCalibrateInfo.RegE9C = 0x0;
1292                 dm_odm->RFCalibrateInfo.RegEBC = 0x0;
1293         }
1294         if (reg_e94 != 0)
1295                 patha_fill_iqk(adapt, pathaok, result, final,
1296                                (reg_ea4 == 0));
1297         if (is2t) {
1298                 if (reg_eb4 != 0)
1299                         pathb_fill_iqk(adapt, pathbok, result, final,
1300                                        (reg_ec4 == 0));
1301         }
1302
1303         if (final < 4) {
1304                 for (i = 0; i < IQK_Matrix_REG_NUM; i++)
1305                         dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[0].Value[0][i] = result[final][i];
1306                 dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[0].bIQKDone = true;
1307         }
1308
1309         save_adda_registers(adapt, iqk_bb_reg_92c,
1310                             dm_odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
1311 }
1312
1313 void rtl88eu_phy_lc_calibrate(struct adapter *adapt)
1314 {
1315         bool singletone = false, carrier_sup = false;
1316         u32 timeout = 2000, timecount = 0;
1317         struct odm_dm_struct *dm_odm = &adapt->HalData->odmpriv;
1318
1319         if (!(dm_odm->SupportAbility & ODM_RF_CALIBRATION))
1320                 return;
1321         if (singletone || carrier_sup)
1322                 return;
1323
1324         while (*(dm_odm->pbScanInProcess) && timecount < timeout) {
1325                 mdelay(50);
1326                 timecount += 50;
1327         }
1328
1329         dm_odm->RFCalibrateInfo.bLCKInProgress = true;
1330
1331         phy_lc_calibrate(adapt, false);
1332
1333         dm_odm->RFCalibrateInfo.bLCKInProgress = false;
1334 }