2 * Copyright (c) Realtek Semiconductor Corp. All rights reserved.
8 * Hardware Initialization and Hardware IO for RTL8185B
10 * Major Change History:
12 * ---------- --------------- -------------------------------
13 * 2006-11-15 Xiong Created
16 * This file is ported from RTL8185B Windows driver.
21 /*--------------------------Include File------------------------------------*/
22 #include <linux/spinlock.h>
25 #include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
26 #include "r8180_93cx6.h" /* Card EEPROM */
28 #include "ieee80211/dot11d.h"
29 /* #define CONFIG_RTL8180_IO_MAP */
30 #define TC_3W_POLL_MAX_TRY_CNT 5
32 static u8 MAC_REG_TABLE[][2] = {
35 * 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in
36 * HwConfigureRTL8185()
37 * 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185().
38 * 0x1F0~0x1F8 set in MacConfig_85BASIC()
40 {0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42},
41 {0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03},
42 {0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03},
43 {0x94, 0x0F}, {0x95, 0x32},
44 {0x96, 0x00}, {0x97, 0x07}, {0xb4, 0x22}, {0xdb, 0x00},
45 {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
46 {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
47 {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
52 * For Flextronics system Logo PCIHCT failure:
53 * 0x1C4~0x1CD set no-zero value to avoid PCI configuration
57 {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24},
58 {0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF},
59 {0x82, 0xFF}, {0x83, 0x03},
61 {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22},
63 {0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22},
69 {0x0c, 0x04}, {0x4c, 0x30}, {0x4d, 0x08}, {0x50, 0x05}, {0x51, 0xf5},
70 {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0xff}, {0x55, 0xff}, {0x56, 0xff},
71 {0x57, 0xff}, {0x58, 0x08}, {0x59, 0x08}, {0x5a, 0x08}, {0x5b, 0x08},
72 {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, {0x63, 0x08}, {0x64, 0x2f},
73 {0x8c, 0x3f}, {0x8d, 0x3f}, {0x8e, 0x3f},
74 {0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff},
75 {0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00},
78 {0x5e, 0x00}, {0x9f, 0x03}
82 static u8 ZEBRA_AGC[] = {
84 0x7E, 0x7E, 0x7E, 0x7E, 0x7D, 0x7C, 0x7B, 0x7A, 0x79, 0x78, 0x77, 0x76,
85 0x75, 0x74, 0x73, 0x72, 0x71, 0x70, 0x6F, 0x6E, 0x6D, 0x6C, 0x6B, 0x6A,
86 0x69, 0x68, 0x67, 0x66, 0x65, 0x64, 0x63, 0x62, 0x48, 0x47, 0x46, 0x45,
87 0x44, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x08, 0x07,
88 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
89 0x00, 0x00, 0x00, 0x00, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f,
90 0x0f, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x15, 0x16, 0x17, 0x17, 0x18, 0x18,
91 0x19, 0x1a, 0x1a, 0x1b, 0x1b, 0x1c, 0x1c, 0x1d, 0x1d, 0x1d, 0x1e, 0x1e,
92 0x1f, 0x1f, 0x1f, 0x20, 0x20, 0x20, 0x20, 0x21, 0x21, 0x21, 0x22, 0x22,
93 0x22, 0x23, 0x23, 0x24, 0x24, 0x25, 0x25, 0x25, 0x26, 0x26, 0x27, 0x27,
94 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F
97 static u32 ZEBRA_RF_RX_GAIN_TABLE[] = {
98 0x0096, 0x0076, 0x0056, 0x0036, 0x0016, 0x01f6, 0x01d6, 0x01b6,
99 0x0196, 0x0176, 0x00F7, 0x00D7, 0x00B7, 0x0097, 0x0077, 0x0057,
100 0x0037, 0x00FB, 0x00DB, 0x00BB, 0x00FF, 0x00E3, 0x00C3, 0x00A3,
101 0x0083, 0x0063, 0x0043, 0x0023, 0x0003, 0x01E3, 0x01C3, 0x01A3,
102 0x0183, 0x0163, 0x0143, 0x0123, 0x0103
105 static u8 OFDM_CONFIG[] = {
106 /* OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX */
107 /* OFDM reg0x3C[4]=1'b1: Enable RX power saving mode */
108 /* ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test */
110 0x10, 0x0F, 0x0A, 0x0C, 0x14, 0xFA, 0xFF, 0x50,
111 0x00, 0x50, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00,
113 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xA8, 0x26,
114 0x32, 0x33, 0x06, 0xA5, 0x6F, 0x55, 0xC8, 0xBB,
116 0x0A, 0xE1, 0x2C, 0x4A, 0x86, 0x83, 0x34, 0x00,
117 0x4F, 0x24, 0x6F, 0xC2, 0x03, 0x40, 0x80, 0x00,
119 0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e,
120 0xD8, 0x3C, 0x7B, 0x10, 0x10
123 /*---------------------------------------------------------------
125 * the code is ported from Windows source code
126 *---------------------------------------------------------------
129 static u8 PlatformIORead1Byte(struct net_device *dev, u32 offset)
131 return read_nic_byte(dev, offset);
134 static void PlatformIOWrite1Byte(struct net_device *dev, u32 offset, u8 data)
136 write_nic_byte(dev, offset, data);
138 * To make sure write operation is completed,
139 * 2005.11.09, by rcnjko.
141 read_nic_byte(dev, offset);
144 static void PlatformIOWrite2Byte(struct net_device *dev, u32 offset, u16 data)
146 write_nic_word(dev, offset, data);
148 * To make sure write operation is completed,
149 * 2005.11.09, by rcnjko.
151 read_nic_word(dev, offset);
154 static void PlatformIOWrite4Byte(struct net_device *dev, u32 offset, u32 data)
156 if (offset == PhyAddr) {
157 /* For Base Band configuration. */
158 unsigned char cmdByte;
159 unsigned long dataBytes;
163 cmdByte = (u8)(data & 0x000000ff);
168 * The critical section is only BB read/write race
169 * condition. Assumption:
170 * 1. We assume NO one will access BB at DIRQL, otherwise,
171 * system will crash for
172 * acquiring the spinlock in such context.
173 * 2. PlatformIOWrite4Byte() MUST NOT be recursive.
175 /* NdisAcquireSpinLock( &(pDevice->IoSpinLock) ); */
177 for (idx = 0; idx < 30; idx++) {
178 /* Make sure command bit is clear before access it. */
179 u1bTmp = PlatformIORead1Byte(dev, PhyAddr);
180 if ((u1bTmp & BIT7) == 0)
186 for (idx = 0; idx < 3; idx++)
187 PlatformIOWrite1Byte(dev, offset+1+idx,
188 ((u8 *)&dataBytes)[idx]);
190 write_nic_byte(dev, offset, cmdByte);
192 /* NdisReleaseSpinLock( &(pDevice->IoSpinLock) ); */
194 write_nic_dword(dev, offset, data);
196 * To make sure write operation is completed, 2005.11.09,
199 read_nic_dword(dev, offset);
203 static void SetOutputEnableOfRfPins(struct net_device *dev)
205 write_nic_word(dev, RFPinsEnable, 0x1bff);
208 static bool HwHSSIThreeWire(struct net_device *dev,
215 /* Check if WE and RE are cleared. */
216 for (TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++) {
217 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
218 if ((u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0)
223 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT) {
225 "HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n",
230 /* RTL8187S HSSI Read/Write Function */
231 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
232 u1bTmp |= RF_SW_CFG_SI; /* reg08[1]=1 Serial Interface(SI) */
233 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
235 /* jong: HW SI read must set reg84[3]=0. */
236 u1bTmp = read_nic_byte(dev, RFPinsSelect);
238 write_nic_byte(dev, RFPinsSelect, u1bTmp);
239 /* Fill up data buffer for write operation. */
241 /* SI - reg274[3:0] : RF register's Address */
243 write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
245 write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
247 /* Set up command: WE or RE. */
249 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
251 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
254 /* Check if DONE is set. */
255 for (TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++) {
256 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
257 if (u1bTmp & SW_3W_CMD1_DONE)
263 write_nic_byte(dev, SW_3W_CMD1, 0);
265 /* Read back data for read operation. */
267 /* Serial Interface : reg363_362[11:0] */
268 *((u16 *)pDataBuf) = read_nic_word(dev, SI_DATA_READ);
269 *((u16 *)pDataBuf) &= 0x0FFF;
275 void RF_WriteReg(struct net_device *dev, u8 offset, u16 data)
277 u16 reg = (data << 4) | (offset & 0x0f);
278 HwHSSIThreeWire(dev, (u8 *)®, true);
281 u16 RF_ReadReg(struct net_device *dev, u8 offset)
283 u16 reg = offset & 0x0f;
284 HwHSSIThreeWire(dev, (u8 *)®, false);
288 static u8 ReadBBPortUchar(struct net_device *dev, u32 addr)
290 PlatformIOWrite4Byte(dev, PhyAddr, addr & 0xffffff7f);
291 return PlatformIORead1Byte(dev, PhyDataR);
294 /* by Owen on 04/07/14 for writing BB register successfully */
295 static void WriteBBPortUchar(struct net_device *dev, u32 Data)
297 PlatformIOWrite4Byte(dev, PhyAddr, Data);
298 ReadBBPortUchar(dev, Data);
303 * Perform Antenna settings with antenna diversity on 87SE.
304 * Created by Roger, 2008.01.25.
306 bool SetAntennaConfig87SE(struct net_device *dev,
307 u8 DefaultAnt, /* 0: Main, 1: Aux. */
308 bool bAntDiversity) /* 1:Enable, 0: Disable. */
310 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
311 bool bAntennaSwitched = true;
312 /* 0x00 = disabled, 0x80 = enabled */
313 u8 ant_diversity_offset = 0x00;
316 * printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n",
317 * DefaultAnt, bAntDiversity);
320 /* Threshold for antenna diversity. */
321 write_phy_cck(dev, 0x0c, 0x09); /* Reg0c : 09 */
323 if (bAntDiversity) /* Enable Antenna Diversity. */
324 ant_diversity_offset = 0x80;
326 if (DefaultAnt == 1) { /* aux Antenna */
327 /* Mac register, aux antenna */
328 write_nic_byte(dev, ANTSEL, 0x00);
330 /* Config CCK RX antenna. */
331 write_phy_cck(dev, 0x11, 0xbb); /* Reg11 : bb */
333 /* Reg01 : 47 | ant_diversity_offset */
334 write_phy_cck(dev, 0x01, 0x47|ant_diversity_offset);
336 /* Config OFDM RX antenna. */
337 write_phy_ofdm(dev, 0x0D, 0x54); /* Reg0d : 54 */
339 write_phy_ofdm(dev, 0x18, 0x32|ant_diversity_offset);
340 } else { /* main Antenna */
341 /* Mac register, main antenna */
342 write_nic_byte(dev, ANTSEL, 0x03);
344 /* Config CCK RX antenna. */
345 write_phy_cck(dev, 0x11, 0x9b); /* Reg11 : 9b */
347 write_phy_cck(dev, 0x01, 0x47|ant_diversity_offset);
349 /* Config OFDM RX antenna. */
350 write_phy_ofdm(dev, 0x0D, 0x5c); /* Reg0d : 5c */
352 write_phy_ofdm(dev, 0x18, 0x32|ant_diversity_offset);
354 priv->CurrAntennaIndex = DefaultAnt; /* Update default settings. */
355 return bAntennaSwitched;
358 *--------------------------------------------------------------
359 * Hardware Initialization.
360 * the code is ported from Windows source code
361 *--------------------------------------------------------------
364 static void ZEBRA_Config_85BASIC_HardCode(struct net_device *dev)
367 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
370 u32 u4bRegOffset, u4bRegValue;
371 u16 u4bRF23, u4bRF24;
377 *===========================================================================
378 * 87S_PCIE :: RADIOCFG.TXT
379 *===========================================================================
383 /* Page1 : reg16-reg30 */
384 RF_WriteReg(dev, 0x00, 0x013f); mdelay(1); /* switch to page1 */
385 u4bRF23 = RF_ReadReg(dev, 0x08); mdelay(1);
386 u4bRF24 = RF_ReadReg(dev, 0x09); mdelay(1);
388 if (u4bRF23 == 0x818 && u4bRF24 == 0x70C) {
390 netdev_info(dev, "card type changed from C- to D-cut\n");
393 /* Page0 : reg0-reg15 */
395 RF_WriteReg(dev, 0x00, 0x009f); mdelay(1);/* 1 */
396 RF_WriteReg(dev, 0x01, 0x06e0); mdelay(1);
397 RF_WriteReg(dev, 0x02, 0x004d); mdelay(1);/* 2 */
398 RF_WriteReg(dev, 0x03, 0x07f1); mdelay(1);/* 3 */
399 RF_WriteReg(dev, 0x04, 0x0975); mdelay(1);
400 RF_WriteReg(dev, 0x05, 0x0c72); mdelay(1);
401 RF_WriteReg(dev, 0x06, 0x0ae6); mdelay(1);
402 RF_WriteReg(dev, 0x07, 0x00ca); mdelay(1);
403 RF_WriteReg(dev, 0x08, 0x0e1c); mdelay(1);
404 RF_WriteReg(dev, 0x09, 0x02f0); mdelay(1);
405 RF_WriteReg(dev, 0x0a, 0x09d0); mdelay(1);
406 RF_WriteReg(dev, 0x0b, 0x01ba); mdelay(1);
407 RF_WriteReg(dev, 0x0c, 0x0640); mdelay(1);
408 RF_WriteReg(dev, 0x0d, 0x08df); mdelay(1);
409 RF_WriteReg(dev, 0x0e, 0x0020); mdelay(1);
410 RF_WriteReg(dev, 0x0f, 0x0990); mdelay(1);
412 /* Page1 : reg16-reg30 */
413 RF_WriteReg(dev, 0x00, 0x013f); mdelay(1);
414 RF_WriteReg(dev, 0x03, 0x0806); mdelay(1);
415 RF_WriteReg(dev, 0x04, 0x03a7); mdelay(1);
416 RF_WriteReg(dev, 0x05, 0x059b); mdelay(1);
417 RF_WriteReg(dev, 0x06, 0x0081); mdelay(1);
418 RF_WriteReg(dev, 0x07, 0x01A0); mdelay(1);
420 * Don't write RF23/RF24 to make a difference between 87S C cut and D cut.
421 * asked by SD3 stevenl.
423 RF_WriteReg(dev, 0x0a, 0x0001); mdelay(1);
424 RF_WriteReg(dev, 0x0b, 0x0418); mdelay(1);
427 RF_WriteReg(dev, 0x0c, 0x0fbe); mdelay(1);
428 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1);
430 RF_WriteReg(dev, 0x0e, 0x0807); mdelay(1);
432 RF_WriteReg(dev, 0x0c, 0x0fbe); mdelay(1);
433 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1);
435 RF_WriteReg(dev, 0x0e, 0x0806); mdelay(1);
438 RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1);
439 RF_WriteReg(dev, 0x00, 0x01d7); mdelay(1); /* 6 */
440 RF_WriteReg(dev, 0x03, 0x0e00); mdelay(1);
441 RF_WriteReg(dev, 0x04, 0x0e50); mdelay(1);
443 for (i = 0; i <= 36; i++) {
444 RF_WriteReg(dev, 0x01, i); mdelay(1);
445 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
448 RF_WriteReg(dev, 0x05, 0x0203); mdelay(1); /* 203, 343 */
449 RF_WriteReg(dev, 0x06, 0x0200); mdelay(1); /* 400 */
450 /* switch to reg16-reg30, and HSSI disable 137 */
451 RF_WriteReg(dev, 0x00, 0x0137); mdelay(1);
452 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
454 /* Z4 synthesizer loop filter setting, 392 */
455 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1);
456 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
458 /* switch to reg0-reg15, and HSSI disable */
459 RF_WriteReg(dev, 0x00, 0x0037); mdelay(1);
460 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
462 /* CBC on, Tx Rx disable, High gain */
463 RF_WriteReg(dev, 0x04, 0x0160); mdelay(1);
464 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
466 /* Z4 setted channel 1 */
467 RF_WriteReg(dev, 0x07, 0x0080); mdelay(1);
468 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
470 RF_WriteReg(dev, 0x02, 0x088D); mdelay(1); /* LC calibration */
471 mdelay(200); /* Deay 200 ms. */ /* 0xfd */
472 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
473 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
475 /* switch to reg16-reg30 137, and HSSI disable 137 */
476 RF_WriteReg(dev, 0x00, 0x0137); mdelay(1);
477 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
479 RF_WriteReg(dev, 0x07, 0x0000); mdelay(1);
480 RF_WriteReg(dev, 0x07, 0x0180); mdelay(1);
481 RF_WriteReg(dev, 0x07, 0x0220); mdelay(1);
482 RF_WriteReg(dev, 0x07, 0x03E0); mdelay(1);
484 /* DAC calibration off 20070702 */
485 RF_WriteReg(dev, 0x06, 0x00c1); mdelay(1);
486 RF_WriteReg(dev, 0x0a, 0x0001); mdelay(1);
487 /* For crystal calibration, added by Roger, 2007.12.11. */
488 if (priv->bXtalCalibration) { /* reg 30. */
490 * enable crystal calibration.
491 * RF Reg[30], (1)Xin:[12:9], Xout:[8:5], addr[4:0].
492 * (2)PA Pwr delay timer[15:14], default: 2.4us,
494 * (3)RF signal on/off when calibration[13], default: on,
496 * So we should minus 4 BITs offset.
498 RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5) |
499 (priv->XtalCal_Xout<<1) | BIT11 | BIT9); mdelay(1);
500 printk("ZEBRA_Config_85BASIC_HardCode(): (%02x)\n",
501 (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) |
504 /* using default value. Xin=6, Xout=6. */
505 RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1);
507 /* switch to reg0-reg15, and HSSI enable */
508 RF_WriteReg(dev, 0x00, 0x00bf); mdelay(1);
509 /* Rx BB start calibration, 00c//+edward */
510 RF_WriteReg(dev, 0x0d, 0x08df); mdelay(1);
511 /* temperature meter off */
512 RF_WriteReg(dev, 0x02, 0x004d); mdelay(1);
513 RF_WriteReg(dev, 0x04, 0x0975); mdelay(1); /* Rx mode */
514 mdelay(10); /* Deay 10 ms.*/ /* 0xfe */
515 mdelay(10); /* Deay 10 ms.*/ /* 0xfe */
516 mdelay(10); /* Deay 10 ms.*/ /* 0xfe */
517 /* Rx mode*/ /*+edward */
518 RF_WriteReg(dev, 0x00, 0x0197); mdelay(1);
519 /* Rx mode*/ /*+edward */
520 RF_WriteReg(dev, 0x05, 0x05ab); mdelay(1);
521 /* Rx mode*/ /*+edward */
522 RF_WriteReg(dev, 0x00, 0x009f); mdelay(1);
523 /* Rx mode*/ /*+edward */
524 RF_WriteReg(dev, 0x01, 0x0000); mdelay(1);
525 /* Rx mode*/ /*+edward */
526 RF_WriteReg(dev, 0x02, 0x0000); mdelay(1);
527 /* power save parameters. */
528 u1b24E = read_nic_byte(dev, 0x24E);
529 write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6))));
531 /*======================================================================
533 *======================================================================
535 *======================================================================
537 * [POWER SAVE] Power Saving Parameters by jong. 2007-11-27
538 * CCK reg0x00[7]=1'b1 :power saving for TX (default)
539 * CCK reg0x00[6]=1'b1: power saving for RX (default)
540 * CCK reg0x06[4]=1'b1: turn off channel estimation related
541 * circuits if not doing channel estimation.
542 * CCK reg0x06[3]=1'b1: turn off unused circuits before cca = 1
543 * CCK reg0x06[2]=1'b1: turn off cck's circuit if macrst =0
546 write_phy_cck(dev, 0x00, 0xc8);
547 write_phy_cck(dev, 0x06, 0x1c);
548 write_phy_cck(dev, 0x10, 0x78);
549 write_phy_cck(dev, 0x2e, 0xd0);
550 write_phy_cck(dev, 0x2f, 0x06);
551 write_phy_cck(dev, 0x01, 0x46);
554 write_nic_byte(dev, CCK_TXAGC, 0x10);
555 write_nic_byte(dev, OFDM_TXAGC, 0x1B);
556 write_nic_byte(dev, ANTSEL, 0x03);
561 *======================================================================
563 *======================================================================
566 write_phy_ofdm(dev, 0x00, 0x12);
568 for (i = 0; i < 128; i++) {
570 data = ZEBRA_AGC[i+1];
572 data = data | 0x0000008F;
574 addr = i + 0x80; /* enable writing AGC table */
576 addr = addr | 0x0000008E;
578 WriteBBPortUchar(dev, data);
579 WriteBBPortUchar(dev, addr);
580 WriteBBPortUchar(dev, 0x0000008E);
583 PlatformIOWrite4Byte(dev, PhyAddr, 0x00001080); /* Annie, 2006-05-05 */
586 *======================================================================
588 *======================================================================
590 *======================================================================
593 for (i = 0; i < 60; i++) {
595 u4bRegValue = OFDM_CONFIG[i];
597 WriteBBPortUchar(dev,
599 (u4bRegOffset & 0x7f) |
600 ((u4bRegValue & 0xff) << 8)));
604 *======================================================================
606 *======================================================================
609 * Config Sw/Hw Combinational Antenna Diversity. Added by Roger,
612 SetAntennaConfig87SE(dev, priv->bDefaultAntenna1,
613 priv->bSwAntennaDiverity);
617 void UpdateInitialGain(struct net_device *dev)
619 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
622 if (priv->eRFPowerState != eRfOn) {
623 /* Don't access BB/RF under disable PLL situation.
624 * RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain -
625 * pHalData->eRFPowerState!=eRfOn\n"));
626 * Back to the original state
628 priv->InitialGain = priv->InitialGainBackUp;
632 switch (priv->InitialGain) {
633 case 1: /* m861dBm */
634 write_phy_ofdm(dev, 0x17, 0x26); mdelay(1);
635 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
636 write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1);
639 case 2: /* m862dBm */
640 write_phy_ofdm(dev, 0x17, 0x36); mdelay(1);
641 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
642 write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1);
645 case 3: /* m863dBm */
646 write_phy_ofdm(dev, 0x17, 0x36); mdelay(1);
647 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
648 write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1);
651 case 4: /* m864dBm */
652 write_phy_ofdm(dev, 0x17, 0x46); mdelay(1);
653 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
654 write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1);
658 write_phy_ofdm(dev, 0x17, 0x46); mdelay(1);
659 write_phy_ofdm(dev, 0x24, 0x96); mdelay(1);
660 write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1);
664 write_phy_ofdm(dev, 0x17, 0x56); mdelay(1);
665 write_phy_ofdm(dev, 0x24, 0x96); mdelay(1);
666 write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1);
670 write_phy_ofdm(dev, 0x17, 0x56); mdelay(1);
671 write_phy_ofdm(dev, 0x24, 0xa6); mdelay(1);
672 write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1);
676 write_phy_ofdm(dev, 0x17, 0x66); mdelay(1);
677 write_phy_ofdm(dev, 0x24, 0xb6); mdelay(1);
678 write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1);
682 write_phy_ofdm(dev, 0x17, 0x26); mdelay(1);
683 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
684 write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1);
690 * Tx Power tracking mechanism routine on 87SE.
691 * Created by Roger, 2007.12.11.
693 static void InitTxPwrTracking87SE(struct net_device *dev)
697 u4bRfReg = RF_ReadReg(dev, 0x02);
699 /* Enable Thermal meter indication. */
700 RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN); mdelay(1);
703 static void PhyConfig8185(struct net_device *dev)
705 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
706 write_nic_dword(dev, RCR, priv->ReceiveConfig);
707 priv->RFProgType = read_nic_byte(dev, CONFIG4) & 0x03;
709 ZEBRA_Config_85BASIC_HardCode(dev);
710 /* Set default initial gain state to 4, approved by SD3 DZ, by Bruce,
713 if (priv->bDigMechanism) {
714 if (priv->InitialGain == 0)
715 priv->InitialGain = 4;
719 * Enable thermal meter indication to implement TxPower tracking
720 * on 87SE. We initialize thermal meter here to avoid unsuccessful
721 * configuration. Added by Roger, 2007.12.11.
723 if (priv->bTxPowerTrack)
724 InitTxPwrTracking87SE(dev);
726 priv->InitialGainBackUp = priv->InitialGain;
727 UpdateInitialGain(dev);
732 static void HwConfigureRTL8185(struct net_device *dev)
735 * RTL8185_TODO: Determine Retrylimit, TxAGC,
736 * AutoRateFallback control.
738 u8 bUNIVERSAL_CONTROL_RL = 0;
739 u8 bUNIVERSAL_CONTROL_AGC = 1;
740 u8 bUNIVERSAL_CONTROL_ANT = 1;
741 u8 bAUTO_RATE_FALLBACK_CTL = 1;
743 write_nic_word(dev, BRSR, 0x0fff);
745 val8 = read_nic_byte(dev, CW_CONF);
747 if (bUNIVERSAL_CONTROL_RL)
752 write_nic_byte(dev, CW_CONF, val8);
755 val8 = read_nic_byte(dev, TXAGC_CTL);
756 if (bUNIVERSAL_CONTROL_AGC) {
757 write_nic_byte(dev, CCK_TXAGC, 128);
758 write_nic_byte(dev, OFDM_TXAGC, 128);
765 write_nic_byte(dev, TXAGC_CTL, val8);
767 /* Tx Antenna including Feedback control */
768 val8 = read_nic_byte(dev, TXAGC_CTL);
770 if (bUNIVERSAL_CONTROL_ANT) {
771 write_nic_byte(dev, ANTSEL, 0x00);
774 val8 = val8 & (val8|0x02); /* xiong-2006-11-15 */
777 write_nic_byte(dev, TXAGC_CTL, val8);
779 /* Auto Rate fallback control */
780 val8 = read_nic_byte(dev, RATE_FALLBACK);
782 if (bAUTO_RATE_FALLBACK_CTL) {
783 val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1;
785 /* <RJ_TODO_8185B> We shall set up the ARFR according
788 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); /* set 1M ~ 54Mbps. */
790 write_nic_byte(dev, RATE_FALLBACK, val8);
793 static void MacConfig_85BASIC_HardCode(struct net_device *dev)
796 *======================================================================
798 *======================================================================
801 u32 u4bRegOffset, u4bRegValue, u4bPageIndex = 0;
804 nLinesRead = sizeof(MAC_REG_TABLE)/2;
806 for (i = 0; i < nLinesRead; i++) { /* nLinesRead=101 */
807 u4bRegOffset = MAC_REG_TABLE[i][0];
808 u4bRegValue = MAC_REG_TABLE[i][1];
810 if (u4bRegOffset == 0x5e)
811 u4bPageIndex = u4bRegValue;
813 u4bRegOffset |= (u4bPageIndex << 8);
815 write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue);
817 /* ================================================================= */
820 static void MacConfig_85BASIC(struct net_device *dev)
824 MacConfig_85BASIC_HardCode(dev);
826 /* ================================================================= */
828 /* Follow TID_AC_MAP of WMac. */
829 write_nic_word(dev, TID_AC_MAP, 0xfa50);
831 /* Interrupt Migration, Jong suggested we use set 0x0000 first,
832 * 2005.12.14, by rcnjko.
834 write_nic_word(dev, IntMig, 0x0000);
836 /* Prevent TPC to cause CRC error. Added by Annie, 2006-06-10. */
837 PlatformIOWrite4Byte(dev, 0x1F0, 0x00000000);
838 PlatformIOWrite4Byte(dev, 0x1F4, 0x00000000);
839 PlatformIOWrite1Byte(dev, 0x1F8, 0x00);
841 /* Asked for by SD3 CM Lin, 2006.06.27, by rcnjko. */
844 * power save parameter based on
845 * "87SE power save parameters 20071127.doc", as follow.
848 /* Enable DA10 TX power saving */
849 u1DA = read_nic_byte(dev, PHYPR);
850 write_nic_byte(dev, PHYPR, (u1DA | BIT2));
853 write_nic_word(dev, 0x360, 0x1000);
854 write_nic_word(dev, 0x362, 0x1000);
857 write_nic_word(dev, 0x370, 0x0560);
858 write_nic_word(dev, 0x372, 0x0560);
859 write_nic_word(dev, 0x374, 0x0DA4);
860 write_nic_word(dev, 0x376, 0x0DA4);
861 write_nic_word(dev, 0x378, 0x0560);
862 write_nic_word(dev, 0x37A, 0x0560);
863 write_nic_word(dev, 0x37C, 0x00EC);
864 write_nic_word(dev, 0x37E, 0x00EC); /* +edward */
865 write_nic_byte(dev, 0x24E, 0x01);
868 static u8 GetSupportedWirelessMode8185(struct net_device *dev)
870 return WIRELESS_MODE_B | WIRELESS_MODE_G;
873 static void ActUpdateChannelAccessSetting(struct net_device *dev,
874 WIRELESS_MODE WirelessMode,
875 PCHANNEL_ACCESS_SETTING ChnlAccessSetting)
881 * TODO: We still don't know how to set up these registers,
882 * just follow WMAC to verify 8185B FPAG.
885 * Jong said CWmin/CWmax register are not functional in 8185B,
886 * so we shall fill channel access realted register into AC
887 * parameter registers,
891 /* Suggested by Jong, 2005.12.08. */
892 ChnlAccessSetting->SIFS_Timer = 0x22;
893 ChnlAccessSetting->DIFS_Timer = 0x1C; /* 2006.06.02, by rcnjko. */
894 ChnlAccessSetting->SlotTimeTimer = 9; /* 2006.06.02, by rcnjko. */
896 * Suggested by wcchu, it is the default value of EIFS register,
899 ChnlAccessSetting->EIFS_Timer = 0x5B;
900 ChnlAccessSetting->CWminIndex = 3; /* 2006.06.02, by rcnjko. */
901 ChnlAccessSetting->CWmaxIndex = 7; /* 2006.06.02, by rcnjko. */
903 write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer);
905 * Rewrited from directly use PlatformEFIOWrite1Byte(),
906 * by Annie, 2006-03-29.
908 write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer);
910 write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer);
913 * <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS
914 * register, 2005.12.08.
916 write_nic_byte(dev, AckTimeOutReg, 0x5B);
918 for (eACI = 0; eACI < AC_MAX; eACI++)
919 write_nic_byte(dev, ACM_CONTROL, 0);
922 static void ActSetWirelessMode8185(struct net_device *dev, u8 btWirelessMode)
924 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
925 struct ieee80211_device *ieee = priv->ieee80211;
926 u8 btSupportedWirelessMode = GetSupportedWirelessMode8185(dev);
928 if ((btWirelessMode & btSupportedWirelessMode) == 0) {
930 * Don't switch to unsupported wireless mode, 2006.02.15,
933 DMESGW("ActSetWirelessMode8185(): WirelessMode(%d) is not supported (%d)!\n",
934 btWirelessMode, btSupportedWirelessMode);
938 /* 1. Assign wireless mode to switch if necessary. */
939 if (btWirelessMode == WIRELESS_MODE_AUTO) {
940 if ((btSupportedWirelessMode & WIRELESS_MODE_A)) {
941 btWirelessMode = WIRELESS_MODE_A;
942 } else if (btSupportedWirelessMode & WIRELESS_MODE_G) {
943 btWirelessMode = WIRELESS_MODE_G;
945 } else if ((btSupportedWirelessMode & WIRELESS_MODE_B)) {
946 btWirelessMode = WIRELESS_MODE_B;
948 DMESGW("ActSetWirelessMode8185(): No valid wireless mode supported, btSupportedWirelessMode(%x)!!!\n",
949 btSupportedWirelessMode);
950 btWirelessMode = WIRELESS_MODE_B;
955 * 2. Swtich band: RF or BB specific actions,
956 * for example, refresh tables in omc8255, or change initial gain if
957 * necessary. Nothing to do for Zebra to switch band. Update current
958 * wireless mode if we switch to specified band successfully.
961 ieee->mode = (WIRELESS_MODE)btWirelessMode;
963 /* 3. Change related setting. */
964 if (ieee->mode == WIRELESS_MODE_A)
965 DMESG("WIRELESS_MODE_A\n");
966 else if (ieee->mode == WIRELESS_MODE_B)
967 DMESG("WIRELESS_MODE_B\n");
968 else if (ieee->mode == WIRELESS_MODE_G)
969 DMESG("WIRELESS_MODE_G\n");
971 ActUpdateChannelAccessSetting(dev, ieee->mode,
972 &priv->ChannelAccessSetting);
975 void rtl8185b_irq_enable(struct net_device *dev)
977 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
979 priv->irq_enabled = 1;
980 write_nic_dword(dev, IMR, priv->IntrMask);
983 static void MgntDisconnectIBSS(struct net_device *dev)
985 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
988 for (i = 0; i < 6; i++)
989 priv->ieee80211->current_network.bssid[i] = 0x55;
993 priv->ieee80211->state = IEEE80211_NOLINK;
997 * Vista add a Adhoc profile, HW radio off until
998 * OID_DOT11_RESET_REQUEST Driver would set MSR=NO_LINK,
999 * then HW Radio ON, MgntQueue Stuck. Because Bcn DMA isn't
1000 * complete, mgnt queue would stuck until Bcn packet send.
1002 * Disable Beacon Queue Own bit, suggested by jong
1004 ieee80211_stop_send_beacons(priv->ieee80211);
1006 priv->ieee80211->link_change(dev);
1007 notify_wx_assoc_event(priv->ieee80211);
1010 static void MlmeDisassociateRequest(struct net_device *dev, u8 *asSta, u8 asRsn)
1012 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1015 SendDisassociation(priv->ieee80211, asSta, asRsn);
1017 if (memcmp(priv->ieee80211->current_network.bssid, asSta, 6) == 0) {
1018 /* ShuChen TODO: change media status. */
1020 for (i = 0; i < 6; i++)
1021 priv->ieee80211->current_network.bssid[i] = 0x22;
1023 ieee80211_disassociate(priv->ieee80211);
1027 static void MgntDisconnectAP(struct net_device *dev, u8 asRsn)
1029 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1032 * Commented out by rcnjko, 2005.01.27:
1033 * I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE().
1035 * 2004/09/15, kcwu, the key should be cleared, or the new
1036 * handshaking will not success
1038 * In WPA WPA2 need to Clear all key ... because new key will set
1039 * after new handshaking. 2004.10.11, by rcnjko.
1041 MlmeDisassociateRequest(dev, priv->ieee80211->current_network.bssid,
1044 priv->ieee80211->state = IEEE80211_NOLINK;
1047 static bool MgntDisconnect(struct net_device *dev, u8 asRsn)
1049 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1051 * Schedule an workitem to wake up for ps mode, 070109, by rcnjko.
1054 if (IS_DOT11D_ENABLE(priv->ieee80211))
1055 Dot11d_Reset(priv->ieee80211);
1056 /* In adhoc mode, update beacon frame. */
1057 if (priv->ieee80211->state == IEEE80211_LINKED) {
1058 if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
1059 MgntDisconnectIBSS(dev);
1061 if (priv->ieee80211->iw_mode == IW_MODE_INFRA) {
1063 * We clear key here instead of MgntDisconnectAP()
1064 * because that MgntActSet_802_11_DISASSOCIATE()
1065 * is an interface called by OS, e.g.
1066 * OID_802_11_DISASSOCIATE in Windows while as
1067 * MgntDisconnectAP() is used to handle
1068 * disassociation related things to AP, e.g. send
1069 * Disassoc frame to AP. 2005.01.27, by rcnjko.
1071 MgntDisconnectAP(dev, asRsn);
1073 /* Indicate Disconnect, 2005.02.23, by rcnjko. */
1079 * Chang RF Power State.
1080 * Note that, only MgntActSet_RF_State() is allowed to set
1086 static bool SetRFPowerState(struct net_device *dev,
1087 RT_RF_POWER_STATE eRFPowerState)
1089 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1090 bool bResult = false;
1092 if (eRFPowerState == priv->eRFPowerState)
1095 bResult = SetZebraRFPowerState8185(dev, eRFPowerState);
1100 bool MgntActSet_RF_State(struct net_device *dev,
1101 RT_RF_POWER_STATE StateToSet, u32 ChangeSource)
1103 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1104 bool bActionAllowed = false;
1105 bool bConnectBySSID = false;
1106 RT_RF_POWER_STATE rtState;
1107 u16 RFWaitCounter = 0;
1110 * Prevent the race condition of RF state change. By Bruce,
1111 * 2007-11-28. Only one thread can change the RF state at one time,
1112 * and others should wait to be executed.
1115 spin_lock_irqsave(&priv->rf_ps_lock, flag);
1116 if (priv->RFChangeInProgress) {
1117 spin_unlock_irqrestore(&priv->rf_ps_lock, flag);
1118 /* Set RF after the previous action is done. */
1119 while (priv->RFChangeInProgress) {
1121 udelay(1000); /* 1 ms */
1124 * Wait too long, return FALSE to avoid
1127 if (RFWaitCounter > 1000) { /* 1sec */
1128 printk("MgntActSet_RF_State(): Wait too long to set RF\n");
1129 /* TODO: Reset RF state? */
1134 priv->RFChangeInProgress = true;
1135 spin_unlock_irqrestore(&priv->rf_ps_lock, flag);
1139 rtState = priv->eRFPowerState;
1141 switch (StateToSet) {
1144 * Turn On RF no matter the IPS setting because we need to
1145 * update the RF state to Ndis under Vista, or the Windows
1146 * does not allow the driver to perform site survey any
1147 * more. By Bruce, 2007-10-02.
1149 priv->RfOffReason &= (~ChangeSource);
1151 if (!priv->RfOffReason) {
1152 priv->RfOffReason = 0;
1153 bActionAllowed = true;
1155 if (rtState == eRfOff &&
1156 ChangeSource >= RF_CHANGE_BY_HW)
1157 bConnectBySSID = true;
1162 /* 070125, rcnjko: we always keep connected in AP mode. */
1164 if (priv->RfOffReason > RF_CHANGE_BY_IPS) {
1167 * Disconnect to current BSS when radio off.
1170 * Calling MgntDisconnect() instead of
1171 * MgntActSet_802_11_DISASSOCIATE(), because
1172 * we do NOT need to set ssid to dummy ones.
1174 MgntDisconnect(dev, disas_lv_ss);
1176 * Clear content of bssDesc[] and bssDesc4Query[]
1177 * to avoid reporting old bss to UI.
1181 priv->RfOffReason |= ChangeSource;
1182 bActionAllowed = true;
1185 priv->RfOffReason |= ChangeSource;
1186 bActionAllowed = true;
1192 if (bActionAllowed) {
1193 /* Config HW to the specified mode. */
1194 SetRFPowerState(dev, StateToSet);
1197 /* Release RF spinlock */
1198 spin_lock_irqsave(&priv->rf_ps_lock, flag);
1199 priv->RFChangeInProgress = false;
1200 spin_unlock_irqrestore(&priv->rf_ps_lock, flag);
1201 return bActionAllowed;
1204 static void InactivePowerSave(struct net_device *dev)
1206 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1208 * This flag "bSwRfProcessing", indicates the status of IPS
1209 * procedure, should be set if the IPS workitem is really
1210 * scheduled. The old code, sets this flag before scheduling the
1211 * IPS workitem and however, at the same time the previous IPS
1212 * workitem did not end yet, fails to schedule the current
1213 * workitem. Thus, bSwRfProcessing blocks the IPS procedure of
1216 priv->bSwRfProcessing = true;
1218 MgntActSet_RF_State(dev, priv->eInactivePowerState, RF_CHANGE_BY_IPS);
1221 * To solve CAM values miss in RF OFF, rewrite CAM values after
1222 * RF ON. By Bruce, 2007-09-20.
1225 priv->bSwRfProcessing = false;
1230 * Enter the inactive power save mode. RF will be off
1232 void IPSEnter(struct net_device *dev)
1234 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1235 RT_RF_POWER_STATE rtState;
1236 if (priv->bInactivePs) {
1237 rtState = priv->eRFPowerState;
1240 * Do not enter IPS in the following conditions:
1241 * (1) RF is already OFF or
1242 * Sleep (2) bSwRfProcessing (indicates the IPS is still
1243 * under going) (3) Connected (only disconnected can
1244 * trigger IPS)(4) IBSS (send Beacon)
1245 * (5) AP mode (send Beacon)
1247 if (rtState == eRfOn && !priv->bSwRfProcessing
1248 && (priv->ieee80211->state != IEEE80211_LINKED)) {
1249 priv->eInactivePowerState = eRfOff;
1250 InactivePowerSave(dev);
1254 void IPSLeave(struct net_device *dev)
1256 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1257 RT_RF_POWER_STATE rtState;
1258 if (priv->bInactivePs) {
1259 rtState = priv->eRFPowerState;
1260 if ((rtState == eRfOff || rtState == eRfSleep) &&
1261 !priv->bSwRfProcessing
1262 && priv->RfOffReason <= RF_CHANGE_BY_IPS) {
1263 priv->eInactivePowerState = eRfOn;
1264 InactivePowerSave(dev);
1269 void rtl8185b_adapter_start(struct net_device *dev)
1271 struct r8180_priv *priv = ieee80211_priv(dev);
1272 struct ieee80211_device *ieee = priv->ieee80211;
1274 u8 SupportedWirelessMode;
1275 u8 InitWirelessMode;
1276 u8 bInvalidWirelessMode = 0;
1282 write_nic_byte(dev, 0x24e, (BIT5|BIT6|BIT0));
1285 priv->dma_poll_mask = 0;
1286 priv->dma_poll_stop_mask = 0;
1288 HwConfigureRTL8185(dev);
1289 write_nic_dword(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
1290 write_nic_word(dev, MAC4, ((u32 *)dev->dev_addr)[1] & 0xffff);
1291 /* default network type to 'No Link' */
1292 write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3);
1293 write_nic_word(dev, BcnItv, 100);
1294 write_nic_word(dev, AtimWnd, 2);
1295 PlatformIOWrite2Byte(dev, FEMR, 0xFFFF);
1296 write_nic_byte(dev, WPA_CONFIG, 0);
1297 MacConfig_85BASIC(dev);
1298 /* Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07,
1301 /* BT_DEMO_BOARD type */
1302 PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a);
1305 *---------------------------------------------------------------------
1306 * Set up PHY related.
1307 *---------------------------------------------------------------------
1309 /* Enable Config3.PARAM_En to revise AnaaParm. */
1310 write_nic_byte(dev, CR9346, 0xc0); /* enable config register write */
1311 tmpu8 = read_nic_byte(dev, CONFIG3);
1312 write_nic_byte(dev, CONFIG3, (tmpu8 | CONFIG3_PARM_En));
1313 /* Turn on Analog power. */
1314 /* Asked for by William, otherwise, MAC 3-wire can't work,
1315 * 2006.06.27, by rcnjko.
1317 write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
1318 write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
1319 write_nic_word(dev, ANAPARAM3, 0x0010);
1321 write_nic_byte(dev, CONFIG3, tmpu8);
1322 write_nic_byte(dev, CR9346, 0x00);
1323 /* enable EEM0 and EEM1 in 9346CR */
1324 btCR9346 = read_nic_byte(dev, CR9346);
1325 write_nic_byte(dev, CR9346, (btCR9346 | 0xC0));
1327 /* B cut use LED1 to control HW RF on/off */
1328 TmpU1b = read_nic_byte(dev, CONFIG5);
1329 TmpU1b = TmpU1b & ~BIT3;
1330 write_nic_byte(dev, CONFIG5, TmpU1b);
1332 /* disable EEM0 and EEM1 in 9346CR */
1333 btCR9346 &= ~(0xC0);
1334 write_nic_byte(dev, CR9346, btCR9346);
1336 /* Enable Led (suggested by Jong) */
1337 /* B-cut RF Radio on/off 5e[3]=0 */
1338 btPSR = read_nic_byte(dev, PSR);
1339 write_nic_byte(dev, PSR, (btPSR | BIT3));
1340 /* setup initial timing for RFE. */
1341 write_nic_word(dev, RFPinsOutput, 0x0480);
1342 SetOutputEnableOfRfPins(dev);
1343 write_nic_word(dev, RFPinsSelect, 0x2488);
1349 * We assume RegWirelessMode has already been initialized before,
1350 * however, we has to validate the wireless mode here and provide a
1351 * reasonable initialized value if necessary. 2005.01.13,
1354 SupportedWirelessMode = GetSupportedWirelessMode8185(dev);
1355 if ((ieee->mode != WIRELESS_MODE_B) &&
1356 (ieee->mode != WIRELESS_MODE_G) &&
1357 (ieee->mode != WIRELESS_MODE_A) &&
1358 (ieee->mode != WIRELESS_MODE_AUTO)) {
1359 /* It should be one of B, G, A, or AUTO. */
1360 bInvalidWirelessMode = 1;
1362 /* One of B, G, A, or AUTO. */
1363 /* Check if the wireless mode is supported by RF. */
1364 if ((ieee->mode != WIRELESS_MODE_AUTO) &&
1365 (ieee->mode & SupportedWirelessMode) == 0) {
1366 bInvalidWirelessMode = 1;
1370 if (bInvalidWirelessMode || ieee->mode == WIRELESS_MODE_AUTO) {
1371 /* Auto or other invalid value. */
1372 /* Assigne a wireless mode to initialize. */
1373 if ((SupportedWirelessMode & WIRELESS_MODE_A)) {
1374 InitWirelessMode = WIRELESS_MODE_A;
1375 } else if ((SupportedWirelessMode & WIRELESS_MODE_G)) {
1376 InitWirelessMode = WIRELESS_MODE_G;
1377 } else if ((SupportedWirelessMode & WIRELESS_MODE_B)) {
1378 InitWirelessMode = WIRELESS_MODE_B;
1380 DMESGW("InitializeAdapter8185(): No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n",
1381 SupportedWirelessMode);
1382 InitWirelessMode = WIRELESS_MODE_B;
1385 /* Initialize RegWirelessMode if it is not a valid one. */
1386 if (bInvalidWirelessMode)
1387 ieee->mode = (WIRELESS_MODE)InitWirelessMode;
1390 /* One of B, G, A. */
1391 InitWirelessMode = ieee->mode;
1393 priv->eRFPowerState = eRfOff;
1394 priv->RfOffReason = 0;
1396 MgntActSet_RF_State(dev, eRfOn, 0);
1399 * If inactive power mode is enabled, disable rf while in
1400 * disconnected state.
1402 if (priv->bInactivePs)
1403 MgntActSet_RF_State(dev , eRfOff, RF_CHANGE_BY_IPS);
1405 ActSetWirelessMode8185(dev, (u8)(InitWirelessMode));
1407 /* ----------------------------------------------------------------- */
1409 rtl8185b_irq_enable(dev);
1411 netif_start_queue(dev);
1414 void rtl8185b_rx_enable(struct net_device *dev)
1417 /* for now we accept data, management & ctl frame*/
1418 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1421 if (dev->flags & IFF_PROMISC)
1422 DMESG("NIC in promisc mode");
1424 if (priv->ieee80211->iw_mode == IW_MODE_MONITOR || dev->flags &
1426 priv->ReceiveConfig = priv->ReceiveConfig & (~RCR_APM);
1427 priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP;
1430 if (priv->ieee80211->iw_mode == IW_MODE_MONITOR)
1431 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF |
1432 RCR_APWRMGT | RCR_AICV;
1435 if (priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
1436 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACRC32;
1438 write_nic_dword(dev, RCR, priv->ReceiveConfig);
1442 cmd = read_nic_byte(dev, CMD);
1443 write_nic_byte(dev, CMD, cmd | (1<<CMD_RX_ENABLE_SHIFT));
1447 void rtl8185b_tx_enable(struct net_device *dev)
1451 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1453 write_nic_dword(dev, TCR, priv->TransmitConfig);
1454 byte = read_nic_byte(dev, MSR);
1455 byte |= MSR_LINK_ENEDCA;
1456 write_nic_byte(dev, MSR, byte);
1460 cmd = read_nic_byte(dev, CMD);
1461 write_nic_byte(dev, CMD, cmd | (1<<CMD_TX_ENABLE_SHIFT));