drivers/staging/r8188eu/include/odm_RegDefine11N.h

   1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */
   3
   4 #ifndef __ODM_REGDEFINE11N_H__
   5 #define __ODM_REGDEFINE11N_H__
   6
   7 /* 2 RF REG LIST */
   8 #define ODM_REG_RF_MODE_11N                             0x00
   9 #define ODM_REG_RF_0B_11N                               0x0B
  10 #define ODM_REG_CHNBW_11N                               0x18
  11 #define ODM_REG_T_METER_11N                             0x24
  12 #define ODM_REG_RF_25_11N                               0x25
  13 #define ODM_REG_RF_26_11N                               0x26
  14 #define ODM_REG_RF_27_11N                               0x27
  15 #define ODM_REG_RF_2B_11N                               0x2B
  16 #define ODM_REG_RF_2C_11N                               0x2C
  17 #define ODM_REG_RXRF_A3_11N                             0x3C
  18 #define ODM_REG_T_METER_92D_11N                 0x42
  19 #define ODM_REG_T_METER_88E_11N                 0x42
  20
  21 /* 2 BB REG LIST */
  22 /* PAGE 8 */
  23 #define ODM_REG_BB_CTRL_11N                             0x800
  24 #define ODM_REG_RF_PIN_11N                              0x804
  25 #define ODM_REG_PSD_CTRL_11N                            0x808
  26 #define ODM_REG_TX_ANT_CTRL_11N                 0x80C
  27 #define ODM_REG_BB_PWR_SAV5_11N                 0x818
  28 #define ODM_REG_CCK_RPT_FORMAT_11N              0x824
  29 #define ODM_REG_RX_DEFUALT_A_11N                0x858
  30 #define ODM_REG_RX_DEFUALT_B_11N                0x85A
  31 #define ODM_REG_BB_PWR_SAV3_11N                 0x85C
  32 #define ODM_REG_ANTSEL_CTRL_11N                 0x860
  33 #define ODM_REG_RX_ANT_CTRL_11N                 0x864
  34 #define ODM_REG_PIN_CTRL_11N                            0x870
  35 #define ODM_REG_BB_PWR_SAV1_11N                 0x874
  36 #define ODM_REG_ANTSEL_PATH_11N                 0x878
  37 #define ODM_REG_BB_3WIRE_11N                    0x88C
  38 #define ODM_REG_SC_CNT_11N                              0x8C4
  39 #define ODM_REG_PSD_DATA_11N                    0x8B4
  40 /* PAGE 9 */
  41 #define ODM_REG_ANT_MAPPING1_11N                0x914
  42 #define ODM_REG_ANT_MAPPING2_11N                0x918
  43 /* PAGE A */
  44 #define ODM_REG_CCK_ANTDIV_PARA1_11N    0xA00
  45 #define ODM_REG_CCK_CCA_11N                             0xA0A
  46 #define ODM_REG_CCK_ANTDIV_PARA2_11N    0xA0C
  47 #define ODM_REG_CCK_ANTDIV_PARA3_11N    0xA10
  48 #define ODM_REG_CCK_ANTDIV_PARA4_11N    0xA14
  49 #define ODM_REG_CCK_FILTER_PARA1_11N    0xA22
  50 #define ODM_REG_CCK_FILTER_PARA2_11N    0xA23
  51 #define ODM_REG_CCK_FILTER_PARA3_11N    0xA24
  52 #define ODM_REG_CCK_FILTER_PARA4_11N    0xA25
  53 #define ODM_REG_CCK_FILTER_PARA5_11N    0xA26
  54 #define ODM_REG_CCK_FILTER_PARA6_11N    0xA27
  55 #define ODM_REG_CCK_FILTER_PARA7_11N    0xA28
  56 #define ODM_REG_CCK_FILTER_PARA8_11N    0xA29
  57 #define ODM_REG_CCK_FA_RST_11N                  0xA2C
  58 #define ODM_REG_CCK_FA_MSB_11N                  0xA58
  59 #define ODM_REG_CCK_FA_LSB_11N                  0xA5C
  60 #define ODM_REG_CCK_CCA_CNT_11N                 0xA60
  61 #define ODM_REG_BB_PWR_SAV4_11N                 0xA74
  62 /* PAGE B */
  63 #define ODM_REG_LNA_SWITCH_11N                  0xB2C
  64 #define ODM_REG_PATH_SWITCH_11N                 0xB30
  65 #define ODM_REG_RSSI_CTRL_11N                   0xB38
  66 #define ODM_REG_CONFIG_ANTA_11N                 0xB68
  67 #define ODM_REG_RSSI_BT_11N                             0xB9C
  68 /* PAGE C */
  69 #define ODM_REG_OFDM_FA_HOLDC_11N               0xC00
  70 #define ODM_REG_RX_PATH_11N                             0xC04
  71 #define ODM_REG_TRMUX_11N                               0xC08
  72 #define ODM_REG_OFDM_FA_RSTC_11N                0xC0C
  73 #define ODM_REG_RXIQI_MATRIX_11N                0xC14
  74 #define ODM_REG_TXIQK_MATRIX_LSB1_11N   0xC4C
  75 #define ODM_REG_IGI_A_11N                               0xC50
  76 #define ODM_REG_ANTDIV_PARA2_11N                0xC54
  77 #define ODM_REG_IGI_B_11N                                       0xC58
  78 #define ODM_REG_ANTDIV_PARA3_11N                0xC5C
  79 #define ODM_REG_BB_PWR_SAV2_11N                 0xC70
  80 #define ODM_REG_RX_OFF_11N                              0xC7C
  81 #define ODM_REG_TXIQK_MATRIXA_11N               0xC80
  82 #define ODM_REG_TXIQK_MATRIXB_11N               0xC88
  83 #define ODM_REG_TXIQK_MATRIXA_LSB2_11N  0xC94
  84 #define ODM_REG_TXIQK_MATRIXB_LSB2_11N  0xC9C
  85 #define ODM_REG_RXIQK_MATRIX_LSB_11N    0xCA0
  86 #define ODM_REG_ANTDIV_PARA1_11N                0xCA4
  87 #define ODM_REG_OFDM_FA_TYPE1_11N               0xCF0
  88 /* PAGE D */
  89 #define ODM_REG_OFDM_FA_RSTD_11N                0xD00
  90 #define ODM_REG_OFDM_FA_TYPE2_11N               0xDA0
  91 #define ODM_REG_OFDM_FA_TYPE3_11N               0xDA4
  92 #define ODM_REG_OFDM_FA_TYPE4_11N               0xDA8
  93 /* PAGE E */
  94 #define ODM_REG_TXAGC_A_6_18_11N                0xE00
  95 #define ODM_REG_TXAGC_A_24_54_11N               0xE04
  96 #define ODM_REG_TXAGC_A_1_MCS32_11N     0xE08
  97 #define ODM_REG_TXAGC_A_MCS0_3_11N              0xE10
  98 #define ODM_REG_TXAGC_A_MCS4_7_11N              0xE14
  99 #define ODM_REG_TXAGC_A_MCS8_11_11N     0xE18
 100 #define ODM_REG_TXAGC_A_MCS12_15_11N    0xE1C
 101 #define ODM_REG_FPGA0_IQK_11N                   0xE28
 102 #define ODM_REG_TXIQK_TONE_A_11N                0xE30
 103 #define ODM_REG_RXIQK_TONE_A_11N                0xE34
 104 #define ODM_REG_TXIQK_PI_A_11N                  0xE38
 105 #define ODM_REG_RXIQK_PI_A_11N                  0xE3C
 106 #define ODM_REG_TXIQK_11N                               0xE40
 107 #define ODM_REG_RXIQK_11N                               0xE44
 108 #define ODM_REG_IQK_AGC_PTS_11N                 0xE48
 109 #define ODM_REG_IQK_AGC_RSP_11N                 0xE4C
 110 #define ODM_REG_BLUETOOTH_11N                   0xE6C
 111 #define ODM_REG_RX_WAIT_CCA_11N                 0xE70
 112 #define ODM_REG_TX_CCK_RFON_11N                 0xE74
 113 #define ODM_REG_TX_CCK_BBON_11N                 0xE78
 114 #define ODM_REG_OFDM_RFON_11N                   0xE7C
 115 #define ODM_REG_OFDM_BBON_11N                   0xE80
 116 #define         ODM_REG_TX2RX_11N                               0xE84
 117 #define ODM_REG_TX2TX_11N                               0xE88
 118 #define ODM_REG_RX_CCK_11N                              0xE8C
 119 #define ODM_REG_RX_OFDM_11N                             0xED0
 120 #define ODM_REG_RX_WAIT_RIFS_11N                0xED4
 121 #define ODM_REG_RX2RX_11N                               0xED8
 122 #define ODM_REG_STANDBY_11N                             0xEDC
 123 #define ODM_REG_SLEEP_11N                               0xEE0
 124 #define ODM_REG_PMPD_ANAEN_11N                  0xEEC
 125
 126 /* 2 MAC REG LIST */
 127 #define ODM_REG_BB_RST_11N                              0x02
 128 #define ODM_REG_ANTSEL_PIN_11N                  0x4C
 129 #define ODM_REG_EARLY_MODE_11N                  0x4D0
 130 #define ODM_REG_RSSI_MONITOR_11N                0x4FE
 131 #define ODM_REG_EDCA_VO_11N                             0x500
 132 #define ODM_REG_EDCA_VI_11N                             0x504
 133 #define ODM_REG_EDCA_BE_11N                             0x508
 134 #define ODM_REG_EDCA_BK_11N                             0x50C
 135 #define ODM_REG_TXPAUSE_11N                             0x522
 136 #define ODM_REG_RESP_TX_11N                             0x6D8
 137 #define ODM_REG_ANT_TRAIN_PARA1_11N     0x7b0
 138 #define ODM_REG_ANT_TRAIN_PARA2_11N     0x7b4
 139
 140 /* DIG Related */
 141 #define ODM_BIT_IGI_11N                                 0x0000007F
 142
 143 #endif