1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
21 #ifndef __HALDMOUTSRC_H__
22 #define __HALDMOUTSRC_H__
25 /* Define all team support ability. */
27 /* Define for all teams. Please Define the constant in your precomp header. */
29 /* define DM_ODM_SUPPORT_AP 0 */
30 /* define DM_ODM_SUPPORT_ADSL 0 */
31 /* define DM_ODM_SUPPORT_CE 0 */
32 /* define DM_ODM_SUPPORT_MP 1 */
34 /* Define ODM SW team support flag. */
36 /* Antenna Switch Relative Definition. */
38 /* Add new function SwAntDivCheck8192C(). */
39 /* This is the main function of Antenna diversity function before link. */
40 /* Mainly, it just retains last scan result and scan again. */
41 /* After that, it compares the scan result to see which one gets better
42 * RSSI. It selects antenna with better receiving power and returns better
48 #define TRAFFIC_HIGH 1
50 /* 3 Tx Power Tracking */
51 /* 3============================================================ */
52 #define DPK_DELTA_MAPPING_NUM 13
53 #define index_mapping_HP_NUM 15
57 /* 3============================================================ */
59 #define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */
60 #define MODE_40M 0 /* 0:20M, 1:40M */
62 #define PSD_CHM 20 /* Minimum channel number for BT AFH */
63 #define SIR_STEP_SIZE 3
64 #define Smooth_Size_1 5
66 #define Smooth_Size_2 10
68 #define Smooth_Size_3 20
70 #define Smooth_Step_Size 5
71 #define Adaptive_SIR 1
73 #define PSD_SCAN_INTERVAL 700 /* ms */
75 /* 8723A High Power IGI Setting */
76 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22
77 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
78 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a
81 #define DM_DIG_FA_TH0_LPS 4 /* 4 in lps */
82 #define DM_DIG_FA_TH1_LPS 15 /* 15 lps */
83 #define DM_DIG_FA_TH2_LPS 30 /* 30 lps */
84 #define RSSI_OFFSET_DIG 0x05;
87 #define ANTTESTALL 0x00 /* Ant A or B will be Testing */
88 #define ANTTESTA 0x01 /* Ant A will be Testing */
89 #define ANTTESTB 0x02 /* Ant B will be testing */
91 /* structure and define */
93 /* Add for AP/ADSLpseudo DM structuer requirement. */
94 /* We need to remove to other position??? */
95 struct rtl8192cd_priv {
101 u8 Dig_Ext_Port_Stage;
109 u8 CurSTAConnectState;
110 u8 PreSTAConnectState;
111 u8 CurMultiSTAConnectState;
118 s8 BackoffVal_range_max;
119 s8 BackoffVal_range_min;
120 u8 rx_gain_range_max;
121 u8 rx_gain_range_min;
133 u8 DIG_Dynamic_MIN_0;
134 u8 DIG_Dynamic_MIN_1;
135 bool bMediaConnect_0;
136 bool bMediaConnect_1;
152 u32 Reg874,RegC70,Reg85C,RegA74;
156 struct false_alarm_stats {
158 u32 Cnt_Rate_Illegal;
165 u32 Cnt_SB_Search_fail;
169 u32 Cnt_BW_USC; /* Gary */
170 u32 Cnt_BW_LSC; /* Gary */
173 struct dyn_primary_cca {
184 u8 PSD_bitmap_RXHP[80];
189 bool First_time_enter;
192 struct timer_list PSDTimer;
195 #define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */
196 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
198 /* This indicates two different steps. */
199 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to
200 * the signal on the air. */
201 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in
202 * SWAW_STEP_PEAK with original RSSI to determine if it is necessary to
205 #define SWAW_STEP_PEAK 0
206 #define SWAW_STEP_DETERMINE 1
210 #define TRAFFIC_LOW 0
211 #define TRAFFIC_HIGH 1
213 struct sw_ant_switch {
220 u8 bTriggerAntennaSwitch;
224 /* Before link Antenna Switch check */
225 u8 SWAS_NoLink_State;
226 u32 SWAS_NoLink_BK_Reg860;
227 bool ANTA_ON; /* To indicate Ant A is or not */
228 bool ANTB_ON; /* To indicate Ant B is on or not */
241 struct timer_list SwAntennaSwitchTimer;
242 /* Hybrid Antenna Diversity */
243 u32 CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
244 u32 CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
245 u32 OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
246 u32 OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
247 u32 RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM];
248 u32 RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM];
249 u8 TxAnt[ASSOCIATE_ENTRY_NUM];
256 bool bCurrentTurboEDCA;
258 u32 prv_traffic_idx; /* edca turbo */
261 struct odm_rate_adapt {
262 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */
263 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */
264 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */
265 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
266 u32 LastRATR; /* RATR Register Content */
269 #define IQK_MAC_REG_NUM 4
270 #define IQK_ADDA_REG_NUM 16
271 #define IQK_BB_REG_NUM_MAX 10
272 #define IQK_BB_REG_NUM 9
273 #define HP_THERMAL_NUM 8
275 #define AVG_THERMAL_NUM 8
276 #define IQK_Matrix_REG_NUM 8
277 #define IQK_Matrix_Settings_NUM 1+24+21
279 #define DM_Type_ByFWi 0
280 #define DM_Type_ByDriver 1
282 /* Declare for common info */
284 struct odm_phy_status_info {
286 u8 SignalQuality; /* in 0-100 index. */
287 u8 RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; /* EVM */
288 u8 RxMIMOSignalStrength[MAX_PATH_NUM_92CS];/* in 0~100 index */
289 s8 RxPower; /* in dBm Translate from PWdB */
290 s8 RecvSignalPower;/* Real power in dBm for this packet, no
291 * beautification and aggregation. Keep this raw
292 * info to be used for the other procedures. */
293 u8 BTRxRSSIPercentage;
294 u8 SignalStrength; /* in 0-100 index. */
295 u8 RxPwr[MAX_PATH_NUM_92CS];/* per-path's pwdb */
296 u8 RxSNR[MAX_PATH_NUM_92CS];/* per-path's SNR */
299 struct odm_phy_dbg_info {
300 /* ODM Write,debug info */
301 s8 RxSNRdB[MAX_PATH_NUM_92CS];
303 u64 NumQryPhyStatusCCK;
304 u64 NumQryPhyStatusOFDM;
306 s32 RxEVM[MAX_PATH_NUM_92CS];
309 struct odm_per_pkt_info {
312 bool bPacketMatchBSSID;
317 struct odm_mac_status_info {
323 ODM_DIG = 0x00000001,
324 ODM_HIGH_POWER = 0x00000002,
325 ODM_CCK_CCA_TH = 0x00000004,
326 ODM_FA_STATISTICS = 0x00000008,
327 ODM_RAMASK = 0x00000010,
328 ODM_RSSI_MONITOR = 0x00000020,
329 ODM_SW_ANTDIV = 0x00000040,
330 ODM_HW_ANTDIV = 0x00000080,
331 ODM_BB_PWRSV = 0x00000100,
332 ODM_2TPATHDIV = 0x00000200,
333 ODM_1TPATHDIV = 0x00000400,
334 ODM_PSD2AFH = 0x00000800
337 /* 2011/20/20 MH For MP driver RT_WLAN_STA = struct sta_info */
338 /* Please declare below ODM relative info in your STA info structure. */
340 struct odm_sta_info {
342 bool bUsed; /* record the sta status link or not? */
343 u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */
346 /* 1 PHY_STATUS_INFO */
347 u8 RSSI_Path[4]; /* */
353 /* 2011/10/20 MH Define Common info enum for all team. */
355 enum odm_common_info_def {
358 /* HOOK BEFORE REG INIT----------- */
359 ODM_CMNINFO_PLATFORM = 0,
360 ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */
361 ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */
362 ODM_CMNINFO_MP_TEST_CHIP,
363 ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */
364 ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */
365 ODM_CMNINFO_FAB_VER, /* ODM_FAB_E */
366 ODM_CMNINFO_RF_TYPE, /* RF_PATH_E or ODM_RF_TYPE_E? */
367 ODM_CMNINFO_BOARD_TYPE, /* ODM_BOARD_TYPE_E */
368 ODM_CMNINFO_EXT_LNA, /* true */
370 ODM_CMNINFO_EXT_TRSW,
371 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */
372 ODM_CMNINFO_BINHCT_TEST,
373 ODM_CMNINFO_BWIFI_TEST,
374 ODM_CMNINFO_SMART_CONCURRENT,
375 /* HOOK BEFORE REG INIT----------- */
378 /* POINTER REFERENCE----------- */
379 ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */
382 ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */
383 ODM_CMNINFO_BAND, /* ODM_BAND_TYPE_E */
384 ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */
385 ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */
386 ODM_CMNINFO_BW, /* ODM_BW_E */
389 ODM_CMNINFO_DMSP_GET_VALUE,
390 ODM_CMNINFO_BUDDY_ADAPTOR,
391 ODM_CMNINFO_DMSP_IS_MASTER,
393 ODM_CMNINFO_POWER_SAVING,
394 ODM_CMNINFO_ONE_PATH_CCA, /* ODM_CCA_PATH_E */
395 ODM_CMNINFO_DRV_STOP,
398 ODM_CMNINFO_ANT_TEST,
399 ODM_CMNINFO_NET_CLOSED,
401 /* POINTER REFERENCE----------- */
403 /* CALL BY VALUE------------- */
404 ODM_CMNINFO_WIFI_DIRECT,
405 ODM_CMNINFO_WIFI_DISPLAY,
407 ODM_CMNINFO_RSSI_MIN,
408 ODM_CMNINFO_DBG_COMP, /* u64 */
409 ODM_CMNINFO_DBG_LEVEL, /* u32 */
410 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */
411 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */
412 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */
413 ODM_CMNINFO_BT_DISABLED,
414 ODM_CMNINFO_BT_OPERATION,
416 ODM_CMNINFO_BT_BUSY, /* Check Bt is using or not */
417 ODM_CMNINFO_BT_DISABLE_EDCA,
418 /* CALL BY VALUE-------------*/
420 /* Dynamic ptr array hook itms. */
421 ODM_CMNINFO_STA_STATUS,
422 ODM_CMNINFO_PHY_STATUS,
423 ODM_CMNINFO_MAC_STATUS,
427 /* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */
429 enum odm_ability_def {
430 /* BB ODM section BIT 0-15 */
432 ODM_BB_RA_MASK = BIT1,
433 ODM_BB_DYNAMIC_TXPWR = BIT2,
434 ODM_BB_FA_CNT = BIT3,
435 ODM_BB_RSSI_MONITOR = BIT4,
436 ODM_BB_CCK_PD = BIT5,
437 ODM_BB_ANT_DIV = BIT6,
438 ODM_BB_PWR_SAVE = BIT7,
439 ODM_BB_PWR_TRA = BIT8,
440 ODM_BB_RATE_ADAPTIVE = BIT9,
441 ODM_BB_PATH_DIV = BIT10,
445 /* MAC DM section BIT 16-23 */
446 ODM_MAC_EDCA_TURBO = BIT16,
447 ODM_MAC_EARLY_MODE = BIT17,
449 /* RF ODM section BIT 24-31 */
450 ODM_RF_TX_PWR_TRACK = BIT24,
451 ODM_RF_RX_GAIN_TRACK = BIT25,
452 ODM_RF_CALIBRATION = BIT26,
455 /* ODM_CMNINFO_INTERFACE */
456 enum odm_interface_def {
463 /* ODM_CMNINFO_IC_TYPE */
474 #define ODM_IC_11N_SERIES \
475 (ODM_RTL8192S | ODM_RTL8192C | ODM_RTL8192D | \
476 ODM_RTL8723A | ODM_RTL8188E)
477 #define ODM_IC_11AC_SERIES (ODM_RTL8812)
479 /* ODM_CMNINFO_CUT_VER */
480 enum odm_cut_version {
490 /* ODM_CMNINFO_FAB_VER */
491 enum odm_fab_Version {
496 /* ODM_CMNINFO_RF_TYPE */
497 /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
520 /* ODM Dynamic common info value definition */
522 enum odm_mac_phy_mode {
528 enum odm_bt_coexist {
535 /* ODM_CMNINFO_OP_MODE */
536 enum odm_operation_mode {
540 ODM_POWERSAVE = BIT3,
542 ODM_CLIENT_MODE = BIT5,
544 ODM_WIFI_DIRECT = BIT7,
545 ODM_WIFI_DISPLAY = BIT8,
548 /* ODM_CMNINFO_WM_MODE */
549 enum odm_wireless_mode {
560 /* ODM_CMNINFO_BAND */
562 ODM_BAND_2_4G = BIT0,
566 /* ODM_CMNINFO_SEC_CHNL_OFFSET */
567 enum odm_sec_chnl_offset {
573 /* ODM_CMNINFO_SEC_MODE */
581 ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */
594 /* ODM_CMNINFO_BOARD_TYPE */
595 enum odm_board_type {
596 ODM_BOARD_NORMAL = 0,
597 ODM_BOARD_HIGHPWR = 1,
598 ODM_BOARD_MINICARD = 2,
603 /* ODM_CMNINFO_ONE_PATH_CCA */
631 u8 PTActive; /* on or off */
632 u8 PTTryState; /* 0 trying state, 1 for decision state */
633 u8 PTStage; /* 0~6 */
634 u8 PTStopCount; /* Stop PT counter */
635 u8 PTPreRate; /* if rate change do PT */
636 u8 PTPreRssi; /* if RSSI change 5% do PT */
637 u8 PTModeSS; /* decide whitch rate should do PT */
638 u8 RAstage; /* StageRA, decide how many times RA will be done
643 struct ijk_matrix_regs_set {
645 s32 Value[1][IQK_Matrix_REG_NUM];
649 /* for tx power tracking */
650 u32 RegA24; /* for TempCCK */
657 bool bTXPowerTrackingInit;
658 bool bTXPowerTracking;
659 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking
662 u8 InternalPA5G[2]; /* pathA / pathB */
664 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0,
670 u8 ThermalValue_AVG[AVG_THERMAL_NUM];
671 u8 ThermalValue_AVG_index;
672 u8 ThermalValue_RxGain;
673 u8 ThermalValue_Crystal;
674 u8 ThermalValue_DPKstore;
675 u8 ThermalValue_DPKtrack;
676 bool TxPowerTrackingInProgress;
679 bool bReloadtxpowerindex;
681 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */
688 u8 ThermalValue_HP[HP_THERMAL_NUM];
689 u8 ThermalValue_HP_index;
690 struct ijk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
705 bool bIQKInitialized;
707 bool bAntennaDetected;
708 u32 ADDA_backup[IQK_ADDA_REG_NUM];
709 u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
710 u32 IQK_BB_backup_recover[9];
711 u32 IQK_BB_backup[IQK_BB_REG_NUM];
714 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
716 u8 bAPKThermalMeterIgnore;
722 /* ODM Dynamic common info value definition */
724 struct fast_ant_train {
734 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
735 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
736 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
737 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
738 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
739 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
740 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
746 FAT_NORMAL_STATE = 0,
747 FAT_TRAINING_STATE = 1,
752 CG_TRX_HW_ANTDIV = 0x01,
753 CGCS_RX_HW_ANTDIV = 0x02,
754 FIXED_HW_ANTDIV = 0x03,
755 CG_TRX_SMART_ANTDIV = 0x04,
756 CGCS_RX_SW_ANTDIV = 0x05,
759 /* Copy from SD4 defined structure. We use to support PHY DM integration. */
760 struct odm_dm_struct {
761 /* Add for different team use temporarily */
762 struct adapter *Adapter; /* For CE/NIC team */
763 struct rtl8192cd_priv *priv; /* For AP/ADSL team */
764 /* WHen you use above pointers, they must be initialized. */
767 struct rtl8192cd_priv *fake_priv;
771 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
773 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */
775 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
777 /* 1 COMMON INFORMATION */
779 /* HOOK BEFORE REG INIT----------- */
780 /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */
782 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ �K�K = 1/2/3/�K */
784 /* ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 */
786 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any
787 * other type = 1/2/3/... */
789 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */
791 /* Fab Version TSMC/UMC = 0/1 */
793 /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */
795 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/. = 0/1/2/3/4/. */
797 /* with external LNA NO/Yes = 0/1 */
799 /* with external PA NO/Yes = 0/1 */
801 /* with external TRSW NO/Yes = 0/1 */
803 u8 PatchID; /* Customer ID */
807 bool bDualMacSmartConcurrent;
808 u32 BK_SupportAbility;
810 /* HOOK BEFORE REG INIT----------- */
813 /* POINTER REFERENCE----------- */
817 struct adapter *adapter_temp;
819 /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */
821 /* TX Unicast byte count */
822 u64 *pNumTxBytesUnicast;
823 /* RX Unicast byte count */
824 u64 *pNumRxBytesUnicast;
825 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */
826 u8 *pWirelessMode; /* ODM_WIRELESS_MODE_E */
827 /* Frequence band 2.4G/5G = 0/1 */
829 /* Secondary channel offset don't_care/below/above = 0/1/2 */
831 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */
833 /* BW info 20M/40M/80M = 0/1/2 */
835 /* Central channel location Ch1/Ch2/.... */
836 u8 *pChannel; /* central channel number */
837 /* Common info for 92D DMSP */
839 bool *pbGetValueFromOtherMac;
840 struct adapter **pBuddyAdapter;
841 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */
842 /* Common info for Status */
843 bool *pbScanInProcess;
845 /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */
847 /* pMgntInfo->AntennaTest */
850 /* POINTER REFERENCE----------- */
852 /* CALL BY VALUE------------- */
857 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */
860 /* Common info for BTDM */
861 bool bBtDisabled; /* BT is disabled */
862 bool bBtHsOperation; /* BT HS mode is under progress */
863 u8 btHsDigVal; /* use BT rssi to decide the DIG value */
864 bool bBtDisableEdcaTurbo;/* Under some condition, don't enable the
866 bool bBtBusy; /* BT is busy. */
867 /* CALL BY VALUE------------- */
869 /* 2 Define STA info. */
871 /* For MP, we need to reduce one array pointer for default port.?? */
872 struct sta_info *pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
875 struct odm_ra_info RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; /* Use MacID as
876 * array index. STA MacID=0,
877 * VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} */
879 /* 2012/02/14 MH Add to share 88E ra with other SW team. */
880 /* We need to colelct all support abilit to a proper area. */
884 /* Define ........... */
886 /* Latest packet phy info (ODM write) */
887 struct odm_phy_dbg_info PhyDbgInfo;
889 /* Latest packet phy info (ODM write) */
890 struct odm_mac_status_info *pMacInfo;
892 /* Different Team independt structure?? */
895 struct fast_ant_train DM_FatTable;
896 struct rtw_dig DM_DigTable;
897 struct rtl_ps DM_PSTable;
898 struct dyn_primary_cca DM_PriCCA;
899 struct rx_hpc DM_RXHP_Table;
900 struct false_alarm_stats FalseAlmCnt;
901 struct false_alarm_stats FlaseAlmCntBuddyAdapter;
902 struct sw_ant_switch DM_SWAT_Table;
905 struct edca_turbo DM_EDCA_Table;
907 /* Copy from SD4 structure */
909 /* ================================================== */
912 bool *pbDriverStopped;
913 bool *pbDriverIsGoingToPnpSetPowerSleep;
914 bool *pinit_adpt_in_progress;
917 bool bUserAssignLevel;
918 struct timer_list PSDTimer;
919 u8 RSSI_BT; /* come from BT */
921 bool bDMInitialGainEnable;
923 /* for rate adaptive, in fact, 88c/92c fw will handle this */
926 struct odm_rate_adapt RateAdaptive;
928 struct odm_rf_cal RFCalibrateInfo;
930 /* TX power tracking */
932 u8 BbSwingIdxOfdmCurrent;
933 u8 BbSwingIdxOfdmBase;
934 bool BbSwingFlagOfdm;
936 u8 BbSwingIdxCckCurrent;
937 u8 BbSwingIdxCckBase;
940 /* ODM system resource. */
942 /* ODM relative time. */
943 struct timer_list PathDivSwitchTimer;
944 /* 2011.09.27 add for Path Diversity */
945 struct timer_list CCKPathDiversityTimer;
946 struct timer_list FastAntTrainingTimer;
947 }; /* DM_Dynamic_Mechanism_Structure */
949 enum ODM_RF_CONTENT {
950 odm_radioa_txt = 0x1000,
951 odm_radiob_txt = 0x1001,
952 odm_radioc_txt = 0x1002,
953 odm_radiod_txt = 0x1003
956 enum odm_bb_config_type {
959 CONFIG_BB_AGC_TAB_2G,
960 CONFIG_BB_AGC_TAB_5G,
961 CONFIG_BB_PHY_REG_PG,
970 RT_STATUS_INVALID_CONTEXT,
971 RT_STATUS_INVALID_PARAMETER,
972 RT_STATUS_NOT_SUPPORT,
973 RT_STATUS_OS_API_FAILED,
976 /* 3=========================================================== */
978 /* 3=========================================================== */
981 RT_TYPE_THRESH_HIGH = 0,
982 RT_TYPE_THRESH_LOW = 1,
984 RT_TYPE_RX_GAIN_MIN = 3,
985 RT_TYPE_RX_GAIN_MAX = 4,
991 #define DM_DIG_THRESH_HIGH 40
992 #define DM_DIG_THRESH_LOW 35
994 #define DM_SCAN_RSSI_TH 0x14 /* scan return issue for LC */
996 #define DM_false_ALARM_THRESH_LOW 400
997 #define DM_false_ALARM_THRESH_HIGH 1000
999 #define DM_DIG_MAX_NIC 0x4e
1000 #define DM_DIG_MIN_NIC 0x1e /* 0x22/0x1c */
1002 #define DM_DIG_MAX_AP 0x32
1003 #define DM_DIG_MIN_AP 0x20
1005 #define DM_DIG_MAX_NIC_HP 0x46
1006 #define DM_DIG_MIN_NIC_HP 0x2e
1008 #define DM_DIG_MAX_AP_HP 0x42
1009 #define DM_DIG_MIN_AP_HP 0x30
1011 /* vivi 92c&92d has different definition, 20110504 */
1012 /* this is for 92c */
1013 #define DM_DIG_FA_TH0 0x200/* 0x20 */
1014 #define DM_DIG_FA_TH1 0x300/* 0x100 */
1015 #define DM_DIG_FA_TH2 0x400/* 0x200 */
1016 /* this is for 92d */
1017 #define DM_DIG_FA_TH0_92D 0x100
1018 #define DM_DIG_FA_TH1_92D 0x400
1019 #define DM_DIG_FA_TH2_92D 0x600
1021 #define DM_DIG_BACKOFF_MAX 12
1022 #define DM_DIG_BACKOFF_MIN -4
1023 #define DM_DIG_BACKOFF_DEFAULT 10
1025 /* 3=========================================================== */
1026 /* 3 AGC RX High Power Mode */
1027 /* 3=========================================================== */
1028 #define LNA_Low_Gain_1 0x64
1029 #define LNA_Low_Gain_2 0x5A
1030 #define LNA_Low_Gain_3 0x58
1032 #define FA_RXHP_TH1 5000
1033 #define FA_RXHP_TH2 1500
1034 #define FA_RXHP_TH3 800
1035 #define FA_RXHP_TH4 600
1036 #define FA_RXHP_TH5 500
1038 /* 3=========================================================== */
1040 /* 3=========================================================== */
1042 /* 3=========================================================== */
1043 /* 3 Dynamic Tx Power */
1044 /* 3=========================================================== */
1045 /* Dynamic Tx Power Control Threshold */
1046 #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
1047 #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
1048 #define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F
1050 #define TxHighPwrLevel_Normal 0
1051 #define TxHighPwrLevel_Level1 1
1052 #define TxHighPwrLevel_Level2 2
1053 #define TxHighPwrLevel_BT1 3
1054 #define TxHighPwrLevel_BT2 4
1055 #define TxHighPwrLevel_15 5
1056 #define TxHighPwrLevel_35 6
1057 #define TxHighPwrLevel_50 7
1058 #define TxHighPwrLevel_70 8
1059 #define TxHighPwrLevel_100 9
1061 /* 3=========================================================== */
1062 /* 3 Rate Adaptive */
1063 /* 3=========================================================== */
1064 #define DM_RATR_STA_INIT 0
1065 #define DM_RATR_STA_HIGH 1
1066 #define DM_RATR_STA_MIDDLE 2
1067 #define DM_RATR_STA_LOW 3
1069 /* 3=========================================================== */
1070 /* 3 BB Power Save */
1071 /* 3=========================================================== */
1085 /* 3=========================================================== */
1086 /* 3 Antenna Diversity */
1087 /* 3=========================================================== */
1094 /* Maximal number of antenna detection mechanism needs to perform. */
1095 #define MAX_ANTENNA_DETECTION_CNT 10
1097 /* Extern Global Variables. */
1098 #define OFDM_TABLE_SIZE_92C 37
1099 #define OFDM_TABLE_SIZE_92D 43
1100 #define CCK_TABLE_SIZE 33
1102 extern u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D];
1103 extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
1104 extern u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
1106 /* check Sta pointer valid or not */
1107 #define IS_STA_VALID(pSta) (pSta)
1108 /* 20100514 Joseph: Add definition for antenna switching test after link. */
1109 /* This indicates two different the steps. */
1110 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the
1111 * signal on the air. */
1112 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in
1114 /* with original RSSI to determine if it is necessary to switch antenna. */
1115 #define SWAW_STEP_PEAK 0
1116 #define SWAW_STEP_DETERMINE 1
1118 void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI);
1119 void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres);
1121 void ODM_SetAntenna(struct odm_dm_struct *pDM_Odm, u8 Antenna);
1123 #define dm_RF_Saving ODM_RF_Saving
1124 void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal);
1126 #define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink
1127 void ODM_SwAntDivRestAfterLink(struct odm_dm_struct *pDM_Odm);
1129 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
1130 void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm);
1132 bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI,
1133 bool bForceUpdate, u8 *pRATRState);
1135 #define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi
1136 void ODM_SwAntDivChkPerPktRssi(struct odm_dm_struct *pDM_Odm, u8 StationID,
1137 struct odm_phy_status_info *pPhyInfo);
1139 u32 ConvertTo_dB(u32 Value);
1141 u32 GetPSDData(struct odm_dm_struct *pDM_Odm, unsigned int point,
1142 u8 initial_gain_psd);
1144 void odm_DIGbyRSSI_LPS(struct odm_dm_struct *pDM_Odm);
1146 u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid,
1147 u32 ra_mask, u8 rssi_level);
1149 void ODM_DMInit(struct odm_dm_struct *pDM_Odm);
1151 void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm);
1153 void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm,
1154 enum odm_common_info_def CmnInfo, u32 Value);
1156 void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm,
1157 enum odm_common_info_def CmnInfo, void *pValue);
1159 void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm,
1160 enum odm_common_info_def CmnInfo,
1161 u16 Index, void *pValue);
1163 void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value);
1165 void ODM_InitAllTimers(struct odm_dm_struct *pDM_Odm);
1167 void ODM_CancelAllTimers(struct odm_dm_struct *pDM_Odm);
1169 void ODM_ReleaseAllTimers(struct odm_dm_struct *pDM_Odm);
1171 void ODM_ResetIQKResult(struct odm_dm_struct *pDM_Odm);
1173 void ODM_AntselStatistics_88C(struct odm_dm_struct *pDM_Odm, u8 MacId,
1174 u32 PWDBAll, bool isCCKrate);
1176 void ODM_SingleDualAntennaDefaultSetting(struct odm_dm_struct *pDM_Odm);
1178 bool ODM_SingleDualAntennaDetection(struct odm_dm_struct *pDM_Odm, u8 mode);
1180 void odm_dtc(struct odm_dm_struct *pDM_Odm);