drivers/staging/r8188eu/hal/usb_halinit.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */
   3
   4 #define _HCI_HAL_INIT_C_
   5
   6 #include "../include/osdep_service.h"
   7 #include "../include/drv_types.h"
   8 #include "../include/rtw_efuse.h"
   9
  10 #include "../include/rtl8188e_hal.h"
  11 #include "../include/rtl8188e_led.h"
  12 #include "../include/rtw_iol.h"
  13 #include "../include/usb_ops.h"
  14 #include "../include/usb_osintf.h"
  15
  16 #define         HAL_MAC_ENABLE  1
  17 #define         HAL_BB_ENABLE           1
  18 #define         HAL_RF_ENABLE           1
  19
  20 static void _ConfigNormalChipOutEP_8188E(struct adapter *adapt, u8 NumOutPipe)
  21 {
  22         struct hal_data_8188e   *haldata        = GET_HAL_DATA(adapt);
  23
  24         switch (NumOutPipe) {
  25         case    3:
  26                 haldata->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
  27                 haldata->OutEpNumber = 3;
  28                 break;
  29         case    2:
  30                 haldata->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
  31                 haldata->OutEpNumber = 2;
  32                 break;
  33         case    1:
  34                 haldata->OutEpQueueSel = TX_SELE_HQ;
  35                 haldata->OutEpNumber = 1;
  36                 break;
  37         default:
  38                 break;
  39         }
  40         DBG_88E("%s OutEpQueueSel(0x%02x), OutEpNumber(%d)\n", __func__, haldata->OutEpQueueSel, haldata->OutEpNumber);
  41 }
  42
  43 static bool HalUsbSetQueuePipeMapping8188EUsb(struct adapter *adapt, u8 NumInPipe, u8 NumOutPipe)
  44 {
  45         struct hal_data_8188e   *haldata        = GET_HAL_DATA(adapt);
  46         bool                    result          = false;
  47
  48         _ConfigNormalChipOutEP_8188E(adapt, NumOutPipe);
  49
  50         /*  Normal chip with one IN and one OUT doesn't have interrupt IN EP. */
  51         if (1 == haldata->OutEpNumber) {
  52                 if (1 != NumInPipe)
  53                         return result;
  54         }
  55
  56         /*  All config other than above support one Bulk IN and one Interrupt IN. */
  57
  58         result = Hal_MappingOutPipe(adapt, NumOutPipe);
  59
  60         return result;
  61 }
  62
  63 static void rtl8188eu_interface_configure(struct adapter *adapt)
  64 {
  65         struct hal_data_8188e   *haldata        = GET_HAL_DATA(adapt);
  66         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(adapt);
  67
  68         if (pdvobjpriv->ishighspeed)
  69                 haldata->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;/* 512 bytes */
  70         else
  71                 haldata->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;/* 64 bytes */
  72
  73         haldata->interfaceIndex = pdvobjpriv->InterfaceNumber;
  74
  75         haldata->UsbTxAggMode           = 1;
  76         haldata->UsbTxAggDescNum        = 0x6;  /*  only 4 bits */
  77
  78         haldata->UsbRxAggMode           = USB_RX_AGG_DMA;/*  USB_RX_AGG_DMA; */
  79         haldata->UsbRxAggBlockCount     = 8; /* unit : 512b */
  80         haldata->UsbRxAggBlockTimeout   = 0x6;
  81         haldata->UsbRxAggPageCount      = 48; /* uint :128 b 0x0A;      10 = MAX_RX_DMA_BUFFER_SIZE/2/haldata->UsbBulkOutSize */
  82         haldata->UsbRxAggPageTimeout    = 0x4; /* 6, absolute time = 34ms/(2^6) */
  83
  84         HalUsbSetQueuePipeMapping8188EUsb(adapt,
  85                                 pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes);
  86 }
  87
  88 static u32 rtl8188eu_InitPowerOn(struct adapter *adapt)
  89 {
  90         u16 value16;
  91         /*  HW Power on sequence */
  92         struct hal_data_8188e   *haldata        = GET_HAL_DATA(adapt);
  93         if (haldata->bMacPwrCtrlOn)
  94                 return _SUCCESS;
  95
  96         if (!HalPwrSeqCmdParsing(adapt, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_PWR_ON_FLOW)) {
  97                 DBG_88E(KERN_ERR "%s: run power on flow fail\n", __func__);
  98                 return _FAIL;
  99         }
 100
 101         /*  Enable MAC DMA/WMAC/SCHEDULE/SEC block */
 102         /*  Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */
 103         rtw_write16(adapt, REG_CR, 0x00);  /* suggseted by zhouzhou, by page, 20111230 */
 104
 105                 /*  Enable MAC DMA/WMAC/SCHEDULE/SEC block */
 106         value16 = rtw_read16(adapt, REG_CR);
 107         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
 108                                 | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
 109         /*  for SDIO - Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */
 110
 111         rtw_write16(adapt, REG_CR, value16);
 112         haldata->bMacPwrCtrlOn = true;
 113
 114         return _SUCCESS;
 115 }
 116
 117 /*  Shall USB interface init this? */
 118 static void _InitInterrupt(struct adapter *Adapter)
 119 {
 120         u32 imr, imr_ex;
 121         u8  usb_opt;
 122         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
 123
 124         /* HISR write one to clear */
 125         rtw_write32(Adapter, REG_HISR_88E, 0xFFFFFFFF);
 126         /*  HIMR - */
 127         imr = IMR_PSTIMEOUT_88E | IMR_TBDER_88E | IMR_CPWM_88E | IMR_CPWM2_88E;
 128         rtw_write32(Adapter, REG_HIMR_88E, imr);
 129         haldata->IntrMask[0] = imr;
 130
 131         imr_ex = IMR_TXERR_88E | IMR_RXERR_88E | IMR_TXFOVW_88E | IMR_RXFOVW_88E;
 132         rtw_write32(Adapter, REG_HIMRE_88E, imr_ex);
 133         haldata->IntrMask[1] = imr_ex;
 134
 135         /*  REG_USB_SPECIAL_OPTION - BIT(4) */
 136         /*  0; Use interrupt endpoint to upload interrupt pkt */
 137         /*  1; Use bulk endpoint to upload interrupt pkt, */
 138         usb_opt = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
 139
 140         if (!adapter_to_dvobj(Adapter)->ishighspeed)
 141                 usb_opt = usb_opt & (~INT_BULK_SEL);
 142         else
 143                 usb_opt = usb_opt | (INT_BULK_SEL);
 144
 145         rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, usb_opt);
 146 }
 147
 148 static void _InitQueueReservedPage(struct adapter *Adapter)
 149 {
 150         struct hal_data_8188e           *haldata = GET_HAL_DATA(Adapter);
 151         struct registry_priv    *pregistrypriv = &Adapter->registrypriv;
 152         u32 numHQ       = 0;
 153         u32 numLQ       = 0;
 154         u32 numNQ       = 0;
 155         u32 numPubQ;
 156         u32 value32;
 157         u8 value8;
 158         bool bWiFiConfig = pregistrypriv->wifi_spec;
 159
 160         if (bWiFiConfig) {
 161                 if (haldata->OutEpQueueSel & TX_SELE_HQ)
 162                         numHQ =  0x29;
 163
 164                 if (haldata->OutEpQueueSel & TX_SELE_LQ)
 165                         numLQ = 0x1C;
 166
 167                 /*  NOTE: This step shall be proceed before writting REG_RQPN. */
 168                 if (haldata->OutEpQueueSel & TX_SELE_NQ)
 169                         numNQ = 0x1C;
 170                 value8 = (u8)_NPQ(numNQ);
 171                 rtw_write8(Adapter, REG_RQPN_NPQ, value8);
 172
 173                 numPubQ = 0xA8 - numHQ - numLQ - numNQ;
 174
 175                 /*  TX DMA */
 176                 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 177                 rtw_write32(Adapter, REG_RQPN, value32);
 178         } else {
 179                 rtw_write16(Adapter, REG_RQPN_NPQ, 0x0000);/* Just follow MP Team,??? Georgia 03/28 */
 180                 rtw_write16(Adapter, REG_RQPN_NPQ, 0x0d);
 181                 rtw_write32(Adapter, REG_RQPN, 0x808E000d);/* reserve 7 page for LPS */
 182         }
 183 }
 184
 185 static void _InitTxBufferBoundary(struct adapter *Adapter, u8 txpktbuf_bndy)
 186 {
 187         rtw_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 188         rtw_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 189         rtw_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
 190         rtw_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
 191         rtw_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
 192 }
 193
 194 static void _InitPageBoundary(struct adapter *Adapter)
 195 {
 196         /*  RX Page Boundary */
 197         /*  */
 198         u16 rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E-1;
 199
 200         rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
 201 }
 202
 203 static void _InitNormalChipRegPriority(struct adapter *Adapter, u16 beQ,
 204                                        u16 bkQ, u16 viQ, u16 voQ, u16 mgtQ,
 205                                        u16 hiQ)
 206 {
 207         u16 value16     = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
 208
 209         value16 |= _TXDMA_BEQ_MAP(beQ)  | _TXDMA_BKQ_MAP(bkQ) |
 210                    _TXDMA_VIQ_MAP(viQ)  | _TXDMA_VOQ_MAP(voQ) |
 211                    _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
 212
 213         rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
 214 }
 215
 216 static void _InitNormalChipOneOutEpPriority(struct adapter *Adapter)
 217 {
 218         struct hal_data_8188e   *haldata        = GET_HAL_DATA(Adapter);
 219
 220         u16 value = 0;
 221         switch (haldata->OutEpQueueSel) {
 222         case TX_SELE_HQ:
 223                 value = QUEUE_HIGH;
 224                 break;
 225         case TX_SELE_LQ:
 226                 value = QUEUE_LOW;
 227                 break;
 228         case TX_SELE_NQ:
 229                 value = QUEUE_NORMAL;
 230                 break;
 231         default:
 232                 break;
 233         }
 234         _InitNormalChipRegPriority(Adapter, value, value, value, value,
 235                                    value, value);
 236 }
 237
 238 static void _InitNormalChipTwoOutEpPriority(struct adapter *Adapter)
 239 {
 240         struct hal_data_8188e   *haldata        = GET_HAL_DATA(Adapter);
 241         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 242         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 243         u16 valueHi = 0;
 244         u16 valueLow = 0;
 245
 246         switch (haldata->OutEpQueueSel) {
 247         case (TX_SELE_HQ | TX_SELE_LQ):
 248                 valueHi = QUEUE_HIGH;
 249                 valueLow = QUEUE_LOW;
 250                 break;
 251         case (TX_SELE_NQ | TX_SELE_LQ):
 252                 valueHi = QUEUE_NORMAL;
 253                 valueLow = QUEUE_LOW;
 254                 break;
 255         case (TX_SELE_HQ | TX_SELE_NQ):
 256                 valueHi = QUEUE_HIGH;
 257                 valueLow = QUEUE_NORMAL;
 258                 break;
 259         default:
 260                 break;
 261         }
 262
 263         if (!pregistrypriv->wifi_spec) {
 264                 beQ     = valueLow;
 265                 bkQ     = valueLow;
 266                 viQ     = valueHi;
 267                 voQ     = valueHi;
 268                 mgtQ    = valueHi;
 269                 hiQ     = valueHi;
 270         } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
 271                 beQ     = valueLow;
 272                 bkQ     = valueHi;
 273                 viQ     = valueHi;
 274                 voQ     = valueLow;
 275                 mgtQ    = valueHi;
 276                 hiQ     = valueHi;
 277         }
 278         _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 279 }
 280
 281 static void _InitNormalChipThreeOutEpPriority(struct adapter *Adapter)
 282 {
 283         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 284         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 285
 286         if (!pregistrypriv->wifi_spec) {/*  typical setting */
 287                 beQ     = QUEUE_LOW;
 288                 bkQ     = QUEUE_LOW;
 289                 viQ     = QUEUE_NORMAL;
 290                 voQ     = QUEUE_HIGH;
 291                 mgtQ    = QUEUE_HIGH;
 292                 hiQ     = QUEUE_HIGH;
 293         } else {/*  for WMM */
 294                 beQ     = QUEUE_LOW;
 295                 bkQ     = QUEUE_NORMAL;
 296                 viQ     = QUEUE_NORMAL;
 297                 voQ     = QUEUE_HIGH;
 298                 mgtQ    = QUEUE_HIGH;
 299                 hiQ     = QUEUE_HIGH;
 300         }
 301         _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 302 }
 303
 304 static void _InitQueuePriority(struct adapter *Adapter)
 305 {
 306         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
 307
 308         switch (haldata->OutEpNumber) {
 309         case 1:
 310                 _InitNormalChipOneOutEpPriority(Adapter);
 311                 break;
 312         case 2:
 313                 _InitNormalChipTwoOutEpPriority(Adapter);
 314                 break;
 315         case 3:
 316                 _InitNormalChipThreeOutEpPriority(Adapter);
 317                 break;
 318         default:
 319                 break;
 320         }
 321 }
 322
 323 static void _InitNetworkType(struct adapter *Adapter)
 324 {
 325         u32 value32;
 326
 327         value32 = rtw_read32(Adapter, REG_CR);
 328         /*  TODO: use the other function to set network type */
 329         value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
 330
 331         rtw_write32(Adapter, REG_CR, value32);
 332 }
 333
 334 static void _InitTransferPageSize(struct adapter *Adapter)
 335 {
 336         /*  Tx page size is always 128. */
 337
 338         u8 value8;
 339         value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
 340         rtw_write8(Adapter, REG_PBP, value8);
 341 }
 342
 343 static void _InitDriverInfoSize(struct adapter *Adapter, u8 drvInfoSize)
 344 {
 345         rtw_write8(Adapter, REG_RX_DRVINFO_SZ, drvInfoSize);
 346 }
 347
 348 static void _InitWMACSetting(struct adapter *Adapter)
 349 {
 350         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
 351
 352         haldata->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AB |
 353                                   RCR_CBSSID_DATA | RCR_CBSSID_BCN |
 354                                   RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
 355                                   RCR_APP_MIC | RCR_APP_PHYSTS;
 356
 357         /*  some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile() */
 358         rtw_write32(Adapter, REG_RCR, haldata->ReceiveConfig);
 359
 360         /*  Accept all multicast address */
 361         rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF);
 362         rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
 363 }
 364
 365 static void _InitAdaptiveCtrl(struct adapter *Adapter)
 366 {
 367         u16 value16;
 368         u32 value32;
 369
 370         /*  Response Rate Set */
 371         value32 = rtw_read32(Adapter, REG_RRSR);
 372         value32 &= ~RATE_BITMAP_ALL;
 373         value32 |= RATE_RRSR_CCK_ONLY_1M;
 374         rtw_write32(Adapter, REG_RRSR, value32);
 375
 376         /*  CF-END Threshold */
 377
 378         /*  SIFS (used in NAV) */
 379         value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
 380         rtw_write16(Adapter, REG_SPEC_SIFS, value16);
 381
 382         /*  Retry Limit */
 383         value16 = _LRL(0x30) | _SRL(0x30);
 384         rtw_write16(Adapter, REG_RL, value16);
 385 }
 386
 387 static void _InitEDCA(struct adapter *Adapter)
 388 {
 389         /*  Set Spec SIFS (used in NAV) */
 390         rtw_write16(Adapter, REG_SPEC_SIFS, 0x100a);
 391         rtw_write16(Adapter, REG_MAC_SPEC_SIFS, 0x100a);
 392
 393         /*  Set SIFS for CCK */
 394         rtw_write16(Adapter, REG_SIFS_CTX, 0x100a);
 395
 396         /*  Set SIFS for OFDM */
 397         rtw_write16(Adapter, REG_SIFS_TRX, 0x100a);
 398
 399         /*  TXOP */
 400         rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
 401         rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
 402         rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
 403         rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
 404 }
 405
 406 static void _InitBeaconMaxError(struct adapter *Adapter, bool           InfraMode)
 407 {
 408 }
 409
 410 static void _InitHWLed(struct adapter *Adapter)
 411 {
 412         struct led_priv *pledpriv = &(Adapter->ledpriv);
 413
 414         if (pledpriv->LedStrategy != HW_LED)
 415                 return;
 416
 417 /*  HW led control */
 418 /*  to do .... */
 419 /* must consider cases of antenna diversity/ commbo card/solo card/mini card */
 420 }
 421
 422 static void _InitRDGSetting(struct adapter *Adapter)
 423 {
 424         rtw_write8(Adapter, REG_RD_CTRL, 0xFF);
 425         rtw_write16(Adapter, REG_RD_NAV_NXT, 0x200);
 426         rtw_write8(Adapter, REG_RD_RESP_PKT_TH, 0x05);
 427 }
 428
 429 static void _InitRxSetting(struct adapter *Adapter)
 430 {
 431         rtw_write32(Adapter, REG_MACID, 0x87654321);
 432         rtw_write32(Adapter, 0x0700, 0x87654321);
 433 }
 434
 435 static void _InitRetryFunction(struct adapter *Adapter)
 436 {
 437         u8 value8;
 438
 439         value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL);
 440         value8 |= EN_AMPDU_RTY_NEW;
 441         rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
 442
 443         /*  Set ACK timeout */
 444         rtw_write8(Adapter, REG_ACKTO, 0x40);
 445 }
 446
 447 /*-----------------------------------------------------------------------------
 448  * Function:    usb_AggSettingTxUpdate()
 449  *
 450  * Overview:    Separate TX/RX parameters update independent for TP detection and
 451  *                      dynamic TX/RX aggreagtion parameters update.
 452  *
 453  * Input:                       struct adapter *
 454  *
 455  * Output/Return:       NONE
 456  *
 457  * Revised History:
 458  *      When            Who             Remark
 459  *      12/10/2010      MHC             Separate to smaller function.
 460  *
 461  *---------------------------------------------------------------------------*/
 462 static void usb_AggSettingTxUpdate(struct adapter *Adapter)
 463 {
 464         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
 465         u32 value32;
 466
 467         if (Adapter->registrypriv.wifi_spec)
 468                 haldata->UsbTxAggMode = false;
 469
 470         if (haldata->UsbTxAggMode) {
 471                 value32 = rtw_read32(Adapter, REG_TDECTRL);
 472                 value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
 473                 value32 |= ((haldata->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
 474
 475                 rtw_write32(Adapter, REG_TDECTRL, value32);
 476         }
 477 }       /*  usb_AggSettingTxUpdate */
 478
 479 /*-----------------------------------------------------------------------------
 480  * Function:    usb_AggSettingRxUpdate()
 481  *
 482  * Overview:    Separate TX/RX parameters update independent for TP detection and
 483  *                      dynamic TX/RX aggreagtion parameters update.
 484  *
 485  * Input:                       struct adapter *
 486  *
 487  * Output/Return:       NONE
 488  *
 489  * Revised History:
 490  *      When            Who             Remark
 491  *      12/10/2010      MHC             Separate to smaller function.
 492  *
 493  *---------------------------------------------------------------------------*/
 494 static void
 495 usb_AggSettingRxUpdate(
 496                 struct adapter *Adapter
 497         )
 498 {
 499         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
 500         u8 valueDMA;
 501         u8 valueUSB;
 502
 503         valueDMA = rtw_read8(Adapter, REG_TRXDMA_CTRL);
 504         valueUSB = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
 505
 506         switch (haldata->UsbRxAggMode) {
 507         case USB_RX_AGG_DMA:
 508                 valueDMA |= RXDMA_AGG_EN;
 509                 valueUSB &= ~USB_AGG_EN;
 510                 break;
 511         case USB_RX_AGG_USB:
 512                 valueDMA &= ~RXDMA_AGG_EN;
 513                 valueUSB |= USB_AGG_EN;
 514                 break;
 515         case USB_RX_AGG_MIX:
 516                 valueDMA |= RXDMA_AGG_EN;
 517                 valueUSB |= USB_AGG_EN;
 518                 break;
 519         case USB_RX_AGG_DISABLE:
 520         default:
 521                 valueDMA &= ~RXDMA_AGG_EN;
 522                 valueUSB &= ~USB_AGG_EN;
 523                 break;
 524         }
 525
 526         rtw_write8(Adapter, REG_TRXDMA_CTRL, valueDMA);
 527         rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, valueUSB);
 528
 529         switch (haldata->UsbRxAggMode) {
 530         case USB_RX_AGG_DMA:
 531                 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, haldata->UsbRxAggPageCount);
 532                 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, haldata->UsbRxAggPageTimeout);
 533                 break;
 534         case USB_RX_AGG_USB:
 535                 rtw_write8(Adapter, REG_USB_AGG_TH, haldata->UsbRxAggBlockCount);
 536                 rtw_write8(Adapter, REG_USB_AGG_TO, haldata->UsbRxAggBlockTimeout);
 537                 break;
 538         case USB_RX_AGG_MIX:
 539                 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, haldata->UsbRxAggPageCount);
 540                 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, (haldata->UsbRxAggPageTimeout & 0x1F));/* 0x280[12:8] */
 541                 rtw_write8(Adapter, REG_USB_AGG_TH, haldata->UsbRxAggBlockCount);
 542                 rtw_write8(Adapter, REG_USB_AGG_TO, haldata->UsbRxAggBlockTimeout);
 543                 break;
 544         case USB_RX_AGG_DISABLE:
 545         default:
 546                 /*  TODO: */
 547                 break;
 548         }
 549
 550         switch (PBP_128) {
 551         case PBP_128:
 552                 haldata->HwRxPageSize = 128;
 553                 break;
 554         case PBP_64:
 555                 haldata->HwRxPageSize = 64;
 556                 break;
 557         case PBP_256:
 558                 haldata->HwRxPageSize = 256;
 559                 break;
 560         case PBP_512:
 561                 haldata->HwRxPageSize = 512;
 562                 break;
 563         case PBP_1024:
 564                 haldata->HwRxPageSize = 1024;
 565                 break;
 566         default:
 567                 break;
 568         }
 569 }       /*  usb_AggSettingRxUpdate */
 570
 571 static void InitUsbAggregationSetting(struct adapter *Adapter)
 572 {
 573         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
 574
 575         /*  Tx aggregation setting */
 576         usb_AggSettingTxUpdate(Adapter);
 577
 578         /*  Rx aggregation setting */
 579         usb_AggSettingRxUpdate(Adapter);
 580
 581         /*  201/12/10 MH Add for USB agg mode dynamic switch. */
 582         haldata->UsbRxHighSpeedMode = false;
 583 }
 584
 585 static void _InitOperationMode(struct adapter *Adapter)
 586 {
 587 }
 588
 589 static void _InitBeaconParameters(struct adapter *Adapter)
 590 {
 591         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
 592
 593         rtw_write16(Adapter, REG_BCN_CTRL, 0x1010);
 594
 595         /*  TODO: Remove these magic number */
 596         rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0x6404);/*  ms */
 597         rtw_write8(Adapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);/*  5ms */
 598         rtw_write8(Adapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME); /*  2ms */
 599
 600         /*  Suggested by designer timchen. Change beacon AIFS to the largest number */
 601         /*  beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 */
 602         rtw_write16(Adapter, REG_BCNTCFG, 0x660F);
 603
 604         haldata->RegBcnCtrlVal = rtw_read8(Adapter, REG_BCN_CTRL);
 605         haldata->RegTxPause = rtw_read8(Adapter, REG_TXPAUSE);
 606         haldata->RegFwHwTxQCtrl = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL+2);
 607         haldata->RegReg542 = rtw_read8(Adapter, REG_TBTT_PROHIBIT+2);
 608         haldata->RegCR_1 = rtw_read8(Adapter, REG_CR+1);
 609 }
 610
 611 static void _BeaconFunctionEnable(struct adapter *Adapter,
 612                                   bool Enable, bool Linked)
 613 {
 614         rtw_write8(Adapter, REG_BCN_CTRL, (BIT4 | BIT3 | BIT1));
 615
 616         rtw_write8(Adapter, REG_RD_CTRL+1, 0x6F);
 617 }
 618
 619 /*  Set CCK and OFDM Block "ON" */
 620 static void _BBTurnOnBlock(struct adapter *Adapter)
 621 {
 622         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
 623         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
 624 }
 625
 626 enum {
 627         Antenna_Lfet = 1,
 628         Antenna_Right = 2,
 629 };
 630
 631 static void _InitAntenna_Selection(struct adapter *Adapter)
 632 {
 633         struct hal_data_8188e   *haldata        = GET_HAL_DATA(Adapter);
 634
 635         if (haldata->AntDivCfg == 0)
 636                 return;
 637         DBG_88E("==>  %s ....\n", __func__);
 638
 639         rtw_write32(Adapter, REG_LEDCFG0, rtw_read32(Adapter, REG_LEDCFG0)|BIT23);
 640         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
 641
 642         if (PHY_QueryBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A)
 643                 haldata->CurAntenna = Antenna_A;
 644         else
 645                 haldata->CurAntenna = Antenna_B;
 646         DBG_88E("%s,Cur_ant:(%x)%s\n", __func__, haldata->CurAntenna, (haldata->CurAntenna == Antenna_A) ? "Antenna_A" : "Antenna_B");
 647 }
 648
 649 /*-----------------------------------------------------------------------------
 650  * Function:    HwSuspendModeEnable92Cu()
 651  *
 652  * Overview:    HW suspend mode switch.
 653  *
 654  * Input:               NONE
 655  *
 656  * Output:      NONE
 657  *
 658  * Return:      NONE
 659  *
 660  * Revised History:
 661  *      When            Who             Remark
 662  *      08/23/2010      MHC             HW suspend mode switch test..
 663  *---------------------------------------------------------------------------*/
 664 enum rt_rf_power_state RfOnOffDetect(struct adapter *adapt)
 665 {
 666         u8 val8;
 667         enum rt_rf_power_state rfpowerstate = rf_off;
 668
 669         if (adapt->pwrctrlpriv.bHWPowerdown) {
 670                 val8 = rtw_read8(adapt, REG_HSISR);
 671                 DBG_88E("pwrdown, 0x5c(BIT7)=%02x\n", val8);
 672                 rfpowerstate = (val8 & BIT7) ? rf_off : rf_on;
 673         } else { /*  rf on/off */
 674                 rtw_write8(adapt, REG_MAC_PINMUX_CFG, rtw_read8(adapt, REG_MAC_PINMUX_CFG)&~(BIT3));
 675                 val8 = rtw_read8(adapt, REG_GPIO_IO_SEL);
 676                 DBG_88E("GPIO_IN=%02x\n", val8);
 677                 rfpowerstate = (val8 & BIT3) ? rf_on : rf_off;
 678         }
 679         return rfpowerstate;
 680 }       /*  HalDetectPwrDownMode */
 681
 682 static u32 rtl8188eu_hal_init(struct adapter *Adapter)
 683 {
 684         u8 value8 = 0;
 685         u16  value16;
 686         u8 txpktbuf_bndy;
 687         u32 status = _SUCCESS;
 688         struct hal_data_8188e           *haldata = GET_HAL_DATA(Adapter);
 689         struct pwrctrl_priv             *pwrctrlpriv = &Adapter->pwrctrlpriv;
 690         struct registry_priv    *pregistrypriv = &Adapter->registrypriv;
 691         u32 init_start_time = jiffies;
 692
 693         #define HAL_INIT_PROFILE_TAG(stage) do {} while (0)
 694
 695         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
 696
 697         if (Adapter->pwrctrlpriv.bkeepfwalive) {
 698                 _ps_open_RF(Adapter);
 699
 700                 if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) {
 701                         PHY_IQCalibrate_8188E(Adapter, true);
 702                 } else {
 703                         PHY_IQCalibrate_8188E(Adapter, false);
 704                         haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
 705                 }
 706
 707                 ODM_TXPowerTrackingCheck(&haldata->odmpriv);
 708                 PHY_LCCalibrate_8188E(Adapter);
 709
 710                 goto exit;
 711         }
 712
 713         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
 714         status = rtl8188eu_InitPowerOn(Adapter);
 715         if (status == _FAIL) {
 716                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n"));
 717                 goto exit;
 718         }
 719
 720         /*  Save target channel */
 721         haldata->CurrentChannel = 6;/* default set to 6 */
 722
 723         if (pwrctrlpriv->reg_rfoff) {
 724                 pwrctrlpriv->rf_pwrstate = rf_off;
 725         }
 726
 727         /*  2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
 728         /*  HW GPIO pin. Before PHY_RFConfig8192C. */
 729         /*  2010/08/26 MH If Efuse does not support sective suspend then disable the function. */
 730
 731         if (!pregistrypriv->wifi_spec) {
 732                 txpktbuf_bndy = TX_PAGE_BOUNDARY_88E;
 733         } else {
 734                 /*  for WMM */
 735                 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_88E;
 736         }
 737
 738         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
 739         _InitQueueReservedPage(Adapter);
 740         _InitQueuePriority(Adapter);
 741         _InitPageBoundary(Adapter);
 742         _InitTransferPageSize(Adapter);
 743
 744         _InitTxBufferBoundary(Adapter, 0);
 745
 746         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
 747         if (Adapter->registrypriv.mp_mode == 1) {
 748                 _InitRxSetting(Adapter);
 749                 Adapter->bFWReady = false;
 750                 haldata->fw_ractrl = false;
 751         } else {
 752                 status = rtl8188e_FirmwareDownload(Adapter);
 753
 754                 if (status != _SUCCESS) {
 755                         DBG_88E("%s: Download Firmware failed!!\n", __func__);
 756                         Adapter->bFWReady = false;
 757                         haldata->fw_ractrl = false;
 758                         return status;
 759                 } else {
 760                         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializeadapt8192CSdio(): Download Firmware Success!!\n"));
 761                         Adapter->bFWReady = true;
 762                         haldata->fw_ractrl = false;
 763                 }
 764         }
 765         rtl8188e_InitializeFirmwareVars(Adapter);
 766
 767         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
 768 #if (HAL_MAC_ENABLE == 1)
 769         status = PHY_MACConfig8188E(Adapter);
 770         if (status == _FAIL) {
 771                 DBG_88E(" ### Failed to init MAC ......\n ");
 772                 goto exit;
 773         }
 774 #endif
 775
 776         /*  */
 777         /* d. Initialize BB related configurations. */
 778         /*  */
 779         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
 780 #if (HAL_BB_ENABLE == 1)
 781         status = PHY_BBConfig8188E(Adapter);
 782         if (status == _FAIL) {
 783                 DBG_88E(" ### Failed to init BB ......\n ");
 784                 goto exit;
 785         }
 786 #endif
 787
 788         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
 789 #if (HAL_RF_ENABLE == 1)
 790         status = PHY_RFConfig8188E(Adapter);
 791         if (status == _FAIL) {
 792                 DBG_88E(" ### Failed to init RF ......\n ");
 793                 goto exit;
 794         }
 795 #endif
 796
 797         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_EFUSE_PATCH);
 798         status = rtl8188e_iol_efuse_patch(Adapter);
 799         if (status == _FAIL) {
 800                 DBG_88E("%s  rtl8188e_iol_efuse_patch failed\n", __func__);
 801                 goto exit;
 802         }
 803
 804         _InitTxBufferBoundary(Adapter, txpktbuf_bndy);
 805
 806         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
 807         status =  InitLLTTable(Adapter, txpktbuf_bndy);
 808         if (status == _FAIL) {
 809                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n"));
 810                 goto exit;
 811         }
 812
 813         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
 814         /*  Get Rx PHY status in order to report RSSI and others. */
 815         _InitDriverInfoSize(Adapter, DRVINFO_SZ);
 816
 817         _InitInterrupt(Adapter);
 818         hal_init_macaddr(Adapter);/* set mac_address */
 819         _InitNetworkType(Adapter);/* set msr */
 820         _InitWMACSetting(Adapter);
 821         _InitAdaptiveCtrl(Adapter);
 822         _InitEDCA(Adapter);
 823         _InitRetryFunction(Adapter);
 824         InitUsbAggregationSetting(Adapter);
 825         _InitOperationMode(Adapter);/* todo */
 826         _InitBeaconParameters(Adapter);
 827         _InitBeaconMaxError(Adapter, true);
 828
 829         /*  */
 830         /*  Init CR MACTXEN, MACRXEN after setting RxFF boundary REG_TRXFF_BNDY to patch */
 831         /*  Hw bug which Hw initials RxFF boundary size to a value which is larger than the real Rx buffer size in 88E. */
 832         /*  */
 833         /*  Enable MACTXEN/MACRXEN block */
 834         value16 = rtw_read16(Adapter, REG_CR);
 835         value16 |= (MACTXEN | MACRXEN);
 836         rtw_write8(Adapter, REG_CR, value16);
 837
 838         if (haldata->bRDGEnable)
 839                 _InitRDGSetting(Adapter);
 840
 841         /* Enable TX Report */
 842         /* Enable Tx Report Timer */
 843         value8 = rtw_read8(Adapter, REG_TX_RPT_CTRL);
 844         rtw_write8(Adapter,  REG_TX_RPT_CTRL, (value8|BIT1|BIT0));
 845         /* Set MAX RPT MACID */
 846         rtw_write8(Adapter,  REG_TX_RPT_CTRL+1, 2);/* FOR sta mode ,0: bc/mc ,1:AP */
 847         /* Tx RPT Timer. Unit: 32us */
 848         rtw_write16(Adapter, REG_TX_RPT_TIME, 0xCdf0);
 849
 850         rtw_write8(Adapter, REG_EARLY_MODE_CONTROL, 0);
 851
 852         rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400);  /*  unit: 256us. 256ms */
 853         rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400);  /*  unit: 256us. 256ms */
 854
 855         _InitHWLed(Adapter);
 856
 857         /* Keep RfRegChnlVal for later use. */
 858         haldata->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (enum rf_radio_path)0, RF_CHNLBW, bRFRegOffsetMask);
 859         haldata->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (enum rf_radio_path)1, RF_CHNLBW, bRFRegOffsetMask);
 860
 861 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
 862         _BBTurnOnBlock(Adapter);
 863
 864 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
 865         invalidate_cam_all(Adapter);
 866
 867 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
 868         /*  2010/12/17 MH We need to set TX power according to EFUSE content at first. */
 869         PHY_SetTxPowerLevel8188E(Adapter, haldata->CurrentChannel);
 870
 871 /*  Move by Neo for USB SS to below setp */
 872 /* _RfPowerSave(Adapter); */
 873
 874         _InitAntenna_Selection(Adapter);
 875
 876         /*  */
 877         /*  Disable BAR, suggested by Scott */
 878         /*  2010.04.09 add by hpfan */
 879         /*  */
 880         rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
 881
 882         /*  HW SEQ CTRL */
 883         /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
 884         rtw_write8(Adapter, REG_HWSEQ_CTRL, 0xFF);
 885
 886         if (pregistrypriv->wifi_spec)
 887                 rtw_write16(Adapter, REG_FAST_EDCA_CTRL, 0);
 888
 889         /* Nav limit , suggest by scott */
 890         rtw_write8(Adapter, 0x652, 0x0);
 891
 892 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
 893         rtl8188e_InitHalDm(Adapter);
 894
 895         if (Adapter->registrypriv.mp_mode == 1) {
 896                 Adapter->mppriv.channel = haldata->CurrentChannel;
 897                 MPT_InitializeAdapter(Adapter, Adapter->mppriv.channel);
 898         } else {
 899                 /*  2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status */
 900                 /*  and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not */
 901                 /*  call initstruct adapter. May cause some problem?? */
 902                 /*  Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed */
 903                 /*  in MgntActSet_RF_State() after wake up, because the value of haldata->eRFPowerState */
 904                 /*  is the same as eRfOff, we should change it to eRfOn after we config RF parameters. */
 905                 /*  Added by tynli. 2010.03.30. */
 906                 pwrctrlpriv->rf_pwrstate = rf_on;
 907
 908                 /*  enable Tx report. */
 909                 rtw_write8(Adapter,  REG_FWHW_TXQ_CTRL+1, 0x0F);
 910
 911                 /*  Suggested by SD1 pisa. Added by tynli. 2011.10.21. */
 912                 rtw_write8(Adapter, REG_EARLY_MODE_CONTROL+3, 0x01);/* Pretx_en, for WEP/TKIP SEC */
 913
 914                 /* tynli_test_tx_report. */
 915                 rtw_write16(Adapter, REG_TX_RPT_TIME, 0x3DF0);
 916
 917                 /* enable tx DMA to drop the redundate data of packet */
 918                 rtw_write16(Adapter, REG_TXDMA_OFFSET_CHK, (rtw_read16(Adapter, REG_TXDMA_OFFSET_CHK) | DROP_DATA_EN));
 919
 920 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
 921                 /*  2010/08/26 MH Merge from 8192CE. */
 922                 if (pwrctrlpriv->rf_pwrstate == rf_on) {
 923                         if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) {
 924                                 PHY_IQCalibrate_8188E(Adapter, true);
 925                         } else {
 926                                 PHY_IQCalibrate_8188E(Adapter, false);
 927                                 haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
 928                         }
 929
 930 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
 931
 932                         ODM_TXPowerTrackingCheck(&haldata->odmpriv);
 933
 934 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
 935                         PHY_LCCalibrate_8188E(Adapter);
 936                 }
 937         }
 938
 939 /* HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS); */
 940 /*      _InitPABias(Adapter); */
 941         rtw_write8(Adapter, REG_USB_HRPWM, 0);
 942
 943         /* ack for xmit mgmt frames. */
 944         rtw_write32(Adapter, REG_FWHW_TXQ_CTRL, rtw_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12));
 945
 946 exit:
 947 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
 948
 949         DBG_88E("%s in %dms\n", __func__, rtw_get_passing_time_ms(init_start_time));
 950
 951         return status;
 952 }
 953
 954 void _ps_open_RF(struct adapter *adapt)
 955 {
 956         /* here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified */
 957         /* phy_SsPwrSwitch92CU(adapt, rf_on, 1); */
 958 }
 959
 960 static void _ps_close_RF(struct adapter *adapt)
 961 {
 962         /* here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified */
 963         /* phy_SsPwrSwitch92CU(adapt, rf_off, 1); */
 964 }
 965
 966 static void CardDisableRTL8188EU(struct adapter *Adapter)
 967 {
 968         u8 val8;
 969         struct hal_data_8188e   *haldata        = GET_HAL_DATA(Adapter);
 970
 971         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("CardDisableRTL8188EU\n"));
 972
 973         /* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */
 974         val8 = rtw_read8(Adapter, REG_TX_RPT_CTRL);
 975         rtw_write8(Adapter, REG_TX_RPT_CTRL, val8&(~BIT1));
 976
 977         /*  stop rx */
 978         rtw_write8(Adapter, REG_CR, 0x0);
 979
 980         /*  Run LPS WL RFOFF flow */
 981         HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_LPS_ENTER_FLOW);
 982
 983         /*  2. 0x1F[7:0] = 0            turn off RF */
 984
 985         val8 = rtw_read8(Adapter, REG_MCUFWDL);
 986         if ((val8 & RAM_DL_SEL) && Adapter->bFWReady) { /* 8051 RAM code */
 987                 /*  Reset MCU 0x2[10]=0. */
 988                 val8 = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
 989                 val8 &= ~BIT(2);        /*  0x2[10], FEN_CPUEN */
 990                 rtw_write8(Adapter, REG_SYS_FUNC_EN+1, val8);
 991         }
 992
 993         /*  reset MCU ready status */
 994         rtw_write8(Adapter, REG_MCUFWDL, 0);
 995
 996         /* YJ,add,111212 */
 997         /* Disable 32k */
 998         val8 = rtw_read8(Adapter, REG_32K_CTRL);
 999         rtw_write8(Adapter, REG_32K_CTRL, val8&(~BIT0));
1000
1001         /*  Card disable power action flow */
1002         HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_DISABLE_FLOW);
1003
1004         /*  Reset MCU IO Wrapper */
1005         val8 = rtw_read8(Adapter, REG_RSV_CTRL+1);
1006         rtw_write8(Adapter, REG_RSV_CTRL+1, (val8&(~BIT3)));
1007         val8 = rtw_read8(Adapter, REG_RSV_CTRL+1);
1008         rtw_write8(Adapter, REG_RSV_CTRL+1, val8|BIT3);
1009
1010         /* YJ,test add, 111207. For Power Consumption. */
1011         val8 = rtw_read8(Adapter, GPIO_IN);
1012         rtw_write8(Adapter, GPIO_OUT, val8);
1013         rtw_write8(Adapter, GPIO_IO_SEL, 0xFF);/* Reg0x46 */
1014
1015         val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL);
1016         rtw_write8(Adapter, REG_GPIO_IO_SEL, (val8<<4));
1017         val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL+1);
1018         rtw_write8(Adapter, REG_GPIO_IO_SEL+1, val8|0x0F);/* Reg0x43 */
1019         rtw_write32(Adapter, REG_BB_PAD_CTRL, 0x00080808);/* set LNA ,TRSW,EX_PA Pin to output mode */
1020         haldata->bMacPwrCtrlOn = false;
1021         Adapter->bFWReady = false;
1022 }
1023 static void rtl8192cu_hw_power_down(struct adapter *adapt)
1024 {
1025         /*  2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c. */
1026         /*  Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1. */
1027
1028         /*  Enable register area 0x0-0xc. */
1029         rtw_write8(adapt, REG_RSV_CTRL, 0x0);
1030         rtw_write16(adapt, REG_APS_FSMCO, 0x8812);
1031 }
1032
1033 static u32 rtl8188eu_hal_deinit(struct adapter *Adapter)
1034 {
1035
1036         DBG_88E("==> %s\n", __func__);
1037
1038         rtw_write32(Adapter, REG_HIMR_88E, IMR_DISABLED_88E);
1039         rtw_write32(Adapter, REG_HIMRE_88E, IMR_DISABLED_88E);
1040
1041         DBG_88E("bkeepfwalive(%x)\n", Adapter->pwrctrlpriv.bkeepfwalive);
1042         if (Adapter->pwrctrlpriv.bkeepfwalive) {
1043                 _ps_close_RF(Adapter);
1044                 if ((Adapter->pwrctrlpriv.bHWPwrPindetect) && (Adapter->pwrctrlpriv.bHWPowerdown))
1045                         rtl8192cu_hw_power_down(Adapter);
1046         } else {
1047                 if (Adapter->hw_init_completed) {
1048                         CardDisableRTL8188EU(Adapter);
1049
1050                         if ((Adapter->pwrctrlpriv.bHWPwrPindetect) && (Adapter->pwrctrlpriv.bHWPowerdown))
1051                                 rtl8192cu_hw_power_down(Adapter);
1052                 }
1053         }
1054         return _SUCCESS;
1055  }
1056
1057 static unsigned int rtl8188eu_inirp_init(struct adapter *Adapter)
1058 {
1059         u8 i;
1060         struct recv_buf *precvbuf;
1061         uint    status;
1062         struct intf_hdl *pintfhdl = &Adapter->iopriv.intf;
1063         struct recv_priv *precvpriv = &(Adapter->recvpriv);
1064         u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
1065
1066         _read_port = pintfhdl->io_ops._read_port;
1067
1068         status = _SUCCESS;
1069
1070         RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1071                  ("===> usb_inirp_init\n"));
1072
1073         precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR;
1074
1075         /* issue Rx irp to receive data */
1076         precvbuf = (struct recv_buf *)precvpriv->precv_buf;
1077         for (i = 0; i < NR_RECVBUFF; i++) {
1078                 if (_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == false) {
1079                         RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("usb_rx_init: usb_read_port error\n"));
1080                         status = _FAIL;
1081                         goto exit;
1082                 }
1083
1084                 precvbuf++;
1085                 precvpriv->free_recv_buf_queue_cnt--;
1086         }
1087
1088 exit:
1089
1090         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("<=== usb_inirp_init\n"));
1091
1092         return status;
1093 }
1094
1095 static unsigned int rtl8188eu_inirp_deinit(struct adapter *Adapter)
1096 {
1097         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("\n ===> usb_rx_deinit\n"));
1098
1099         rtw_read_port_cancel(Adapter);
1100
1101         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("\n <=== usb_rx_deinit\n"));
1102
1103         return _SUCCESS;
1104 }
1105
1106 /*  */
1107 /*  */
1108 /*      EEPROM/EFUSE Content Parsing */
1109 /*  */
1110 /*  */
1111 static void _ReadLEDSetting(struct adapter *Adapter, u8 *PROMContent, bool AutoloadFail)
1112 {
1113         struct led_priv *pledpriv = &(Adapter->ledpriv);
1114         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
1115
1116         pledpriv->bRegUseLed = true;
1117         pledpriv->LedStrategy = SW_LED_MODE1;
1118         haldata->bLedOpenDrain = true;/*  Support Open-drain arrangement for controlling the LED. */
1119 }
1120
1121 static void Hal_EfuseParsePIDVID_8188EU(struct adapter *adapt, u8 *hwinfo, bool AutoLoadFail)
1122 {
1123         struct hal_data_8188e   *haldata = GET_HAL_DATA(adapt);
1124
1125         if (!AutoLoadFail) {
1126                 /*  VID, PID */
1127                 haldata->EEPROMVID = EF2BYTE(*(__le16 *)&hwinfo[EEPROM_VID_88EU]);
1128                 haldata->EEPROMPID = EF2BYTE(*(__le16 *)&hwinfo[EEPROM_PID_88EU]);
1129
1130                 /*  Customer ID, 0x00 and 0xff are reserved for Realtek. */
1131                 haldata->EEPROMCustomerID = *(u8 *)&hwinfo[EEPROM_CUSTOMERID_88E];
1132                 haldata->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
1133         } else {
1134                 haldata->EEPROMVID                      = EEPROM_Default_VID;
1135                 haldata->EEPROMPID                      = EEPROM_Default_PID;
1136
1137                 /*  Customer ID, 0x00 and 0xff are reserved for Realtek. */
1138                 haldata->EEPROMCustomerID               = EEPROM_Default_CustomerID;
1139                 haldata->EEPROMSubCustomerID    = EEPROM_Default_SubCustomerID;
1140         }
1141
1142         DBG_88E("VID = 0x%04X, PID = 0x%04X\n", haldata->EEPROMVID, haldata->EEPROMPID);
1143         DBG_88E("Customer ID: 0x%02X, SubCustomer ID: 0x%02X\n", haldata->EEPROMCustomerID, haldata->EEPROMSubCustomerID);
1144 }
1145
1146 static void Hal_EfuseParseMACAddr_8188EU(struct adapter *adapt, u8 *hwinfo, bool AutoLoadFail)
1147 {
1148         u16 i;
1149         u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x88, 0x02};
1150         struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
1151
1152         if (AutoLoadFail) {
1153                 for (i = 0; i < 6; i++)
1154                         eeprom->mac_addr[i] = sMacAddr[i];
1155         } else {
1156                 /* Read Permanent MAC address */
1157                 memcpy(eeprom->mac_addr, &hwinfo[EEPROM_MAC_ADDR_88EU], ETH_ALEN);
1158         }
1159         RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
1160                  ("Hal_EfuseParseMACAddr_8188EU: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
1161                  eeprom->mac_addr[0], eeprom->mac_addr[1],
1162                  eeprom->mac_addr[2], eeprom->mac_addr[3],
1163                  eeprom->mac_addr[4], eeprom->mac_addr[5]));
1164 }
1165
1166 static void Hal_CustomizeByCustomerID_8188EU(struct adapter *adapt)
1167 {
1168 }
1169
1170 static void
1171 readAdapterInfo_8188EU(
1172                 struct adapter *adapt
1173         )
1174 {
1175         struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
1176
1177         /* parse the eeprom/efuse content */
1178         Hal_EfuseParseIDCode88E(adapt, eeprom->efuse_eeprom_data);
1179         Hal_EfuseParsePIDVID_8188EU(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1180         Hal_EfuseParseMACAddr_8188EU(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1181
1182         Hal_ReadPowerSavingMode88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1183         Hal_ReadTxPowerInfo88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1184         Hal_EfuseParseEEPROMVer88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1185         rtl8188e_EfuseParseChnlPlan(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1186         Hal_EfuseParseXtal_8188E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1187         Hal_EfuseParseCustomerID88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1188         Hal_ReadAntennaDiversity88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1189         Hal_EfuseParseBoardType88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1190         Hal_ReadThermalMeter_88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1191
1192         /*  */
1193         /*  The following part initialize some vars by PG info. */
1194         /*  */
1195         Hal_InitChannelPlan(adapt);
1196         Hal_CustomizeByCustomerID_8188EU(adapt);
1197
1198         _ReadLEDSetting(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1199 }
1200
1201 static void _ReadPROMContent(
1202         struct adapter *Adapter
1203         )
1204 {
1205         struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(Adapter);
1206         u8 eeValue;
1207
1208         /* check system boot selection */
1209         eeValue = rtw_read8(Adapter, REG_9346CR);
1210         eeprom->EepromOrEfuse           = (eeValue & BOOT_FROM_EEPROM) ? true : false;
1211         eeprom->bautoload_fail_flag     = (eeValue & EEPROM_EN) ? false : true;
1212
1213         DBG_88E("Boot from %s, Autoload %s !\n", (eeprom->EepromOrEfuse ? "EEPROM" : "EFUSE"),
1214                 (eeprom->bautoload_fail_flag ? "Fail" : "OK"));
1215
1216         Hal_InitPGData88E(Adapter);
1217         readAdapterInfo_8188EU(Adapter);
1218 }
1219
1220 static void _ReadRFType(struct adapter *Adapter)
1221 {
1222         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
1223
1224         haldata->rf_chip = RF_6052;
1225 }
1226
1227 static int _ReadAdapterInfo8188EU(struct adapter *Adapter)
1228 {
1229         u32 start = jiffies;
1230
1231         MSG_88E("====> %s\n", __func__);
1232
1233         _ReadRFType(Adapter);/* rf_chip -> _InitRFType() */
1234         _ReadPROMContent(Adapter);
1235
1236         MSG_88E("<==== %s in %d ms\n", __func__, rtw_get_passing_time_ms(start));
1237
1238         return _SUCCESS;
1239 }
1240
1241 static void ReadAdapterInfo8188EU(struct adapter *Adapter)
1242 {
1243         /*  Read EEPROM size before call any EEPROM function */
1244         Adapter->EepromAddressSize = GetEEPROMSize8188E(Adapter);
1245
1246         _ReadAdapterInfo8188EU(Adapter);
1247 }
1248
1249 #define GPIO_DEBUG_PORT_NUM 0
1250 static void rtl8192cu_trigger_gpio_0(struct adapter *adapt)
1251 {
1252 }
1253
1254 static void ResumeTxBeacon(struct adapter *adapt)
1255 {
1256         struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
1257
1258         /*  2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */
1259         /*  which should be read from register to a global variable. */
1260
1261         rtw_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) | BIT6);
1262         haldata->RegFwHwTxQCtrl |= BIT6;
1263         rtw_write8(adapt, REG_TBTT_PROHIBIT+1, 0xff);
1264         haldata->RegReg542 |= BIT0;
1265         rtw_write8(adapt, REG_TBTT_PROHIBIT+2, haldata->RegReg542);
1266 }
1267
1268 static void StopTxBeacon(struct adapter *adapt)
1269 {
1270         struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
1271
1272         /*  2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */
1273         /*  which should be read from register to a global variable. */
1274
1275         rtw_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) & (~BIT6));
1276         haldata->RegFwHwTxQCtrl &= (~BIT6);
1277         rtw_write8(adapt, REG_TBTT_PROHIBIT+1, 0x64);
1278         haldata->RegReg542 &= ~(BIT0);
1279         rtw_write8(adapt, REG_TBTT_PROHIBIT+2, haldata->RegReg542);
1280
1281          /* todo: CheckFwRsvdPageContent(Adapter);  2010.06.23. Added by tynli. */
1282 }
1283
1284 static void hw_var_set_opmode(struct adapter *Adapter, u8 variable, u8 *val)
1285 {
1286         u8 val8;
1287         u8 mode = *((u8 *)val);
1288
1289         /*  disable Port0 TSF update */
1290         rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
1291
1292         /*  set net_type */
1293         val8 = rtw_read8(Adapter, MSR)&0x0c;
1294         val8 |= mode;
1295         rtw_write8(Adapter, MSR, val8);
1296
1297         DBG_88E("%s()-%d mode = %d\n", __func__, __LINE__, mode);
1298
1299         if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
1300                 StopTxBeacon(Adapter);
1301
1302                 rtw_write8(Adapter, REG_BCN_CTRL, 0x19);/* disable atim wnd */
1303         } else if ((mode == _HW_STATE_ADHOC_)) {
1304                 ResumeTxBeacon(Adapter);
1305                 rtw_write8(Adapter, REG_BCN_CTRL, 0x1a);
1306         } else if (mode == _HW_STATE_AP_) {
1307                 ResumeTxBeacon(Adapter);
1308
1309                 rtw_write8(Adapter, REG_BCN_CTRL, 0x12);
1310
1311                 /* Set RCR */
1312                 rtw_write32(Adapter, REG_RCR, 0x7000208e);/* CBSSID_DATA must set to 0,reject ICV_ERR packet */
1313                 /* enable to rx data frame */
1314                 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1315                 /* enable to rx ps-poll */
1316                 rtw_write16(Adapter, REG_RXFLTMAP1, 0x0400);
1317
1318                 /* Beacon Control related register for first time */
1319                 rtw_write8(Adapter, REG_BCNDMATIM, 0x02); /*  2ms */
1320
1321                 rtw_write8(Adapter, REG_ATIMWND, 0x0a); /*  10ms */
1322                 rtw_write16(Adapter, REG_BCNTCFG, 0x00);
1323                 rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04);
1324                 rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/*  +32767 (~32ms) */
1325
1326                 /* reset TSF */
1327                 rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0));
1328
1329                 /* BIT3 - If set 0, hw will clr bcnq when tx becon ok/fail or port 0 */
1330                 rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM) | BIT(3) | BIT(4));
1331
1332                 /* enable BCN0 Function for if1 */
1333                 /* don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) */
1334                 rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | BIT(1)));
1335
1336                 /* dis BCN1 ATIM  WND if if2 is station */
1337                 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1) | BIT(0));
1338         }
1339 }
1340
1341 static void hw_var_set_macaddr(struct adapter *Adapter, u8 variable, u8 *val)
1342 {
1343         u8 idx = 0;
1344         u32 reg_macid;
1345
1346         reg_macid = REG_MACID;
1347
1348         for (idx = 0; idx < 6; idx++)
1349                 rtw_write8(Adapter, (reg_macid+idx), val[idx]);
1350 }
1351
1352 static void hw_var_set_bssid(struct adapter *Adapter, u8 variable, u8 *val)
1353 {
1354         u8 idx = 0;
1355         u32 reg_bssid;
1356
1357         reg_bssid = REG_BSSID;
1358
1359         for (idx = 0; idx < 6; idx++)
1360                 rtw_write8(Adapter, (reg_bssid+idx), val[idx]);
1361 }
1362
1363 static void hw_var_set_bcn_func(struct adapter *Adapter, u8 variable, u8 *val)
1364 {
1365         u32 bcn_ctrl_reg;
1366
1367         bcn_ctrl_reg = REG_BCN_CTRL;
1368
1369         if (*((u8 *)val))
1370                 rtw_write8(Adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
1371         else
1372                 rtw_write8(Adapter, bcn_ctrl_reg, rtw_read8(Adapter, bcn_ctrl_reg)&(~(EN_BCN_FUNCTION | EN_TXBCN_RPT)));
1373 }
1374
1375 static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val)
1376 {
1377         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
1378         struct dm_priv  *pdmpriv = &haldata->dmpriv;
1379         struct odm_dm_struct *podmpriv = &haldata->odmpriv;
1380
1381         switch (variable) {
1382         case HW_VAR_MEDIA_STATUS:
1383                 {
1384                         u8 val8;
1385
1386                         val8 = rtw_read8(Adapter, MSR)&0x0c;
1387                         val8 |= *((u8 *)val);
1388                         rtw_write8(Adapter, MSR, val8);
1389                 }
1390                 break;
1391         case HW_VAR_MEDIA_STATUS1:
1392                 {
1393                         u8 val8;
1394
1395                         val8 = rtw_read8(Adapter, MSR) & 0x03;
1396                         val8 |= *((u8 *)val) << 2;
1397                         rtw_write8(Adapter, MSR, val8);
1398                 }
1399                 break;
1400         case HW_VAR_SET_OPMODE:
1401                 hw_var_set_opmode(Adapter, variable, val);
1402                 break;
1403         case HW_VAR_MAC_ADDR:
1404                 hw_var_set_macaddr(Adapter, variable, val);
1405                 break;
1406         case HW_VAR_BSSID:
1407                 hw_var_set_bssid(Adapter, variable, val);
1408                 break;
1409         case HW_VAR_BASIC_RATE:
1410                 {
1411                         u16 BrateCfg = 0;
1412                         u8 RateIndex = 0;
1413
1414                         /*  2007.01.16, by Emily */
1415                         /*  Select RRSR (in Legacy-OFDM and CCK) */
1416                         /*  For 8190, we select only 24M, 12M, 6M, 11M, 5.5M, 2M, and 1M from the Basic rate. */
1417                         /*  We do not use other rates. */
1418                         HalSetBrateCfg(Adapter, val, &BrateCfg);
1419                         DBG_88E("HW_VAR_BASIC_RATE: BrateCfg(%#x)\n", BrateCfg);
1420
1421                         /* 2011.03.30 add by Luke Lee */
1422                         /* CCK 2M ACK should be disabled for some BCM and Atheros AP IOT */
1423                         /* because CCK 2M has poor TXEVM */
1424                         /* CCK 5.5M & 11M ACK should be enabled for better performance */
1425
1426                         BrateCfg = (BrateCfg | 0xd) & 0x15d;
1427                         haldata->BasicRateSet = BrateCfg;
1428
1429                         BrateCfg |= 0x01; /*  default enable 1M ACK rate */
1430                         /*  Set RRSR rate table. */
1431                         rtw_write8(Adapter, REG_RRSR, BrateCfg & 0xff);
1432                         rtw_write8(Adapter, REG_RRSR+1, (BrateCfg >> 8) & 0xff);
1433                         rtw_write8(Adapter, REG_RRSR+2, rtw_read8(Adapter, REG_RRSR+2)&0xf0);
1434
1435                         /*  Set RTS initial rate */
1436                         while (BrateCfg > 0x1) {
1437                                 BrateCfg = (BrateCfg >> 1);
1438                                 RateIndex++;
1439                         }
1440                         /*  Ziv - Check */
1441                         rtw_write8(Adapter, REG_INIRTS_RATE_SEL, RateIndex);
1442                 }
1443                 break;
1444         case HW_VAR_TXPAUSE:
1445                 rtw_write8(Adapter, REG_TXPAUSE, *((u8 *)val));
1446                 break;
1447         case HW_VAR_BCN_FUNC:
1448                 hw_var_set_bcn_func(Adapter, variable, val);
1449                 break;
1450         case HW_VAR_CORRECT_TSF:
1451                 {
1452                         u64     tsf;
1453                         struct mlme_ext_priv    *pmlmeext = &Adapter->mlmeextpriv;
1454                         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
1455
1456                         tsf = pmlmeext->TSFValue - do_div(pmlmeext->TSFValue,
1457                                                           pmlmeinfo->bcn_interval * 1024) - 1024; /* us */
1458
1459                         if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
1460                                 StopTxBeacon(Adapter);
1461
1462                         /* disable related TSF function */
1463                         rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3)));
1464
1465                         rtw_write32(Adapter, REG_TSFTR, tsf);
1466                         rtw_write32(Adapter, REG_TSFTR+4, tsf>>32);
1467
1468                         /* enable related TSF function */
1469                         rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3));
1470
1471                         if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
1472                                 ResumeTxBeacon(Adapter);
1473                 }
1474                 break;
1475         case HW_VAR_CHECK_BSSID:
1476                 if (*((u8 *)val)) {
1477                         rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
1478                 } else {
1479                         u32 val32;
1480
1481                         val32 = rtw_read32(Adapter, REG_RCR);
1482
1483                         val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1484
1485                         rtw_write32(Adapter, REG_RCR, val32);
1486                 }
1487                 break;
1488         case HW_VAR_MLME_DISCONNECT:
1489                 /* Set RCR to not to receive data frame when NO LINK state */
1490                 /* reject all data frames */
1491                 rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
1492
1493                 /* reset TSF */
1494                 rtw_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
1495
1496                 /* disable update TSF */
1497                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
1498                 break;
1499         case HW_VAR_MLME_SITESURVEY:
1500                 if (*((u8 *)val)) { /* under sitesurvey */
1501                         /* config RCR to receive different BSSID & not to receive data frame */
1502                         u32 v = rtw_read32(Adapter, REG_RCR);
1503                         v &= ~(RCR_CBSSID_BCN);
1504                         rtw_write32(Adapter, REG_RCR, v);
1505                         /* reject all data frame */
1506                         rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
1507
1508                         /* disable update TSF */
1509                         rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
1510                 } else { /* sitesurvey done */
1511                         struct mlme_ext_priv    *pmlmeext = &Adapter->mlmeextpriv;
1512                         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
1513
1514                         if ((is_client_associated_to_ap(Adapter)) ||
1515                             ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)) {
1516                                 /* enable to rx data frame */
1517                                 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1518
1519                                 /* enable update TSF */
1520                                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
1521                         } else if ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) {
1522                                 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1523                                 /* enable update TSF */
1524                                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
1525                         }
1526                         if ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) {
1527                                 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
1528                         } else {
1529                                 if (Adapter->in_cta_test) {
1530                                         u32 v = rtw_read32(Adapter, REG_RCR);
1531                                         v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);/*  RCR_ADF */
1532                                         rtw_write32(Adapter, REG_RCR, v);
1533                                 } else {
1534                                         rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
1535                                 }
1536                         }
1537                 }
1538                 break;
1539         case HW_VAR_MLME_JOIN:
1540                 {
1541                         u8 RetryLimit = 0x30;
1542                         u8 type = *((u8 *)val);
1543                         struct mlme_priv        *pmlmepriv = &Adapter->mlmepriv;
1544
1545                         if (type == 0) { /*  prepare to join */
1546                                 /* enable to rx data frame.Accept all data frame */
1547                                 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1548
1549                                 if (Adapter->in_cta_test) {
1550                                         u32 v = rtw_read32(Adapter, REG_RCR);
1551                                         v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);/*  RCR_ADF */
1552                                         rtw_write32(Adapter, REG_RCR, v);
1553                                 } else {
1554                                         rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
1555                                 }
1556
1557                                 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE))
1558                                         RetryLimit = (haldata->CustomerID == RT_CID_CCX) ? 7 : 48;
1559                                 else /*  Ad-hoc Mode */
1560                                         RetryLimit = 0x7;
1561                         } else if (type == 1) {
1562                                 /* joinbss_event call back when join res < 0 */
1563                                 rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
1564                         } else if (type == 2) {
1565                                 /* sta add event call back */
1566                                 /* enable update TSF */
1567                                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
1568
1569                                 if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
1570                                         RetryLimit = 0x7;
1571                         }
1572                         rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
1573                 }
1574                 break;
1575         case HW_VAR_BEACON_INTERVAL:
1576                 rtw_write16(Adapter, REG_BCN_INTERVAL, *((u16 *)val));
1577                 break;
1578         case HW_VAR_SLOT_TIME:
1579                 {
1580                         u8 u1bAIFS, aSifsTime;
1581                         struct mlme_ext_priv    *pmlmeext = &Adapter->mlmeextpriv;
1582                         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
1583
1584                         rtw_write8(Adapter, REG_SLOT, val[0]);
1585
1586                         if (pmlmeinfo->WMM_enable == 0) {
1587                                 if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
1588                                         aSifsTime = 10;
1589                                 else
1590                                         aSifsTime = 16;
1591
1592                                 u1bAIFS = aSifsTime + (2 * pmlmeinfo->slotTime);
1593
1594                                 /*  <Roger_EXP> Temporary removed, 2008.06.20. */
1595                                 rtw_write8(Adapter, REG_EDCA_VO_PARAM, u1bAIFS);
1596                                 rtw_write8(Adapter, REG_EDCA_VI_PARAM, u1bAIFS);
1597                                 rtw_write8(Adapter, REG_EDCA_BE_PARAM, u1bAIFS);
1598                                 rtw_write8(Adapter, REG_EDCA_BK_PARAM, u1bAIFS);
1599                         }
1600                 }
1601                 break;
1602         case HW_VAR_RESP_SIFS:
1603                 /* RESP_SIFS for CCK */
1604                 rtw_write8(Adapter, REG_R2T_SIFS, val[0]); /*  SIFS_T2T_CCK (0x08) */
1605                 rtw_write8(Adapter, REG_R2T_SIFS+1, val[1]); /* SIFS_R2T_CCK(0x08) */
1606                 /* RESP_SIFS for OFDM */
1607                 rtw_write8(Adapter, REG_T2T_SIFS, val[2]); /* SIFS_T2T_OFDM (0x0a) */
1608                 rtw_write8(Adapter, REG_T2T_SIFS+1, val[3]); /* SIFS_R2T_OFDM(0x0a) */
1609                 break;
1610         case HW_VAR_ACK_PREAMBLE:
1611                 {
1612                         u8 regTmp;
1613                         u8 bShortPreamble = *((bool *)val);
1614                         /*  Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) */
1615                         regTmp = (haldata->nCur40MhzPrimeSC)<<5;
1616                         if (bShortPreamble)
1617                                 regTmp |= 0x80;
1618
1619                         rtw_write8(Adapter, REG_RRSR+2, regTmp);
1620                 }
1621                 break;
1622         case HW_VAR_SEC_CFG:
1623                 rtw_write8(Adapter, REG_SECCFG, *((u8 *)val));
1624                 break;
1625         case HW_VAR_DM_FLAG:
1626                 podmpriv->SupportAbility = *((u8 *)val);
1627                 break;
1628         case HW_VAR_DM_FUNC_OP:
1629                 if (val[0])
1630                         podmpriv->BK_SupportAbility = podmpriv->SupportAbility;
1631                 else
1632                         podmpriv->SupportAbility = podmpriv->BK_SupportAbility;
1633                 break;
1634         case HW_VAR_DM_FUNC_SET:
1635                 if (*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE) {
1636                         pdmpriv->DMFlag = pdmpriv->InitDMFlag;
1637                         podmpriv->SupportAbility =      pdmpriv->InitODMFlag;
1638                 } else {
1639                         podmpriv->SupportAbility |= *((u32 *)val);
1640                 }
1641                 break;
1642         case HW_VAR_DM_FUNC_CLR:
1643                 podmpriv->SupportAbility &= *((u32 *)val);
1644                 break;
1645         case HW_VAR_CAM_EMPTY_ENTRY:
1646                 {
1647                         u8 ucIndex = *((u8 *)val);
1648                         u8 i;
1649                         u32 ulCommand = 0;
1650                         u32 ulContent = 0;
1651                         u32 ulEncAlgo = CAM_AES;
1652
1653                         for (i = 0; i < CAM_CONTENT_COUNT; i++) {
1654                                 /*  filled id in CAM config 2 byte */
1655                                 if (i == 0)
1656                                         ulContent |= (ucIndex & 0x03) | ((u16)(ulEncAlgo)<<2);
1657                                 else
1658                                         ulContent = 0;
1659                                 /*  polling bit, and No Write enable, and address */
1660                                 ulCommand = CAM_CONTENT_COUNT*ucIndex+i;
1661                                 ulCommand = ulCommand | CAM_POLLINIG|CAM_WRITE;
1662                                 /*  write content 0 is equall to mark invalid */
1663                                 rtw_write32(Adapter, WCAMI, ulContent);  /* delay_ms(40); */
1664                                 rtw_write32(Adapter, RWCAM, ulCommand);  /* delay_ms(40); */
1665                         }
1666                 }
1667                 break;
1668         case HW_VAR_CAM_INVALID_ALL:
1669                 rtw_write32(Adapter, RWCAM, BIT(31)|BIT(30));
1670                 break;
1671         case HW_VAR_CAM_WRITE:
1672                 {
1673                         u32 cmd;
1674                         u32 *cam_val = (u32 *)val;
1675                         rtw_write32(Adapter, WCAMI, cam_val[0]);
1676
1677                         cmd = CAM_POLLINIG | CAM_WRITE | cam_val[1];
1678                         rtw_write32(Adapter, RWCAM, cmd);
1679                 }
1680                 break;
1681         case HW_VAR_AC_PARAM_VO:
1682                 rtw_write32(Adapter, REG_EDCA_VO_PARAM, ((u32 *)(val))[0]);
1683                 break;
1684         case HW_VAR_AC_PARAM_VI:
1685                 rtw_write32(Adapter, REG_EDCA_VI_PARAM, ((u32 *)(val))[0]);
1686                 break;
1687         case HW_VAR_AC_PARAM_BE:
1688                 haldata->AcParam_BE = ((u32 *)(val))[0];
1689                 rtw_write32(Adapter, REG_EDCA_BE_PARAM, ((u32 *)(val))[0]);
1690                 break;
1691         case HW_VAR_AC_PARAM_BK:
1692                 rtw_write32(Adapter, REG_EDCA_BK_PARAM, ((u32 *)(val))[0]);
1693                 break;
1694         case HW_VAR_ACM_CTRL:
1695                 {
1696                         u8 acm_ctrl = *((u8 *)val);
1697                         u8 AcmCtrl = rtw_read8(Adapter, REG_ACMHWCTRL);
1698
1699                         if (acm_ctrl > 1)
1700                                 AcmCtrl = AcmCtrl | 0x1;
1701
1702                         if (acm_ctrl & BIT(3))
1703                                 AcmCtrl |= AcmHw_VoqEn;
1704                         else
1705                                 AcmCtrl &= (~AcmHw_VoqEn);
1706
1707                         if (acm_ctrl & BIT(2))
1708                                 AcmCtrl |= AcmHw_ViqEn;
1709                         else
1710                                 AcmCtrl &= (~AcmHw_ViqEn);
1711
1712                         if (acm_ctrl & BIT(1))
1713                                 AcmCtrl |= AcmHw_BeqEn;
1714                         else
1715                                 AcmCtrl &= (~AcmHw_BeqEn);
1716
1717                         DBG_88E("[HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
1718                         rtw_write8(Adapter, REG_ACMHWCTRL, AcmCtrl);
1719                 }
1720                 break;
1721         case HW_VAR_AMPDU_MIN_SPACE:
1722                 {
1723                         u8 MinSpacingToSet;
1724                         u8 SecMinSpace;
1725
1726                         MinSpacingToSet = *((u8 *)val);
1727                         if (MinSpacingToSet <= 7) {
1728                                 switch (Adapter->securitypriv.dot11PrivacyAlgrthm) {
1729                                 case _NO_PRIVACY_:
1730                                 case _AES_:
1731                                         SecMinSpace = 0;
1732                                         break;
1733                                 case _WEP40_:
1734                                 case _WEP104_:
1735                                 case _TKIP_:
1736                                 case _TKIP_WTMIC_:
1737                                         SecMinSpace = 6;
1738                                         break;
1739                                 default:
1740                                         SecMinSpace = 7;
1741                                         break;
1742                                 }
1743                                 if (MinSpacingToSet < SecMinSpace)
1744                                         MinSpacingToSet = SecMinSpace;
1745                                 rtw_write8(Adapter, REG_AMPDU_MIN_SPACE, (rtw_read8(Adapter, REG_AMPDU_MIN_SPACE) & 0xf8) | MinSpacingToSet);
1746                         }
1747                 }
1748                 break;
1749         case HW_VAR_AMPDU_FACTOR:
1750                 {
1751                         u8 RegToSet_Normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1752                         u8 FactorToSet;
1753                         u8 *pRegToSet;
1754                         u8 index = 0;
1755
1756                         pRegToSet = RegToSet_Normal; /*  0xb972a841; */
1757                         FactorToSet = *((u8 *)val);
1758                         if (FactorToSet <= 3) {
1759                                 FactorToSet = (1<<(FactorToSet + 2));
1760                                 if (FactorToSet > 0xf)
1761                                         FactorToSet = 0xf;
1762
1763                                 for (index = 0; index < 4; index++) {
1764                                         if ((pRegToSet[index] & 0xf0) > (FactorToSet<<4))
1765                                                 pRegToSet[index] = (pRegToSet[index] & 0x0f) | (FactorToSet<<4);
1766
1767                                         if ((pRegToSet[index] & 0x0f) > FactorToSet)
1768                                                 pRegToSet[index] = (pRegToSet[index] & 0xf0) | (FactorToSet);
1769
1770                                         rtw_write8(Adapter, (REG_AGGLEN_LMT+index), pRegToSet[index]);
1771                                 }
1772                         }
1773                 }
1774                 break;
1775         case HW_VAR_RXDMA_AGG_PG_TH:
1776                 {
1777                         u8 threshold = *((u8 *)val);
1778                         if (threshold == 0)
1779                                 threshold = haldata->UsbRxAggPageCount;
1780                         rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, threshold);
1781                 }
1782                 break;
1783         case HW_VAR_SET_RPWM:
1784                 break;
1785         case HW_VAR_H2C_FW_PWRMODE:
1786                 {
1787                         u8 psmode = (*(u8 *)val);
1788
1789                         /*  Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power */
1790                         /*  saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang. */
1791                         if ((psmode != PS_MODE_ACTIVE) && (!IS_92C_SERIAL(haldata->VersionID)))
1792                                 ODM_RF_Saving(podmpriv, true);
1793                         rtl8188e_set_FwPwrMode_cmd(Adapter, psmode);
1794                 }
1795                 break;
1796         case HW_VAR_H2C_FW_JOINBSSRPT:
1797                 {
1798                         u8 mstatus = (*(u8 *)val);
1799                         rtl8188e_set_FwJoinBssReport_cmd(Adapter, mstatus);
1800                 }
1801                 break;
1802 #ifdef CONFIG_88EU_P2P
1803         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
1804                 {
1805                         u8 p2p_ps_state = (*(u8 *)val);
1806                         rtl8188e_set_p2p_ps_offload_cmd(Adapter, p2p_ps_state);
1807                 }
1808                 break;
1809 #endif
1810         case HW_VAR_INITIAL_GAIN:
1811                 {
1812                         struct rtw_dig *pDigTable = &podmpriv->DM_DigTable;
1813                         u32 rx_gain = ((u32 *)(val))[0];
1814
1815                         if (rx_gain == 0xff) {/* restore rx gain */
1816                                 ODM_Write_DIG(podmpriv, pDigTable->BackupIGValue);
1817                         } else {
1818                                 pDigTable->BackupIGValue = pDigTable->CurIGValue;
1819                                 ODM_Write_DIG(podmpriv, rx_gain);
1820                         }
1821                 }
1822                 break;
1823         case HW_VAR_TRIGGER_GPIO_0:
1824                 rtl8192cu_trigger_gpio_0(Adapter);
1825                 break;
1826         case HW_VAR_RPT_TIMER_SETTING:
1827                 {
1828                         u16 min_rpt_time = (*(u16 *)val);
1829                         ODM_RA_Set_TxRPT_Time(podmpriv, min_rpt_time);
1830                 }
1831                 break;
1832         case HW_VAR_ANTENNA_DIVERSITY_SELECT:
1833                 {
1834                         u8 Optimum_antenna = (*(u8 *)val);
1835                         u8 Ant;
1836                         /* switch antenna to Optimum_antenna */
1837                         if (haldata->CurAntenna !=  Optimum_antenna) {
1838                                 Ant = (Optimum_antenna == 2) ? MAIN_ANT : AUX_ANT;
1839                                 ODM_UpdateRxIdleAnt_88E(&haldata->odmpriv, Ant);
1840
1841                                 haldata->CurAntenna = Optimum_antenna;
1842                         }
1843                 }
1844                 break;
1845         case HW_VAR_EFUSE_BYTES: /*  To set EFUE total used bytes, added by Roger, 2008.12.22. */
1846                 haldata->EfuseUsedBytes = *((u16 *)val);
1847                 break;
1848         case HW_VAR_FIFO_CLEARN_UP:
1849                 {
1850                         struct pwrctrl_priv *pwrpriv = &Adapter->pwrctrlpriv;
1851                         u8 trycnt = 100;
1852
1853                         /* pause tx */
1854                         rtw_write8(Adapter, REG_TXPAUSE, 0xff);
1855
1856                         /* keep sn */
1857                         Adapter->xmitpriv.nqos_ssn = rtw_read16(Adapter, REG_NQOS_SEQ);
1858
1859                         if (!pwrpriv->bkeepfwalive) {
1860                                 /* RX DMA stop */
1861                                 rtw_write32(Adapter, REG_RXPKT_NUM, (rtw_read32(Adapter, REG_RXPKT_NUM)|RW_RELEASE_EN));
1862                                 do {
1863                                         if (!(rtw_read32(Adapter, REG_RXPKT_NUM)&RXDMA_IDLE))
1864                                                 break;
1865                                 } while (trycnt--);
1866                                 if (trycnt == 0)
1867                                         DBG_88E("Stop RX DMA failed......\n");
1868
1869                                 /* RQPN Load 0 */
1870                                 rtw_write16(Adapter, REG_RQPN_NPQ, 0x0);
1871                                 rtw_write32(Adapter, REG_RQPN, 0x80000000);
1872                                 rtw_mdelay_os(10);
1873                         }
1874                 }
1875                 break;
1876         case HW_VAR_CHECK_TXBUF:
1877                 break;
1878         case HW_VAR_APFM_ON_MAC:
1879                 haldata->bMacPwrCtrlOn = *val;
1880                 DBG_88E("%s: bMacPwrCtrlOn=%d\n", __func__, haldata->bMacPwrCtrlOn);
1881                 break;
1882         case HW_VAR_TX_RPT_MAX_MACID:
1883                 {
1884                         u8 maxMacid = *val;
1885                         DBG_88E("### MacID(%d),Set Max Tx RPT MID(%d)\n", maxMacid, maxMacid+1);
1886                         rtw_write8(Adapter, REG_TX_RPT_CTRL+1, maxMacid+1);
1887                 }
1888                 break;
1889         case HW_VAR_H2C_MEDIA_STATUS_RPT:
1890                 rtl8188e_set_FwMediaStatus_cmd(Adapter, (*(__le16 *)val));
1891                 break;
1892         case HW_VAR_BCN_VALID:
1893                 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw */
1894                 rtw_write8(Adapter, REG_TDECTRL+2, rtw_read8(Adapter, REG_TDECTRL+2) | BIT0);
1895                 break;
1896         default:
1897                 break;
1898         }
1899
1900 }
1901
1902 static void GetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val)
1903 {
1904         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
1905         struct odm_dm_struct *podmpriv = &haldata->odmpriv;
1906
1907         switch (variable) {
1908         case HW_VAR_BASIC_RATE:
1909                 *((u16 *)(val)) = haldata->BasicRateSet;
1910                 __attribute__((__fallthrough__));
1911         case HW_VAR_TXPAUSE:
1912                 val[0] = rtw_read8(Adapter, REG_TXPAUSE);
1913                 break;
1914         case HW_VAR_BCN_VALID:
1915                 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2 */
1916                 val[0] = (BIT0 & rtw_read8(Adapter, REG_TDECTRL+2)) ? true : false;
1917                 break;
1918         case HW_VAR_DM_FLAG:
1919                 val[0] = podmpriv->SupportAbility;
1920                 break;
1921         case HW_VAR_RF_TYPE:
1922                 val[0] = haldata->rf_type;
1923                 break;
1924         case HW_VAR_FWLPS_RF_ON:
1925                 {
1926                         /* When we halt NIC, we should check if FW LPS is leave. */
1927                         if (Adapter->pwrctrlpriv.rf_pwrstate == rf_off) {
1928                                 /*  If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave, */
1929                                 /*  because Fw is unload. */
1930                                 val[0] = true;
1931                         } else {
1932                                 u32 valRCR;
1933                                 valRCR = rtw_read32(Adapter, REG_RCR);
1934                                 valRCR &= 0x00070000;
1935                                 if (valRCR)
1936                                         val[0] = false;
1937                                 else
1938                                         val[0] = true;
1939                         }
1940                 }
1941                 break;
1942         case HW_VAR_CURRENT_ANTENNA:
1943                 val[0] = haldata->CurAntenna;
1944                 break;
1945         case HW_VAR_EFUSE_BYTES: /*  To get EFUE total used bytes, added by Roger, 2008.12.22. */
1946                 *((u16 *)(val)) = haldata->EfuseUsedBytes;
1947                 break;
1948         case HW_VAR_APFM_ON_MAC:
1949                 *val = haldata->bMacPwrCtrlOn;
1950                 break;
1951         case HW_VAR_CHK_HI_QUEUE_EMPTY:
1952                 *val = ((rtw_read32(Adapter, REG_HGQ_INFORMATION)&0x0000ff00) == 0) ? true : false;
1953                 break;
1954         default:
1955                 break;
1956         }
1957
1958 }
1959
1960 /*  */
1961 /*      Description: */
1962 /*              Query setting of specified variable. */
1963 /*  */
1964 static u8
1965 GetHalDefVar8188EUsb(
1966                 struct adapter *Adapter,
1967                 enum hal_def_variable eVariable,
1968                 void *pValue
1969         )
1970 {
1971         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
1972         u8 bResult = _SUCCESS;
1973
1974         switch (eVariable) {
1975         case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
1976                 {
1977                         struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
1978                         struct sta_priv *pstapriv = &Adapter->stapriv;
1979                         struct sta_info *psta;
1980                         psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
1981                         if (psta)
1982                                 *((int *)pValue) = psta->rssi_stat.UndecoratedSmoothedPWDB;
1983                 }
1984                 break;
1985         case HAL_DEF_IS_SUPPORT_ANT_DIV:
1986                 *((u8 *)pValue) = (haldata->AntDivCfg == 0) ? false : true;
1987                 break;
1988         case HAL_DEF_CURRENT_ANTENNA:
1989                 *((u8 *)pValue) = haldata->CurAntenna;
1990                 break;
1991         case HAL_DEF_DRVINFO_SZ:
1992                 *((u32 *)pValue) = DRVINFO_SZ;
1993                 break;
1994         case HAL_DEF_MAX_RECVBUF_SZ:
1995                 *((u32 *)pValue) = MAX_RECVBUF_SZ;
1996                 break;
1997         case HAL_DEF_RX_PACKET_OFFSET:
1998                 *((u32 *)pValue) = RXDESC_SIZE + DRVINFO_SZ;
1999                 break;
2000         case HAL_DEF_DBG_DM_FUNC:
2001                 *((u32 *)pValue) = haldata->odmpriv.SupportAbility;
2002                 break;
2003         case HAL_DEF_RA_DECISION_RATE:
2004                 {
2005                         u8 MacID = *((u8 *)pValue);
2006                         *((u8 *)pValue) = ODM_RA_GetDecisionRate_8188E(&(haldata->odmpriv), MacID);
2007                 }
2008                 break;
2009         case HAL_DEF_RA_SGI:
2010                 {
2011                         u8 MacID = *((u8 *)pValue);
2012                         *((u8 *)pValue) = ODM_RA_GetShortGI_8188E(&(haldata->odmpriv), MacID);
2013                 }
2014                 break;
2015         case HAL_DEF_PT_PWR_STATUS:
2016                 {
2017                         u8 MacID = *((u8 *)pValue);
2018                         *((u8 *)pValue) = ODM_RA_GetHwPwrStatus_8188E(&(haldata->odmpriv), MacID);
2019                 }
2020                 break;
2021         case HW_VAR_MAX_RX_AMPDU_FACTOR:
2022                 *((u32 *)pValue) = MAX_AMPDU_FACTOR_64K;
2023                 break;
2024         case HW_DEF_RA_INFO_DUMP:
2025                 {
2026                         u8 entry_id = *((u8 *)pValue);
2027                         if (check_fwstate(&Adapter->mlmepriv, _FW_LINKED)) {
2028                                 DBG_88E("============ RA status check ===================\n");
2029                                 DBG_88E("Mac_id:%d , RateID = %d, RAUseRate = 0x%08x, RateSGI = %d, DecisionRate = 0x%02x ,PTStage = %d\n",
2030                                         entry_id,
2031                                         haldata->odmpriv.RAInfo[entry_id].RateID,
2032                                         haldata->odmpriv.RAInfo[entry_id].RAUseRate,
2033                                         haldata->odmpriv.RAInfo[entry_id].RateSGI,
2034                                         haldata->odmpriv.RAInfo[entry_id].DecisionRate,
2035                                         haldata->odmpriv.RAInfo[entry_id].PTStage);
2036                         }
2037                 }
2038                 break;
2039         case HAL_DEF_DBG_DUMP_RXPKT:
2040                 *((u8 *)pValue) = haldata->bDumpRxPkt;
2041                 break;
2042         case HAL_DEF_DBG_DUMP_TXPKT:
2043                 *((u8 *)pValue) = haldata->bDumpTxPkt;
2044                 break;
2045         default:
2046                 bResult = _FAIL;
2047                 break;
2048         }
2049
2050         return bResult;
2051 }
2052
2053 /*  */
2054 /*      Description: */
2055 /*              Change default setting of specified variable. */
2056 /*  */
2057 static u8 SetHalDefVar8188EUsb(struct adapter *Adapter, enum hal_def_variable eVariable, void *pValue)
2058 {
2059         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
2060         u8 bResult = _SUCCESS;
2061
2062         switch (eVariable) {
2063         case HAL_DEF_DBG_DM_FUNC:
2064                 {
2065                         u8 dm_func = *((u8 *)pValue);
2066                         struct odm_dm_struct *podmpriv = &haldata->odmpriv;
2067
2068                         if (dm_func == 0) { /* disable all dynamic func */
2069                                 podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE;
2070                                 DBG_88E("==> Disable all dynamic function...\n");
2071                         } else if (dm_func == 1) {/* disable DIG */
2072                                 podmpriv->SupportAbility  &= (~DYNAMIC_BB_DIG);
2073                                 DBG_88E("==> Disable DIG...\n");
2074                         } else if (dm_func == 2) {/* disable High power */
2075                                 podmpriv->SupportAbility  &= (~DYNAMIC_BB_DYNAMIC_TXPWR);
2076                         } else if (dm_func == 3) {/* disable tx power tracking */
2077                                 podmpriv->SupportAbility  &= (~DYNAMIC_RF_CALIBRATION);
2078                                 DBG_88E("==> Disable tx power tracking...\n");
2079                         } else if (dm_func == 5) {/* disable antenna diversity */
2080                                 podmpriv->SupportAbility  &= (~DYNAMIC_BB_ANT_DIV);
2081                         } else if (dm_func == 6) {/* turn on all dynamic func */
2082                                 if (!(podmpriv->SupportAbility  & DYNAMIC_BB_DIG)) {
2083                                         struct rtw_dig *pDigTable = &podmpriv->DM_DigTable;
2084                                         pDigTable->CurIGValue = rtw_read8(Adapter, 0xc50);
2085                                 }
2086                                 podmpriv->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE;
2087                                 DBG_88E("==> Turn on all dynamic function...\n");
2088                         }
2089                 }
2090                 break;
2091         case HAL_DEF_DBG_DUMP_RXPKT:
2092                 haldata->bDumpRxPkt = *((u8 *)pValue);
2093                 break;
2094         case HAL_DEF_DBG_DUMP_TXPKT:
2095                 haldata->bDumpTxPkt = *((u8 *)pValue);
2096                 break;
2097         default:
2098                 bResult = _FAIL;
2099                 break;
2100         }
2101
2102         return bResult;
2103 }
2104
2105 static void UpdateHalRAMask8188EUsb(struct adapter *adapt, u32 mac_id, u8 rssi_level)
2106 {
2107         u8 init_rate = 0;
2108         u8 networkType, raid;
2109         u32 mask, rate_bitmap;
2110         u8 shortGIrate = false;
2111         int     supportRateNum = 0;
2112         struct sta_info *psta;
2113         struct hal_data_8188e   *haldata = GET_HAL_DATA(adapt);
2114         struct mlme_ext_priv    *pmlmeext = &adapt->mlmeextpriv;
2115         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
2116         struct wlan_bssid_ex    *cur_network = &(pmlmeinfo->network);
2117
2118         if (mac_id >= NUM_STA) /* CAM_SIZE */
2119                 return;
2120         psta = pmlmeinfo->FW_sta_info[mac_id].psta;
2121         if (!psta)
2122                 return;
2123         switch (mac_id) {
2124         case 0:/*  for infra mode */
2125                 supportRateNum = rtw_get_rateset_len(cur_network->SupportedRates);
2126                 networkType = judge_network_type(adapt, cur_network->SupportedRates, supportRateNum) & 0xf;
2127                 raid = networktype_to_raid(networkType);
2128                 mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
2129                 mask |= (pmlmeinfo->HT_enable) ? update_MSC_rate(&(pmlmeinfo->HT_caps)) : 0;
2130                 if (support_short_GI(adapt, &(pmlmeinfo->HT_caps)))
2131                         shortGIrate = true;
2132                 break;
2133         case 1:/* for broadcast/multicast */
2134                 supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
2135                 if (pmlmeext->cur_wireless_mode & WIRELESS_11B)
2136                         networkType = WIRELESS_11B;
2137                 else
2138                         networkType = WIRELESS_11G;
2139                 raid = networktype_to_raid(networkType);
2140                 mask = update_basic_rate(cur_network->SupportedRates, supportRateNum);
2141                 break;
2142         default: /* for each sta in IBSS */
2143                 supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
2144                 networkType = judge_network_type(adapt, pmlmeinfo->FW_sta_info[mac_id].SupportedRates, supportRateNum) & 0xf;
2145                 raid = networktype_to_raid(networkType);
2146                 mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
2147
2148                 /* todo: support HT in IBSS */
2149                 break;
2150         }
2151
2152         rate_bitmap = 0x0fffffff;
2153         rate_bitmap = ODM_Get_Rate_Bitmap(&haldata->odmpriv, mac_id, mask, rssi_level);
2154         DBG_88E("%s => mac_id:%d, networkType:0x%02x, mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n",
2155                 __func__, mac_id, networkType, mask, rssi_level, rate_bitmap);
2156
2157         mask &= rate_bitmap;
2158
2159         init_rate = get_highest_rate_idx(mask)&0x3f;
2160
2161         if (haldata->fw_ractrl) {
2162                 u8 arg;
2163
2164                 arg = mac_id & 0x1f;/* MACID */
2165                 arg |= BIT(7);
2166                 if (shortGIrate)
2167                         arg |= BIT(5);
2168                 mask |= ((raid << 28) & 0xf0000000);
2169                 DBG_88E("update raid entry, mask=0x%x, arg=0x%x\n", mask, arg);
2170                 psta->ra_mask = mask;
2171                 mask |= ((raid << 28) & 0xf0000000);
2172
2173                 /* to do ,for 8188E-SMIC */
2174                 rtl8188e_set_raid_cmd(adapt, mask);
2175         } else {
2176                 ODM_RA_UpdateRateInfo_8188E(&(haldata->odmpriv),
2177                                 mac_id,
2178                                 raid,
2179                                 mask,
2180                                 shortGIrate
2181                                 );
2182         }
2183         /* set ra_id */
2184         psta->raid = raid;
2185         psta->init_rate = init_rate;
2186 }
2187
2188 static void SetBeaconRelatedRegisters8188EUsb(struct adapter *adapt)
2189 {
2190         u32 value32;
2191         struct mlme_ext_priv    *pmlmeext = &(adapt->mlmeextpriv);
2192         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
2193         u32 bcn_ctrl_reg                        = REG_BCN_CTRL;
2194         /* reset TSF, enable update TSF, correcting TSF On Beacon */
2195
2196         /* BCN interval */
2197         rtw_write16(adapt, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
2198         rtw_write8(adapt, REG_ATIMWND, 0x02);/*  2ms */
2199
2200         _InitBeaconParameters(adapt);
2201
2202         rtw_write8(adapt, REG_SLOT, 0x09);
2203
2204         value32 = rtw_read32(adapt, REG_TCR);
2205         value32 &= ~TSFRST;
2206         rtw_write32(adapt,  REG_TCR, value32);
2207
2208         value32 |= TSFRST;
2209         rtw_write32(adapt, REG_TCR, value32);
2210
2211         /*  NOTE: Fix test chip's bug (about contention windows's randomness) */
2212         rtw_write8(adapt,  REG_RXTSF_OFFSET_CCK, 0x50);
2213         rtw_write8(adapt, REG_RXTSF_OFFSET_OFDM, 0x50);
2214
2215         _BeaconFunctionEnable(adapt, true, true);
2216
2217         ResumeTxBeacon(adapt);
2218
2219         rtw_write8(adapt, bcn_ctrl_reg, rtw_read8(adapt, bcn_ctrl_reg)|BIT(1));
2220 }
2221
2222 static void rtl8188eu_init_default_value(struct adapter *adapt)
2223 {
2224         struct hal_data_8188e *haldata;
2225         struct pwrctrl_priv *pwrctrlpriv;
2226         u8 i;
2227
2228         haldata = GET_HAL_DATA(adapt);
2229         pwrctrlpriv = &adapt->pwrctrlpriv;
2230
2231         /* init default value */
2232         haldata->fw_ractrl = false;
2233         if (!pwrctrlpriv->bkeepfwalive)
2234                 haldata->LastHMEBoxNum = 0;
2235
2236         /* init dm default value */
2237         haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = false;
2238         haldata->odmpriv.RFCalibrateInfo.TM_Trigger = 0;/* for IQK */
2239         haldata->pwrGroupCnt = 0;
2240         haldata->PGMaxGroup = 13;
2241         haldata->odmpriv.RFCalibrateInfo.ThermalValue_HP_index = 0;
2242         for (i = 0; i < HP_THERMAL_NUM; i++)
2243                 haldata->odmpriv.RFCalibrateInfo.ThermalValue_HP[i] = 0;
2244 }
2245
2246 static u8 rtl8188eu_ps_func(struct adapter *Adapter, enum hal_intf_ps_func efunc_id, u8 *val)
2247 {
2248         u8 bResult = true;
2249         return bResult;
2250 }
2251
2252 void rtl8188eu_set_hal_ops(struct adapter *adapt)
2253 {
2254         struct hal_ops  *halfunc = &adapt->HalFunc;
2255
2256         adapt->HalData = rtw_zmalloc(sizeof(struct hal_data_8188e));
2257         if (!adapt->HalData)
2258                 DBG_88E("cant not alloc memory for HAL DATA\n");
2259         adapt->hal_data_sz = sizeof(struct hal_data_8188e);
2260
2261         halfunc->hal_power_on = rtl8188eu_InitPowerOn;
2262         halfunc->hal_init = &rtl8188eu_hal_init;
2263         halfunc->hal_deinit = &rtl8188eu_hal_deinit;
2264
2265         halfunc->inirp_init = &rtl8188eu_inirp_init;
2266         halfunc->inirp_deinit = &rtl8188eu_inirp_deinit;
2267
2268         halfunc->init_xmit_priv = &rtl8188eu_init_xmit_priv;
2269         halfunc->free_xmit_priv = &rtl8188eu_free_xmit_priv;
2270
2271         halfunc->init_recv_priv = &rtl8188eu_init_recv_priv;
2272         halfunc->free_recv_priv = &rtl8188eu_free_recv_priv;
2273         halfunc->InitSwLeds = &rtl8188eu_InitSwLeds;
2274         halfunc->DeInitSwLeds = &rtl8188eu_DeInitSwLeds;
2275
2276         halfunc->init_default_value = &rtl8188eu_init_default_value;
2277         halfunc->intf_chip_configure = &rtl8188eu_interface_configure;
2278         halfunc->read_adapter_info = &ReadAdapterInfo8188EU;
2279
2280         halfunc->SetHwRegHandler = &SetHwReg8188EU;
2281         halfunc->GetHwRegHandler = &GetHwReg8188EU;
2282         halfunc->GetHalDefVarHandler = &GetHalDefVar8188EUsb;
2283         halfunc->SetHalDefVarHandler = &SetHalDefVar8188EUsb;
2284
2285         halfunc->UpdateRAMaskHandler = &UpdateHalRAMask8188EUsb;
2286         halfunc->SetBeaconRelatedRegistersHandler = &SetBeaconRelatedRegisters8188EUsb;
2287
2288         halfunc->hal_xmit = &rtl8188eu_hal_xmit;
2289         halfunc->mgnt_xmit = &rtl8188eu_mgnt_xmit;
2290
2291         halfunc->interface_ps_func = &rtl8188eu_ps_func;
2292
2293         rtl8188e_set_hal_ops(halfunc);
2294
2295 }