drivers/staging/r8188eu/hal/usb_halinit.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */
   3
   4 #define _HCI_HAL_INIT_C_
   5
   6 #include <osdep_service.h>
   7 #include <drv_types.h>
   8 #include <rtw_efuse.h>
   9
  10 #include <rtl8188e_hal.h>
  11 #include <rtl8188e_led.h>
  12 #include <rtw_iol.h>
  13 #include <usb_ops.h>
  14 #include <usb_hal.h>
  15 #include <usb_osintf.h>
  16
  17 #define         HAL_MAC_ENABLE  1
  18 #define         HAL_BB_ENABLE           1
  19 #define         HAL_RF_ENABLE           1
  20
  21 static void _ConfigNormalChipOutEP_8188E(struct adapter *adapt, u8 NumOutPipe)
  22 {
  23         struct hal_data_8188e   *haldata        = GET_HAL_DATA(adapt);
  24
  25         switch (NumOutPipe) {
  26         case    3:
  27                 haldata->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
  28                 haldata->OutEpNumber = 3;
  29                 break;
  30         case    2:
  31                 haldata->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
  32                 haldata->OutEpNumber = 2;
  33                 break;
  34         case    1:
  35                 haldata->OutEpQueueSel = TX_SELE_HQ;
  36                 haldata->OutEpNumber = 1;
  37                 break;
  38         default:
  39                 break;
  40         }
  41         DBG_88E("%s OutEpQueueSel(0x%02x), OutEpNumber(%d)\n", __func__, haldata->OutEpQueueSel, haldata->OutEpNumber);
  42 }
  43
  44 static bool HalUsbSetQueuePipeMapping8188EUsb(struct adapter *adapt, u8 NumInPipe, u8 NumOutPipe)
  45 {
  46         struct hal_data_8188e   *haldata        = GET_HAL_DATA(adapt);
  47         bool                    result          = false;
  48
  49         _ConfigNormalChipOutEP_8188E(adapt, NumOutPipe);
  50
  51         /*  Normal chip with one IN and one OUT doesn't have interrupt IN EP. */
  52         if (1 == haldata->OutEpNumber) {
  53                 if (1 != NumInPipe)
  54                         return result;
  55         }
  56
  57         /*  All config other than above support one Bulk IN and one Interrupt IN. */
  58
  59         result = Hal_MappingOutPipe(adapt, NumOutPipe);
  60
  61         return result;
  62 }
  63
  64 static void rtl8188eu_interface_configure(struct adapter *adapt)
  65 {
  66         struct hal_data_8188e   *haldata        = GET_HAL_DATA(adapt);
  67         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(adapt);
  68
  69         if (pdvobjpriv->ishighspeed)
  70                 haldata->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;/* 512 bytes */
  71         else
  72                 haldata->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;/* 64 bytes */
  73
  74         haldata->interfaceIndex = pdvobjpriv->InterfaceNumber;
  75
  76         haldata->UsbTxAggMode           = 1;
  77         haldata->UsbTxAggDescNum        = 0x6;  /*  only 4 bits */
  78
  79         haldata->UsbRxAggMode           = USB_RX_AGG_DMA;/*  USB_RX_AGG_DMA; */
  80         haldata->UsbRxAggBlockCount     = 8; /* unit : 512b */
  81         haldata->UsbRxAggBlockTimeout   = 0x6;
  82         haldata->UsbRxAggPageCount      = 48; /* uint :128 b 0x0A;      10 = MAX_RX_DMA_BUFFER_SIZE/2/haldata->UsbBulkOutSize */
  83         haldata->UsbRxAggPageTimeout    = 0x4; /* 6, absolute time = 34ms/(2^6) */
  84
  85         HalUsbSetQueuePipeMapping8188EUsb(adapt,
  86                                 pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes);
  87 }
  88
  89 static u32 rtl8188eu_InitPowerOn(struct adapter *adapt)
  90 {
  91         u16 value16;
  92         /*  HW Power on sequence */
  93         struct hal_data_8188e   *haldata        = GET_HAL_DATA(adapt);
  94         if (haldata->bMacPwrCtrlOn)
  95                 return _SUCCESS;
  96
  97         if (!HalPwrSeqCmdParsing(adapt, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_PWR_ON_FLOW)) {
  98                 DBG_88E(KERN_ERR "%s: run power on flow fail\n", __func__);
  99                 return _FAIL;
 100         }
 101
 102         /*  Enable MAC DMA/WMAC/SCHEDULE/SEC block */
 103         /*  Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */
 104         rtw_write16(adapt, REG_CR, 0x00);  /* suggseted by zhouzhou, by page, 20111230 */
 105
 106                 /*  Enable MAC DMA/WMAC/SCHEDULE/SEC block */
 107         value16 = rtw_read16(adapt, REG_CR);
 108         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
 109                                 | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
 110         /*  for SDIO - Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */
 111
 112         rtw_write16(adapt, REG_CR, value16);
 113         haldata->bMacPwrCtrlOn = true;
 114
 115         return _SUCCESS;
 116 }
 117
 118 /*  Shall USB interface init this? */
 119 static void _InitInterrupt(struct adapter *Adapter)
 120 {
 121         u32 imr, imr_ex;
 122         u8  usb_opt;
 123         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
 124
 125         /* HISR write one to clear */
 126         rtw_write32(Adapter, REG_HISR_88E, 0xFFFFFFFF);
 127         /*  HIMR - */
 128         imr = IMR_PSTIMEOUT_88E | IMR_TBDER_88E | IMR_CPWM_88E | IMR_CPWM2_88E;
 129         rtw_write32(Adapter, REG_HIMR_88E, imr);
 130         haldata->IntrMask[0] = imr;
 131
 132         imr_ex = IMR_TXERR_88E | IMR_RXERR_88E | IMR_TXFOVW_88E | IMR_RXFOVW_88E;
 133         rtw_write32(Adapter, REG_HIMRE_88E, imr_ex);
 134         haldata->IntrMask[1] = imr_ex;
 135
 136         /*  REG_USB_SPECIAL_OPTION - BIT(4) */
 137         /*  0; Use interrupt endpoint to upload interrupt pkt */
 138         /*  1; Use bulk endpoint to upload interrupt pkt, */
 139         usb_opt = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
 140
 141         if (!adapter_to_dvobj(Adapter)->ishighspeed)
 142                 usb_opt = usb_opt & (~INT_BULK_SEL);
 143         else
 144                 usb_opt = usb_opt | (INT_BULK_SEL);
 145
 146         rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, usb_opt);
 147 }
 148
 149 static void _InitQueueReservedPage(struct adapter *Adapter)
 150 {
 151         struct hal_data_8188e           *haldata = GET_HAL_DATA(Adapter);
 152         struct registry_priv    *pregistrypriv = &Adapter->registrypriv;
 153         u32 numHQ       = 0;
 154         u32 numLQ       = 0;
 155         u32 numNQ       = 0;
 156         u32 numPubQ;
 157         u32 value32;
 158         u8 value8;
 159         bool bWiFiConfig = pregistrypriv->wifi_spec;
 160
 161         if (bWiFiConfig) {
 162                 if (haldata->OutEpQueueSel & TX_SELE_HQ)
 163                         numHQ =  0x29;
 164
 165                 if (haldata->OutEpQueueSel & TX_SELE_LQ)
 166                         numLQ = 0x1C;
 167
 168                 /*  NOTE: This step shall be proceed before writting REG_RQPN. */
 169                 if (haldata->OutEpQueueSel & TX_SELE_NQ)
 170                         numNQ = 0x1C;
 171                 value8 = (u8)_NPQ(numNQ);
 172                 rtw_write8(Adapter, REG_RQPN_NPQ, value8);
 173
 174                 numPubQ = 0xA8 - numHQ - numLQ - numNQ;
 175
 176                 /*  TX DMA */
 177                 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 178                 rtw_write32(Adapter, REG_RQPN, value32);
 179         } else {
 180                 rtw_write16(Adapter, REG_RQPN_NPQ, 0x0000);/* Just follow MP Team,??? Georgia 03/28 */
 181                 rtw_write16(Adapter, REG_RQPN_NPQ, 0x0d);
 182                 rtw_write32(Adapter, REG_RQPN, 0x808E000d);/* reserve 7 page for LPS */
 183         }
 184 }
 185
 186 static void _InitTxBufferBoundary(struct adapter *Adapter, u8 txpktbuf_bndy)
 187 {
 188         rtw_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 189         rtw_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 190         rtw_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
 191         rtw_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
 192         rtw_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
 193 }
 194
 195 static void _InitPageBoundary(struct adapter *Adapter)
 196 {
 197         /*  RX Page Boundary */
 198         /*  */
 199         u16 rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E-1;
 200
 201         rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
 202 }
 203
 204 static void _InitNormalChipRegPriority(struct adapter *Adapter, u16 beQ,
 205                                        u16 bkQ, u16 viQ, u16 voQ, u16 mgtQ,
 206                                        u16 hiQ)
 207 {
 208         u16 value16     = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
 209
 210         value16 |= _TXDMA_BEQ_MAP(beQ)  | _TXDMA_BKQ_MAP(bkQ) |
 211                    _TXDMA_VIQ_MAP(viQ)  | _TXDMA_VOQ_MAP(voQ) |
 212                    _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
 213
 214         rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
 215 }
 216
 217 static void _InitNormalChipOneOutEpPriority(struct adapter *Adapter)
 218 {
 219         struct hal_data_8188e   *haldata        = GET_HAL_DATA(Adapter);
 220
 221         u16 value = 0;
 222         switch (haldata->OutEpQueueSel) {
 223         case TX_SELE_HQ:
 224                 value = QUEUE_HIGH;
 225                 break;
 226         case TX_SELE_LQ:
 227                 value = QUEUE_LOW;
 228                 break;
 229         case TX_SELE_NQ:
 230                 value = QUEUE_NORMAL;
 231                 break;
 232         default:
 233                 break;
 234         }
 235         _InitNormalChipRegPriority(Adapter, value, value, value, value,
 236                                    value, value);
 237 }
 238
 239 static void _InitNormalChipTwoOutEpPriority(struct adapter *Adapter)
 240 {
 241         struct hal_data_8188e   *haldata        = GET_HAL_DATA(Adapter);
 242         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 243         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 244         u16 valueHi = 0;
 245         u16 valueLow = 0;
 246
 247         switch (haldata->OutEpQueueSel) {
 248         case (TX_SELE_HQ | TX_SELE_LQ):
 249                 valueHi = QUEUE_HIGH;
 250                 valueLow = QUEUE_LOW;
 251                 break;
 252         case (TX_SELE_NQ | TX_SELE_LQ):
 253                 valueHi = QUEUE_NORMAL;
 254                 valueLow = QUEUE_LOW;
 255                 break;
 256         case (TX_SELE_HQ | TX_SELE_NQ):
 257                 valueHi = QUEUE_HIGH;
 258                 valueLow = QUEUE_NORMAL;
 259                 break;
 260         default:
 261                 break;
 262         }
 263
 264         if (!pregistrypriv->wifi_spec) {
 265                 beQ     = valueLow;
 266                 bkQ     = valueLow;
 267                 viQ     = valueHi;
 268                 voQ     = valueHi;
 269                 mgtQ    = valueHi;
 270                 hiQ     = valueHi;
 271         } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
 272                 beQ     = valueLow;
 273                 bkQ     = valueHi;
 274                 viQ     = valueHi;
 275                 voQ     = valueLow;
 276                 mgtQ    = valueHi;
 277                 hiQ     = valueHi;
 278         }
 279         _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 280 }
 281
 282 static void _InitNormalChipThreeOutEpPriority(struct adapter *Adapter)
 283 {
 284         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 285         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 286
 287         if (!pregistrypriv->wifi_spec) {/*  typical setting */
 288                 beQ     = QUEUE_LOW;
 289                 bkQ     = QUEUE_LOW;
 290                 viQ     = QUEUE_NORMAL;
 291                 voQ     = QUEUE_HIGH;
 292                 mgtQ    = QUEUE_HIGH;
 293                 hiQ     = QUEUE_HIGH;
 294         } else {/*  for WMM */
 295                 beQ     = QUEUE_LOW;
 296                 bkQ     = QUEUE_NORMAL;
 297                 viQ     = QUEUE_NORMAL;
 298                 voQ     = QUEUE_HIGH;
 299                 mgtQ    = QUEUE_HIGH;
 300                 hiQ     = QUEUE_HIGH;
 301         }
 302         _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 303 }
 304
 305 static void _InitQueuePriority(struct adapter *Adapter)
 306 {
 307         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
 308
 309         switch (haldata->OutEpNumber) {
 310         case 1:
 311                 _InitNormalChipOneOutEpPriority(Adapter);
 312                 break;
 313         case 2:
 314                 _InitNormalChipTwoOutEpPriority(Adapter);
 315                 break;
 316         case 3:
 317                 _InitNormalChipThreeOutEpPriority(Adapter);
 318                 break;
 319         default:
 320                 break;
 321         }
 322 }
 323
 324 static void _InitNetworkType(struct adapter *Adapter)
 325 {
 326         u32 value32;
 327
 328         value32 = rtw_read32(Adapter, REG_CR);
 329         /*  TODO: use the other function to set network type */
 330         value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
 331
 332         rtw_write32(Adapter, REG_CR, value32);
 333 }
 334
 335 static void _InitTransferPageSize(struct adapter *Adapter)
 336 {
 337         /*  Tx page size is always 128. */
 338
 339         u8 value8;
 340         value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
 341         rtw_write8(Adapter, REG_PBP, value8);
 342 }
 343
 344 static void _InitDriverInfoSize(struct adapter *Adapter, u8 drvInfoSize)
 345 {
 346         rtw_write8(Adapter, REG_RX_DRVINFO_SZ, drvInfoSize);
 347 }
 348
 349 static void _InitWMACSetting(struct adapter *Adapter)
 350 {
 351         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
 352
 353         haldata->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AB |
 354                                   RCR_CBSSID_DATA | RCR_CBSSID_BCN |
 355                                   RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
 356                                   RCR_APP_MIC | RCR_APP_PHYSTS;
 357
 358         /*  some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile() */
 359         rtw_write32(Adapter, REG_RCR, haldata->ReceiveConfig);
 360
 361         /*  Accept all multicast address */
 362         rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF);
 363         rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
 364 }
 365
 366 static void _InitAdaptiveCtrl(struct adapter *Adapter)
 367 {
 368         u16 value16;
 369         u32 value32;
 370
 371         /*  Response Rate Set */
 372         value32 = rtw_read32(Adapter, REG_RRSR);
 373         value32 &= ~RATE_BITMAP_ALL;
 374         value32 |= RATE_RRSR_CCK_ONLY_1M;
 375         rtw_write32(Adapter, REG_RRSR, value32);
 376
 377         /*  CF-END Threshold */
 378
 379         /*  SIFS (used in NAV) */
 380         value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
 381         rtw_write16(Adapter, REG_SPEC_SIFS, value16);
 382
 383         /*  Retry Limit */
 384         value16 = _LRL(0x30) | _SRL(0x30);
 385         rtw_write16(Adapter, REG_RL, value16);
 386 }
 387
 388 static void _InitEDCA(struct adapter *Adapter)
 389 {
 390         /*  Set Spec SIFS (used in NAV) */
 391         rtw_write16(Adapter, REG_SPEC_SIFS, 0x100a);
 392         rtw_write16(Adapter, REG_MAC_SPEC_SIFS, 0x100a);
 393
 394         /*  Set SIFS for CCK */
 395         rtw_write16(Adapter, REG_SIFS_CTX, 0x100a);
 396
 397         /*  Set SIFS for OFDM */
 398         rtw_write16(Adapter, REG_SIFS_TRX, 0x100a);
 399
 400         /*  TXOP */
 401         rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
 402         rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
 403         rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
 404         rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
 405 }
 406
 407 static void _InitBeaconMaxError(struct adapter *Adapter, bool           InfraMode)
 408 {
 409 }
 410
 411 static void _InitHWLed(struct adapter *Adapter)
 412 {
 413         struct led_priv *pledpriv = &(Adapter->ledpriv);
 414
 415         if (pledpriv->LedStrategy != HW_LED)
 416                 return;
 417
 418 /*  HW led control */
 419 /*  to do .... */
 420 /* must consider cases of antenna diversity/ commbo card/solo card/mini card */
 421 }
 422
 423 static void _InitRDGSetting(struct adapter *Adapter)
 424 {
 425         rtw_write8(Adapter, REG_RD_CTRL, 0xFF);
 426         rtw_write16(Adapter, REG_RD_NAV_NXT, 0x200);
 427         rtw_write8(Adapter, REG_RD_RESP_PKT_TH, 0x05);
 428 }
 429
 430 static void _InitRxSetting(struct adapter *Adapter)
 431 {
 432         rtw_write32(Adapter, REG_MACID, 0x87654321);
 433         rtw_write32(Adapter, 0x0700, 0x87654321);
 434 }
 435
 436 static void _InitRetryFunction(struct adapter *Adapter)
 437 {
 438         u8 value8;
 439
 440         value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL);
 441         value8 |= EN_AMPDU_RTY_NEW;
 442         rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
 443
 444         /*  Set ACK timeout */
 445         rtw_write8(Adapter, REG_ACKTO, 0x40);
 446 }
 447
 448 /*-----------------------------------------------------------------------------
 449  * Function:    usb_AggSettingTxUpdate()
 450  *
 451  * Overview:    Separate TX/RX parameters update independent for TP detection and
 452  *                      dynamic TX/RX aggreagtion parameters update.
 453  *
 454  * Input:                       struct adapter *
 455  *
 456  * Output/Return:       NONE
 457  *
 458  * Revised History:
 459  *      When            Who             Remark
 460  *      12/10/2010      MHC             Separate to smaller function.
 461  *
 462  *---------------------------------------------------------------------------*/
 463 static void usb_AggSettingTxUpdate(struct adapter *Adapter)
 464 {
 465         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
 466         u32 value32;
 467
 468         if (Adapter->registrypriv.wifi_spec)
 469                 haldata->UsbTxAggMode = false;
 470
 471         if (haldata->UsbTxAggMode) {
 472                 value32 = rtw_read32(Adapter, REG_TDECTRL);
 473                 value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
 474                 value32 |= ((haldata->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
 475
 476                 rtw_write32(Adapter, REG_TDECTRL, value32);
 477         }
 478 }       /*  usb_AggSettingTxUpdate */
 479
 480 /*-----------------------------------------------------------------------------
 481  * Function:    usb_AggSettingRxUpdate()
 482  *
 483  * Overview:    Separate TX/RX parameters update independent for TP detection and
 484  *                      dynamic TX/RX aggreagtion parameters update.
 485  *
 486  * Input:                       struct adapter *
 487  *
 488  * Output/Return:       NONE
 489  *
 490  * Revised History:
 491  *      When            Who             Remark
 492  *      12/10/2010      MHC             Separate to smaller function.
 493  *
 494  *---------------------------------------------------------------------------*/
 495 static void
 496 usb_AggSettingRxUpdate(
 497                 struct adapter *Adapter
 498         )
 499 {
 500         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
 501         u8 valueDMA;
 502         u8 valueUSB;
 503
 504         valueDMA = rtw_read8(Adapter, REG_TRXDMA_CTRL);
 505         valueUSB = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
 506
 507         switch (haldata->UsbRxAggMode) {
 508         case USB_RX_AGG_DMA:
 509                 valueDMA |= RXDMA_AGG_EN;
 510                 valueUSB &= ~USB_AGG_EN;
 511                 break;
 512         case USB_RX_AGG_USB:
 513                 valueDMA &= ~RXDMA_AGG_EN;
 514                 valueUSB |= USB_AGG_EN;
 515                 break;
 516         case USB_RX_AGG_MIX:
 517                 valueDMA |= RXDMA_AGG_EN;
 518                 valueUSB |= USB_AGG_EN;
 519                 break;
 520         case USB_RX_AGG_DISABLE:
 521         default:
 522                 valueDMA &= ~RXDMA_AGG_EN;
 523                 valueUSB &= ~USB_AGG_EN;
 524                 break;
 525         }
 526
 527         rtw_write8(Adapter, REG_TRXDMA_CTRL, valueDMA);
 528         rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, valueUSB);
 529
 530         switch (haldata->UsbRxAggMode) {
 531         case USB_RX_AGG_DMA:
 532                 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, haldata->UsbRxAggPageCount);
 533                 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, haldata->UsbRxAggPageTimeout);
 534                 break;
 535         case USB_RX_AGG_USB:
 536                 rtw_write8(Adapter, REG_USB_AGG_TH, haldata->UsbRxAggBlockCount);
 537                 rtw_write8(Adapter, REG_USB_AGG_TO, haldata->UsbRxAggBlockTimeout);
 538                 break;
 539         case USB_RX_AGG_MIX:
 540                 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, haldata->UsbRxAggPageCount);
 541                 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, (haldata->UsbRxAggPageTimeout & 0x1F));/* 0x280[12:8] */
 542                 rtw_write8(Adapter, REG_USB_AGG_TH, haldata->UsbRxAggBlockCount);
 543                 rtw_write8(Adapter, REG_USB_AGG_TO, haldata->UsbRxAggBlockTimeout);
 544                 break;
 545         case USB_RX_AGG_DISABLE:
 546         default:
 547                 /*  TODO: */
 548                 break;
 549         }
 550
 551         switch (PBP_128) {
 552         case PBP_128:
 553                 haldata->HwRxPageSize = 128;
 554                 break;
 555         case PBP_64:
 556                 haldata->HwRxPageSize = 64;
 557                 break;
 558         case PBP_256:
 559                 haldata->HwRxPageSize = 256;
 560                 break;
 561         case PBP_512:
 562                 haldata->HwRxPageSize = 512;
 563                 break;
 564         case PBP_1024:
 565                 haldata->HwRxPageSize = 1024;
 566                 break;
 567         default:
 568                 break;
 569         }
 570 }       /*  usb_AggSettingRxUpdate */
 571
 572 static void InitUsbAggregationSetting(struct adapter *Adapter)
 573 {
 574         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
 575
 576         /*  Tx aggregation setting */
 577         usb_AggSettingTxUpdate(Adapter);
 578
 579         /*  Rx aggregation setting */
 580         usb_AggSettingRxUpdate(Adapter);
 581
 582         /*  201/12/10 MH Add for USB agg mode dynamic switch. */
 583         haldata->UsbRxHighSpeedMode = false;
 584 }
 585
 586 static void _InitOperationMode(struct adapter *Adapter)
 587 {
 588 }
 589
 590 static void _InitBeaconParameters(struct adapter *Adapter)
 591 {
 592         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
 593
 594         rtw_write16(Adapter, REG_BCN_CTRL, 0x1010);
 595
 596         /*  TODO: Remove these magic number */
 597         rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0x6404);/*  ms */
 598         rtw_write8(Adapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);/*  5ms */
 599         rtw_write8(Adapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME); /*  2ms */
 600
 601         /*  Suggested by designer timchen. Change beacon AIFS to the largest number */
 602         /*  beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 */
 603         rtw_write16(Adapter, REG_BCNTCFG, 0x660F);
 604
 605         haldata->RegBcnCtrlVal = rtw_read8(Adapter, REG_BCN_CTRL);
 606         haldata->RegTxPause = rtw_read8(Adapter, REG_TXPAUSE);
 607         haldata->RegFwHwTxQCtrl = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL+2);
 608         haldata->RegReg542 = rtw_read8(Adapter, REG_TBTT_PROHIBIT+2);
 609         haldata->RegCR_1 = rtw_read8(Adapter, REG_CR+1);
 610 }
 611
 612 static void _BeaconFunctionEnable(struct adapter *Adapter,
 613                                   bool Enable, bool Linked)
 614 {
 615         rtw_write8(Adapter, REG_BCN_CTRL, (BIT4 | BIT3 | BIT1));
 616
 617         rtw_write8(Adapter, REG_RD_CTRL+1, 0x6F);
 618 }
 619
 620 /*  Set CCK and OFDM Block "ON" */
 621 static void _BBTurnOnBlock(struct adapter *Adapter)
 622 {
 623         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
 624         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
 625 }
 626
 627 enum {
 628         Antenna_Lfet = 1,
 629         Antenna_Right = 2,
 630 };
 631
 632 static void _InitAntenna_Selection(struct adapter *Adapter)
 633 {
 634         struct hal_data_8188e   *haldata        = GET_HAL_DATA(Adapter);
 635
 636         if (haldata->AntDivCfg == 0)
 637                 return;
 638         DBG_88E("==>  %s ....\n", __func__);
 639
 640         rtw_write32(Adapter, REG_LEDCFG0, rtw_read32(Adapter, REG_LEDCFG0)|BIT23);
 641         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
 642
 643         if (PHY_QueryBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A)
 644                 haldata->CurAntenna = Antenna_A;
 645         else
 646                 haldata->CurAntenna = Antenna_B;
 647         DBG_88E("%s,Cur_ant:(%x)%s\n", __func__, haldata->CurAntenna, (haldata->CurAntenna == Antenna_A) ? "Antenna_A" : "Antenna_B");
 648 }
 649
 650 /*-----------------------------------------------------------------------------
 651  * Function:    HwSuspendModeEnable92Cu()
 652  *
 653  * Overview:    HW suspend mode switch.
 654  *
 655  * Input:               NONE
 656  *
 657  * Output:      NONE
 658  *
 659  * Return:      NONE
 660  *
 661  * Revised History:
 662  *      When            Who             Remark
 663  *      08/23/2010      MHC             HW suspend mode switch test..
 664  *---------------------------------------------------------------------------*/
 665 enum rt_rf_power_state RfOnOffDetect(struct adapter *adapt)
 666 {
 667         u8 val8;
 668         enum rt_rf_power_state rfpowerstate = rf_off;
 669
 670         if (adapt->pwrctrlpriv.bHWPowerdown) {
 671                 val8 = rtw_read8(adapt, REG_HSISR);
 672                 DBG_88E("pwrdown, 0x5c(BIT7)=%02x\n", val8);
 673                 rfpowerstate = (val8 & BIT7) ? rf_off : rf_on;
 674         } else { /*  rf on/off */
 675                 rtw_write8(adapt, REG_MAC_PINMUX_CFG, rtw_read8(adapt, REG_MAC_PINMUX_CFG)&~(BIT3));
 676                 val8 = rtw_read8(adapt, REG_GPIO_IO_SEL);
 677                 DBG_88E("GPIO_IN=%02x\n", val8);
 678                 rfpowerstate = (val8 & BIT3) ? rf_on : rf_off;
 679         }
 680         return rfpowerstate;
 681 }       /*  HalDetectPwrDownMode */
 682
 683 static u32 rtl8188eu_hal_init(struct adapter *Adapter)
 684 {
 685         u8 value8 = 0;
 686         u16  value16;
 687         u8 txpktbuf_bndy;
 688         u32 status = _SUCCESS;
 689         struct hal_data_8188e           *haldata = GET_HAL_DATA(Adapter);
 690         struct pwrctrl_priv             *pwrctrlpriv = &Adapter->pwrctrlpriv;
 691         struct registry_priv    *pregistrypriv = &Adapter->registrypriv;
 692         u32 init_start_time = jiffies;
 693
 694         #define HAL_INIT_PROFILE_TAG(stage) do {} while (0)
 695
 696         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
 697
 698         if (Adapter->pwrctrlpriv.bkeepfwalive) {
 699                 _ps_open_RF(Adapter);
 700
 701                 if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) {
 702                         PHY_IQCalibrate_8188E(Adapter, true);
 703                 } else {
 704                         PHY_IQCalibrate_8188E(Adapter, false);
 705                         haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
 706                 }
 707
 708                 ODM_TXPowerTrackingCheck(&haldata->odmpriv);
 709                 PHY_LCCalibrate_8188E(Adapter);
 710
 711                 goto exit;
 712         }
 713
 714         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
 715         status = rtl8188eu_InitPowerOn(Adapter);
 716         if (status == _FAIL) {
 717                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n"));
 718                 goto exit;
 719         }
 720
 721         /*  Save target channel */
 722         haldata->CurrentChannel = 6;/* default set to 6 */
 723
 724         if (pwrctrlpriv->reg_rfoff) {
 725                 pwrctrlpriv->rf_pwrstate = rf_off;
 726         }
 727
 728         /*  2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
 729         /*  HW GPIO pin. Before PHY_RFConfig8192C. */
 730         /*  2010/08/26 MH If Efuse does not support sective suspend then disable the function. */
 731
 732         if (!pregistrypriv->wifi_spec) {
 733                 txpktbuf_bndy = TX_PAGE_BOUNDARY_88E;
 734         } else {
 735                 /*  for WMM */
 736                 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_88E;
 737         }
 738
 739         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
 740         _InitQueueReservedPage(Adapter);
 741         _InitQueuePriority(Adapter);
 742         _InitPageBoundary(Adapter);
 743         _InitTransferPageSize(Adapter);
 744
 745         _InitTxBufferBoundary(Adapter, 0);
 746
 747         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
 748         if (Adapter->registrypriv.mp_mode == 1) {
 749                 _InitRxSetting(Adapter);
 750                 Adapter->bFWReady = false;
 751                 haldata->fw_ractrl = false;
 752         } else {
 753                 status = rtl8188e_FirmwareDownload(Adapter);
 754
 755                 if (status != _SUCCESS) {
 756                         DBG_88E("%s: Download Firmware failed!!\n", __func__);
 757                         Adapter->bFWReady = false;
 758                         haldata->fw_ractrl = false;
 759                         return status;
 760                 } else {
 761                         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializeadapt8192CSdio(): Download Firmware Success!!\n"));
 762                         Adapter->bFWReady = true;
 763                         haldata->fw_ractrl = false;
 764                 }
 765         }
 766         rtl8188e_InitializeFirmwareVars(Adapter);
 767
 768         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
 769 #if (HAL_MAC_ENABLE == 1)
 770         status = PHY_MACConfig8188E(Adapter);
 771         if (status == _FAIL) {
 772                 DBG_88E(" ### Failed to init MAC ......\n ");
 773                 goto exit;
 774         }
 775 #endif
 776
 777         /*  */
 778         /* d. Initialize BB related configurations. */
 779         /*  */
 780         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
 781 #if (HAL_BB_ENABLE == 1)
 782         status = PHY_BBConfig8188E(Adapter);
 783         if (status == _FAIL) {
 784                 DBG_88E(" ### Failed to init BB ......\n ");
 785                 goto exit;
 786         }
 787 #endif
 788
 789         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
 790 #if (HAL_RF_ENABLE == 1)
 791         status = PHY_RFConfig8188E(Adapter);
 792         if (status == _FAIL) {
 793                 DBG_88E(" ### Failed to init RF ......\n ");
 794                 goto exit;
 795         }
 796 #endif
 797
 798         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_EFUSE_PATCH);
 799         status = rtl8188e_iol_efuse_patch(Adapter);
 800         if (status == _FAIL) {
 801                 DBG_88E("%s  rtl8188e_iol_efuse_patch failed\n", __func__);
 802                 goto exit;
 803         }
 804
 805         _InitTxBufferBoundary(Adapter, txpktbuf_bndy);
 806
 807         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
 808         status =  InitLLTTable(Adapter, txpktbuf_bndy);
 809         if (status == _FAIL) {
 810                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n"));
 811                 goto exit;
 812         }
 813
 814         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
 815         /*  Get Rx PHY status in order to report RSSI and others. */
 816         _InitDriverInfoSize(Adapter, DRVINFO_SZ);
 817
 818         _InitInterrupt(Adapter);
 819         hal_init_macaddr(Adapter);/* set mac_address */
 820         _InitNetworkType(Adapter);/* set msr */
 821         _InitWMACSetting(Adapter);
 822         _InitAdaptiveCtrl(Adapter);
 823         _InitEDCA(Adapter);
 824         _InitRetryFunction(Adapter);
 825         InitUsbAggregationSetting(Adapter);
 826         _InitOperationMode(Adapter);/* todo */
 827         _InitBeaconParameters(Adapter);
 828         _InitBeaconMaxError(Adapter, true);
 829
 830         /*  */
 831         /*  Init CR MACTXEN, MACRXEN after setting RxFF boundary REG_TRXFF_BNDY to patch */
 832         /*  Hw bug which Hw initials RxFF boundary size to a value which is larger than the real Rx buffer size in 88E. */
 833         /*  */
 834         /*  Enable MACTXEN/MACRXEN block */
 835         value16 = rtw_read16(Adapter, REG_CR);
 836         value16 |= (MACTXEN | MACRXEN);
 837         rtw_write8(Adapter, REG_CR, value16);
 838
 839         if (haldata->bRDGEnable)
 840                 _InitRDGSetting(Adapter);
 841
 842         /* Enable TX Report */
 843         /* Enable Tx Report Timer */
 844         value8 = rtw_read8(Adapter, REG_TX_RPT_CTRL);
 845         rtw_write8(Adapter,  REG_TX_RPT_CTRL, (value8|BIT1|BIT0));
 846         /* Set MAX RPT MACID */
 847         rtw_write8(Adapter,  REG_TX_RPT_CTRL+1, 2);/* FOR sta mode ,0: bc/mc ,1:AP */
 848         /* Tx RPT Timer. Unit: 32us */
 849         rtw_write16(Adapter, REG_TX_RPT_TIME, 0xCdf0);
 850
 851         rtw_write8(Adapter, REG_EARLY_MODE_CONTROL, 0);
 852
 853         rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400);  /*  unit: 256us. 256ms */
 854         rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400);  /*  unit: 256us. 256ms */
 855
 856         _InitHWLed(Adapter);
 857
 858         /* Keep RfRegChnlVal for later use. */
 859         haldata->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (enum rf_radio_path)0, RF_CHNLBW, bRFRegOffsetMask);
 860         haldata->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (enum rf_radio_path)1, RF_CHNLBW, bRFRegOffsetMask);
 861
 862 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
 863         _BBTurnOnBlock(Adapter);
 864
 865 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
 866         invalidate_cam_all(Adapter);
 867
 868 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
 869         /*  2010/12/17 MH We need to set TX power according to EFUSE content at first. */
 870         PHY_SetTxPowerLevel8188E(Adapter, haldata->CurrentChannel);
 871
 872 /*  Move by Neo for USB SS to below setp */
 873 /* _RfPowerSave(Adapter); */
 874
 875         _InitAntenna_Selection(Adapter);
 876
 877         /*  */
 878         /*  Disable BAR, suggested by Scott */
 879         /*  2010.04.09 add by hpfan */
 880         /*  */
 881         rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
 882
 883         /*  HW SEQ CTRL */
 884         /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
 885         rtw_write8(Adapter, REG_HWSEQ_CTRL, 0xFF);
 886
 887         if (pregistrypriv->wifi_spec)
 888                 rtw_write16(Adapter, REG_FAST_EDCA_CTRL, 0);
 889
 890         /* Nav limit , suggest by scott */
 891         rtw_write8(Adapter, 0x652, 0x0);
 892
 893 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
 894         rtl8188e_InitHalDm(Adapter);
 895
 896         if (Adapter->registrypriv.mp_mode == 1) {
 897                 Adapter->mppriv.channel = haldata->CurrentChannel;
 898                 MPT_InitializeAdapter(Adapter, Adapter->mppriv.channel);
 899         } else {
 900                 /*  2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status */
 901                 /*  and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not */
 902                 /*  call initstruct adapter. May cause some problem?? */
 903                 /*  Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed */
 904                 /*  in MgntActSet_RF_State() after wake up, because the value of haldata->eRFPowerState */
 905                 /*  is the same as eRfOff, we should change it to eRfOn after we config RF parameters. */
 906                 /*  Added by tynli. 2010.03.30. */
 907                 pwrctrlpriv->rf_pwrstate = rf_on;
 908
 909                 /*  enable Tx report. */
 910                 rtw_write8(Adapter,  REG_FWHW_TXQ_CTRL+1, 0x0F);
 911
 912                 /*  Suggested by SD1 pisa. Added by tynli. 2011.10.21. */
 913                 rtw_write8(Adapter, REG_EARLY_MODE_CONTROL+3, 0x01);/* Pretx_en, for WEP/TKIP SEC */
 914
 915                 /* tynli_test_tx_report. */
 916                 rtw_write16(Adapter, REG_TX_RPT_TIME, 0x3DF0);
 917
 918                 /* enable tx DMA to drop the redundate data of packet */
 919                 rtw_write16(Adapter, REG_TXDMA_OFFSET_CHK, (rtw_read16(Adapter, REG_TXDMA_OFFSET_CHK) | DROP_DATA_EN));
 920
 921 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
 922                 /*  2010/08/26 MH Merge from 8192CE. */
 923                 if (pwrctrlpriv->rf_pwrstate == rf_on) {
 924                         if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) {
 925                                 PHY_IQCalibrate_8188E(Adapter, true);
 926                         } else {
 927                                 PHY_IQCalibrate_8188E(Adapter, false);
 928                                 haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
 929                         }
 930
 931 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
 932
 933                         ODM_TXPowerTrackingCheck(&haldata->odmpriv);
 934
 935 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
 936                         PHY_LCCalibrate_8188E(Adapter);
 937                 }
 938         }
 939
 940 /* HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS); */
 941 /*      _InitPABias(Adapter); */
 942         rtw_write8(Adapter, REG_USB_HRPWM, 0);
 943
 944         /* ack for xmit mgmt frames. */
 945         rtw_write32(Adapter, REG_FWHW_TXQ_CTRL, rtw_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12));
 946
 947 exit:
 948 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
 949
 950         DBG_88E("%s in %dms\n", __func__, rtw_get_passing_time_ms(init_start_time));
 951
 952         return status;
 953 }
 954
 955 void _ps_open_RF(struct adapter *adapt)
 956 {
 957         /* here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified */
 958         /* phy_SsPwrSwitch92CU(adapt, rf_on, 1); */
 959 }
 960
 961 static void _ps_close_RF(struct adapter *adapt)
 962 {
 963         /* here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified */
 964         /* phy_SsPwrSwitch92CU(adapt, rf_off, 1); */
 965 }
 966
 967 static void CardDisableRTL8188EU(struct adapter *Adapter)
 968 {
 969         u8 val8;
 970         struct hal_data_8188e   *haldata        = GET_HAL_DATA(Adapter);
 971
 972         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("CardDisableRTL8188EU\n"));
 973
 974         /* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */
 975         val8 = rtw_read8(Adapter, REG_TX_RPT_CTRL);
 976         rtw_write8(Adapter, REG_TX_RPT_CTRL, val8&(~BIT1));
 977
 978         /*  stop rx */
 979         rtw_write8(Adapter, REG_CR, 0x0);
 980
 981         /*  Run LPS WL RFOFF flow */
 982         HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_LPS_ENTER_FLOW);
 983
 984         /*  2. 0x1F[7:0] = 0            turn off RF */
 985
 986         val8 = rtw_read8(Adapter, REG_MCUFWDL);
 987         if ((val8 & RAM_DL_SEL) && Adapter->bFWReady) { /* 8051 RAM code */
 988                 /*  Reset MCU 0x2[10]=0. */
 989                 val8 = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
 990                 val8 &= ~BIT(2);        /*  0x2[10], FEN_CPUEN */
 991                 rtw_write8(Adapter, REG_SYS_FUNC_EN+1, val8);
 992         }
 993
 994         /*  reset MCU ready status */
 995         rtw_write8(Adapter, REG_MCUFWDL, 0);
 996
 997         /* YJ,add,111212 */
 998         /* Disable 32k */
 999         val8 = rtw_read8(Adapter, REG_32K_CTRL);
1000         rtw_write8(Adapter, REG_32K_CTRL, val8&(~BIT0));
1001
1002         /*  Card disable power action flow */
1003         HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_DISABLE_FLOW);
1004
1005         /*  Reset MCU IO Wrapper */
1006         val8 = rtw_read8(Adapter, REG_RSV_CTRL+1);
1007         rtw_write8(Adapter, REG_RSV_CTRL+1, (val8&(~BIT3)));
1008         val8 = rtw_read8(Adapter, REG_RSV_CTRL+1);
1009         rtw_write8(Adapter, REG_RSV_CTRL+1, val8|BIT3);
1010
1011         /* YJ,test add, 111207. For Power Consumption. */
1012         val8 = rtw_read8(Adapter, GPIO_IN);
1013         rtw_write8(Adapter, GPIO_OUT, val8);
1014         rtw_write8(Adapter, GPIO_IO_SEL, 0xFF);/* Reg0x46 */
1015
1016         val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL);
1017         rtw_write8(Adapter, REG_GPIO_IO_SEL, (val8<<4));
1018         val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL+1);
1019         rtw_write8(Adapter, REG_GPIO_IO_SEL+1, val8|0x0F);/* Reg0x43 */
1020         rtw_write32(Adapter, REG_BB_PAD_CTRL, 0x00080808);/* set LNA ,TRSW,EX_PA Pin to output mode */
1021         haldata->bMacPwrCtrlOn = false;
1022         Adapter->bFWReady = false;
1023 }
1024 static void rtl8192cu_hw_power_down(struct adapter *adapt)
1025 {
1026         /*  2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c. */
1027         /*  Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1. */
1028
1029         /*  Enable register area 0x0-0xc. */
1030         rtw_write8(adapt, REG_RSV_CTRL, 0x0);
1031         rtw_write16(adapt, REG_APS_FSMCO, 0x8812);
1032 }
1033
1034 static u32 rtl8188eu_hal_deinit(struct adapter *Adapter)
1035 {
1036
1037         DBG_88E("==> %s\n", __func__);
1038
1039         rtw_write32(Adapter, REG_HIMR_88E, IMR_DISABLED_88E);
1040         rtw_write32(Adapter, REG_HIMRE_88E, IMR_DISABLED_88E);
1041
1042         DBG_88E("bkeepfwalive(%x)\n", Adapter->pwrctrlpriv.bkeepfwalive);
1043         if (Adapter->pwrctrlpriv.bkeepfwalive) {
1044                 _ps_close_RF(Adapter);
1045                 if ((Adapter->pwrctrlpriv.bHWPwrPindetect) && (Adapter->pwrctrlpriv.bHWPowerdown))
1046                         rtl8192cu_hw_power_down(Adapter);
1047         } else {
1048                 if (Adapter->hw_init_completed) {
1049                         CardDisableRTL8188EU(Adapter);
1050
1051                         if ((Adapter->pwrctrlpriv.bHWPwrPindetect) && (Adapter->pwrctrlpriv.bHWPowerdown))
1052                                 rtl8192cu_hw_power_down(Adapter);
1053                 }
1054         }
1055         return _SUCCESS;
1056  }
1057
1058 static unsigned int rtl8188eu_inirp_init(struct adapter *Adapter)
1059 {
1060         u8 i;
1061         struct recv_buf *precvbuf;
1062         uint    status;
1063         struct intf_hdl *pintfhdl = &Adapter->iopriv.intf;
1064         struct recv_priv *precvpriv = &(Adapter->recvpriv);
1065         u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
1066
1067         _read_port = pintfhdl->io_ops._read_port;
1068
1069         status = _SUCCESS;
1070
1071         RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1072                  ("===> usb_inirp_init\n"));
1073
1074         precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR;
1075
1076         /* issue Rx irp to receive data */
1077         precvbuf = (struct recv_buf *)precvpriv->precv_buf;
1078         for (i = 0; i < NR_RECVBUFF; i++) {
1079                 if (_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == false) {
1080                         RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("usb_rx_init: usb_read_port error\n"));
1081                         status = _FAIL;
1082                         goto exit;
1083                 }
1084
1085                 precvbuf++;
1086                 precvpriv->free_recv_buf_queue_cnt--;
1087         }
1088
1089 exit:
1090
1091         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("<=== usb_inirp_init\n"));
1092
1093         return status;
1094 }
1095
1096 static unsigned int rtl8188eu_inirp_deinit(struct adapter *Adapter)
1097 {
1098         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("\n ===> usb_rx_deinit\n"));
1099
1100         rtw_read_port_cancel(Adapter);
1101
1102         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("\n <=== usb_rx_deinit\n"));
1103
1104         return _SUCCESS;
1105 }
1106
1107 /*  */
1108 /*  */
1109 /*      EEPROM/EFUSE Content Parsing */
1110 /*  */
1111 /*  */
1112 static void _ReadLEDSetting(struct adapter *Adapter, u8 *PROMContent, bool AutoloadFail)
1113 {
1114         struct led_priv *pledpriv = &(Adapter->ledpriv);
1115         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
1116
1117         pledpriv->bRegUseLed = true;
1118         pledpriv->LedStrategy = SW_LED_MODE1;
1119         haldata->bLedOpenDrain = true;/*  Support Open-drain arrangement for controlling the LED. */
1120 }
1121
1122 static void Hal_EfuseParsePIDVID_8188EU(struct adapter *adapt, u8 *hwinfo, bool AutoLoadFail)
1123 {
1124         struct hal_data_8188e   *haldata = GET_HAL_DATA(adapt);
1125
1126         if (!AutoLoadFail) {
1127                 /*  VID, PID */
1128                 haldata->EEPROMVID = EF2BYTE(*(__le16 *)&hwinfo[EEPROM_VID_88EU]);
1129                 haldata->EEPROMPID = EF2BYTE(*(__le16 *)&hwinfo[EEPROM_PID_88EU]);
1130
1131                 /*  Customer ID, 0x00 and 0xff are reserved for Realtek. */
1132                 haldata->EEPROMCustomerID = *(u8 *)&hwinfo[EEPROM_CUSTOMERID_88E];
1133                 haldata->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
1134         } else {
1135                 haldata->EEPROMVID                      = EEPROM_Default_VID;
1136                 haldata->EEPROMPID                      = EEPROM_Default_PID;
1137
1138                 /*  Customer ID, 0x00 and 0xff are reserved for Realtek. */
1139                 haldata->EEPROMCustomerID               = EEPROM_Default_CustomerID;
1140                 haldata->EEPROMSubCustomerID    = EEPROM_Default_SubCustomerID;
1141         }
1142
1143         DBG_88E("VID = 0x%04X, PID = 0x%04X\n", haldata->EEPROMVID, haldata->EEPROMPID);
1144         DBG_88E("Customer ID: 0x%02X, SubCustomer ID: 0x%02X\n", haldata->EEPROMCustomerID, haldata->EEPROMSubCustomerID);
1145 }
1146
1147 static void Hal_EfuseParseMACAddr_8188EU(struct adapter *adapt, u8 *hwinfo, bool AutoLoadFail)
1148 {
1149         u16 i;
1150         u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x88, 0x02};
1151         struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
1152
1153         if (AutoLoadFail) {
1154                 for (i = 0; i < 6; i++)
1155                         eeprom->mac_addr[i] = sMacAddr[i];
1156         } else {
1157                 /* Read Permanent MAC address */
1158                 memcpy(eeprom->mac_addr, &hwinfo[EEPROM_MAC_ADDR_88EU], ETH_ALEN);
1159         }
1160         RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
1161                  ("Hal_EfuseParseMACAddr_8188EU: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
1162                  eeprom->mac_addr[0], eeprom->mac_addr[1],
1163                  eeprom->mac_addr[2], eeprom->mac_addr[3],
1164                  eeprom->mac_addr[4], eeprom->mac_addr[5]));
1165 }
1166
1167 static void Hal_CustomizeByCustomerID_8188EU(struct adapter *adapt)
1168 {
1169 }
1170
1171 static void
1172 readAdapterInfo_8188EU(
1173                 struct adapter *adapt
1174         )
1175 {
1176         struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
1177
1178         /* parse the eeprom/efuse content */
1179         Hal_EfuseParseIDCode88E(adapt, eeprom->efuse_eeprom_data);
1180         Hal_EfuseParsePIDVID_8188EU(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1181         Hal_EfuseParseMACAddr_8188EU(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1182
1183         Hal_ReadPowerSavingMode88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1184         Hal_ReadTxPowerInfo88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1185         Hal_EfuseParseEEPROMVer88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1186         rtl8188e_EfuseParseChnlPlan(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1187         Hal_EfuseParseXtal_8188E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1188         Hal_EfuseParseCustomerID88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1189         Hal_ReadAntennaDiversity88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1190         Hal_EfuseParseBoardType88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1191         Hal_ReadThermalMeter_88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1192
1193         /*  */
1194         /*  The following part initialize some vars by PG info. */
1195         /*  */
1196         Hal_InitChannelPlan(adapt);
1197         Hal_CustomizeByCustomerID_8188EU(adapt);
1198
1199         _ReadLEDSetting(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1200 }
1201
1202 static void _ReadPROMContent(
1203         struct adapter *Adapter
1204         )
1205 {
1206         struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(Adapter);
1207         u8 eeValue;
1208
1209         /* check system boot selection */
1210         eeValue = rtw_read8(Adapter, REG_9346CR);
1211         eeprom->EepromOrEfuse           = (eeValue & BOOT_FROM_EEPROM) ? true : false;
1212         eeprom->bautoload_fail_flag     = (eeValue & EEPROM_EN) ? false : true;
1213
1214         DBG_88E("Boot from %s, Autoload %s !\n", (eeprom->EepromOrEfuse ? "EEPROM" : "EFUSE"),
1215                 (eeprom->bautoload_fail_flag ? "Fail" : "OK"));
1216
1217         Hal_InitPGData88E(Adapter);
1218         readAdapterInfo_8188EU(Adapter);
1219 }
1220
1221 static void _ReadRFType(struct adapter *Adapter)
1222 {
1223         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
1224
1225         haldata->rf_chip = RF_6052;
1226 }
1227
1228 static int _ReadAdapterInfo8188EU(struct adapter *Adapter)
1229 {
1230         u32 start = jiffies;
1231
1232         MSG_88E("====> %s\n", __func__);
1233
1234         _ReadRFType(Adapter);/* rf_chip -> _InitRFType() */
1235         _ReadPROMContent(Adapter);
1236
1237         MSG_88E("<==== %s in %d ms\n", __func__, rtw_get_passing_time_ms(start));
1238
1239         return _SUCCESS;
1240 }
1241
1242 static void ReadAdapterInfo8188EU(struct adapter *Adapter)
1243 {
1244         /*  Read EEPROM size before call any EEPROM function */
1245         Adapter->EepromAddressSize = GetEEPROMSize8188E(Adapter);
1246
1247         _ReadAdapterInfo8188EU(Adapter);
1248 }
1249
1250 #define GPIO_DEBUG_PORT_NUM 0
1251 static void rtl8192cu_trigger_gpio_0(struct adapter *adapt)
1252 {
1253 }
1254
1255 static void ResumeTxBeacon(struct adapter *adapt)
1256 {
1257         struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
1258
1259         /*  2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */
1260         /*  which should be read from register to a global variable. */
1261
1262         rtw_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) | BIT6);
1263         haldata->RegFwHwTxQCtrl |= BIT6;
1264         rtw_write8(adapt, REG_TBTT_PROHIBIT+1, 0xff);
1265         haldata->RegReg542 |= BIT0;
1266         rtw_write8(adapt, REG_TBTT_PROHIBIT+2, haldata->RegReg542);
1267 }
1268
1269 static void StopTxBeacon(struct adapter *adapt)
1270 {
1271         struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
1272
1273         /*  2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */
1274         /*  which should be read from register to a global variable. */
1275
1276         rtw_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) & (~BIT6));
1277         haldata->RegFwHwTxQCtrl &= (~BIT6);
1278         rtw_write8(adapt, REG_TBTT_PROHIBIT+1, 0x64);
1279         haldata->RegReg542 &= ~(BIT0);
1280         rtw_write8(adapt, REG_TBTT_PROHIBIT+2, haldata->RegReg542);
1281
1282          /* todo: CheckFwRsvdPageContent(Adapter);  2010.06.23. Added by tynli. */
1283 }
1284
1285 static void hw_var_set_opmode(struct adapter *Adapter, u8 variable, u8 *val)
1286 {
1287         u8 val8;
1288         u8 mode = *((u8 *)val);
1289
1290         /*  disable Port0 TSF update */
1291         rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
1292
1293         /*  set net_type */
1294         val8 = rtw_read8(Adapter, MSR)&0x0c;
1295         val8 |= mode;
1296         rtw_write8(Adapter, MSR, val8);
1297
1298         DBG_88E("%s()-%d mode = %d\n", __func__, __LINE__, mode);
1299
1300         if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
1301                 StopTxBeacon(Adapter);
1302
1303                 rtw_write8(Adapter, REG_BCN_CTRL, 0x19);/* disable atim wnd */
1304         } else if ((mode == _HW_STATE_ADHOC_)) {
1305                 ResumeTxBeacon(Adapter);
1306                 rtw_write8(Adapter, REG_BCN_CTRL, 0x1a);
1307         } else if (mode == _HW_STATE_AP_) {
1308                 ResumeTxBeacon(Adapter);
1309
1310                 rtw_write8(Adapter, REG_BCN_CTRL, 0x12);
1311
1312                 /* Set RCR */
1313                 rtw_write32(Adapter, REG_RCR, 0x7000208e);/* CBSSID_DATA must set to 0,reject ICV_ERR packet */
1314                 /* enable to rx data frame */
1315                 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1316                 /* enable to rx ps-poll */
1317                 rtw_write16(Adapter, REG_RXFLTMAP1, 0x0400);
1318
1319                 /* Beacon Control related register for first time */
1320                 rtw_write8(Adapter, REG_BCNDMATIM, 0x02); /*  2ms */
1321
1322                 rtw_write8(Adapter, REG_ATIMWND, 0x0a); /*  10ms */
1323                 rtw_write16(Adapter, REG_BCNTCFG, 0x00);
1324                 rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04);
1325                 rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/*  +32767 (~32ms) */
1326
1327                 /* reset TSF */
1328                 rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0));
1329
1330                 /* BIT3 - If set 0, hw will clr bcnq when tx becon ok/fail or port 0 */
1331                 rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM) | BIT(3) | BIT(4));
1332
1333                 /* enable BCN0 Function for if1 */
1334                 /* don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) */
1335                 rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | BIT(1)));
1336
1337                 /* dis BCN1 ATIM  WND if if2 is station */
1338                 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1) | BIT(0));
1339         }
1340 }
1341
1342 static void hw_var_set_macaddr(struct adapter *Adapter, u8 variable, u8 *val)
1343 {
1344         u8 idx = 0;
1345         u32 reg_macid;
1346
1347         reg_macid = REG_MACID;
1348
1349         for (idx = 0; idx < 6; idx++)
1350                 rtw_write8(Adapter, (reg_macid+idx), val[idx]);
1351 }
1352
1353 static void hw_var_set_bssid(struct adapter *Adapter, u8 variable, u8 *val)
1354 {
1355         u8 idx = 0;
1356         u32 reg_bssid;
1357
1358         reg_bssid = REG_BSSID;
1359
1360         for (idx = 0; idx < 6; idx++)
1361                 rtw_write8(Adapter, (reg_bssid+idx), val[idx]);
1362 }
1363
1364 static void hw_var_set_bcn_func(struct adapter *Adapter, u8 variable, u8 *val)
1365 {
1366         u32 bcn_ctrl_reg;
1367
1368         bcn_ctrl_reg = REG_BCN_CTRL;
1369
1370         if (*((u8 *)val))
1371                 rtw_write8(Adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
1372         else
1373                 rtw_write8(Adapter, bcn_ctrl_reg, rtw_read8(Adapter, bcn_ctrl_reg)&(~(EN_BCN_FUNCTION | EN_TXBCN_RPT)));
1374 }
1375
1376 static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val)
1377 {
1378         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
1379         struct dm_priv  *pdmpriv = &haldata->dmpriv;
1380         struct odm_dm_struct *podmpriv = &haldata->odmpriv;
1381
1382         switch (variable) {
1383         case HW_VAR_MEDIA_STATUS:
1384                 {
1385                         u8 val8;
1386
1387                         val8 = rtw_read8(Adapter, MSR)&0x0c;
1388                         val8 |= *((u8 *)val);
1389                         rtw_write8(Adapter, MSR, val8);
1390                 }
1391                 break;
1392         case HW_VAR_MEDIA_STATUS1:
1393                 {
1394                         u8 val8;
1395
1396                         val8 = rtw_read8(Adapter, MSR) & 0x03;
1397                         val8 |= *((u8 *)val) << 2;
1398                         rtw_write8(Adapter, MSR, val8);
1399                 }
1400                 break;
1401         case HW_VAR_SET_OPMODE:
1402                 hw_var_set_opmode(Adapter, variable, val);
1403                 break;
1404         case HW_VAR_MAC_ADDR:
1405                 hw_var_set_macaddr(Adapter, variable, val);
1406                 break;
1407         case HW_VAR_BSSID:
1408                 hw_var_set_bssid(Adapter, variable, val);
1409                 break;
1410         case HW_VAR_BASIC_RATE:
1411                 {
1412                         u16 BrateCfg = 0;
1413                         u8 RateIndex = 0;
1414
1415                         /*  2007.01.16, by Emily */
1416                         /*  Select RRSR (in Legacy-OFDM and CCK) */
1417                         /*  For 8190, we select only 24M, 12M, 6M, 11M, 5.5M, 2M, and 1M from the Basic rate. */
1418                         /*  We do not use other rates. */
1419                         HalSetBrateCfg(Adapter, val, &BrateCfg);
1420                         DBG_88E("HW_VAR_BASIC_RATE: BrateCfg(%#x)\n", BrateCfg);
1421
1422                         /* 2011.03.30 add by Luke Lee */
1423                         /* CCK 2M ACK should be disabled for some BCM and Atheros AP IOT */
1424                         /* because CCK 2M has poor TXEVM */
1425                         /* CCK 5.5M & 11M ACK should be enabled for better performance */
1426
1427                         BrateCfg = (BrateCfg | 0xd) & 0x15d;
1428                         haldata->BasicRateSet = BrateCfg;
1429
1430                         BrateCfg |= 0x01; /*  default enable 1M ACK rate */
1431                         /*  Set RRSR rate table. */
1432                         rtw_write8(Adapter, REG_RRSR, BrateCfg & 0xff);
1433                         rtw_write8(Adapter, REG_RRSR+1, (BrateCfg >> 8) & 0xff);
1434                         rtw_write8(Adapter, REG_RRSR+2, rtw_read8(Adapter, REG_RRSR+2)&0xf0);
1435
1436                         /*  Set RTS initial rate */
1437                         while (BrateCfg > 0x1) {
1438                                 BrateCfg = (BrateCfg >> 1);
1439                                 RateIndex++;
1440                         }
1441                         /*  Ziv - Check */
1442                         rtw_write8(Adapter, REG_INIRTS_RATE_SEL, RateIndex);
1443                 }
1444                 break;
1445         case HW_VAR_TXPAUSE:
1446                 rtw_write8(Adapter, REG_TXPAUSE, *((u8 *)val));
1447                 break;
1448         case HW_VAR_BCN_FUNC:
1449                 hw_var_set_bcn_func(Adapter, variable, val);
1450                 break;
1451         case HW_VAR_CORRECT_TSF:
1452                 {
1453                         u64     tsf;
1454                         struct mlme_ext_priv    *pmlmeext = &Adapter->mlmeextpriv;
1455                         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
1456
1457                         tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) - 1024; /* us */
1458
1459                         if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
1460                                 StopTxBeacon(Adapter);
1461
1462                         /* disable related TSF function */
1463                         rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3)));
1464
1465                         rtw_write32(Adapter, REG_TSFTR, tsf);
1466                         rtw_write32(Adapter, REG_TSFTR+4, tsf>>32);
1467
1468                         /* enable related TSF function */
1469                         rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3));
1470
1471                         if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
1472                                 ResumeTxBeacon(Adapter);
1473                 }
1474                 break;
1475         case HW_VAR_CHECK_BSSID:
1476                 if (*((u8 *)val)) {
1477                         rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
1478                 } else {
1479                         u32 val32;
1480
1481                         val32 = rtw_read32(Adapter, REG_RCR);
1482
1483                         val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1484
1485                         rtw_write32(Adapter, REG_RCR, val32);
1486                 }
1487                 break;
1488         case HW_VAR_MLME_DISCONNECT:
1489                 /* Set RCR to not to receive data frame when NO LINK state */
1490                 /* reject all data frames */
1491                 rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
1492
1493                 /* reset TSF */
1494                 rtw_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
1495
1496                 /* disable update TSF */
1497                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
1498                 break;
1499         case HW_VAR_MLME_SITESURVEY:
1500                 if (*((u8 *)val)) { /* under sitesurvey */
1501                         /* config RCR to receive different BSSID & not to receive data frame */
1502                         u32 v = rtw_read32(Adapter, REG_RCR);
1503                         v &= ~(RCR_CBSSID_BCN);
1504                         rtw_write32(Adapter, REG_RCR, v);
1505                         /* reject all data frame */
1506                         rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
1507
1508                         /* disable update TSF */
1509                         rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
1510                 } else { /* sitesurvey done */
1511                         struct mlme_ext_priv    *pmlmeext = &Adapter->mlmeextpriv;
1512                         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
1513
1514                         if ((is_client_associated_to_ap(Adapter)) ||
1515                             ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)) {
1516                                 /* enable to rx data frame */
1517                                 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1518
1519                                 /* enable update TSF */
1520                                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
1521                         } else if ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) {
1522                                 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1523                                 /* enable update TSF */
1524                                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
1525                         }
1526                         if ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) {
1527                                 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
1528                         } else {
1529                                 if (Adapter->in_cta_test) {
1530                                         u32 v = rtw_read32(Adapter, REG_RCR);
1531                                         v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);/*  RCR_ADF */
1532                                         rtw_write32(Adapter, REG_RCR, v);
1533                                 } else {
1534                                         rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
1535                                 }
1536                         }
1537                 }
1538                 break;
1539         case HW_VAR_MLME_JOIN:
1540                 {
1541                         u8 RetryLimit = 0x30;
1542                         u8 type = *((u8 *)val);
1543                         struct mlme_priv        *pmlmepriv = &Adapter->mlmepriv;
1544
1545                         if (type == 0) { /*  prepare to join */
1546                                 /* enable to rx data frame.Accept all data frame */
1547                                 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1548
1549                                 if (Adapter->in_cta_test) {
1550                                         u32 v = rtw_read32(Adapter, REG_RCR);
1551                                         v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);/*  RCR_ADF */
1552                                         rtw_write32(Adapter, REG_RCR, v);
1553                                 } else {
1554                                         rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
1555                                 }
1556
1557                                 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE))
1558                                         RetryLimit = (haldata->CustomerID == RT_CID_CCX) ? 7 : 48;
1559                                 else /*  Ad-hoc Mode */
1560                                         RetryLimit = 0x7;
1561                         } else if (type == 1) {
1562                                 /* joinbss_event call back when join res < 0 */
1563                                 rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
1564                         } else if (type == 2) {
1565                                 /* sta add event call back */
1566                                 /* enable update TSF */
1567                                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
1568
1569                                 if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
1570                                         RetryLimit = 0x7;
1571                         }
1572                         rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
1573                 }
1574                 break;
1575         case HW_VAR_BEACON_INTERVAL:
1576                 rtw_write16(Adapter, REG_BCN_INTERVAL, *((u16 *)val));
1577                 break;
1578         case HW_VAR_SLOT_TIME:
1579                 {
1580                         u8 u1bAIFS, aSifsTime;
1581                         struct mlme_ext_priv    *pmlmeext = &Adapter->mlmeextpriv;
1582                         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
1583
1584                         rtw_write8(Adapter, REG_SLOT, val[0]);
1585
1586                         if (pmlmeinfo->WMM_enable == 0) {
1587                                 if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
1588                                         aSifsTime = 10;
1589                                 else
1590                                         aSifsTime = 16;
1591
1592                                 u1bAIFS = aSifsTime + (2 * pmlmeinfo->slotTime);
1593
1594                                 /*  <Roger_EXP> Temporary removed, 2008.06.20. */
1595                                 rtw_write8(Adapter, REG_EDCA_VO_PARAM, u1bAIFS);
1596                                 rtw_write8(Adapter, REG_EDCA_VI_PARAM, u1bAIFS);
1597                                 rtw_write8(Adapter, REG_EDCA_BE_PARAM, u1bAIFS);
1598                                 rtw_write8(Adapter, REG_EDCA_BK_PARAM, u1bAIFS);
1599                         }
1600                 }
1601                 break;
1602         case HW_VAR_RESP_SIFS:
1603                 /* RESP_SIFS for CCK */
1604                 rtw_write8(Adapter, REG_R2T_SIFS, val[0]); /*  SIFS_T2T_CCK (0x08) */
1605                 rtw_write8(Adapter, REG_R2T_SIFS+1, val[1]); /* SIFS_R2T_CCK(0x08) */
1606                 /* RESP_SIFS for OFDM */
1607                 rtw_write8(Adapter, REG_T2T_SIFS, val[2]); /* SIFS_T2T_OFDM (0x0a) */
1608                 rtw_write8(Adapter, REG_T2T_SIFS+1, val[3]); /* SIFS_R2T_OFDM(0x0a) */
1609                 break;
1610         case HW_VAR_ACK_PREAMBLE:
1611                 {
1612                         u8 regTmp;
1613                         u8 bShortPreamble = *((bool *)val);
1614                         /*  Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) */
1615                         regTmp = (haldata->nCur40MhzPrimeSC)<<5;
1616                         if (bShortPreamble)
1617                                 regTmp |= 0x80;
1618
1619                         rtw_write8(Adapter, REG_RRSR+2, regTmp);
1620                 }
1621                 break;
1622         case HW_VAR_SEC_CFG:
1623                 rtw_write8(Adapter, REG_SECCFG, *((u8 *)val));
1624                 break;
1625         case HW_VAR_DM_FLAG:
1626                 podmpriv->SupportAbility = *((u8 *)val);
1627                 break;
1628         case HW_VAR_DM_FUNC_OP:
1629                 if (val[0])
1630                         podmpriv->BK_SupportAbility = podmpriv->SupportAbility;
1631                 else
1632                         podmpriv->SupportAbility = podmpriv->BK_SupportAbility;
1633                 break;
1634         case HW_VAR_DM_FUNC_SET:
1635                 if (*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE) {
1636                         pdmpriv->DMFlag = pdmpriv->InitDMFlag;
1637                         podmpriv->SupportAbility =      pdmpriv->InitODMFlag;
1638                 } else {
1639                         podmpriv->SupportAbility |= *((u32 *)val);
1640                 }
1641                 break;
1642         case HW_VAR_DM_FUNC_CLR:
1643                 podmpriv->SupportAbility &= *((u32 *)val);
1644                 break;
1645         case HW_VAR_CAM_EMPTY_ENTRY:
1646                 {
1647                         u8 ucIndex = *((u8 *)val);
1648                         u8 i;
1649                         u32 ulCommand = 0;
1650                         u32 ulContent = 0;
1651                         u32 ulEncAlgo = CAM_AES;
1652
1653                         for (i = 0; i < CAM_CONTENT_COUNT; i++) {
1654                                 /*  filled id in CAM config 2 byte */
1655                                 if (i == 0)
1656                                         ulContent |= (ucIndex & 0x03) | ((u16)(ulEncAlgo)<<2);
1657                                 else
1658                                         ulContent = 0;
1659                                 /*  polling bit, and No Write enable, and address */
1660                                 ulCommand = CAM_CONTENT_COUNT*ucIndex+i;
1661                                 ulCommand = ulCommand | CAM_POLLINIG|CAM_WRITE;
1662                                 /*  write content 0 is equall to mark invalid */
1663                                 rtw_write32(Adapter, WCAMI, ulContent);  /* delay_ms(40); */
1664                                 rtw_write32(Adapter, RWCAM, ulCommand);  /* delay_ms(40); */
1665                         }
1666                 }
1667                 break;
1668         case HW_VAR_CAM_INVALID_ALL:
1669                 rtw_write32(Adapter, RWCAM, BIT(31)|BIT(30));
1670                 break;
1671         case HW_VAR_CAM_WRITE:
1672                 {
1673                         u32 cmd;
1674                         u32 *cam_val = (u32 *)val;
1675                         rtw_write32(Adapter, WCAMI, cam_val[0]);
1676
1677                         cmd = CAM_POLLINIG | CAM_WRITE | cam_val[1];
1678                         rtw_write32(Adapter, RWCAM, cmd);
1679                 }
1680                 break;
1681         case HW_VAR_AC_PARAM_VO:
1682                 rtw_write32(Adapter, REG_EDCA_VO_PARAM, ((u32 *)(val))[0]);
1683                 break;
1684         case HW_VAR_AC_PARAM_VI:
1685                 rtw_write32(Adapter, REG_EDCA_VI_PARAM, ((u32 *)(val))[0]);
1686                 break;
1687         case HW_VAR_AC_PARAM_BE:
1688                 haldata->AcParam_BE = ((u32 *)(val))[0];
1689                 rtw_write32(Adapter, REG_EDCA_BE_PARAM, ((u32 *)(val))[0]);
1690                 break;
1691         case HW_VAR_AC_PARAM_BK:
1692                 rtw_write32(Adapter, REG_EDCA_BK_PARAM, ((u32 *)(val))[0]);
1693                 break;
1694         case HW_VAR_ACM_CTRL:
1695                 {
1696                         u8 acm_ctrl = *((u8 *)val);
1697                         u8 AcmCtrl = rtw_read8(Adapter, REG_ACMHWCTRL);
1698
1699                         if (acm_ctrl > 1)
1700                                 AcmCtrl = AcmCtrl | 0x1;
1701
1702                         if (acm_ctrl & BIT(3))
1703                                 AcmCtrl |= AcmHw_VoqEn;
1704                         else
1705                                 AcmCtrl &= (~AcmHw_VoqEn);
1706
1707                         if (acm_ctrl & BIT(2))
1708                                 AcmCtrl |= AcmHw_ViqEn;
1709                         else
1710                                 AcmCtrl &= (~AcmHw_ViqEn);
1711
1712                         if (acm_ctrl & BIT(1))
1713                                 AcmCtrl |= AcmHw_BeqEn;
1714                         else
1715                                 AcmCtrl &= (~AcmHw_BeqEn);
1716
1717                         DBG_88E("[HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
1718                         rtw_write8(Adapter, REG_ACMHWCTRL, AcmCtrl);
1719                 }
1720                 break;
1721         case HW_VAR_AMPDU_MIN_SPACE:
1722                 {
1723                         u8 MinSpacingToSet;
1724                         u8 SecMinSpace;
1725
1726                         MinSpacingToSet = *((u8 *)val);
1727                         if (MinSpacingToSet <= 7) {
1728                                 switch (Adapter->securitypriv.dot11PrivacyAlgrthm) {
1729                                 case _NO_PRIVACY_:
1730                                 case _AES_:
1731                                         SecMinSpace = 0;
1732                                         break;
1733                                 case _WEP40_:
1734                                 case _WEP104_:
1735                                 case _TKIP_:
1736                                 case _TKIP_WTMIC_:
1737                                         SecMinSpace = 6;
1738                                         break;
1739                                 default:
1740                                         SecMinSpace = 7;
1741                                         break;
1742                                 }
1743                                 if (MinSpacingToSet < SecMinSpace)
1744                                         MinSpacingToSet = SecMinSpace;
1745                                 rtw_write8(Adapter, REG_AMPDU_MIN_SPACE, (rtw_read8(Adapter, REG_AMPDU_MIN_SPACE) & 0xf8) | MinSpacingToSet);
1746                         }
1747                 }
1748                 break;
1749         case HW_VAR_AMPDU_FACTOR:
1750                 {
1751                         u8 RegToSet_Normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1752                         u8 FactorToSet;
1753                         u8 *pRegToSet;
1754                         u8 index = 0;
1755
1756                         pRegToSet = RegToSet_Normal; /*  0xb972a841; */
1757                         FactorToSet = *((u8 *)val);
1758                         if (FactorToSet <= 3) {
1759                                 FactorToSet = (1<<(FactorToSet + 2));
1760                                 if (FactorToSet > 0xf)
1761                                         FactorToSet = 0xf;
1762
1763                                 for (index = 0; index < 4; index++) {
1764                                         if ((pRegToSet[index] & 0xf0) > (FactorToSet<<4))
1765                                                 pRegToSet[index] = (pRegToSet[index] & 0x0f) | (FactorToSet<<4);
1766
1767                                         if ((pRegToSet[index] & 0x0f) > FactorToSet)
1768                                                 pRegToSet[index] = (pRegToSet[index] & 0xf0) | (FactorToSet);
1769
1770                                         rtw_write8(Adapter, (REG_AGGLEN_LMT+index), pRegToSet[index]);
1771                                 }
1772                         }
1773                 }
1774                 break;
1775         case HW_VAR_RXDMA_AGG_PG_TH:
1776                 {
1777                         u8 threshold = *((u8 *)val);
1778                         if (threshold == 0)
1779                                 threshold = haldata->UsbRxAggPageCount;
1780                         rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, threshold);
1781                 }
1782                 break;
1783         case HW_VAR_SET_RPWM:
1784                 break;
1785         case HW_VAR_H2C_FW_PWRMODE:
1786                 {
1787                         u8 psmode = (*(u8 *)val);
1788
1789                         /*  Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power */
1790                         /*  saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang. */
1791                         if ((psmode != PS_MODE_ACTIVE) && (!IS_92C_SERIAL(haldata->VersionID)))
1792                                 ODM_RF_Saving(podmpriv, true);
1793                         rtl8188e_set_FwPwrMode_cmd(Adapter, psmode);
1794                 }
1795                 break;
1796         case HW_VAR_H2C_FW_JOINBSSRPT:
1797                 {
1798                         u8 mstatus = (*(u8 *)val);
1799                         rtl8188e_set_FwJoinBssReport_cmd(Adapter, mstatus);
1800                 }
1801                 break;
1802 #ifdef CONFIG_88EU_P2P
1803         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
1804                 {
1805                         u8 p2p_ps_state = (*(u8 *)val);
1806                         rtl8188e_set_p2p_ps_offload_cmd(Adapter, p2p_ps_state);
1807                 }
1808                 break;
1809 #endif
1810         case HW_VAR_INITIAL_GAIN:
1811                 {
1812                         struct rtw_dig *pDigTable = &podmpriv->DM_DigTable;
1813                         u32 rx_gain = ((u32 *)(val))[0];
1814
1815                         if (rx_gain == 0xff) {/* restore rx gain */
1816                                 ODM_Write_DIG(podmpriv, pDigTable->BackupIGValue);
1817                         } else {
1818                                 pDigTable->BackupIGValue = pDigTable->CurIGValue;
1819                                 ODM_Write_DIG(podmpriv, rx_gain);
1820                         }
1821                 }
1822                 break;
1823         case HW_VAR_TRIGGER_GPIO_0:
1824                 rtl8192cu_trigger_gpio_0(Adapter);
1825                 break;
1826         case HW_VAR_RPT_TIMER_SETTING:
1827                 {
1828                         u16 min_rpt_time = (*(u16 *)val);
1829                         ODM_RA_Set_TxRPT_Time(podmpriv, min_rpt_time);
1830                 }
1831                 break;
1832         case HW_VAR_ANTENNA_DIVERSITY_SELECT:
1833                 {
1834                         u8 Optimum_antenna = (*(u8 *)val);
1835                         u8 Ant;
1836                         /* switch antenna to Optimum_antenna */
1837                         if (haldata->CurAntenna !=  Optimum_antenna) {
1838                                 Ant = (Optimum_antenna == 2) ? MAIN_ANT : AUX_ANT;
1839                                 ODM_UpdateRxIdleAnt_88E(&haldata->odmpriv, Ant);
1840
1841                                 haldata->CurAntenna = Optimum_antenna;
1842                         }
1843                 }
1844                 break;
1845         case HW_VAR_EFUSE_BYTES: /*  To set EFUE total used bytes, added by Roger, 2008.12.22. */
1846                 haldata->EfuseUsedBytes = *((u16 *)val);
1847                 break;
1848         case HW_VAR_FIFO_CLEARN_UP:
1849                 {
1850                         struct pwrctrl_priv *pwrpriv = &Adapter->pwrctrlpriv;
1851                         u8 trycnt = 100;
1852
1853                         /* pause tx */
1854                         rtw_write8(Adapter, REG_TXPAUSE, 0xff);
1855
1856                         /* keep sn */
1857                         Adapter->xmitpriv.nqos_ssn = rtw_read16(Adapter, REG_NQOS_SEQ);
1858
1859                         if (!pwrpriv->bkeepfwalive) {
1860                                 /* RX DMA stop */
1861                                 rtw_write32(Adapter, REG_RXPKT_NUM, (rtw_read32(Adapter, REG_RXPKT_NUM)|RW_RELEASE_EN));
1862                                 do {
1863                                         if (!(rtw_read32(Adapter, REG_RXPKT_NUM)&RXDMA_IDLE))
1864                                                 break;
1865                                 } while (trycnt--);
1866                                 if (trycnt == 0)
1867                                         DBG_88E("Stop RX DMA failed......\n");
1868
1869                                 /* RQPN Load 0 */
1870                                 rtw_write16(Adapter, REG_RQPN_NPQ, 0x0);
1871                                 rtw_write32(Adapter, REG_RQPN, 0x80000000);
1872                                 rtw_mdelay_os(10);
1873                         }
1874                 }
1875                 break;
1876         case HW_VAR_CHECK_TXBUF:
1877                 break;
1878         case HW_VAR_APFM_ON_MAC:
1879                 haldata->bMacPwrCtrlOn = *val;
1880                 DBG_88E("%s: bMacPwrCtrlOn=%d\n", __func__, haldata->bMacPwrCtrlOn);
1881                 break;
1882         case HW_VAR_TX_RPT_MAX_MACID:
1883                 {
1884                         u8 maxMacid = *val;
1885                         DBG_88E("### MacID(%d),Set Max Tx RPT MID(%d)\n", maxMacid, maxMacid+1);
1886                         rtw_write8(Adapter, REG_TX_RPT_CTRL+1, maxMacid+1);
1887                 }
1888                 break;
1889         case HW_VAR_H2C_MEDIA_STATUS_RPT:
1890                 rtl8188e_set_FwMediaStatus_cmd(Adapter , (*(__le16 *)val));
1891                 break;
1892         case HW_VAR_BCN_VALID:
1893                 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw */
1894                 rtw_write8(Adapter, REG_TDECTRL+2, rtw_read8(Adapter, REG_TDECTRL+2) | BIT0);
1895                 break;
1896         default:
1897                 break;
1898         }
1899
1900 }
1901
1902 static void GetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val)
1903 {
1904         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
1905         struct odm_dm_struct *podmpriv = &haldata->odmpriv;
1906
1907         switch (variable) {
1908         case HW_VAR_BASIC_RATE:
1909                 *((u16 *)(val)) = haldata->BasicRateSet;
1910                 __attribute__((__fallthrough__));
1911         case HW_VAR_TXPAUSE:
1912                 val[0] = rtw_read8(Adapter, REG_TXPAUSE);
1913                 break;
1914         case HW_VAR_BCN_VALID:
1915                 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2 */
1916                 val[0] = (BIT0 & rtw_read8(Adapter, REG_TDECTRL+2)) ? true : false;
1917                 break;
1918         case HW_VAR_DM_FLAG:
1919                 val[0] = podmpriv->SupportAbility;
1920                 break;
1921         case HW_VAR_RF_TYPE:
1922                 val[0] = haldata->rf_type;
1923                 break;
1924         case HW_VAR_FWLPS_RF_ON:
1925                 {
1926                         /* When we halt NIC, we should check if FW LPS is leave. */
1927                         if (Adapter->pwrctrlpriv.rf_pwrstate == rf_off) {
1928                                 /*  If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave, */
1929                                 /*  because Fw is unload. */
1930                                 val[0] = true;
1931                         } else {
1932                                 u32 valRCR;
1933                                 valRCR = rtw_read32(Adapter, REG_RCR);
1934                                 valRCR &= 0x00070000;
1935                                 if (valRCR)
1936                                         val[0] = false;
1937                                 else
1938                                         val[0] = true;
1939                         }
1940                 }
1941                 break;
1942         case HW_VAR_CURRENT_ANTENNA:
1943                 val[0] = haldata->CurAntenna;
1944                 break;
1945         case HW_VAR_EFUSE_BYTES: /*  To get EFUE total used bytes, added by Roger, 2008.12.22. */
1946                 *((u16 *)(val)) = haldata->EfuseUsedBytes;
1947                 break;
1948         case HW_VAR_APFM_ON_MAC:
1949                 *val = haldata->bMacPwrCtrlOn;
1950                 break;
1951         case HW_VAR_CHK_HI_QUEUE_EMPTY:
1952                 *val = ((rtw_read32(Adapter, REG_HGQ_INFORMATION)&0x0000ff00) == 0) ? true : false;
1953                 break;
1954         default:
1955                 break;
1956         }
1957
1958 }
1959
1960 /*  */
1961 /*      Description: */
1962 /*              Query setting of specified variable. */
1963 /*  */
1964 static u8
1965 GetHalDefVar8188EUsb(
1966                 struct adapter *Adapter,
1967                 enum hal_def_variable eVariable,
1968                 void *pValue
1969         )
1970 {
1971         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
1972         u8 bResult = _SUCCESS;
1973
1974         switch (eVariable) {
1975         case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
1976                 {
1977                         struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
1978                         struct sta_priv *pstapriv = &Adapter->stapriv;
1979                         struct sta_info *psta;
1980                         psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
1981                         if (psta)
1982                                 *((int *)pValue) = psta->rssi_stat.UndecoratedSmoothedPWDB;
1983                 }
1984                 break;
1985         case HAL_DEF_IS_SUPPORT_ANT_DIV:
1986                 *((u8 *)pValue) = (haldata->AntDivCfg == 0) ? false : true;
1987                 break;
1988         case HAL_DEF_CURRENT_ANTENNA:
1989                 *((u8 *)pValue) = haldata->CurAntenna;
1990                 break;
1991         case HAL_DEF_DRVINFO_SZ:
1992                 *((u32 *)pValue) = DRVINFO_SZ;
1993                 break;
1994         case HAL_DEF_MAX_RECVBUF_SZ:
1995                 *((u32 *)pValue) = MAX_RECVBUF_SZ;
1996                 break;
1997         case HAL_DEF_RX_PACKET_OFFSET:
1998                 *((u32 *)pValue) = RXDESC_SIZE + DRVINFO_SZ;
1999                 break;
2000         case HAL_DEF_DBG_DM_FUNC:
2001                 *((u32 *)pValue) = haldata->odmpriv.SupportAbility;
2002                 break;
2003         case HAL_DEF_RA_DECISION_RATE:
2004                 {
2005                         u8 MacID = *((u8 *)pValue);
2006                         *((u8 *)pValue) = ODM_RA_GetDecisionRate_8188E(&(haldata->odmpriv), MacID);
2007                 }
2008                 break;
2009         case HAL_DEF_RA_SGI:
2010                 {
2011                         u8 MacID = *((u8 *)pValue);
2012                         *((u8 *)pValue) = ODM_RA_GetShortGI_8188E(&(haldata->odmpriv), MacID);
2013                 }
2014                 break;
2015         case HAL_DEF_PT_PWR_STATUS:
2016                 {
2017                         u8 MacID = *((u8 *)pValue);
2018                         *((u8 *)pValue) = ODM_RA_GetHwPwrStatus_8188E(&(haldata->odmpriv), MacID);
2019                 }
2020                 break;
2021         case HW_VAR_MAX_RX_AMPDU_FACTOR:
2022                 *((u32 *)pValue) = MAX_AMPDU_FACTOR_64K;
2023                 break;
2024         case HW_DEF_RA_INFO_DUMP:
2025                 {
2026                         u8 entry_id = *((u8 *)pValue);
2027                         if (check_fwstate(&Adapter->mlmepriv, _FW_LINKED)) {
2028                                 DBG_88E("============ RA status check ===================\n");
2029                                 DBG_88E("Mac_id:%d , RateID = %d, RAUseRate = 0x%08x, RateSGI = %d, DecisionRate = 0x%02x ,PTStage = %d\n",
2030                                         entry_id,
2031                                         haldata->odmpriv.RAInfo[entry_id].RateID,
2032                                         haldata->odmpriv.RAInfo[entry_id].RAUseRate,
2033                                         haldata->odmpriv.RAInfo[entry_id].RateSGI,
2034                                         haldata->odmpriv.RAInfo[entry_id].DecisionRate,
2035                                         haldata->odmpriv.RAInfo[entry_id].PTStage);
2036                         }
2037                 }
2038                 break;
2039         case HW_DEF_ODM_DBG_FLAG:
2040                 {
2041                         struct odm_dm_struct *dm_ocm = &(haldata->odmpriv);
2042                         pr_info("dm_ocm->DebugComponents = 0x%llx\n", dm_ocm->DebugComponents);
2043                 }
2044                 break;
2045         case HAL_DEF_DBG_DUMP_RXPKT:
2046                 *((u8 *)pValue) = haldata->bDumpRxPkt;
2047                 break;
2048         case HAL_DEF_DBG_DUMP_TXPKT:
2049                 *((u8 *)pValue) = haldata->bDumpTxPkt;
2050                 break;
2051         default:
2052                 bResult = _FAIL;
2053                 break;
2054         }
2055
2056         return bResult;
2057 }
2058
2059 /*  */
2060 /*      Description: */
2061 /*              Change default setting of specified variable. */
2062 /*  */
2063 static u8 SetHalDefVar8188EUsb(struct adapter *Adapter, enum hal_def_variable eVariable, void *pValue)
2064 {
2065         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
2066         u8 bResult = _SUCCESS;
2067
2068         switch (eVariable) {
2069         case HAL_DEF_DBG_DM_FUNC:
2070                 {
2071                         u8 dm_func = *((u8 *)pValue);
2072                         struct odm_dm_struct *podmpriv = &haldata->odmpriv;
2073
2074                         if (dm_func == 0) { /* disable all dynamic func */
2075                                 podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE;
2076                                 DBG_88E("==> Disable all dynamic function...\n");
2077                         } else if (dm_func == 1) {/* disable DIG */
2078                                 podmpriv->SupportAbility  &= (~DYNAMIC_BB_DIG);
2079                                 DBG_88E("==> Disable DIG...\n");
2080                         } else if (dm_func == 2) {/* disable High power */
2081                                 podmpriv->SupportAbility  &= (~DYNAMIC_BB_DYNAMIC_TXPWR);
2082                         } else if (dm_func == 3) {/* disable tx power tracking */
2083                                 podmpriv->SupportAbility  &= (~DYNAMIC_RF_CALIBRATION);
2084                                 DBG_88E("==> Disable tx power tracking...\n");
2085                         } else if (dm_func == 5) {/* disable antenna diversity */
2086                                 podmpriv->SupportAbility  &= (~DYNAMIC_BB_ANT_DIV);
2087                         } else if (dm_func == 6) {/* turn on all dynamic func */
2088                                 if (!(podmpriv->SupportAbility  & DYNAMIC_BB_DIG)) {
2089                                         struct rtw_dig *pDigTable = &podmpriv->DM_DigTable;
2090                                         pDigTable->CurIGValue = rtw_read8(Adapter, 0xc50);
2091                                 }
2092                                 podmpriv->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE;
2093                                 DBG_88E("==> Turn on all dynamic function...\n");
2094                         }
2095                 }
2096                 break;
2097         case HAL_DEF_DBG_DUMP_RXPKT:
2098                 haldata->bDumpRxPkt = *((u8 *)pValue);
2099                 break;
2100         case HAL_DEF_DBG_DUMP_TXPKT:
2101                 haldata->bDumpTxPkt = *((u8 *)pValue);
2102                 break;
2103         case HW_DEF_FA_CNT_DUMP:
2104                 {
2105                         u8 bRSSIDump = *((u8 *)pValue);
2106                         struct odm_dm_struct *dm_ocm = &(haldata->odmpriv);
2107                         if (bRSSIDump)
2108                                 dm_ocm->DebugComponents =       ODM_COMP_DIG|ODM_COMP_FA_CNT    ;
2109                         else
2110                                 dm_ocm->DebugComponents = 0;
2111                 }
2112                 break;
2113         case HW_DEF_ODM_DBG_FLAG:
2114                 {
2115                         u64     DebugComponents = *((u64 *)pValue);
2116                         struct odm_dm_struct *dm_ocm = &(haldata->odmpriv);
2117                         dm_ocm->DebugComponents = DebugComponents;
2118                 }
2119                 break;
2120         default:
2121                 bResult = _FAIL;
2122                 break;
2123         }
2124
2125         return bResult;
2126 }
2127
2128 static void UpdateHalRAMask8188EUsb(struct adapter *adapt, u32 mac_id, u8 rssi_level)
2129 {
2130         u8 init_rate = 0;
2131         u8 networkType, raid;
2132         u32 mask, rate_bitmap;
2133         u8 shortGIrate = false;
2134         int     supportRateNum = 0;
2135         struct sta_info *psta;
2136         struct hal_data_8188e   *haldata = GET_HAL_DATA(adapt);
2137         struct mlme_ext_priv    *pmlmeext = &adapt->mlmeextpriv;
2138         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
2139         struct wlan_bssid_ex    *cur_network = &(pmlmeinfo->network);
2140
2141         if (mac_id >= NUM_STA) /* CAM_SIZE */
2142                 return;
2143         psta = pmlmeinfo->FW_sta_info[mac_id].psta;
2144         if (psta == NULL)
2145                 return;
2146         switch (mac_id) {
2147         case 0:/*  for infra mode */
2148                 supportRateNum = rtw_get_rateset_len(cur_network->SupportedRates);
2149                 networkType = judge_network_type(adapt, cur_network->SupportedRates, supportRateNum) & 0xf;
2150                 raid = networktype_to_raid(networkType);
2151                 mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
2152                 mask |= (pmlmeinfo->HT_enable) ? update_MSC_rate(&(pmlmeinfo->HT_caps)) : 0;
2153                 if (support_short_GI(adapt, &(pmlmeinfo->HT_caps)))
2154                         shortGIrate = true;
2155                 break;
2156         case 1:/* for broadcast/multicast */
2157                 supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
2158                 if (pmlmeext->cur_wireless_mode & WIRELESS_11B)
2159                         networkType = WIRELESS_11B;
2160                 else
2161                         networkType = WIRELESS_11G;
2162                 raid = networktype_to_raid(networkType);
2163                 mask = update_basic_rate(cur_network->SupportedRates, supportRateNum);
2164                 break;
2165         default: /* for each sta in IBSS */
2166                 supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
2167                 networkType = judge_network_type(adapt, pmlmeinfo->FW_sta_info[mac_id].SupportedRates, supportRateNum) & 0xf;
2168                 raid = networktype_to_raid(networkType);
2169                 mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
2170
2171                 /* todo: support HT in IBSS */
2172                 break;
2173         }
2174
2175         rate_bitmap = 0x0fffffff;
2176         rate_bitmap = ODM_Get_Rate_Bitmap(&haldata->odmpriv, mac_id, mask, rssi_level);
2177         DBG_88E("%s => mac_id:%d, networkType:0x%02x, mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n",
2178                 __func__, mac_id, networkType, mask, rssi_level, rate_bitmap);
2179
2180         mask &= rate_bitmap;
2181
2182         init_rate = get_highest_rate_idx(mask)&0x3f;
2183
2184         if (haldata->fw_ractrl) {
2185                 u8 arg;
2186
2187                 arg = mac_id & 0x1f;/* MACID */
2188                 arg |= BIT(7);
2189                 if (shortGIrate)
2190                         arg |= BIT(5);
2191                 mask |= ((raid << 28) & 0xf0000000);
2192                 DBG_88E("update raid entry, mask=0x%x, arg=0x%x\n", mask, arg);
2193                 psta->ra_mask = mask;
2194                 mask |= ((raid << 28) & 0xf0000000);
2195
2196                 /* to do ,for 8188E-SMIC */
2197                 rtl8188e_set_raid_cmd(adapt, mask);
2198         } else {
2199                 ODM_RA_UpdateRateInfo_8188E(&(haldata->odmpriv),
2200                                 mac_id,
2201                                 raid,
2202                                 mask,
2203                                 shortGIrate
2204                                 );
2205         }
2206         /* set ra_id */
2207         psta->raid = raid;
2208         psta->init_rate = init_rate;
2209 }
2210
2211 static void SetBeaconRelatedRegisters8188EUsb(struct adapter *adapt)
2212 {
2213         u32 value32;
2214         struct mlme_ext_priv    *pmlmeext = &(adapt->mlmeextpriv);
2215         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
2216         u32 bcn_ctrl_reg                        = REG_BCN_CTRL;
2217         /* reset TSF, enable update TSF, correcting TSF On Beacon */
2218
2219         /* BCN interval */
2220         rtw_write16(adapt, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
2221         rtw_write8(adapt, REG_ATIMWND, 0x02);/*  2ms */
2222
2223         _InitBeaconParameters(adapt);
2224
2225         rtw_write8(adapt, REG_SLOT, 0x09);
2226
2227         value32 = rtw_read32(adapt, REG_TCR);
2228         value32 &= ~TSFRST;
2229         rtw_write32(adapt,  REG_TCR, value32);
2230
2231         value32 |= TSFRST;
2232         rtw_write32(adapt, REG_TCR, value32);
2233
2234         /*  NOTE: Fix test chip's bug (about contention windows's randomness) */
2235         rtw_write8(adapt,  REG_RXTSF_OFFSET_CCK, 0x50);
2236         rtw_write8(adapt, REG_RXTSF_OFFSET_OFDM, 0x50);
2237
2238         _BeaconFunctionEnable(adapt, true, true);
2239
2240         ResumeTxBeacon(adapt);
2241
2242         rtw_write8(adapt, bcn_ctrl_reg, rtw_read8(adapt, bcn_ctrl_reg)|BIT(1));
2243 }
2244
2245 static void rtl8188eu_init_default_value(struct adapter *adapt)
2246 {
2247         struct hal_data_8188e *haldata;
2248         struct pwrctrl_priv *pwrctrlpriv;
2249         u8 i;
2250
2251         haldata = GET_HAL_DATA(adapt);
2252         pwrctrlpriv = &adapt->pwrctrlpriv;
2253
2254         /* init default value */
2255         haldata->fw_ractrl = false;
2256         if (!pwrctrlpriv->bkeepfwalive)
2257                 haldata->LastHMEBoxNum = 0;
2258
2259         /* init dm default value */
2260         haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = false;
2261         haldata->odmpriv.RFCalibrateInfo.TM_Trigger = 0;/* for IQK */
2262         haldata->pwrGroupCnt = 0;
2263         haldata->PGMaxGroup = 13;
2264         haldata->odmpriv.RFCalibrateInfo.ThermalValue_HP_index = 0;
2265         for (i = 0; i < HP_THERMAL_NUM; i++)
2266                 haldata->odmpriv.RFCalibrateInfo.ThermalValue_HP[i] = 0;
2267 }
2268
2269 static u8 rtl8188eu_ps_func(struct adapter *Adapter, enum hal_intf_ps_func efunc_id, u8 *val)
2270 {
2271         u8 bResult = true;
2272         return bResult;
2273 }
2274
2275 void rtl8188eu_set_hal_ops(struct adapter *adapt)
2276 {
2277         struct hal_ops  *halfunc = &adapt->HalFunc;
2278
2279         adapt->HalData = rtw_zmalloc(sizeof(struct hal_data_8188e));
2280         if (adapt->HalData == NULL)
2281                 DBG_88E("cant not alloc memory for HAL DATA\n");
2282         adapt->hal_data_sz = sizeof(struct hal_data_8188e);
2283
2284         halfunc->hal_power_on = rtl8188eu_InitPowerOn;
2285         halfunc->hal_init = &rtl8188eu_hal_init;
2286         halfunc->hal_deinit = &rtl8188eu_hal_deinit;
2287
2288         halfunc->inirp_init = &rtl8188eu_inirp_init;
2289         halfunc->inirp_deinit = &rtl8188eu_inirp_deinit;
2290
2291         halfunc->init_xmit_priv = &rtl8188eu_init_xmit_priv;
2292         halfunc->free_xmit_priv = &rtl8188eu_free_xmit_priv;
2293
2294         halfunc->init_recv_priv = &rtl8188eu_init_recv_priv;
2295         halfunc->free_recv_priv = &rtl8188eu_free_recv_priv;
2296         halfunc->InitSwLeds = &rtl8188eu_InitSwLeds;
2297         halfunc->DeInitSwLeds = &rtl8188eu_DeInitSwLeds;
2298
2299         halfunc->init_default_value = &rtl8188eu_init_default_value;
2300         halfunc->intf_chip_configure = &rtl8188eu_interface_configure;
2301         halfunc->read_adapter_info = &ReadAdapterInfo8188EU;
2302
2303         halfunc->SetHwRegHandler = &SetHwReg8188EU;
2304         halfunc->GetHwRegHandler = &GetHwReg8188EU;
2305         halfunc->GetHalDefVarHandler = &GetHalDefVar8188EUsb;
2306         halfunc->SetHalDefVarHandler = &SetHalDefVar8188EUsb;
2307
2308         halfunc->UpdateRAMaskHandler = &UpdateHalRAMask8188EUsb;
2309         halfunc->SetBeaconRelatedRegistersHandler = &SetBeaconRelatedRegisters8188EUsb;
2310
2311         halfunc->hal_xmit = &rtl8188eu_hal_xmit;
2312         halfunc->mgnt_xmit = &rtl8188eu_mgnt_xmit;
2313
2314         halfunc->interface_ps_func = &rtl8188eu_ps_func;
2315
2316         rtl8188e_set_hal_ops(halfunc);
2317
2318 }