1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
20 #define _RTL8188E_XMIT_C_
21 #include <osdep_service.h>
22 #include <drv_types.h>
24 #include <osdep_intf.h>
26 #include <rtl8188e_hal.h>
28 s32 rtl8188eu_init_xmit_priv(struct adapter *adapt)
30 struct xmit_priv *pxmitpriv = &adapt->xmitpriv;
32 tasklet_init(&pxmitpriv->xmit_tasklet,
33 (void(*)(unsigned long))rtl8188eu_xmit_tasklet,
34 (unsigned long)adapt);
38 void rtl8188eu_free_xmit_priv(struct adapter *adapt)
42 static u8 urb_zero_packet_chk(struct adapter *adapt, int sz)
44 u8 set_tx_desc_offset;
45 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
46 set_tx_desc_offset = (((sz + TXDESC_SIZE) % haldata->UsbBulkOutSize) == 0) ? 1 : 0;
48 return set_tx_desc_offset;
51 static void rtl8188eu_cal_txdesc_chksum(struct tx_desc *ptxdesc)
53 u16 *usptr = (u16 *)ptxdesc;
54 u32 count = 16; /* (32 bytes / 2 bytes per XOR) => 16 times */
59 ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
61 for (index = 0; index < count; index++)
62 checksum = checksum ^ le16_to_cpu(*(__le16 *)(usptr + index));
63 ptxdesc->txdw7 |= cpu_to_le32(0x0000ffff & checksum);
66 /* Description: In normal chip, we should send some packet to Hw which will be used by Fw */
67 /* in FW LPS mode. The function is to fill the Tx descriptor of this packets, then */
68 /* Fw can tell Hw to send these packet derectly. */
69 void rtl8188e_fill_fake_txdesc(struct adapter *adapt, u8 *desc, u32 BufferLen, u8 ispspoll, u8 is_btqosnull)
71 struct tx_desc *ptxdesc;
73 /* Clear all status */
74 ptxdesc = (struct tx_desc *)desc;
75 memset(desc, 0, TXDESC_SIZE);
78 ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG); /* own, bFirstSeg, bLastSeg; */
80 ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<<OFFSET_SHT)&0x00ff0000); /* 32 bytes for TX Desc */
82 ptxdesc->txdw0 |= cpu_to_le32(BufferLen&0x0000ffff); /* Buffer size + command header */
85 ptxdesc->txdw1 |= cpu_to_le32((QSLT_MGNT<<QSEL_SHT)&0x00001f00); /* Fixed queue of Mgnt queue */
87 /* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw. */
89 ptxdesc->txdw1 |= cpu_to_le32(NAVUSEHDR);
91 ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); /* Hw set sequence number */
92 ptxdesc->txdw3 |= cpu_to_le32((8 << 28)); /* set bit3 to 1. Suugested by TimChen. 2009.12.29. */
96 ptxdesc->txdw2 |= cpu_to_le32(BIT(23)); /* BT NULL */
99 ptxdesc->txdw4 |= cpu_to_le32(BIT(8));/* driver uses rate */
101 /* USB interface drop packet if the checksum of descriptor isn't correct. */
102 /* Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.). */
103 rtl8188eu_cal_txdesc_chksum(ptxdesc);
106 static void fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc)
108 if ((pattrib->encrypt > 0) && !pattrib->bswenc) {
109 switch (pattrib->encrypt) {
110 /* SEC_TYPE : 0:NO_ENC,1:WEP40/TKIP,2:WAPI,3:AES */
113 ptxdesc->txdw1 |= cpu_to_le32((0x01<<SEC_TYPE_SHT)&0x00c00000);
114 ptxdesc->txdw2 |= cpu_to_le32(0x7 << AMPDU_DENSITY_SHT);
118 ptxdesc->txdw1 |= cpu_to_le32((0x01<<SEC_TYPE_SHT)&0x00c00000);
119 ptxdesc->txdw2 |= cpu_to_le32(0x7 << AMPDU_DENSITY_SHT);
122 ptxdesc->txdw1 |= cpu_to_le32((0x03<<SEC_TYPE_SHT)&0x00c00000);
123 ptxdesc->txdw2 |= cpu_to_le32(0x7 << AMPDU_DENSITY_SHT);
132 static void fill_txdesc_vcs(struct pkt_attrib *pattrib, __le32 *pdw)
134 switch (pattrib->vcs_mode) {
136 *pdw |= cpu_to_le32(RTS_EN);
139 *pdw |= cpu_to_le32(CTS_2_SELF);
145 if (pattrib->vcs_mode) {
146 *pdw |= cpu_to_le32(HW_RTS_EN);
148 if (pattrib->ht_en) {
149 *pdw |= (pattrib->bwmode&HT_CHANNEL_WIDTH_40) ? cpu_to_le32(BIT(27)) : 0;
151 if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
152 *pdw |= cpu_to_le32((0x01 << 28) & 0x30000000);
153 else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
154 *pdw |= cpu_to_le32((0x02 << 28) & 0x30000000);
155 else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)
158 *pdw |= cpu_to_le32((0x03 << 28) & 0x30000000);
163 static void fill_txdesc_phy(struct pkt_attrib *pattrib, __le32 *pdw)
165 if (pattrib->ht_en) {
166 *pdw |= (pattrib->bwmode&HT_CHANNEL_WIDTH_40) ? cpu_to_le32(BIT(25)) : 0;
168 if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
169 *pdw |= cpu_to_le32((0x01 << DATA_SC_SHT) & 0x003f0000);
170 else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
171 *pdw |= cpu_to_le32((0x02 << DATA_SC_SHT) & 0x003f0000);
172 else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)
175 *pdw |= cpu_to_le32((0x03 << DATA_SC_SHT) & 0x003f0000);
179 static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz, u8 bagg_pkt)
183 u8 data_rate, pwr_status, offset;
184 struct adapter *adapt = pxmitframe->padapter;
185 struct pkt_attrib *pattrib = &pxmitframe->attrib;
186 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
187 struct tx_desc *ptxdesc = (struct tx_desc *)pmem;
188 struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv;
189 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
190 int bmcst = IS_MCAST(pattrib->ra);
192 if (adapt->registrypriv.mp_mode == 0) {
193 if ((!bagg_pkt) && (urb_zero_packet_chk(adapt, sz) == 0)) {
194 ptxdesc = (struct tx_desc *)(pmem+PACKET_OFFSET_SZ);
199 memset(ptxdesc, 0, sizeof(struct tx_desc));
202 ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
203 ptxdesc->txdw0 |= cpu_to_le32(sz & 0x0000ffff);/* update TXPKTSIZE */
205 offset = TXDESC_SIZE + OFFSET_SZ;
207 ptxdesc->txdw0 |= cpu_to_le32(((offset) << OFFSET_SHT) & 0x00ff0000);/* 32 bytes for TX Desc */
210 ptxdesc->txdw0 |= cpu_to_le32(BMC);
212 if (adapt->registrypriv.mp_mode == 0) {
214 if ((pull) && (pxmitframe->pkt_offset > 0))
215 pxmitframe->pkt_offset = pxmitframe->pkt_offset - 1;
219 /* pkt_offset, unit:8 bytes padding */
220 if (pxmitframe->pkt_offset > 0)
221 ptxdesc->txdw1 |= cpu_to_le32((pxmitframe->pkt_offset << 26) & 0x7c000000);
223 /* driver uses rate */
224 ptxdesc->txdw4 |= cpu_to_le32(USERATE);/* rate control always by driver */
226 if ((pxmitframe->frame_tag & 0x0f) == DATA_FRAMETAG) {
228 ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id & 0x3F);
230 qsel = (uint)(pattrib->qsel & 0x0000001f);
231 ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00);
233 ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000F0000);
235 fill_txdesc_sectype(pattrib, ptxdesc);
237 if (pattrib->ampdu_en) {
238 ptxdesc->txdw2 |= cpu_to_le32(AGG_EN);/* AGG EN */
239 ptxdesc->txdw6 = cpu_to_le32(0x6666f800);
241 ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);/* AGG BK */
247 ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum << SEQ_SHT) & 0x0FFF0000);
249 /* offset 16 , offset 20 */
251 ptxdesc->txdw4 |= cpu_to_le32(QOS);/* QoS */
254 if (pxmitframe->agg_num > 1)
255 ptxdesc->txdw5 |= cpu_to_le32((pxmitframe->agg_num << USB_TXAGG_NUM_SHT) & 0xFF000000);
257 if ((pattrib->ether_type != 0x888e) &&
258 (pattrib->ether_type != 0x0806) &&
259 (pattrib->ether_type != 0x88b4) &&
260 (pattrib->dhcp_pkt != 1)) {
261 /* Non EAP & ARP & DHCP type data packet */
263 fill_txdesc_vcs(pattrib, &ptxdesc->txdw4);
264 fill_txdesc_phy(pattrib, &ptxdesc->txdw4);
266 ptxdesc->txdw4 |= cpu_to_le32(0x00000008);/* RTS Rate=24M */
267 ptxdesc->txdw5 |= cpu_to_le32(0x0001ff00);/* DATA/RTS Rate FB LMT */
269 if (pattrib->ht_en) {
270 if (ODM_RA_GetShortGI_8188E(&haldata->odmpriv, pattrib->mac_id))
271 ptxdesc->txdw5 |= cpu_to_le32(SGI);/* SGI */
273 data_rate = ODM_RA_GetDecisionRate_8188E(&haldata->odmpriv, pattrib->mac_id);
274 ptxdesc->txdw5 |= cpu_to_le32(data_rate & 0x3F);
275 pwr_status = ODM_RA_GetHwPwrStatus_8188E(&haldata->odmpriv, pattrib->mac_id);
276 ptxdesc->txdw4 |= cpu_to_le32((pwr_status & 0x7) << PWR_STATUS_SHT);
278 /* EAP data packet and ARP packet and DHCP. */
279 /* Use the 1M data rate to send the EAP/ARP packet. */
280 /* This will maybe make the handshake smooth. */
281 ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);/* AGG BK */
282 if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
283 ptxdesc->txdw4 |= cpu_to_le32(BIT(24));/* DATA_SHORT */
284 ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
286 } else if ((pxmitframe->frame_tag&0x0f) == MGNT_FRAMETAG) {
288 ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id & 0x3f);
290 qsel = (uint)(pattrib->qsel&0x0000001f);
291 ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00);
293 ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000f0000);
296 /* CCX-TXRPT ack for xmit mgmt frames. */
297 if (pxmitframe->ack_report)
298 ptxdesc->txdw2 |= cpu_to_le32(BIT(19));
301 ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<SEQ_SHT)&0x0FFF0000);
304 ptxdesc->txdw5 |= cpu_to_le32(RTY_LMT_EN);/* retry limit enable */
305 if (pattrib->retry_ctrl)
306 ptxdesc->txdw5 |= cpu_to_le32(0x00180000);/* retry limit = 6 */
308 ptxdesc->txdw5 |= cpu_to_le32(0x00300000);/* retry limit = 12 */
310 ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
311 } else if ((pxmitframe->frame_tag&0x0f) == TXAGG_FRAMETAG) {
312 DBG_88E("pxmitframe->frame_tag == TXAGG_FRAMETAG\n");
313 } else if (((pxmitframe->frame_tag&0x0f) == MP_FRAMETAG) &&
314 (adapt->registrypriv.mp_mode == 1)) {
315 fill_txdesc_for_mp(adapt, ptxdesc);
317 DBG_88E("pxmitframe->frame_tag = %d\n", pxmitframe->frame_tag);
320 ptxdesc->txdw1 |= cpu_to_le32((4) & 0x3f);/* CAM_ID(MAC_ID) */
322 ptxdesc->txdw1 |= cpu_to_le32((6 << RATE_ID_SHT) & 0x000f0000);/* raid */
327 ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<SEQ_SHT)&0x0fff0000);
330 ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
333 /* 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS. */
334 /* (1) The sequence number of each non-Qos frame / broadcast / multicast / */
335 /* mgnt frame should be controlled by Hw because Fw will also send null data */
336 /* which we cannot control when Fw LPS enable. */
337 /* --> default enable non-Qos data sequense number. 2010.06.23. by tynli. */
338 /* (2) Enable HW SEQ control for beacon packet, because we use Hw beacon. */
339 /* (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets. */
340 /* 2010.06.23. Added by tynli. */
341 if (!pattrib->qos_en) {
342 ptxdesc->txdw3 |= cpu_to_le32(EN_HWSEQ); /* Hw set sequence number */
343 ptxdesc->txdw4 |= cpu_to_le32(HW_SSN); /* Hw set sequence number */
346 ODM_SetTxAntByTxInfo_88E(&haldata->odmpriv, pmem, pattrib->mac_id);
348 rtl8188eu_cal_txdesc_chksum(ptxdesc);
349 _dbg_dump_tx_info(adapt, pxmitframe->frame_tag, ptxdesc);
353 /* for non-agg data frame or management frame */
354 static s32 rtw_dump_xframe(struct adapter *adapt, struct xmit_frame *pxmitframe)
357 s32 inner_ret = _SUCCESS;
358 int t, sz, w_sz, pull = 0;
361 struct xmit_buf *pxmitbuf = pxmitframe->pxmitbuf;
362 struct pkt_attrib *pattrib = &pxmitframe->attrib;
363 struct xmit_priv *pxmitpriv = &adapt->xmitpriv;
364 struct security_priv *psecuritypriv = &adapt->securitypriv;
365 if ((pxmitframe->frame_tag == DATA_FRAMETAG) &&
366 (pxmitframe->attrib.ether_type != 0x0806) &&
367 (pxmitframe->attrib.ether_type != 0x888e) &&
368 (pxmitframe->attrib.ether_type != 0x88b4) &&
369 (pxmitframe->attrib.dhcp_pkt != 1))
370 rtw_issue_addbareq_cmd(adapt, pxmitframe);
371 mem_addr = pxmitframe->buf_addr;
373 RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_dump_xframe()\n"));
375 for (t = 0; t < pattrib->nr_frags; t++) {
376 if (inner_ret != _SUCCESS && ret == _SUCCESS)
379 if (t != (pattrib->nr_frags - 1)) {
380 RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("pattrib->nr_frags=%d\n", pattrib->nr_frags));
382 sz = pxmitpriv->frag_len;
383 sz = sz - 4 - (psecuritypriv->sw_encrypt ? 0 : pattrib->icv_len);
386 sz = pattrib->last_txcmdsz;
389 pull = update_txdesc(pxmitframe, mem_addr, sz, false);
392 mem_addr += PACKET_OFFSET_SZ; /* pull txdesc head */
393 pxmitframe->buf_addr = mem_addr;
394 w_sz = sz + TXDESC_SIZE;
396 w_sz = sz + TXDESC_SIZE + PACKET_OFFSET_SZ;
398 ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe);
400 inner_ret = rtw_write_port(adapt, ff_hwaddr, w_sz, (unsigned char *)pxmitbuf);
402 rtw_count_tx_stats(adapt, pxmitframe, sz);
404 RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_write_port, w_sz=%d\n", w_sz));
408 mem_addr = (u8 *)RND4(((size_t)(mem_addr)));
411 rtw_free_xmitframe(pxmitpriv, pxmitframe);
414 rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_UNKNOWN);
419 static u32 xmitframe_need_length(struct xmit_frame *pxmitframe)
421 struct pkt_attrib *pattrib = &pxmitframe->attrib;
425 /* no consider fragement */
426 len = pattrib->hdrlen + pattrib->iv_len +
427 SNAP_SIZE + sizeof(u16) +
429 ((pattrib->bswenc) ? pattrib->icv_len : 0);
431 if (pattrib->encrypt == _TKIP_)
437 s32 rtl8188eu_xmitframe_complete(struct adapter *adapt, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)
439 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
440 struct xmit_frame *pxmitframe = NULL;
441 struct xmit_frame *pfirstframe = NULL;
443 /* aggregate variable */
444 struct hw_xmit *phwxmit;
445 struct sta_info *psta = NULL;
446 struct tx_servq *ptxservq = NULL;
447 struct list_head *xmitframe_plist = NULL, *xmitframe_phead = NULL;
449 u32 pbuf; /* next pkt address */
450 u32 pbuf_tail; /* last pkt tail */
451 u32 len; /* packet length, except TXDESC_SIZE and PKT_OFFSET */
453 u32 bulksize = haldata->UsbBulkOutSize;
457 /* dump frame variable */
460 RT_TRACE(_module_rtl8192c_xmit_c_, _drv_info_, ("+xmitframe_complete\n"));
462 /* check xmitbuffer is ok */
463 if (pxmitbuf == NULL) {
464 pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
465 if (pxmitbuf == NULL)
469 /* 3 1. pick up first frame */
471 rtw_free_xmitframe(pxmitpriv, pxmitframe);
473 pxmitframe = rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry);
474 if (pxmitframe == NULL) {
475 /* no more xmit frame, release xmit buffer */
476 rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
480 pxmitframe->pxmitbuf = pxmitbuf;
481 pxmitframe->buf_addr = pxmitbuf->pbuf;
482 pxmitbuf->priv_data = pxmitframe;
484 pxmitframe->agg_num = 1; /* alloc xmitframe should assign to 1. */
485 pxmitframe->pkt_offset = 1; /* first frame of aggregation, reserve offset */
487 rtw_xmitframe_coalesce(adapt, pxmitframe->pkt, pxmitframe);
489 /* always return ndis_packet after rtw_xmitframe_coalesce */
490 rtw_os_xmit_complete(adapt, pxmitframe);
495 /* 3 2. aggregate same priority and same DA(AP or STA) frames */
496 pfirstframe = pxmitframe;
497 len = xmitframe_need_length(pfirstframe) + TXDESC_SIZE + (pfirstframe->pkt_offset*PACKET_OFFSET_SZ);
499 pbuf = _RND8(pbuf_tail);
501 /* check pkt amount in one bulk */
504 if (pbuf < bulkptr) {
508 bulkptr = ((pbuf / bulksize) + 1) * bulksize; /* round to next bulksize */
511 /* dequeue same priority packet from station tx queue */
512 psta = pfirstframe->attrib.psta;
513 switch (pfirstframe->attrib.priority) {
516 ptxservq = &(psta->sta_xmitpriv.bk_q);
517 phwxmit = pxmitpriv->hwxmits + 3;
521 ptxservq = &(psta->sta_xmitpriv.vi_q);
522 phwxmit = pxmitpriv->hwxmits + 1;
526 ptxservq = &(psta->sta_xmitpriv.vo_q);
527 phwxmit = pxmitpriv->hwxmits;
532 ptxservq = &(psta->sta_xmitpriv.be_q);
533 phwxmit = pxmitpriv->hwxmits + 2;
536 spin_lock_bh(&pxmitpriv->lock);
538 xmitframe_phead = get_list_head(&ptxservq->sta_pending);
539 xmitframe_plist = xmitframe_phead->next;
541 while (xmitframe_phead != xmitframe_plist) {
542 pxmitframe = container_of(xmitframe_plist, struct xmit_frame, list);
543 xmitframe_plist = xmitframe_plist->next;
545 pxmitframe->agg_num = 0; /* not first frame of aggregation */
546 pxmitframe->pkt_offset = 0; /* not first frame of aggregation, no need to reserve offset */
548 len = xmitframe_need_length(pxmitframe) + TXDESC_SIZE + (pxmitframe->pkt_offset*PACKET_OFFSET_SZ);
550 if (_RND8(pbuf + len) > MAX_XMITBUF_SZ) {
551 pxmitframe->agg_num = 1;
552 pxmitframe->pkt_offset = 1;
555 list_del_init(&pxmitframe->list);
559 pxmitframe->buf_addr = pxmitbuf->pbuf + pbuf;
561 rtw_xmitframe_coalesce(adapt, pxmitframe->pkt, pxmitframe);
562 /* always return ndis_packet after rtw_xmitframe_coalesce */
563 rtw_os_xmit_complete(adapt, pxmitframe);
565 /* (len - TXDESC_SIZE) == pxmitframe->attrib.last_txcmdsz */
566 update_txdesc(pxmitframe, pxmitframe->buf_addr, pxmitframe->attrib.last_txcmdsz, true);
568 /* don't need xmitframe any more */
569 rtw_free_xmitframe(pxmitpriv, pxmitframe);
571 /* handle pointer and stop condition */
572 pbuf_tail = pbuf + len;
573 pbuf = _RND8(pbuf_tail);
575 pfirstframe->agg_num++;
576 if (MAX_TX_AGG_PACKET_NUMBER == pfirstframe->agg_num)
579 if (pbuf < bulkptr) {
581 if (desc_cnt == haldata->UsbTxAggDescNum)
585 bulkptr = ((pbuf / bulksize) + 1) * bulksize;
587 } /* end while (aggregate same priority and same DA(AP or STA) frames) */
589 if (list_empty(&ptxservq->sta_pending.queue))
590 list_del_init(&ptxservq->tx_pending);
592 spin_unlock_bh(&pxmitpriv->lock);
593 if ((pfirstframe->attrib.ether_type != 0x0806) &&
594 (pfirstframe->attrib.ether_type != 0x888e) &&
595 (pfirstframe->attrib.ether_type != 0x88b4) &&
596 (pfirstframe->attrib.dhcp_pkt != 1))
597 rtw_issue_addbareq_cmd(adapt, pfirstframe);
598 /* 3 3. update first frame txdesc */
599 if ((pbuf_tail % bulksize) == 0) {
600 /* remove pkt_offset */
601 pbuf_tail -= PACKET_OFFSET_SZ;
602 pfirstframe->buf_addr += PACKET_OFFSET_SZ;
603 pfirstframe->pkt_offset--;
606 update_txdesc(pfirstframe, pfirstframe->buf_addr, pfirstframe->attrib.last_txcmdsz, true);
608 /* 3 4. write xmit buffer to USB FIFO */
609 ff_hwaddr = rtw_get_ff_hwaddr(pfirstframe);
610 rtw_write_port(adapt, ff_hwaddr, pbuf_tail, (u8 *)pxmitbuf);
612 /* 3 5. update statisitc */
613 pbuf_tail -= (pfirstframe->agg_num * TXDESC_SIZE);
614 pbuf_tail -= (pfirstframe->pkt_offset * PACKET_OFFSET_SZ);
616 rtw_count_tx_stats(adapt, pfirstframe, pbuf_tail);
618 rtw_free_xmitframe(pxmitpriv, pfirstframe);
623 static s32 xmitframe_direct(struct adapter *adapt, struct xmit_frame *pxmitframe)
627 res = rtw_xmitframe_coalesce(adapt, pxmitframe->pkt, pxmitframe);
629 rtw_dump_xframe(adapt, pxmitframe);
631 DBG_88E("==> %s xmitframe_coalsece failed\n", __func__);
637 * true dump packet directly
638 * false enqueue packet
640 static s32 pre_xmitframe(struct adapter *adapt, struct xmit_frame *pxmitframe)
643 struct xmit_buf *pxmitbuf = NULL;
644 struct xmit_priv *pxmitpriv = &adapt->xmitpriv;
645 struct pkt_attrib *pattrib = &pxmitframe->attrib;
646 struct mlme_priv *pmlmepriv = &adapt->mlmepriv;
648 spin_lock_bh(&pxmitpriv->lock);
650 if (rtw_txframes_sta_ac_pending(adapt, pattrib) > 0)
653 if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == true)
656 pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
657 if (pxmitbuf == NULL)
660 spin_unlock_bh(&pxmitpriv->lock);
662 pxmitframe->pxmitbuf = pxmitbuf;
663 pxmitframe->buf_addr = pxmitbuf->pbuf;
664 pxmitbuf->priv_data = pxmitframe;
666 if (xmitframe_direct(adapt, pxmitframe) != _SUCCESS) {
667 rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
668 rtw_free_xmitframe(pxmitpriv, pxmitframe);
674 res = rtw_xmitframe_enqueue(adapt, pxmitframe);
675 spin_unlock_bh(&pxmitpriv->lock);
677 if (res != _SUCCESS) {
678 RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("pre_xmitframe: enqueue xmitframe fail\n"));
679 rtw_free_xmitframe(pxmitpriv, pxmitframe);
681 /* Trick, make the statistics correct */
682 pxmitpriv->tx_pkts--;
683 pxmitpriv->tx_drop++;
690 s32 rtl8188eu_mgnt_xmit(struct adapter *adapt, struct xmit_frame *pmgntframe)
692 return rtw_dump_xframe(adapt, pmgntframe);
697 * true dump packet directly ok
698 * false temporary can't transmit packets to hardware
700 s32 rtl8188eu_hal_xmit(struct adapter *adapt, struct xmit_frame *pxmitframe)
702 return pre_xmitframe(adapt, pxmitframe);